Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
58.56	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	46	44	48.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	46	44	48.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	200	1			T28	4		T33	4		T35	4
all_values[1]	200	1			T28	4		T33	4		T35	4
all_values[2]	200	1			T28	4		T33	4		T35	4
all_values[3]	200	1			T28	4		T33	4		T35	4
all_values[4]	200	1			T28	4		T33	4		T35	4
all_values[5]	200	1			T28	4		T33	4		T35	4
all_values[6]	200	1			T28	4		T33	4		T35	4
all_values[7]	200	1			T28	4		T33	4		T35	4
all_values[8]	200	1			T28	4		T33	4		T35	4
all_values[9]	200	1			T28	4		T33	4		T35	4
all_values[10]	200	1			T28	4		T33	4		T35	4
all_values[11]	200	1			T28	4		T33	4		T35	4
all_values[12]	200	1			T28	4		T33	4		T35	4
all_values[13]	200	1			T28	4		T33	4		T35	4
all_values[14]	200	1			T28	4		T33	4		T35	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1750

1

T28

35

T33

35

T35

35

auto[1]

1250

1

T28

25

T33

25

T35

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T28

21

T33

21

T35

21

auto[1]

1950

1

T28

39

T33

39

T35

39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2050

1

T28

41

T33

41

T35

41

auto[1]

950

1

T28

19

T33

19

T35

19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	46	44	48.89	46
Automatically Generated Cross Bins	90	46	44	48.89	46
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	[auto[0]]	*	--	--	2
[all_values[2]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[3]]	*	*	[auto[1]]	--	--	4
[all_values[4]]	[auto[0]]	[auto[1]]	*	--	--	2
[all_values[5]]	[auto[0]]	[auto[1]]	*	--	--	2
[all_values[6] , all_values[7]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[8] , all_values[9]]	*	*	[auto[1]]	--	--	8
[all_values[10]]	*	[auto[0]]	[auto[1]]	--	--	2
[all_values[11]]	[auto[0]]	[auto[0]]	*	--	--	2
[all_values[12]]	[auto[0]]	[auto[1]]	*	--	--	2
[all_values[13]]	*	*	[auto[1]]	--	--	4
[all_values[14]]	[auto[0]]	*	[auto[0]]	--	--	2

Uncovered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[1]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[5]]	[auto[0]]	[auto[0]]	[auto[0]]	0	1	1
[all_values[5]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[all_values[6] , all_values[7]]	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2
[all_values[11]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[0]	auto[1]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[0]	auto[1]	auto[1]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[1]	auto[0]	auto[0]	auto[0]	50	1			T28	1		T33	1		T35	1
all_values[1]	auto[0]	auto[1]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[1]	auto[1]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[2]	auto[0]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[2]	auto[1]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[2]	auto[1]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[3]	auto[0]	auto[0]	auto[0]	150	1			T28	3		T33	3		T35	3
all_values[3]	auto[0]	auto[1]	auto[0]	50	1			T28	1		T33	1		T35	1
all_values[4]	auto[0]	auto[0]	auto[0]	50	1			T28	1		T33	1		T35	1
all_values[4]	auto[0]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[4]	auto[1]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[4]	auto[1]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[5]	auto[0]	auto[0]	auto[1]	150	1			T28	3		T33	3		T35	3
all_values[5]	auto[1]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[6]	auto[0]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[6]	auto[0]	auto[1]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[6]	auto[1]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[7]	auto[0]	auto[0]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[7]	auto[0]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[7]	auto[1]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[8]	auto[0]	auto[0]	auto[0]	150	1			T28	3		T33	3		T35	3
all_values[8]	auto[0]	auto[1]	auto[0]	50	1			T28	1		T33	1		T35	1
all_values[9]	auto[0]	auto[0]	auto[0]	150	1			T28	3		T33	3		T35	3
all_values[9]	auto[0]	auto[1]	auto[0]	50	1			T28	1		T33	1		T35	1
all_values[10]	auto[0]	auto[0]	auto[0]	50	1			T28	1		T33	1		T35	1
all_values[10]	auto[0]	auto[1]	auto[0]	50	1			T28	1		T33	1		T35	1
all_values[10]	auto[0]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[10]	auto[1]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[11]	auto[0]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[11]	auto[1]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[11]	auto[1]	auto[1]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[12]	auto[0]	auto[0]	auto[0]	50	1			T28	1		T33	1		T35	1
all_values[12]	auto[0]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[12]	auto[1]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[12]	auto[1]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[13]	auto[0]	auto[0]	auto[0]	100	1			T28	2		T33	2		T35	2
all_values[13]	auto[0]	auto[1]	auto[0]	100	1			T28	2		T33	2		T35	2
all_values[14]	auto[0]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[14]	auto[0]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[14]	auto[1]	auto[0]	auto[1]	100	1			T28	2		T33	2		T35	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal