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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.12 98.93 91.44 99.76 91.30 97.69 98.39 81.30


Total test records in report: 1672
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T1505 /workspace/coverage/default/39.i2c_host_override.110604154388237712125967769866942534888473439234531136306747879523296985996886 Nov 22 02:38:32 PM PST 23 Nov 22 02:38:33 PM PST 23 23672229 ps
T1506 /workspace/coverage/default/39.i2c_target_stress_rd.113351619079283556411003403393723244975910163174865219426841810199521614974777 Nov 22 02:38:32 PM PST 23 Nov 22 02:38:42 PM PST 23 997771563 ps
T1507 /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.95858553063281546264587981632155904107239369870218566370296293777868982823731 Nov 22 02:21:12 PM PST 23 Nov 22 02:21:14 PM PST 23 209010032 ps
T1508 /workspace/coverage/default/20.i2c_target_tx_ovf.21670297718978128800360930206934647762940578342125029624266203281072938376953 Nov 22 02:21:25 PM PST 23 Nov 22 02:23:21 PM PST 23 5445414553 ps
T1509 /workspace/coverage/default/37.i2c_target_fifo_reset_tx.61463687132363966066280361425179783518364710199918920731044853518607454554726 Nov 22 02:38:10 PM PST 23 Nov 22 02:38:47 PM PST 23 10065199023 ps
T1510 /workspace/coverage/default/34.i2c_target_fifo_reset_acq.8129917938956287865265872194696823772983302709272861294474360379626635245524 Nov 22 02:37:42 PM PST 23 Nov 22 02:38:15 PM PST 23 10166144644 ps
T1511 /workspace/coverage/default/5.i2c_target_intr_smoke.64478944872698217118255709668337167929638902589651290880336403434643614028566 Nov 22 02:18:49 PM PST 23 Nov 22 02:18:54 PM PST 23 1588231125 ps
T1512 /workspace/coverage/default/0.i2c_host_rx_oversample.106322525824037228306267118404999039563302901370486088592212662332466605353183 Nov 22 02:17:14 PM PST 23 Nov 22 02:18:57 PM PST 23 3939158762 ps
T1513 /workspace/coverage/default/24.i2c_host_rx_oversample.101632282619110436607342802547188489962110697725889105549616958787296146315558 Nov 22 02:22:03 PM PST 23 Nov 22 02:23:48 PM PST 23 3939158762 ps
T1514 /workspace/coverage/default/32.i2c_target_hrst.52683473955627428378345055170796271190943455128692346579599309504922057575363 Nov 22 02:36:29 PM PST 23 Nov 22 02:36:32 PM PST 23 825344371 ps
T1515 /workspace/coverage/default/10.i2c_host_perf.51808742747475611000893086022408436428414395116856037081568458098236938498778 Nov 22 02:19:34 PM PST 23 Nov 22 02:20:37 PM PST 23 6830796343 ps
T1516 /workspace/coverage/default/33.i2c_target_fifo_reset_acq.45997217634860169032121777605440876818925675241391421298666033518482130519774 Nov 22 02:36:44 PM PST 23 Nov 22 02:37:15 PM PST 23 10166144644 ps
T1517 /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.43354242195615373280838839916498742634848735892417465302233912751419700744745 Nov 22 02:18:36 PM PST 23 Nov 22 02:18:37 PM PST 23 209010032 ps
T1518 /workspace/coverage/default/36.i2c_target_intr_smoke.31497880498867943992420202645675692350063632334324332777433321963102382990777 Nov 22 02:37:43 PM PST 23 Nov 22 02:37:49 PM PST 23 1588231125 ps
T1519 /workspace/coverage/default/7.i2c_host_rx_oversample.31243937170568768233271441265393137721590500018083727288379305242836343242713 Nov 22 02:19:06 PM PST 23 Nov 22 02:21:05 PM PST 23 3939158762 ps
T1520 /workspace/coverage/default/24.i2c_target_unexp_stop.21971633361509796208666571891164269460809111715042263730111830086834972038851 Nov 22 02:22:20 PM PST 23 Nov 22 02:22:34 PM PST 23 1922317738 ps
T1521 /workspace/coverage/default/39.i2c_host_error_intr.16753157332280607020829381692151074396259075861097809065394456443949335563809 Nov 22 02:38:36 PM PST 23 Nov 22 02:38:38 PM PST 23 74225396 ps
T1522 /workspace/coverage/default/26.i2c_host_stress_all.22523355689580408400011323289793269037334276672515201758610024968852872554847 Nov 22 02:22:02 PM PST 23 Nov 22 02:39:45 PM PST 23 32807463528 ps
T1523 /workspace/coverage/default/17.i2c_target_intr_smoke.5308258376136323012808999897153104628233881130044687599135607071107065790423 Nov 22 02:21:02 PM PST 23 Nov 22 02:21:07 PM PST 23 1588231125 ps
T1524 /workspace/coverage/default/48.i2c_host_fifo_full.111896095284195637046155567655112068406184810066021723508575292563345805780924 Nov 22 02:40:30 PM PST 23 Nov 22 02:41:48 PM PST 23 3768267272 ps
T1525 /workspace/coverage/default/22.i2c_host_override.57229137249525334103308878079393219227380271168487476495388139185759487796254 Nov 22 02:22:07 PM PST 23 Nov 22 02:22:13 PM PST 23 23672229 ps
T1526 /workspace/coverage/default/27.i2c_host_smoke.109687337222973860234310263074301738617967760975588105407199056388326027682624 Nov 22 02:22:03 PM PST 23 Nov 22 02:22:42 PM PST 23 2343171530 ps
T1527 /workspace/coverage/default/49.i2c_target_tx_ovf.54760343471194713560509629298012382813429753064592258712855283467387853541057 Nov 22 02:40:35 PM PST 23 Nov 22 02:42:46 PM PST 23 5445414553 ps
T1528 /workspace/coverage/default/43.i2c_host_rx_oversample.66077921167308833242416964656670816362527833291172163450073415783317892969948 Nov 22 02:40:35 PM PST 23 Nov 22 02:42:24 PM PST 23 3939158762 ps
T1529 /workspace/coverage/default/25.i2c_target_stress_rd.8689806049079997154079328505019853083385087482419661820166303521193679919663 Nov 22 02:22:08 PM PST 23 Nov 22 02:22:22 PM PST 23 997771563 ps
T1530 /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.36266681802872149595099996967884667547246097797138724046183568190237104845197 Nov 22 02:21:10 PM PST 23 Nov 22 02:21:12 PM PST 23 209010032 ps
T1531 /workspace/coverage/default/37.i2c_host_fifo_full.84801587669815490206135460714523199975770997511943611306186670214113229780989 Nov 22 02:38:09 PM PST 23 Nov 22 02:39:17 PM PST 23 3768267272 ps
T1532 /workspace/coverage/default/49.i2c_host_perf.79518546619907708139840685814042916724067625865050512237941052047270128647402 Nov 22 02:40:47 PM PST 23 Nov 22 02:41:48 PM PST 23 6830796343 ps
T1533 /workspace/coverage/default/1.i2c_host_mode_toggle.66841485693048616907019492858168824644294712078030415904546184426376804005692 Nov 22 02:17:40 PM PST 23 Nov 22 02:18:34 PM PST 23 3754070957 ps
T1534 /workspace/coverage/default/17.i2c_target_intr_stress_wr.43053974578139638968883347963158475935617056416576895812915373514787948213847 Nov 22 02:21:13 PM PST 23 Nov 22 02:21:36 PM PST 23 5106060125 ps
T1535 /workspace/coverage/default/6.i2c_target_timeout.21871169207856789501403814355003034279157934069989436640738825007472786993850 Nov 22 02:18:49 PM PST 23 Nov 22 02:18:57 PM PST 23 2856220981 ps
T1536 /workspace/coverage/default/5.i2c_target_stress_wr.98743247938839657289085710285916768349915422270161835966016059074946578904167 Nov 22 02:18:48 PM PST 23 Nov 22 02:20:07 PM PST 23 14461449567 ps
T1537 /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.57693135588403240756483036465038083820987513168677661904779467912683487027428 Nov 22 02:38:59 PM PST 23 Nov 22 02:39:01 PM PST 23 209010032 ps
T1538 /workspace/coverage/default/30.i2c_host_mode_toggle.98177112124372072369231702334643644029471424046580731987165138118517102895694 Nov 22 02:23:19 PM PST 23 Nov 22 02:24:10 PM PST 23 3754070957 ps
T1539 /workspace/coverage/default/23.i2c_alert_test.100657072522994445574913288890002059754325188417911972632391242810857599931009 Nov 22 02:22:06 PM PST 23 Nov 22 02:22:12 PM PST 23 19975830 ps
T1540 /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.18764791375180138595428495476571081343901528548400696955406931356505271264365 Nov 22 02:22:08 PM PST 23 Nov 22 02:22:20 PM PST 23 606667565 ps
T1541 /workspace/coverage/default/16.i2c_host_fifo_full.70402578607457068338545420355761536536263038389963806815628278657478401277131 Nov 22 02:21:10 PM PST 23 Nov 22 02:22:24 PM PST 23 3768267272 ps
T1542 /workspace/coverage/default/15.i2c_host_rx_oversample.9967430564506087639342814428552331520415415946862332307914300193882990928163 Nov 22 02:20:47 PM PST 23 Nov 22 02:22:32 PM PST 23 3939158762 ps
T1543 /workspace/coverage/default/33.i2c_target_tx_ovf.29573737316969858364011825051946573299259864907694773487526462739676514867407 Nov 22 02:36:28 PM PST 23 Nov 22 02:38:29 PM PST 23 5445414553 ps
T1544 /workspace/coverage/default/5.i2c_target_timeout.96232940922564763205585094857104828171812086340530005843967795523717940064014 Nov 22 02:19:10 PM PST 23 Nov 22 02:19:18 PM PST 23 2856220981 ps
T1545 /workspace/coverage/default/5.i2c_target_smoke.70153526990254673055188507321152447190722016140403712199586795924430536552253 Nov 22 02:18:34 PM PST 23 Nov 22 02:18:45 PM PST 23 1504713936 ps
T1546 /workspace/coverage/default/14.i2c_target_bad_addr.60527385892341332002179723860849790069230096772283200525286173932039763891209 Nov 22 02:21:02 PM PST 23 Nov 22 02:21:06 PM PST 23 1519570960 ps
T1547 /workspace/coverage/default/1.i2c_target_bad_addr.69620873939780726506759645878391799894060803772996274346969585234571171350757 Nov 22 02:18:07 PM PST 23 Nov 22 02:18:11 PM PST 23 1519570960 ps
T1548 /workspace/coverage/default/44.i2c_alert_test.4952513578199182481159023832801114553427624706733485010157644087372620701092 Nov 22 02:40:34 PM PST 23 Nov 22 02:40:36 PM PST 23 19975830 ps
T1549 /workspace/coverage/default/27.i2c_host_stress_all.2592789789824197473525210010000463726413541667486913843267239526210720314559 Nov 22 02:22:11 PM PST 23 Nov 22 02:39:33 PM PST 23 32807463528 ps
T1550 /workspace/coverage/default/46.i2c_target_stress_all.14441839408469503415795654283240398217131704765190602805525236369219863944739 Nov 22 02:40:28 PM PST 23 Nov 22 03:04:54 PM PST 23 66540157934 ps
T1551 /workspace/coverage/default/10.i2c_host_error_intr.111123586583586652497865853151976688230080708540176040556581212436083613702603 Nov 22 02:19:34 PM PST 23 Nov 22 02:19:36 PM PST 23 74225396 ps
T1552 /workspace/coverage/default/39.i2c_host_smoke.115691021173367209302109254925596921870032658377913172876010257767295224172562 Nov 22 02:38:33 PM PST 23 Nov 22 02:39:11 PM PST 23 2343171530 ps
T1553 /workspace/coverage/default/39.i2c_target_unexp_stop.47080393176402546511383422358957651963516128314510956702496378953335228375887 Nov 22 02:38:35 PM PST 23 Nov 22 02:38:42 PM PST 23 1922317738 ps
T1554 /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.53914926928276684312621361252435196205828999498104866761989221772302730157874 Nov 22 02:38:36 PM PST 23 Nov 22 02:38:43 PM PST 23 606667565 ps
T1555 /workspace/coverage/default/20.i2c_host_fifo_watermark.93253501931161051938894460320963165149621582286967583435052833488528169952059 Nov 22 02:21:09 PM PST 23 Nov 22 02:24:36 PM PST 23 7918519784 ps
T1556 /workspace/coverage/default/46.i2c_host_fifo_reset_rx.27784968672617091237356797807768876033009590194586385780742250498563139890472 Nov 22 02:39:58 PM PST 23 Nov 22 02:40:02 PM PST 23 236313385 ps
T1557 /workspace/coverage/default/41.i2c_host_perf.54966807886580204796266772536576491714455452947884788456572465507896893564548 Nov 22 02:39:51 PM PST 23 Nov 22 02:40:52 PM PST 23 6830796343 ps
T1558 /workspace/coverage/default/17.i2c_host_override.94295287931839352457163054522107518339038943378286720456181478225592618470676 Nov 22 02:21:01 PM PST 23 Nov 22 02:21:03 PM PST 23 23672229 ps
T1559 /workspace/coverage/default/23.i2c_target_intr_smoke.56123614100125685987177290260841401350831407457618254876977400465279390808951 Nov 22 02:22:02 PM PST 23 Nov 22 02:22:10 PM PST 23 1588231125 ps
T1560 /workspace/coverage/default/46.i2c_host_fifo_full.30549116137530020404357145647577920638059150258027310240056104371370302038624 Nov 22 02:39:56 PM PST 23 Nov 22 02:41:07 PM PST 23 3768267272 ps
T1561 /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.27303372851576334475221795292004800119137950733669554697711495714534150035933 Nov 22 02:18:09 PM PST 23 Nov 22 02:18:16 PM PST 23 606667565 ps
T1562 /workspace/coverage/default/32.i2c_target_bad_addr.92825809795923851166307111898935058567867082725530383731309772223315969922775 Nov 22 02:36:17 PM PST 23 Nov 22 02:36:22 PM PST 23 1519570960 ps
T1563 /workspace/coverage/default/18.i2c_host_override.2551479708369131327852093861737371322997871928738260368550575266147100694907 Nov 22 02:20:57 PM PST 23 Nov 22 02:20:59 PM PST 23 23672229 ps
T1564 /workspace/coverage/default/10.i2c_target_tx_ovf.35057110798916721428013286266928709351358507021092720193681232456887712121716 Nov 22 02:19:51 PM PST 23 Nov 22 02:22:02 PM PST 23 5445414553 ps
T1565 /workspace/coverage/default/21.i2c_host_stress_all.62422202045698303857314456667347526467442539617330152960946248284111204301568 Nov 22 02:21:42 PM PST 23 Nov 22 02:40:15 PM PST 23 32807463528 ps
T1566 /workspace/coverage/default/5.i2c_target_tx_ovf.94869738935207514977870250893172094284416934333201302709098204092542325899647 Nov 22 02:18:36 PM PST 23 Nov 22 02:20:47 PM PST 23 5445414553 ps
T1567 /workspace/coverage/default/12.i2c_target_perf.114385228142710626605161092332508737816224770378426198029940618677175504061459 Nov 22 02:20:11 PM PST 23 Nov 22 02:20:15 PM PST 23 834576440 ps
T1568 /workspace/coverage/default/16.i2c_host_rx_oversample.73012487669163896393967118000633773220700189598856697983738469624265604475010 Nov 22 02:21:12 PM PST 23 Nov 22 02:22:51 PM PST 23 3939158762 ps
T1569 /workspace/coverage/default/44.i2c_target_stress_rd.4705304756412732560806180335423545572907718356283855481869373717737157623081 Nov 22 02:40:10 PM PST 23 Nov 22 02:40:20 PM PST 23 997771563 ps
T1570 /workspace/coverage/default/13.i2c_target_bad_addr.89654995631631885534827432671636176658886447671329875515406014043027228796932 Nov 22 02:21:10 PM PST 23 Nov 22 02:21:15 PM PST 23 1519570960 ps
T1571 /workspace/coverage/default/2.i2c_target_stress_wr.51542796500276363810482557716870694774146571093175008080635728901141608416918 Nov 22 02:18:18 PM PST 23 Nov 22 02:19:49 PM PST 23 14461449567 ps
T1572 /workspace/coverage/default/2.i2c_target_smoke.97311688799930665009490218249865798621203843016382405536888720981191008536233 Nov 22 02:18:09 PM PST 23 Nov 22 02:18:20 PM PST 23 1504713936 ps
T1573 /workspace/coverage/default/46.i2c_target_intr_smoke.21540270547842011526840348467470722426778831610163262896656841552111290362600 Nov 22 02:40:32 PM PST 23 Nov 22 02:40:37 PM PST 23 1588231125 ps
T1574 /workspace/coverage/default/46.i2c_host_fifo_overflow.77669770477578030187732964429553034193794037795813416965485825548092133255369 Nov 22 02:40:29 PM PST 23 Nov 22 02:44:31 PM PST 23 7925734012 ps
T1575 /workspace/coverage/default/37.i2c_target_timeout.106009353579319217961034164807027658540337804430959424420516950544336196093654 Nov 22 02:38:11 PM PST 23 Nov 22 02:38:20 PM PST 23 2856220981 ps
T1576 /workspace/coverage/default/20.i2c_host_mode_toggle.16407741478681483443516352454447028052755146290713759340857904771466911982586 Nov 22 02:22:00 PM PST 23 Nov 22 02:22:58 PM PST 23 3754070957 ps
T1577 /workspace/coverage/default/5.i2c_host_stretch_timeout.22393042026167510668862021965930485081947196975325377727656836386801558543450 Nov 22 02:18:52 PM PST 23 Nov 22 02:19:06 PM PST 23 1466624971 ps
T1578 /workspace/coverage/default/32.i2c_host_fifo_watermark.60849935794077734700407340507857640403355686713417051471943700208113046133354 Nov 22 02:23:19 PM PST 23 Nov 22 02:26:54 PM PST 23 7918519784 ps
T1579 /workspace/coverage/default/23.i2c_target_tx_ovf.53032279097588298851609490971924226216348161746456165479180496445556721794296 Nov 22 02:22:03 PM PST 23 Nov 22 02:24:04 PM PST 23 5445414553 ps
T1580 /workspace/coverage/default/43.i2c_host_fifo_overflow.724241469940991853718934734355862660880592697516681136475732542318557462771 Nov 22 02:39:37 PM PST 23 Nov 22 02:43:19 PM PST 23 7925734012 ps
T1581 /workspace/coverage/default/7.i2c_host_stress_all.41339112825830704562797779933134799683876270218515768138798469905701374835962 Nov 22 02:18:44 PM PST 23 Nov 22 02:35:17 PM PST 23 32807463528 ps
T1582 /workspace/coverage/default/47.i2c_target_stress_wr.9104881332171157832724578038827739460775210630886516521252923046865447484923 Nov 22 02:40:17 PM PST 23 Nov 22 02:41:49 PM PST 23 14461449567 ps
T1583 /workspace/coverage/default/26.i2c_alert_test.62358230035037802171678098213875806789602075734765597572137880741479775864587 Nov 22 02:22:04 PM PST 23 Nov 22 02:22:10 PM PST 23 19975830 ps
T96 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.21563191129418836292137549097372439980838413924765903127236350384843554202558 Nov 22 01:03:02 PM PST 23 Nov 22 01:03:04 PM PST 23 48993455 ps
T1584 /workspace/coverage/cover_reg_top/36.i2c_intr_test.72637762527124499698397210603803880216585174744308311695950200288069332532339 Nov 22 01:03:52 PM PST 23 Nov 22 01:03:54 PM PST 23 24422223 ps
T1585 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.93400265347288338098314344534874603727863625013897261724421109680915893201310 Nov 22 01:02:53 PM PST 23 Nov 22 01:02:56 PM PST 23 336669725 ps
T1586 /workspace/coverage/cover_reg_top/40.i2c_intr_test.70938313806981683326450693097164356894001934762049824612338442912615192947595 Nov 22 01:03:45 PM PST 23 Nov 22 01:03:46 PM PST 23 24422223 ps
T1587 /workspace/coverage/cover_reg_top/32.i2c_intr_test.53828380445207578655531060044119780342951085360561787095437355460331462458575 Nov 22 01:03:50 PM PST 23 Nov 22 01:03:53 PM PST 23 24422223 ps
T88 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.27355702358420651318978658810168895418223946707127693576103157198652505735562 Nov 22 01:03:00 PM PST 23 Nov 22 01:03:02 PM PST 23 97278783 ps
T1588 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.43822482440822266918171236191276070614836414452049842379328288199525436179983 Nov 22 01:02:51 PM PST 23 Nov 22 01:02:54 PM PST 23 114885785 ps
T1589 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.41812011804001220373418671452120850048133326537975125382364435755387657341096 Nov 22 01:03:46 PM PST 23 Nov 22 01:03:48 PM PST 23 48993455 ps
T1590 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.23487727518856174814626482956050897793854418746745532736455169780142620133031 Nov 22 01:03:08 PM PST 23 Nov 22 01:03:10 PM PST 23 33779291 ps
T1591 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.76039505959325185160026638535781394555791234808749214866726269089814128107904 Nov 22 01:02:54 PM PST 23 Nov 22 01:02:56 PM PST 23 64475474 ps
T1592 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.63985045590435792057636878540920855876061873194050612101964643419753968621523 Nov 22 01:03:10 PM PST 23 Nov 22 01:03:12 PM PST 23 33779291 ps
T1593 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.11494324840893110887246647493710682364607908228193867125619104390071314936848 Nov 22 01:01:41 PM PST 23 Nov 22 01:01:43 PM PST 23 64475474 ps
T1594 /workspace/coverage/cover_reg_top/5.i2c_intr_test.81629734859710892910326659512142343370049810766088166456957611287272437148151 Nov 22 01:03:01 PM PST 23 Nov 22 01:03:02 PM PST 23 24422223 ps
T89 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.39154893968668273880825384205127600792026051919338812977279076732131609633235 Nov 22 01:03:50 PM PST 23 Nov 22 01:03:52 PM PST 23 97278783 ps
T1595 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.96419850889939122965026889160490761092899627924813565277951787726316509153675 Nov 22 01:01:38 PM PST 23 Nov 22 01:01:40 PM PST 23 114885785 ps
T1596 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.15092490215964864023218256060798396735136703919958443165906929280710906000826 Nov 22 01:02:39 PM PST 23 Nov 22 01:02:41 PM PST 23 30047178 ps
T1597 /workspace/coverage/cover_reg_top/27.i2c_intr_test.56600574105545547101220225562687371677594244686329955831902354825045056966399 Nov 22 01:03:56 PM PST 23 Nov 22 01:03:58 PM PST 23 24422223 ps
T90 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.51190172897394155595735810245392998258317056513241928597889905099935297000100 Nov 22 01:03:04 PM PST 23 Nov 22 01:03:06 PM PST 23 97278783 ps
T1598 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.21912213814040599217880520996138610291304012167221930605878179865779837879695 Nov 22 01:03:46 PM PST 23 Nov 22 01:03:47 PM PST 23 33779291 ps
T1599 /workspace/coverage/cover_reg_top/26.i2c_intr_test.32636594868802515509588601211738774823197630624176606349048681282356159790221 Nov 22 01:03:49 PM PST 23 Nov 22 01:03:51 PM PST 23 24422223 ps
T1600 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.103690746236288054544093316088996158775042481690740665339870934756478440578996 Nov 22 01:01:41 PM PST 23 Nov 22 01:01:44 PM PST 23 336669725 ps
T1601 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.84325811898926019839133230212587412911849696822819540196871016240354295541787 Nov 22 01:01:37 PM PST 23 Nov 22 01:01:39 PM PST 23 97278783 ps
T1602 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.98398756469579679214330505956046706549892856518807044714505168264890127656135 Nov 22 01:02:28 PM PST 23 Nov 22 01:02:31 PM PST 23 48993455 ps
T1603 /workspace/coverage/cover_reg_top/47.i2c_intr_test.32827630554577558374620788968687411381889114257040728396637684957101793181341 Nov 22 01:03:43 PM PST 23 Nov 22 01:03:44 PM PST 23 24422223 ps
T1604 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.4790871706381872379537420536720114199241393436539923835157430415715749095642 Nov 22 01:02:47 PM PST 23 Nov 22 01:02:50 PM PST 23 114885785 ps
T1605 /workspace/coverage/cover_reg_top/46.i2c_intr_test.23115069750865362447405771087006295378410621800809539103731943663209588943919 Nov 22 01:03:50 PM PST 23 Nov 22 01:03:52 PM PST 23 24422223 ps
T1606 /workspace/coverage/cover_reg_top/34.i2c_intr_test.103122344272199577002954193779715903356684943519380379514842511215492086179639 Nov 22 01:03:55 PM PST 23 Nov 22 01:03:58 PM PST 23 24422223 ps
T1607 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.97523541216325804182668780517912915502039790384567804092500821911653254441918 Nov 22 01:03:08 PM PST 23 Nov 22 01:03:10 PM PST 23 48993455 ps
T1608 /workspace/coverage/cover_reg_top/28.i2c_intr_test.84955118048146715458237535011711618032775574495790907944750513959933434734821 Nov 22 01:03:49 PM PST 23 Nov 22 01:03:52 PM PST 23 24422223 ps
T1609 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.14298794635006810907453432388382474051580993965184652608023300510281887726452 Nov 22 01:03:10 PM PST 23 Nov 22 01:03:12 PM PST 23 97278783 ps
T1610 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.13496759211401441653858973122905741571013320076069480999466148410324215676737 Nov 22 01:03:48 PM PST 23 Nov 22 01:03:50 PM PST 23 28136479 ps
T1611 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.91928021815749448690412589594587818671796197901073899786427065885479968554039 Nov 22 01:02:55 PM PST 23 Nov 22 01:02:58 PM PST 23 97278783 ps
T1612 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.49327527128696032085895465736689826328226522349667139711563497918735094638889 Nov 22 01:03:04 PM PST 23 Nov 22 01:03:06 PM PST 23 114885785 ps
T1613 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.34211416672987898451363155776097568500347786759544283209174577512721671563423 Nov 22 01:03:07 PM PST 23 Nov 22 01:03:09 PM PST 23 114885785 ps
T1614 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.106706478154872221729832192726374919831946971575030028112375678628902053396190 Nov 22 01:02:49 PM PST 23 Nov 22 01:02:51 PM PST 23 28136479 ps
T1615 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.57179282726723498899468828611847387001262382374248591677337565479263263000326 Nov 22 01:02:44 PM PST 23 Nov 22 01:02:47 PM PST 23 114885785 ps
T1616 /workspace/coverage/cover_reg_top/10.i2c_intr_test.83161752718363420643144813480035665655118492655995810410553761061784546223097 Nov 22 01:03:02 PM PST 23 Nov 22 01:03:04 PM PST 23 24422223 ps
T1617 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.95016362545550485013534667225469449416353327772912966014645762104563907415010 Nov 22 01:02:41 PM PST 23 Nov 22 01:02:44 PM PST 23 64475474 ps
T1618 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.40189970085480553320964190070402890229578072994379536125727994232805241562160 Nov 22 01:02:43 PM PST 23 Nov 22 01:02:46 PM PST 23 30047178 ps
T1619 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.87310199627095132271108118157205639658537161048766410229119487068061565598719 Nov 22 01:03:15 PM PST 23 Nov 22 01:03:17 PM PST 23 48993455 ps
T1620 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.22806539284591235602812555988249020092346817282184795596792565250625887497437 Nov 22 01:02:53 PM PST 23 Nov 22 01:02:55 PM PST 23 97278783 ps
T1621 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.63103607856140513609345829196207787411151394394581750667429036378845672789036 Nov 22 01:03:42 PM PST 23 Nov 22 01:03:44 PM PST 23 48993455 ps
T1622 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.30892372442799015872965163391816242719621461489244892221036063794091572857168 Nov 22 01:02:48 PM PST 23 Nov 22 01:02:51 PM PST 23 97278783 ps
T1623 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.108650063979758821558898735277186138068987762954124841682316921527431603044650 Nov 22 01:01:53 PM PST 23 Nov 22 01:01:55 PM PST 23 97278783 ps
T1624 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.81655044451028349567469923850513444237579066967076030642035056255225769695329 Nov 22 01:02:56 PM PST 23 Nov 22 01:02:58 PM PST 23 28136479 ps
T1625 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.64540032892474616682378230923114436398801077298037661506329782703879492869488 Nov 22 01:03:50 PM PST 23 Nov 22 01:03:52 PM PST 23 97278783 ps
T1626 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.56075887547278694320177350206345035717529792509343033938153213689320427165794 Nov 22 01:02:40 PM PST 23 Nov 22 01:02:42 PM PST 23 33779291 ps
T1627 /workspace/coverage/cover_reg_top/6.i2c_intr_test.79657403574278831965359054533060736137203415617195001826263770749340195227270 Nov 22 01:03:07 PM PST 23 Nov 22 01:03:09 PM PST 23 24422223 ps
T1628 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.88844539053217035893413502713014286566431342665121121578143476319292987452330 Nov 22 01:02:48 PM PST 23 Nov 22 01:02:50 PM PST 23 28136479 ps
T1629 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.46429599490575354948659327883996638097566443850169138730014217710685752010989 Nov 22 01:03:50 PM PST 23 Nov 22 01:03:53 PM PST 23 97278783 ps
T1630 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.112361768548390198001102372835573134255952592657364224155363353975170490708042 Nov 22 01:03:00 PM PST 23 Nov 22 01:03:02 PM PST 23 28136479 ps
T1631 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.83522967338282116577408121526490919719882693004761587989249601120475045133687 Nov 22 01:03:00 PM PST 23 Nov 22 01:03:02 PM PST 23 33779291 ps
T1632 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.62225358117713277680193024223670480056910566398879682473427743389785221146840 Nov 22 01:03:49 PM PST 23 Nov 22 01:03:51 PM PST 23 33779291 ps
T1633 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.89627403301885130811531592121295214682723573865874850240128900420654850540273 Nov 22 01:02:52 PM PST 23 Nov 22 01:02:53 PM PST 23 48993455 ps
T1634 /workspace/coverage/cover_reg_top/35.i2c_intr_test.49423756454636939298828014539725053941000232202937343788333608211755210418685 Nov 22 01:03:52 PM PST 23 Nov 22 01:03:54 PM PST 23 24422223 ps
T1635 /workspace/coverage/cover_reg_top/4.i2c_intr_test.42450997748028698495829437963196556178825250692597473708879099128639528434382 Nov 22 01:02:50 PM PST 23 Nov 22 01:02:52 PM PST 23 24422223 ps
T1636 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.95853523211580501744996760447628107402986736458381231241093400174363649476258 Nov 22 01:03:08 PM PST 23 Nov 22 01:03:10 PM PST 23 28136479 ps
T1637 /workspace/coverage/cover_reg_top/1.i2c_intr_test.105067253560764698685364809958905005372328886523800513964456540644296035739212 Nov 22 01:02:40 PM PST 23 Nov 22 01:02:42 PM PST 23 24422223 ps
T1638 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.59511648968676601906403182239991602310065948506172370659982830088914921413545 Nov 22 01:03:15 PM PST 23 Nov 22 01:03:17 PM PST 23 48993455 ps
T1639 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.114773527835628304050222831989001624395991095852405107402841865905252888146187 Nov 22 01:03:07 PM PST 23 Nov 22 01:03:09 PM PST 23 114885785 ps
T1640 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4277497851842420045812720028074891224953905162945724220626676171297716347487 Nov 22 01:02:44 PM PST 23 Nov 22 01:02:47 PM PST 23 48993455 ps
T1641 /workspace/coverage/cover_reg_top/38.i2c_intr_test.48175471424283125777615984435314459106573517067235078706478351077903562706691 Nov 22 01:03:51 PM PST 23 Nov 22 01:03:54 PM PST 23 24422223 ps
T1642 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.15923676789844313180381529098491449046953602471384392786392248431975192472861 Nov 22 01:02:40 PM PST 23 Nov 22 01:02:42 PM PST 23 28136479 ps
T1643 /workspace/coverage/cover_reg_top/29.i2c_intr_test.77514067883264465884152825160389605090251894564341931379045578868113217702270 Nov 22 01:03:51 PM PST 23 Nov 22 01:03:53 PM PST 23 24422223 ps
T1644 /workspace/coverage/cover_reg_top/12.i2c_intr_test.100659693568527159679994029092209257797796421883880216190112242264565916100785 Nov 22 01:03:05 PM PST 23 Nov 22 01:03:07 PM PST 23 24422223 ps
T1645 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.90669620610093363906776910302139945070160486890533447341432584100373101998368 Nov 22 01:03:15 PM PST 23 Nov 22 01:03:18 PM PST 23 114885785 ps
T1646 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.101982850839025789972325024237207843869988701931094365063415894364671905339035 Nov 22 01:03:47 PM PST 23 Nov 22 01:03:49 PM PST 23 28136479 ps
T1647 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.31417128784614082253184741411795380665971879359857054148639074247024960913011 Nov 22 01:02:53 PM PST 23 Nov 22 01:02:55 PM PST 23 114885785 ps
T1648 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.93483622522039437947231039823680428520362689858982913717482385099965159541504 Nov 22 01:03:02 PM PST 23 Nov 22 01:03:04 PM PST 23 97278783 ps
T1649 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.93410883516989527614766902065692854795548410769688528410712690695834578913596 Nov 22 01:01:41 PM PST 23 Nov 22 01:01:43 PM PST 23 30047178 ps
T1650 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.82120893387892046284615967849771741323310654683546537667026954538751763146953 Nov 22 01:03:02 PM PST 23 Nov 22 01:03:04 PM PST 23 64475474 ps
T1651 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.73859880017432316056777855416143677501875601390963015690373287660218610513737 Nov 22 01:01:54 PM PST 23 Nov 22 01:01:56 PM PST 23 48993455 ps
T1652 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.60886560717603611427882871253397895591965294254438474565652265696252907831237 Nov 22 01:02:40 PM PST 23 Nov 22 01:02:43 PM PST 23 97278783 ps
T1653 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.34609889533738390698495984732464768089210851685748376765676061339031393550692 Nov 22 01:03:45 PM PST 23 Nov 22 01:03:47 PM PST 23 33779291 ps
T1654 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.103755608010594515730761537215475513274283673108976884010824293794620497906832 Nov 22 01:03:07 PM PST 23 Nov 22 01:03:09 PM PST 23 114885785 ps
T1655 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.21099387945517068175084874810890637916265098203888292620285267633490523842591 Nov 22 01:02:44 PM PST 23 Nov 22 01:02:48 PM PST 23 336669725 ps
T1656 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.10337112842878051882088445605186745090324190191282025464999694406765927001163 Nov 22 01:02:50 PM PST 23 Nov 22 01:02:52 PM PST 23 33779291 ps
T1657 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.86839594476578638572218063528349802868015231502625402451522128897028312597046 Nov 22 01:03:41 PM PST 23 Nov 22 01:03:43 PM PST 23 114885785 ps
T1658 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.32238160390993126342464402221001376912262351227844093571519325659852031397854 Nov 22 01:02:44 PM PST 23 Nov 22 01:02:46 PM PST 23 28136479 ps
T1659 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.19405141544106893609821982324506284107398044942802479162431613470488998963160 Nov 22 01:02:49 PM PST 23 Nov 22 01:02:52 PM PST 23 28136479 ps
T1660 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.16820383808382278046940313500911535933945737620246781210120865249465141897736 Nov 22 01:03:07 PM PST 23 Nov 22 01:03:08 PM PST 23 28136479 ps
T1661 /workspace/coverage/cover_reg_top/49.i2c_intr_test.34395744975314298591930099780075715065333334080060845992763651773429381028130 Nov 22 01:03:50 PM PST 23 Nov 22 01:03:52 PM PST 23 24422223 ps
T1662 /workspace/coverage/cover_reg_top/42.i2c_intr_test.83372388737558863964097461678280633887459377730479722029597527819116450331911 Nov 22 01:03:47 PM PST 23 Nov 22 01:03:50 PM PST 23 24422223 ps
T1663 /workspace/coverage/cover_reg_top/7.i2c_intr_test.24934215564129493125188499403793506174607917010803482108480159085036711019978 Nov 22 01:02:47 PM PST 23 Nov 22 01:02:49 PM PST 23 24422223 ps
T1664 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.103947923989448932760620955376185712356917339076667264566429565020488346664989 Nov 22 01:02:52 PM PST 23 Nov 22 01:02:54 PM PST 23 114885785 ps
T1665 /workspace/coverage/cover_reg_top/24.i2c_intr_test.4865355834807315787252762606943669273972578940314417996284784709144632913827 Nov 22 01:03:43 PM PST 23 Nov 22 01:03:45 PM PST 23 24422223 ps
T1666 /workspace/coverage/cover_reg_top/13.i2c_intr_test.100325239855341841050832580653533987798751438148798716063170342066722383771734 Nov 22 01:03:07 PM PST 23 Nov 22 01:03:09 PM PST 23 24422223 ps
T1667 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.19376280489043507779320925928762704633255494982741374743442807435054191914349 Nov 22 01:03:45 PM PST 23 Nov 22 01:03:47 PM PST 23 48993455 ps
T1668 /workspace/coverage/cover_reg_top/21.i2c_intr_test.16141857268132856749245844319931682405415341202034180646668882389718247888042 Nov 22 01:03:47 PM PST 23 Nov 22 01:03:49 PM PST 23 24422223 ps
T1669 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.92442923455117265901911514432306771271870516796866144144478765012346161961608 Nov 22 01:02:55 PM PST 23 Nov 22 01:02:58 PM PST 23 28136479 ps
T1670 /workspace/coverage/cover_reg_top/3.i2c_intr_test.82717492076125977589953868080186847351412931653424870289971035649327555947841 Nov 22 01:02:46 PM PST 23 Nov 22 01:02:49 PM PST 23 24422223 ps
T1671 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.13854330342467103463462098584786067704033862501654387575827003738186225107007 Nov 22 01:02:44 PM PST 23 Nov 22 01:02:47 PM PST 23 64475474 ps
T1672 /workspace/coverage/cover_reg_top/0.i2c_intr_test.49332284218726808366450433273346736760370211553809727022553554243303089442267 Nov 22 01:01:41 PM PST 23 Nov 22 01:01:43 PM PST 23 24422223 ps

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.46739952864349892336533390337319578340784844652178339707824289841191029803204
Short name T26
Test name
Test status
Simulation time 48993455 ps
CPU time 0.82 seconds
Started Nov 22 01:03:47 PM PST 23
Finished Nov 22 01:03:49 PM PST 23
Peak memory 202780 kb
Host smart-c65917cb-bae5-4629-9732-d598ab9880b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46739952864349892336533390337319578340784844652178339707824289841191029803204
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_outstanding.46739952864349892336533390337319578340784844652178339707824289841191029803204
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/21.i2c_host_rx_oversample.107449519808108165548537904158963843788792860419133235443729480081570569051632
Short name T4
Test name
Test status
Simulation time 3939158762 ps
CPU time 125.46 seconds
Started Nov 22 02:21:27 PM PST 23
Finished Nov 22 02:23:33 PM PST 23
Peak memory 345968 kb
Host smart-d7eac0e8-04df-49db-9495-377ff86277a9
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107449519808108165548537904158963843788792860419133235443729480081570569051632 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_rx_oversample.107449519808108165548537904158963843788792860419133235443729480081570569051632
Directory /workspace/21.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.75388401031468778231359053656900669517163345549537054893112256227749732125091
Short name T12
Test name
Test status
Simulation time 66540157934 ps
CPU time 1606.25 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:48:02 PM PST 23
Peak memory 6983308 kb
Host smart-5aa41066-be04-48b1-a30c-c69b050cd3e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75388401031468778231359053656900669517163345549537
054893112256227749732125091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_all.75388401031468778231359053656900669517
163345549537054893112256227749732125091
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.86639782591007373864612292486652498645390476626838751172422545473541918135892
Short name T28
Test name
Test status
Simulation time 24422223 ps
CPU time 0.62 seconds
Started Nov 22 01:03:08 PM PST 23
Finished Nov 22 01:03:09 PM PST 23
Peak memory 202768 kb
Host smart-78bd1008-1d6b-457f-aa03-359c1f7d8041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86639782591007373864612292486652498645390476626838751172422545473541918135892 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.i2c_intr_test.86639782591007373864612292486652498645390476626838751172422545473541918135892
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.19629058556044000190874551319273507727452424951067453569698429124665678564396
Short name T30
Test name
Test status
Simulation time 114885785 ps
CPU time 1.32 seconds
Started Nov 22 01:02:58 PM PST 23
Finished Nov 22 01:03:00 PM PST 23
Peak memory 203012 kb
Host smart-4a0abb88-2a73-4bbf-b09e-cb4e60d033dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629058556044000190874551319273507727452424951067453569698429124665678564396 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.19629058556044000190874551319273507727452424951067453569698429124665678564396
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.86857081786788154023810753061435251066600129568491988709181414941689475156244
Short name T32
Test name
Test status
Simulation time 97278783 ps
CPU time 1.41 seconds
Started Nov 22 01:03:49 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 203000 kb
Host smart-3689a107-abf6-460c-8788-da49d31d9461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86857081786788154023810753061435251066600129568491988709181414941689475156244 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.i2c_tl_errors.86857081786788154023810753061435251066600129568491988709181414941689475156244
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.83436687373893347957025150983749513461386332453043500736708941455120914513282
Short name T54
Test name
Test status
Simulation time 32807463528 ps
CPU time 1083.43 seconds
Started Nov 22 02:37:37 PM PST 23
Finished Nov 22 02:55:41 PM PST 23
Peak memory 1957072 kb
Host smart-ab27b22c-a847-424a-acc6-6546a32f16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83436687373893347957025150983749513461386332453043500736708941455120914513282 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_host_stress_all.83436687373893347957025150983749513461386332453043500736708941455120914513282
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_override.25275406214749576294043326345755556224330923414830186538828205029558371843843
Short name T281
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:20:29 PM PST 23
Finished Nov 22 02:20:30 PM PST 23
Peak memory 202852 kb
Host smart-b0ea6b08-8978-4b3c-9d9b-da24c6c51729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25275406214749576294043326345755556224330923414830186538828205029558371843843 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_host_override.25275406214749576294043326345755556224330923414830186538828205029558371843843
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.105649725708160498090859928432930251391623500467989800081563863431079303406238
Short name T15
Test name
Test status
Simulation time 7925734012 ps
CPU time 245.71 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:26:17 PM PST 23
Peak memory 1271524 kb
Host smart-6b0f467f-6b2f-4a5c-bdd7-c91a41666a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105649725708160498090859928432930251391623500467989800081563863431079303406238 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.i2c_host_fifo_overflow.105649725708160498090859928432930251391623500467989800081563863431079303406238
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.29252051190289394936650980530580445289517510678752941948386444577591279914342
Short name T39
Test name
Test status
Simulation time 62618346 ps
CPU time 0.88 seconds
Started Nov 22 02:18:06 PM PST 23
Finished Nov 22 02:18:07 PM PST 23
Peak memory 219952 kb
Host smart-a47e9322-1687-4cf4-8925-2c18ccabf162
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29252051190289394936650980530580445289517510678752941948386444577591279914342 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_sec_cm.29252051190289394936650980530580445289517510678752941948386444577591279914342
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.78965506719259910728118164885970527169731836384616232690654291989554149719275
Short name T67
Test name
Test status
Simulation time 1417071796 ps
CPU time 3.98 seconds
Started Nov 22 02:17:18 PM PST 23
Finished Nov 22 02:17:23 PM PST 23
Peak memory 203292 kb
Host smart-543153f3-ecb5-40b3-8020-1a6d32c391c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78965506719259910728118164885970527169731836384616232690654291989554149719275 -assert nop
ostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.78965506719259910728118164885970527169731836384616232690654291989554149719275
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.103538993142427349873455843448818029601356564045089016534909301710923994904919
Short name T29
Test name
Test status
Simulation time 33779291 ps
CPU time 0.75 seconds
Started Nov 22 01:01:35 PM PST 23
Finished Nov 22 01:01:37 PM PST 23
Peak memory 202920 kb
Host smart-5d64a05c-04a5-45e1-904b-68485cd1836a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035389931424273498734558434488180296013565
64045089016534909301710923994904919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.103538993142427349873455843
448818029601356564045089016534909301710923994904919
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.86990612965355529980646797618830963495931796526717365314047002402242052184471
Short name T57
Test name
Test status
Simulation time 3754070957 ps
CPU time 53.49 seconds
Started Nov 22 02:21:11 PM PST 23
Finished Nov 22 02:22:06 PM PST 23
Peak memory 293772 kb
Host smart-6e79e7c9-7520-465c-934d-4f9a71d4a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86990612965355529980646797618830963495931796526717365314047002402242052184471 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_host_mode_toggle.86990612965355529980646797618830963495931796526717365314047002402242052184471
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_perf.61078387869687322328188250875382815407586406224611222774818088431990212090726
Short name T207
Test name
Test status
Simulation time 6830796343 ps
CPU time 63.31 seconds
Started Nov 22 02:19:53 PM PST 23
Finished Nov 22 02:20:57 PM PST 23
Peak memory 211308 kb
Host smart-67dfedab-61f3-43e0-8be0-d2d727a7f6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61078387869687322328188250875382815407586406224611222774818088431990212090726 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.i2c_host_perf.61078387869687322328188250875382815407586406224611222774818088431990212090726
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_target_tx_ovf.36394429573567007030922612755164348918484448752936729548202499865675381595592
Short name T18
Test name
Test status
Simulation time 5445414553 ps
CPU time 141.05 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:24:34 PM PST 23
Peak memory 406812 kb
Host smart-6351df4a-998b-41e6-b0ec-b13561f95bf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36394429573567007030922612755164348918484448752936
729548202499865675381595592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_tx_ovf.3639442957356700703092261275516434891848444875
2936729548202499865675381595592
Directory /workspace/26.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.59300529105701765945997840838052344951237024990953230321166871863688629462229
Short name T292
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.75 seconds
Started Nov 22 02:20:05 PM PST 23
Finished Nov 22 02:20:10 PM PST 23
Peak memory 202960 kb
Host smart-87237ef4-8622-4b6d-95c5-e6649960d7a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5930052910570176594599784083805
2344951237024990953230321166871863688629462229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.59300529105701765945997840
838052344951237024990953230321166871863688629462229
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.25579034510241233767932419263303325817714588058518077429154020683107529509404
Short name T417
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:20:54 PM PST 23
Finished Nov 22 02:20:56 PM PST 23
Peak memory 203052 kb
Host smart-e6cc33b3-e296-4fc0-8191-a8cb04c8a6c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25579034510241233767932419263303325817714588058518077429154020683107529509404 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.25579034510241233767932419263303325817714588058518077429154020683107529509404
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.10117143501534438764910928537319227400285838248199026355086483708075937294988
Short name T36
Test name
Test status
Simulation time 28136479 ps
CPU time 0.65 seconds
Started Nov 22 01:01:41 PM PST 23
Finished Nov 22 01:01:43 PM PST 23
Peak memory 202740 kb
Host smart-eaac4b56-50e2-4768-8e2f-6b83f7d497c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10117143501534438764910928537319227400285838248199026355086483708075937294988 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.10117143501534438764910928537319227400285838248199026355086483708075937294988
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/default/11.i2c_alert_test.103356070198035900163712171167784764534308967840954462840124944520256633924544
Short name T177
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:20:10 PM PST 23
Finished Nov 22 02:20:11 PM PST 23
Peak memory 202656 kb
Host smart-701d5215-ddfc-4b5e-821d-6482623b434e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103356070198035900163712171167784764534308967840954462840124944520256633924544 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_alert_test.103356070198035900163712171167784764534308967840954462840124944520256633924544
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.85961216465471895713300488302327528666528872678278019681920858957268092271182
Short name T99
Test name
Test status
Simulation time 236313385 ps
CPU time 3.84 seconds
Started Nov 22 02:19:17 PM PST 23
Finished Nov 22 02:19:22 PM PST 23
Peak memory 225476 kb
Host smart-097ec763-df94-48bf-890f-bb253e6a5b3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85961216465471895713300488302327528666528872678278019681920858957268092271182 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.85961216465471895713300488302327528666528872678278019681920858957268092271182
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.47643450400962185798473186184175996539531051362431306103193086706408643942878
Short name T159
Test name
Test status
Simulation time 10065199023 ps
CPU time 41.33 seconds
Started Nov 22 02:20:51 PM PST 23
Finished Nov 22 02:21:33 PM PST 23
Peak memory 462068 kb
Host smart-7e037b57-92ff-4b91-8c33-f6b7467e2f60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476434504009621857984731861841759965395310513624313
06103193086706408643942878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_tx.476434504009621857984731861841759
96539531051362431306103193086706408643942878
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.11494324840893110887246647493710682364607908228193867125619104390071314936848
Short name T1593
Test name
Test status
Simulation time 64475474 ps
CPU time 0.98 seconds
Started Nov 22 01:01:41 PM PST 23
Finished Nov 22 01:01:43 PM PST 23
Peak memory 202740 kb
Host smart-cdee70a4-c4d2-46c2-8a3c-d4f7d6359aea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11494324840893110887246647493710682364607908228193867125619104390071314936848 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.11494324840893110887246647493710682364607908228193867125619104390071314936848
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.103690746236288054544093316088996158775042481690740665339870934756478440578996
Short name T1600
Test name
Test status
Simulation time 336669725 ps
CPU time 2.39 seconds
Started Nov 22 01:01:41 PM PST 23
Finished Nov 22 01:01:44 PM PST 23
Peak memory 202852 kb
Host smart-c91e6064-d77a-4167-b0d0-0104a4a096d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103690746236288054544093316088996158775042481690740665339870934756478440578996 -assert nop
ostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.103690746236288054544093316088996158775042481690740665339870934756478440578996
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.93410883516989527614766902065692854795548410769688528410712690695834578913596
Short name T1649
Test name
Test status
Simulation time 30047178 ps
CPU time 0.69 seconds
Started Nov 22 01:01:41 PM PST 23
Finished Nov 22 01:01:43 PM PST 23
Peak memory 202692 kb
Host smart-a4f4572d-888d-4521-b71f-71666e7d3356
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93410883516989527614766902065692854795548410769688528410712690695834578913596 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.93410883516989527614766902065692854795548410769688528410712690695834578913596
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.49332284218726808366450433273346736760370211553809727022553554243303089442267
Short name T1672
Test name
Test status
Simulation time 24422223 ps
CPU time 0.66 seconds
Started Nov 22 01:01:41 PM PST 23
Finished Nov 22 01:01:43 PM PST 23
Peak memory 202756 kb
Host smart-e5db0507-400a-49a4-ac49-be0b1847c113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49332284218726808366450433273346736760370211553809727022553554243303089442267 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.i2c_intr_test.49332284218726808366450433273346736760370211553809727022553554243303089442267
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.73859880017432316056777855416143677501875601390963015690373287660218610513737
Short name T1651
Test name
Test status
Simulation time 48993455 ps
CPU time 0.82 seconds
Started Nov 22 01:01:54 PM PST 23
Finished Nov 22 01:01:56 PM PST 23
Peak memory 202812 kb
Host smart-293f2a6c-7de3-4317-aedb-f8fc9a06b4c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73859880017432316056777855416143677501875601390963015690373287660218610513737
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outstanding.73859880017432316056777855416143677501875601390963015690373287660218610513737
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.84325811898926019839133230212587412911849696822819540196871016240354295541787
Short name T1601
Test name
Test status
Simulation time 97278783 ps
CPU time 1.32 seconds
Started Nov 22 01:01:37 PM PST 23
Finished Nov 22 01:01:39 PM PST 23
Peak memory 203044 kb
Host smart-b73b26f4-05b9-4801-94e7-afa2bc3b3edd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84325811898926019839133230212587412911849696822819540196871016240354295541787 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.i2c_tl_errors.84325811898926019839133230212587412911849696822819540196871016240354295541787
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.96419850889939122965026889160490761092899627924813565277951787726316509153675
Short name T1595
Test name
Test status
Simulation time 114885785 ps
CPU time 1.34 seconds
Started Nov 22 01:01:38 PM PST 23
Finished Nov 22 01:01:40 PM PST 23
Peak memory 203040 kb
Host smart-446f2039-9996-42d1-87cc-dd32c82a199a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96419850889939122965026889160490761092899627924813565277951787726316509153675 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.96419850889939122965026889160490761092899627924813565277951787726316509153675
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.95016362545550485013534667225469449416353327772912966014645762104563907415010
Short name T1617
Test name
Test status
Simulation time 64475474 ps
CPU time 0.96 seconds
Started Nov 22 01:02:41 PM PST 23
Finished Nov 22 01:02:44 PM PST 23
Peak memory 202812 kb
Host smart-2c19cb07-f9c1-4e31-8a7a-689eaf5f3ddc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95016362545550485013534667225469449416353327772912966014645762104563907415010 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.95016362545550485013534667225469449416353327772912966014645762104563907415010
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.89228922592396428455960947179832981212223211958308554168726660698829055734955
Short name T52
Test name
Test status
Simulation time 336669725 ps
CPU time 2.47 seconds
Started Nov 22 01:02:41 PM PST 23
Finished Nov 22 01:02:46 PM PST 23
Peak memory 203004 kb
Host smart-1b15c946-ae24-4e1d-be44-1425fa935fe0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89228922592396428455960947179832981212223211958308554168726660698829055734955 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.89228922592396428455960947179832981212223211958308554168726660698829055734955
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4425310642207328071313547854216436095178681175137074217101411530238600647178
Short name T69
Test name
Test status
Simulation time 30047178 ps
CPU time 0.72 seconds
Started Nov 22 01:02:32 PM PST 23
Finished Nov 22 01:02:33 PM PST 23
Peak memory 202848 kb
Host smart-0ab7650b-df77-4e80-86d2-2ecf5a0baf55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4425310642207328071313547854216436095178681175137074217101411530238600647178 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.4425310642207328071313547854216436095178681175137074217101411530238600647178
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.56075887547278694320177350206345035717529792509343033938153213689320427165794
Short name T1626
Test name
Test status
Simulation time 33779291 ps
CPU time 0.76 seconds
Started Nov 22 01:02:40 PM PST 23
Finished Nov 22 01:02:42 PM PST 23
Peak memory 202636 kb
Host smart-d7f15d03-b7d2-4ddd-b70e-ad9d71026f84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5607588754727869432017735020634503571752979
2509343033938153213689320427165794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.5607588754727869432017735020
6345035717529792509343033938153213689320427165794
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.16139711133302342350186290846426844521733061404480728647855648587206453339321
Short name T37
Test name
Test status
Simulation time 28136479 ps
CPU time 0.64 seconds
Started Nov 22 01:02:39 PM PST 23
Finished Nov 22 01:02:40 PM PST 23
Peak memory 202740 kb
Host smart-007a8471-0f62-4d5c-8887-24fdc978d074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16139711133302342350186290846426844521733061404480728647855648587206453339321 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.16139711133302342350186290846426844521733061404480728647855648587206453339321
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.105067253560764698685364809958905005372328886523800513964456540644296035739212
Short name T1637
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:02:40 PM PST 23
Finished Nov 22 01:02:42 PM PST 23
Peak memory 202732 kb
Host smart-7b101ac8-af3d-49dc-b94c-960e50458cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105067253560764698685364809958905005372328886523800513964456540644296035739212 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.i2c_intr_test.105067253560764698685364809958905005372328886523800513964456540644296035739212
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.98398756469579679214330505956046706549892856518807044714505168264890127656135
Short name T1602
Test name
Test status
Simulation time 48993455 ps
CPU time 0.86 seconds
Started Nov 22 01:02:28 PM PST 23
Finished Nov 22 01:02:31 PM PST 23
Peak memory 202828 kb
Host smart-e0812505-e463-4c3f-81dc-abd9b232a320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98398756469579679214330505956046706549892856518807044714505168264890127656135
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outstanding.98398756469579679214330505956046706549892856518807044714505168264890127656135
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.108650063979758821558898735277186138068987762954124841682316921527431603044650
Short name T1623
Test name
Test status
Simulation time 97278783 ps
CPU time 1.28 seconds
Started Nov 22 01:01:53 PM PST 23
Finished Nov 22 01:01:55 PM PST 23
Peak memory 203068 kb
Host smart-66e87299-4e45-4dbd-bb9a-3f12fbf170d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108650063979758821558898735277186138068987762954124841682316921527431603044650 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.i2c_tl_errors.108650063979758821558898735277186138068987762954124841682316921527431603044650
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.103947923989448932760620955376185712356917339076667264566429565020488346664989
Short name T1664
Test name
Test status
Simulation time 114885785 ps
CPU time 1.29 seconds
Started Nov 22 01:02:52 PM PST 23
Finished Nov 22 01:02:54 PM PST 23
Peak memory 203016 kb
Host smart-8e22aa3d-7149-49e0-9004-2192c18996a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103947923989448932760620955376185712356917339076667264566429565020488346664989 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.103947923989448932760620955376185712356917339076667264566429565020488346664989
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.8087713713254000717911558166062325010673419566281365494206906411049829885277
Short name T129
Test name
Test status
Simulation time 33779291 ps
CPU time 0.74 seconds
Started Nov 22 01:03:03 PM PST 23
Finished Nov 22 01:03:04 PM PST 23
Peak memory 202904 kb
Host smart-f26729b2-19da-482b-a8ef-88ffe31ff6a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8087713713254000717911558166062325010673419
566281365494206906411049829885277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.8087713713254000717911558166
062325010673419566281365494206906411049829885277
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.95853523211580501744996760447628107402986736458381231241093400174363649476258
Short name T1636
Test name
Test status
Simulation time 28136479 ps
CPU time 0.69 seconds
Started Nov 22 01:03:08 PM PST 23
Finished Nov 22 01:03:10 PM PST 23
Peak memory 202048 kb
Host smart-9351b5dc-90aa-4d9d-8ee0-03573725750b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95853523211580501744996760447628107402986736458381231241093400174363649476258 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.95853523211580501744996760447628107402986736458381231241093400174363649476258
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.83161752718363420643144813480035665655118492655995810410553761061784546223097
Short name T1616
Test name
Test status
Simulation time 24422223 ps
CPU time 0.63 seconds
Started Nov 22 01:03:02 PM PST 23
Finished Nov 22 01:03:04 PM PST 23
Peak memory 202776 kb
Host smart-9c7af8cb-71de-4cfe-8f83-539e517af0fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83161752718363420643144813480035665655118492655995810410553761061784546223097 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.i2c_intr_test.83161752718363420643144813480035665655118492655995810410553761061784546223097
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.87310199627095132271108118157205639658537161048766410229119487068061565598719
Short name T1619
Test name
Test status
Simulation time 48993455 ps
CPU time 0.92 seconds
Started Nov 22 01:03:15 PM PST 23
Finished Nov 22 01:03:17 PM PST 23
Peak memory 202716 kb
Host smart-65685884-3d21-40bb-8346-7020927307e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87310199627095132271108118157205639658537161048766410229119487068061565598719
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outstanding.87310199627095132271108118157205639658537161048766410229119487068061565598719
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.27355702358420651318978658810168895418223946707127693576103157198652505735562
Short name T88
Test name
Test status
Simulation time 97278783 ps
CPU time 1.29 seconds
Started Nov 22 01:03:00 PM PST 23
Finished Nov 22 01:03:02 PM PST 23
Peak memory 203116 kb
Host smart-782b1f77-ab95-4edf-bdb9-4401639d066d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27355702358420651318978658810168895418223946707127693576103157198652505735562 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.i2c_tl_errors.27355702358420651318978658810168895418223946707127693576103157198652505735562
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.90669620610093363906776910302139945070160486890533447341432584100373101998368
Short name T1645
Test name
Test status
Simulation time 114885785 ps
CPU time 1.38 seconds
Started Nov 22 01:03:15 PM PST 23
Finished Nov 22 01:03:18 PM PST 23
Peak memory 202972 kb
Host smart-92167911-b353-4595-85ba-2a0d3ee92d60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90669620610093363906776910302139945070160486890533447341432584100373101998368 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.90669620610093363906776910302139945070160486890533447341432584100373101998368
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.23487727518856174814626482956050897793854418746745532736455169780142620133031
Short name T1590
Test name
Test status
Simulation time 33779291 ps
CPU time 0.78 seconds
Started Nov 22 01:03:08 PM PST 23
Finished Nov 22 01:03:10 PM PST 23
Peak memory 201996 kb
Host smart-ff229c15-eb44-45c2-8cef-5017e823db27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348772751885617481462648295605089779385441
8746745532736455169780142620133031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.234877275188561748146264829
56050897793854418746745532736455169780142620133031
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.84733396851217515044886183153282341117045189281187529199629629235966911864762
Short name T113
Test name
Test status
Simulation time 28136479 ps
CPU time 0.64 seconds
Started Nov 22 01:03:06 PM PST 23
Finished Nov 22 01:03:08 PM PST 23
Peak memory 202752 kb
Host smart-5f54791d-a462-4a86-9271-e3e158d9189b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84733396851217515044886183153282341117045189281187529199629629235966911864762 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.84733396851217515044886183153282341117045189281187529199629629235966911864762
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.97523541216325804182668780517912915502039790384567804092500821911653254441918
Short name T1607
Test name
Test status
Simulation time 48993455 ps
CPU time 0.82 seconds
Started Nov 22 01:03:08 PM PST 23
Finished Nov 22 01:03:10 PM PST 23
Peak memory 202736 kb
Host smart-88000368-36ff-4f6f-9079-d610534f0bf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97523541216325804182668780517912915502039790384567804092500821911653254441918
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_outstanding.97523541216325804182668780517912915502039790384567804092500821911653254441918
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.51190172897394155595735810245392998258317056513241928597889905099935297000100
Short name T90
Test name
Test status
Simulation time 97278783 ps
CPU time 1.33 seconds
Started Nov 22 01:03:04 PM PST 23
Finished Nov 22 01:03:06 PM PST 23
Peak memory 203080 kb
Host smart-13ec3630-efe7-440e-acff-445a33cd1ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51190172897394155595735810245392998258317056513241928597889905099935297000100 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.i2c_tl_errors.51190172897394155595735810245392998258317056513241928597889905099935297000100
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.49327527128696032085895465736689826328226522349667139711563497918735094638889
Short name T1612
Test name
Test status
Simulation time 114885785 ps
CPU time 1.32 seconds
Started Nov 22 01:03:04 PM PST 23
Finished Nov 22 01:03:06 PM PST 23
Peak memory 202956 kb
Host smart-88ade31c-8ed7-4083-8832-d1a4221d1ace
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49327527128696032085895465736689826328226522349667139711563497918735094638889 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.49327527128696032085895465736689826328226522349667139711563497918735094638889
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.92925334259991613589534022106284688873575421154529960327097834555874666548876
Short name T78
Test name
Test status
Simulation time 33779291 ps
CPU time 0.73 seconds
Started Nov 22 01:02:57 PM PST 23
Finished Nov 22 01:02:59 PM PST 23
Peak memory 202908 kb
Host smart-863dd7fb-5c34-4dc4-b5ba-f284f4b43022
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9292533425999161358953402210628468887357542
1154529960327097834555874666548876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.929253342599916135895340221
06284688873575421154529960327097834555874666548876
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.105455119801758232808145341624808628422778433640045522430541223610933425695260
Short name T38
Test name
Test status
Simulation time 28136479 ps
CPU time 0.67 seconds
Started Nov 22 01:03:05 PM PST 23
Finished Nov 22 01:03:07 PM PST 23
Peak memory 202664 kb
Host smart-5cd4a92a-79b7-4d51-aefc-41733f0abf1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105455119801758232808145341624808628422778433640045522430541223610933425695260 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.105455119801758232808145341624808628422778433640045522430541223610933425695260
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.100659693568527159679994029092209257797796421883880216190112242264565916100785
Short name T1644
Test name
Test status
Simulation time 24422223 ps
CPU time 0.65 seconds
Started Nov 22 01:03:05 PM PST 23
Finished Nov 22 01:03:07 PM PST 23
Peak memory 202760 kb
Host smart-e91a2293-8319-4e78-9f92-a1fa1c51ba1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100659693568527159679994029092209257797796421883880216190112242264565916100785 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.i2c_intr_test.100659693568527159679994029092209257797796421883880216190112242264565916100785
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.59511648968676601906403182239991602310065948506172370659982830088914921413545
Short name T1638
Test name
Test status
Simulation time 48993455 ps
CPU time 0.83 seconds
Started Nov 22 01:03:15 PM PST 23
Finished Nov 22 01:03:17 PM PST 23
Peak memory 202784 kb
Host smart-b19319f7-f7cd-4a9c-8775-89d48b625f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59511648968676601906403182239991602310065948506172370659982830088914921413545
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outstanding.59511648968676601906403182239991602310065948506172370659982830088914921413545
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.14298794635006810907453432388382474051580993965184652608023300510281887726452
Short name T1609
Test name
Test status
Simulation time 97278783 ps
CPU time 1.25 seconds
Started Nov 22 01:03:10 PM PST 23
Finished Nov 22 01:03:12 PM PST 23
Peak memory 202960 kb
Host smart-15e80e58-2f95-41a0-9014-8ddfe4d3e472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14298794635006810907453432388382474051580993965184652608023300510281887726452 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.i2c_tl_errors.14298794635006810907453432388382474051580993965184652608023300510281887726452
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.63985045590435792057636878540920855876061873194050612101964643419753968621523
Short name T1592
Test name
Test status
Simulation time 33779291 ps
CPU time 0.71 seconds
Started Nov 22 01:03:10 PM PST 23
Finished Nov 22 01:03:12 PM PST 23
Peak memory 202884 kb
Host smart-659218a7-5f9a-45a9-9eb2-69b3730ccf4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6398504559043579205763687854092085587606187
3194050612101964643419753968621523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.639850455904357920576368785
40920855876061873194050612101964643419753968621523
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.16820383808382278046940313500911535933945737620246781210120865249465141897736
Short name T1660
Test name
Test status
Simulation time 28136479 ps
CPU time 0.69 seconds
Started Nov 22 01:03:07 PM PST 23
Finished Nov 22 01:03:08 PM PST 23
Peak memory 202748 kb
Host smart-96d35e8b-c764-43ab-b9c7-d5afa031bdcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16820383808382278046940313500911535933945737620246781210120865249465141897736 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.16820383808382278046940313500911535933945737620246781210120865249465141897736
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.100325239855341841050832580653533987798751438148798716063170342066722383771734
Short name T1666
Test name
Test status
Simulation time 24422223 ps
CPU time 0.67 seconds
Started Nov 22 01:03:07 PM PST 23
Finished Nov 22 01:03:09 PM PST 23
Peak memory 202828 kb
Host smart-6baf7da7-a019-4ce3-b7e8-b374445c4fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100325239855341841050832580653533987798751438148798716063170342066722383771734 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.i2c_intr_test.100325239855341841050832580653533987798751438148798716063170342066722383771734
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.22112809441422771667484104662354161245857967325968536363826214927130166767405
Short name T53
Test name
Test status
Simulation time 48993455 ps
CPU time 0.81 seconds
Started Nov 22 01:03:12 PM PST 23
Finished Nov 22 01:03:14 PM PST 23
Peak memory 202784 kb
Host smart-50f20b16-3380-4522-9d0a-9467d63f3c6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22112809441422771667484104662354161245857967325968536363826214927130166767405
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_outstanding.22112809441422771667484104662354161245857967325968536363826214927130166767405
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.275403314364209567721246707119654798951221476149666098015250098229653527251
Short name T87
Test name
Test status
Simulation time 97278783 ps
CPU time 1.33 seconds
Started Nov 22 01:03:15 PM PST 23
Finished Nov 22 01:03:17 PM PST 23
Peak memory 203056 kb
Host smart-bf876603-ccef-4d8b-9e9a-eaa48e8b3209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275403314364209567721246707119654798951221476149666098015250098229653527251 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.i2c_tl_errors.275403314364209567721246707119654798951221476149666098015250098229653527251
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.34211416672987898451363155776097568500347786759544283209174577512721671563423
Short name T1613
Test name
Test status
Simulation time 114885785 ps
CPU time 1.32 seconds
Started Nov 22 01:03:07 PM PST 23
Finished Nov 22 01:03:09 PM PST 23
Peak memory 202820 kb
Host smart-1dfbb875-0918-4fcc-958b-c844a12d809a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34211416672987898451363155776097568500347786759544283209174577512721671563423 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.34211416672987898451363155776097568500347786759544283209174577512721671563423
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.21912213814040599217880520996138610291304012167221930605878179865779837879695
Short name T1598
Test name
Test status
Simulation time 33779291 ps
CPU time 0.74 seconds
Started Nov 22 01:03:46 PM PST 23
Finished Nov 22 01:03:47 PM PST 23
Peak memory 202948 kb
Host smart-ca81405b-5210-4b48-90b3-8a0360712700
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191221381404059921788052099613861029130401
2167221930605878179865779837879695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.219122138140405992178805209
96138610291304012167221930605878179865779837879695
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.52175216614952995723252133411129567899094207955053982177036206042213097622407
Short name T110
Test name
Test status
Simulation time 28136479 ps
CPU time 0.66 seconds
Started Nov 22 01:03:08 PM PST 23
Finished Nov 22 01:03:10 PM PST 23
Peak memory 202676 kb
Host smart-dc5a0003-3c60-4a15-93b0-ef7eb9530110
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52175216614952995723252133411129567899094207955053982177036206042213097622407 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.52175216614952995723252133411129567899094207955053982177036206042213097622407
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.25603673982243776701882899580970877027582565761013260143992193612068655539898
Short name T84
Test name
Test status
Simulation time 24422223 ps
CPU time 0.63 seconds
Started Nov 22 01:03:09 PM PST 23
Finished Nov 22 01:03:11 PM PST 23
Peak memory 202828 kb
Host smart-ee592453-444f-4c71-b942-3cfa480b9c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25603673982243776701882899580970877027582565761013260143992193612068655539898 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.i2c_intr_test.25603673982243776701882899580970877027582565761013260143992193612068655539898
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.55613691564370841511440147750727776952248551070853981746008386840211396442312
Short name T94
Test name
Test status
Simulation time 48993455 ps
CPU time 0.79 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202784 kb
Host smart-262586f2-3141-48bf-bce5-df3909b7b109
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55613691564370841511440147750727776952248551070853981746008386840211396442312
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_outstanding.55613691564370841511440147750727776952248551070853981746008386840211396442312
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.78092954056262999319154690501623491519138765191178324567280203069873038262541
Short name T85
Test name
Test status
Simulation time 97278783 ps
CPU time 1.28 seconds
Started Nov 22 01:03:10 PM PST 23
Finished Nov 22 01:03:12 PM PST 23
Peak memory 202936 kb
Host smart-ebf62216-bac8-4a22-8407-ba816982a250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78092954056262999319154690501623491519138765191178324567280203069873038262541 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.i2c_tl_errors.78092954056262999319154690501623491519138765191178324567280203069873038262541
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.103755608010594515730761537215475513274283673108976884010824293794620497906832
Short name T1654
Test name
Test status
Simulation time 114885785 ps
CPU time 1.33 seconds
Started Nov 22 01:03:07 PM PST 23
Finished Nov 22 01:03:09 PM PST 23
Peak memory 202948 kb
Host smart-e87ff3e2-fadc-423e-abad-d488954f1d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103755608010594515730761537215475513274283673108976884010824293794620497906832 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.103755608010594515730761537215475513274283673108976884010824293794620497906832
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.22800401047037697458416510111608386433586095649113731525282652490835823377572
Short name T117
Test name
Test status
Simulation time 33779291 ps
CPU time 0.74 seconds
Started Nov 22 01:03:43 PM PST 23
Finished Nov 22 01:03:45 PM PST 23
Peak memory 202900 kb
Host smart-d7cbb7fd-f5a2-4ed2-b392-354cae003b0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280040104703769745841651011160838643358609
5649113731525282652490835823377572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.228004010470376974584165101
11608386433586095649113731525282652490835823377572
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.101982850839025789972325024237207843869988701931094365063415894364671905339035
Short name T1646
Test name
Test status
Simulation time 28136479 ps
CPU time 0.66 seconds
Started Nov 22 01:03:47 PM PST 23
Finished Nov 22 01:03:49 PM PST 23
Peak memory 201808 kb
Host smart-d8eee59f-af43-4883-b985-5c06028a3872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101982850839025789972325024237207843869988701931094365063415894364671905339035 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.101982850839025789972325024237207843869988701931094365063415894364671905339035
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.31546576145135511160609994837740592797893169874924884399133331003727657113741
Short name T126
Test name
Test status
Simulation time 24422223 ps
CPU time 0.62 seconds
Started Nov 22 01:03:46 PM PST 23
Finished Nov 22 01:03:47 PM PST 23
Peak memory 202776 kb
Host smart-20884ae6-ea08-4a5f-9b11-c982fde37bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31546576145135511160609994837740592797893169874924884399133331003727657113741 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.i2c_intr_test.31546576145135511160609994837740592797893169874924884399133331003727657113741
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.63103607856140513609345829196207787411151394394581750667429036378845672789036
Short name T1621
Test name
Test status
Simulation time 48993455 ps
CPU time 0.85 seconds
Started Nov 22 01:03:42 PM PST 23
Finished Nov 22 01:03:44 PM PST 23
Peak memory 202720 kb
Host smart-2523989a-fda4-4861-a3ce-312466556e54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63103607856140513609345829196207787411151394394581750667429036378845672789036
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_outstanding.63103607856140513609345829196207787411151394394581750667429036378845672789036
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.86839594476578638572218063528349802868015231502625402451522128897028312597046
Short name T1657
Test name
Test status
Simulation time 114885785 ps
CPU time 1.3 seconds
Started Nov 22 01:03:41 PM PST 23
Finished Nov 22 01:03:43 PM PST 23
Peak memory 203056 kb
Host smart-e4b3f2e2-b5f7-4134-a4d2-b82f022c1df5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86839594476578638572218063528349802868015231502625402451522128897028312597046 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.86839594476578638572218063528349802868015231502625402451522128897028312597046
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.55323096550702284971090381793930559986805375890210970904075440712399403385445
Short name T116
Test name
Test status
Simulation time 33779291 ps
CPU time 0.77 seconds
Started Nov 22 01:03:42 PM PST 23
Finished Nov 22 01:03:43 PM PST 23
Peak memory 202896 kb
Host smart-3e6a397d-cd54-48a2-9e41-a5d1e5f91be6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5532309655070228497109038179393055998680537
5890210970904075440712399403385445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.553230965507022849710903817
93930559986805375890210970904075440712399403385445
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.34443682801484983161001100752512614858459085372665902768215967796235363156059
Short name T122
Test name
Test status
Simulation time 28136479 ps
CPU time 0.64 seconds
Started Nov 22 01:03:56 PM PST 23
Finished Nov 22 01:03:58 PM PST 23
Peak memory 202748 kb
Host smart-26f06ee5-11cb-4dce-9de4-04114740144f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34443682801484983161001100752512614858459085372665902768215967796235363156059 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.34443682801484983161001100752512614858459085372665902768215967796235363156059
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.15578695042866623221536586170116686827459464340700126598389878895054618573610
Short name T140
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:03:47 PM PST 23
Finished Nov 22 01:03:49 PM PST 23
Peak memory 202852 kb
Host smart-515d6a79-b206-4853-9bb3-d0094d4cd600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15578695042866623221536586170116686827459464340700126598389878895054618573610 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.i2c_intr_test.15578695042866623221536586170116686827459464340700126598389878895054618573610
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.29060440222027705382916355829652401711849607484588600715023080752653719360067
Short name T34
Test name
Test status
Simulation time 48993455 ps
CPU time 0.79 seconds
Started Nov 22 01:03:51 PM PST 23
Finished Nov 22 01:03:53 PM PST 23
Peak memory 202784 kb
Host smart-5e87589a-fdab-4acb-95d0-0836ae0a15eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29060440222027705382916355829652401711849607484588600715023080752653719360067
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_outstanding.29060440222027705382916355829652401711849607484588600715023080752653719360067
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.39154893968668273880825384205127600792026051919338812977279076732131609633235
Short name T89
Test name
Test status
Simulation time 97278783 ps
CPU time 1.34 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202996 kb
Host smart-9fb2e44b-d4ab-4bd2-8d90-a447fce57fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154893968668273880825384205127600792026051919338812977279076732131609633235 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.i2c_tl_errors.39154893968668273880825384205127600792026051919338812977279076732131609633235
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.51549013345973508346760368277004950219136187801548773883338063431851133349895
Short name T141
Test name
Test status
Simulation time 114885785 ps
CPU time 1.32 seconds
Started Nov 22 01:03:47 PM PST 23
Finished Nov 22 01:03:50 PM PST 23
Peak memory 203036 kb
Host smart-21605cea-f784-4cc1-aafe-b6f052381ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51549013345973508346760368277004950219136187801548773883338063431851133349895 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.51549013345973508346760368277004950219136187801548773883338063431851133349895
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.74668799772292610944158688834532819850469148206772834362296263311956890439943
Short name T121
Test name
Test status
Simulation time 33779291 ps
CPU time 0.76 seconds
Started Nov 22 01:03:45 PM PST 23
Finished Nov 22 01:03:46 PM PST 23
Peak memory 202908 kb
Host smart-56d3ee3f-334d-4e13-b5ba-7927487dc839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7466879977229261094415868883453281985046914
8206772834362296263311956890439943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.746687997722926109441586888
34532819850469148206772834362296263311956890439943
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.62281600814644780083279936214011884609603143792237658133713438694943417419026
Short name T112
Test name
Test status
Simulation time 28136479 ps
CPU time 0.66 seconds
Started Nov 22 01:03:48 PM PST 23
Finished Nov 22 01:03:51 PM PST 23
Peak memory 202668 kb
Host smart-00e7b77f-aa0c-4b8b-a43e-00f0073d245e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62281600814644780083279936214011884609603143792237658133713438694943417419026 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.62281600814644780083279936214011884609603143792237658133713438694943417419026
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.103139595129143696228844039720494840088949563377599189088772754486656134482615
Short name T120
Test name
Test status
Simulation time 24422223 ps
CPU time 0.66 seconds
Started Nov 22 01:03:45 PM PST 23
Finished Nov 22 01:03:46 PM PST 23
Peak memory 202840 kb
Host smart-64cca884-e91d-4e74-8815-b221766a347b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103139595129143696228844039720494840088949563377599189088772754486656134482615 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.i2c_intr_test.103139595129143696228844039720494840088949563377599189088772754486656134482615
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.64540032892474616682378230923114436398801077298037661506329782703879492869488
Short name T1625
Test name
Test status
Simulation time 97278783 ps
CPU time 1.28 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 203060 kb
Host smart-95b42887-83ea-44fe-b97a-54ef9028a492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64540032892474616682378230923114436398801077298037661506329782703879492869488 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.i2c_tl_errors.64540032892474616682378230923114436398801077298037661506329782703879492869488
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.83573643554529154115214838310833338007074968352853683511939071797535313234917
Short name T79
Test name
Test status
Simulation time 114885785 ps
CPU time 1.3 seconds
Started Nov 22 01:03:40 PM PST 23
Finished Nov 22 01:03:42 PM PST 23
Peak memory 203052 kb
Host smart-03ea4985-2265-49a9-b0b7-a91f3b37bff1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83573643554529154115214838310833338007074968352853683511939071797535313234917 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.83573643554529154115214838310833338007074968352853683511939071797535313234917
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.34609889533738390698495984732464768089210851685748376765676061339031393550692
Short name T1653
Test name
Test status
Simulation time 33779291 ps
CPU time 0.78 seconds
Started Nov 22 01:03:45 PM PST 23
Finished Nov 22 01:03:47 PM PST 23
Peak memory 202888 kb
Host smart-1a53f478-3c60-4de1-aafa-830c6bc5521f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460988953373839069849598473246476808921085
1685748376765676061339031393550692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.346098895337383906984959847
32464768089210851685748376765676061339031393550692
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.13496759211401441653858973122905741571013320076069480999466148410324215676737
Short name T1610
Test name
Test status
Simulation time 28136479 ps
CPU time 0.65 seconds
Started Nov 22 01:03:48 PM PST 23
Finished Nov 22 01:03:50 PM PST 23
Peak memory 202748 kb
Host smart-473ad0ef-b5be-4a29-a634-5a4756358b1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13496759211401441653858973122905741571013320076069480999466148410324215676737 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.13496759211401441653858973122905741571013320076069480999466148410324215676737
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.11364754668567059985162661420272803040655623222572249063689512006720960360374
Short name T135
Test name
Test status
Simulation time 24422223 ps
CPU time 0.66 seconds
Started Nov 22 01:03:49 PM PST 23
Finished Nov 22 01:03:51 PM PST 23
Peak memory 202760 kb
Host smart-c3a94797-2a7d-48c2-9ebe-1a128d14fa31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11364754668567059985162661420272803040655623222572249063689512006720960360374 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.i2c_intr_test.11364754668567059985162661420272803040655623222572249063689512006720960360374
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.19376280489043507779320925928762704633255494982741374743442807435054191914349
Short name T1667
Test name
Test status
Simulation time 48993455 ps
CPU time 0.8 seconds
Started Nov 22 01:03:45 PM PST 23
Finished Nov 22 01:03:47 PM PST 23
Peak memory 202844 kb
Host smart-896000ff-3952-4192-84ca-d4f72b270704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19376280489043507779320925928762704633255494982741374743442807435054191914349
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_outstanding.19376280489043507779320925928762704633255494982741374743442807435054191914349
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.46429599490575354948659327883996638097566443850169138730014217710685752010989
Short name T1629
Test name
Test status
Simulation time 97278783 ps
CPU time 1.4 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:53 PM PST 23
Peak memory 203036 kb
Host smart-25f51099-47f3-4573-a421-af97ac807c7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46429599490575354948659327883996638097566443850169138730014217710685752010989 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.i2c_tl_errors.46429599490575354948659327883996638097566443850169138730014217710685752010989
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.38727969264710945276496800668138937704208365961751794299806783888072460204889
Short name T136
Test name
Test status
Simulation time 114885785 ps
CPU time 1.39 seconds
Started Nov 22 01:03:48 PM PST 23
Finished Nov 22 01:03:51 PM PST 23
Peak memory 203032 kb
Host smart-aa182722-17d1-49c7-8395-d6ca16e5e72e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38727969264710945276496800668138937704208365961751794299806783888072460204889 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.38727969264710945276496800668138937704208365961751794299806783888072460204889
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.62225358117713277680193024223670480056910566398879682473427743389785221146840
Short name T1632
Test name
Test status
Simulation time 33779291 ps
CPU time 0.76 seconds
Started Nov 22 01:03:49 PM PST 23
Finished Nov 22 01:03:51 PM PST 23
Peak memory 202812 kb
Host smart-88c94a10-d01d-4794-9aa1-706ea4cc9161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6222535811771327768019302422367048005691056
6398879682473427743389785221146840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.622253581177132776801930242
23670480056910566398879682473427743389785221146840
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.46370356172064342440166349011286274893422505025448241652513165117527606033966
Short name T134
Test name
Test status
Simulation time 28136479 ps
CPU time 0.68 seconds
Started Nov 22 01:03:57 PM PST 23
Finished Nov 22 01:04:05 PM PST 23
Peak memory 202760 kb
Host smart-1865ec40-6687-4fbe-ba43-35bc170a5683
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46370356172064342440166349011286274893422505025448241652513165117527606033966 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.46370356172064342440166349011286274893422505025448241652513165117527606033966
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.43859960660157590368634483694802321518952878684241750868668910299867669133352
Short name T128
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:03:43 PM PST 23
Finished Nov 22 01:03:44 PM PST 23
Peak memory 201748 kb
Host smart-a788c9af-b3d8-4d4e-9fa5-ba06c9a29d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43859960660157590368634483694802321518952878684241750868668910299867669133352 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.i2c_intr_test.43859960660157590368634483694802321518952878684241750868668910299867669133352
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.41812011804001220373418671452120850048133326537975125382364435755387657341096
Short name T1589
Test name
Test status
Simulation time 48993455 ps
CPU time 0.81 seconds
Started Nov 22 01:03:46 PM PST 23
Finished Nov 22 01:03:48 PM PST 23
Peak memory 202800 kb
Host smart-e598dc4b-360d-414e-933d-bab1019a3390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41812011804001220373418671452120850048133326537975125382364435755387657341096
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outstanding.41812011804001220373418671452120850048133326537975125382364435755387657341096
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.24344314839591607881121461539393664737770214986415420983590307308745400848185
Short name T76
Test name
Test status
Simulation time 97278783 ps
CPU time 1.3 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:53 PM PST 23
Peak memory 203060 kb
Host smart-75e53572-7310-43de-828f-e204e6042b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24344314839591607881121461539393664737770214986415420983590307308745400848185 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.i2c_tl_errors.24344314839591607881121461539393664737770214986415420983590307308745400848185
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.7838379337643659906087795834158396130768966523856467705017409311663611265568
Short name T75
Test name
Test status
Simulation time 114885785 ps
CPU time 1.27 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 203032 kb
Host smart-414d38bb-56d2-4a6d-83d4-61433d24c198
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7838379337643659906087795834158396130768966523856467705017409311663611265568 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.7838379337643659906087795834158396130768966523856467705017409311663611265568
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.13854330342467103463462098584786067704033862501654387575827003738186225107007
Short name T1671
Test name
Test status
Simulation time 64475474 ps
CPU time 0.96 seconds
Started Nov 22 01:02:44 PM PST 23
Finished Nov 22 01:02:47 PM PST 23
Peak memory 202740 kb
Host smart-4b2383c5-6fa7-417b-bffc-f9aa31b6bb56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854330342467103463462098584786067704033862501654387575827003738186225107007 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.13854330342467103463462098584786067704033862501654387575827003738186225107007
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.21099387945517068175084874810890637916265098203888292620285267633490523842591
Short name T1655
Test name
Test status
Simulation time 336669725 ps
CPU time 2.38 seconds
Started Nov 22 01:02:44 PM PST 23
Finished Nov 22 01:02:48 PM PST 23
Peak memory 202988 kb
Host smart-a3667999-b3da-4daf-8a6e-a17f0f1e9608
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21099387945517068175084874810890637916265098203888292620285267633490523842591 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.21099387945517068175084874810890637916265098203888292620285267633490523842591
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.15092490215964864023218256060798396735136703919958443165906929280710906000826
Short name T1596
Test name
Test status
Simulation time 30047178 ps
CPU time 0.68 seconds
Started Nov 22 01:02:39 PM PST 23
Finished Nov 22 01:02:41 PM PST 23
Peak memory 202824 kb
Host smart-9bf45cfa-06af-44ca-ba82-e509484f5540
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15092490215964864023218256060798396735136703919958443165906929280710906000826 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.15092490215964864023218256060798396735136703919958443165906929280710906000826
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.23731242901853145390037828519102608799865011137235504556837257934569135687164
Short name T123
Test name
Test status
Simulation time 33779291 ps
CPU time 0.72 seconds
Started Nov 22 01:02:52 PM PST 23
Finished Nov 22 01:02:54 PM PST 23
Peak memory 202888 kb
Host smart-b6dbb3e1-4bf0-4ff0-ac60-79bc0f329d24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373124290185314539003782851910260879986501
1137235504556837257934569135687164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2373124290185314539003782851
9102608799865011137235504556837257934569135687164
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.15923676789844313180381529098491449046953602471384392786392248431975192472861
Short name T1642
Test name
Test status
Simulation time 28136479 ps
CPU time 0.65 seconds
Started Nov 22 01:02:40 PM PST 23
Finished Nov 22 01:02:42 PM PST 23
Peak memory 202528 kb
Host smart-ee6f7d41-6799-4e00-848b-88bc336dc347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15923676789844313180381529098491449046953602471384392786392248431975192472861 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.15923676789844313180381529098491449046953602471384392786392248431975192472861
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.115778616048941641454350455473051789825992496589066947805172167048923080967102
Short name T130
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:02:38 PM PST 23
Finished Nov 22 01:02:40 PM PST 23
Peak memory 202856 kb
Host smart-1f1ed6ac-0011-4b17-98ca-a2a33f46a799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115778616048941641454350455473051789825992496589066947805172167048923080967102 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.i2c_intr_test.115778616048941641454350455473051789825992496589066947805172167048923080967102
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4277497851842420045812720028074891224953905162945724220626676171297716347487
Short name T1640
Test name
Test status
Simulation time 48993455 ps
CPU time 0.85 seconds
Started Nov 22 01:02:44 PM PST 23
Finished Nov 22 01:02:47 PM PST 23
Peak memory 202836 kb
Host smart-65b5d8d1-b73e-4b2f-b8b4-cb4499cddc53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277497851842420045812720028074891224953905162945724220626676171297716347487 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outstanding.4277497851842420045812720028074891224953905162945724220626676171297716347487
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.23781614037248258703840563460778162616338471287189141960288985599125188098055
Short name T86
Test name
Test status
Simulation time 97278783 ps
CPU time 1.35 seconds
Started Nov 22 01:02:52 PM PST 23
Finished Nov 22 01:02:54 PM PST 23
Peak memory 203072 kb
Host smart-2f728f0a-abcc-41c5-9512-bc546fc2a36b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781614037248258703840563460778162616338471287189141960288985599125188098055 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.i2c_tl_errors.23781614037248258703840563460778162616338471287189141960288985599125188098055
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.43822482440822266918171236191276070614836414452049842379328288199525436179983
Short name T1588
Test name
Test status
Simulation time 114885785 ps
CPU time 1.34 seconds
Started Nov 22 01:02:51 PM PST 23
Finished Nov 22 01:02:54 PM PST 23
Peak memory 202972 kb
Host smart-90263328-5d20-4eaf-9491-d3fda843aa1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43822482440822266918171236191276070614836414452049842379328288199525436179983 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.43822482440822266918171236191276070614836414452049842379328288199525436179983
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.18095035893972196990775274011666408724616878246427364723713873341939020525641
Short name T114
Test name
Test status
Simulation time 24422223 ps
CPU time 0.69 seconds
Started Nov 22 01:03:57 PM PST 23
Finished Nov 22 01:04:05 PM PST 23
Peak memory 202852 kb
Host smart-2e9d6f41-039d-4a55-bebc-22beab64c41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18095035893972196990775274011666408724616878246427364723713873341939020525641 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 20.i2c_intr_test.18095035893972196990775274011666408724616878246427364723713873341939020525641
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.16141857268132856749245844319931682405415341202034180646668882389718247888042
Short name T1668
Test name
Test status
Simulation time 24422223 ps
CPU time 0.65 seconds
Started Nov 22 01:03:47 PM PST 23
Finished Nov 22 01:03:49 PM PST 23
Peak memory 202044 kb
Host smart-a6805caf-d3d4-416e-98f1-1a94cb19d305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141857268132856749245844319931682405415341202034180646668882389718247888042 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 21.i2c_intr_test.16141857268132856749245844319931682405415341202034180646668882389718247888042
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.108383702825355252536589204379556075731614613395407467253302460879396304295205
Short name T127
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:03:44 PM PST 23
Finished Nov 22 01:03:45 PM PST 23
Peak memory 202824 kb
Host smart-6c48a892-bc69-45ce-97ef-937b4a8738eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108383702825355252536589204379556075731614613395407467253302460879396304295205 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 22.i2c_intr_test.108383702825355252536589204379556075731614613395407467253302460879396304295205
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.45485095243843050652136346646044056062454532994833961575361082697379407592377
Short name T142
Test name
Test status
Simulation time 24422223 ps
CPU time 0.7 seconds
Started Nov 22 01:03:48 PM PST 23
Finished Nov 22 01:03:51 PM PST 23
Peak memory 202856 kb
Host smart-6c71f363-fa19-4ce9-a07a-cdb13d2fed1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45485095243843050652136346646044056062454532994833961575361082697379407592377 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 23.i2c_intr_test.45485095243843050652136346646044056062454532994833961575361082697379407592377
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.4865355834807315787252762606943669273972578940314417996284784709144632913827
Short name T1665
Test name
Test status
Simulation time 24422223 ps
CPU time 0.71 seconds
Started Nov 22 01:03:43 PM PST 23
Finished Nov 22 01:03:45 PM PST 23
Peak memory 201668 kb
Host smart-e38c0fc2-7f3e-4cb3-8541-59fd6af17658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4865355834807315787252762606943669273972578940314417996284784709144632913827 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 24.i2c_intr_test.4865355834807315787252762606943669273972578940314417996284784709144632913827
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.47772860738930087523611836485149769902284324403650054770659093526874701670908
Short name T131
Test name
Test status
Simulation time 24422223 ps
CPU time 0.62 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202820 kb
Host smart-d9e2cc7d-38ed-475b-9b06-060c62e2321c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47772860738930087523611836485149769902284324403650054770659093526874701670908 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 25.i2c_intr_test.47772860738930087523611836485149769902284324403650054770659093526874701670908
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.32636594868802515509588601211738774823197630624176606349048681282356159790221
Short name T1599
Test name
Test status
Simulation time 24422223 ps
CPU time 0.65 seconds
Started Nov 22 01:03:49 PM PST 23
Finished Nov 22 01:03:51 PM PST 23
Peak memory 202760 kb
Host smart-9c29ff86-7f55-4cac-ae68-9f7e6c0bfdcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32636594868802515509588601211738774823197630624176606349048681282356159790221 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 26.i2c_intr_test.32636594868802515509588601211738774823197630624176606349048681282356159790221
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.56600574105545547101220225562687371677594244686329955831902354825045056966399
Short name T1597
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:03:56 PM PST 23
Finished Nov 22 01:03:58 PM PST 23
Peak memory 202840 kb
Host smart-82321c0e-4e56-42c1-818e-16d4fb5a4f8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56600574105545547101220225562687371677594244686329955831902354825045056966399 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 27.i2c_intr_test.56600574105545547101220225562687371677594244686329955831902354825045056966399
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.84955118048146715458237535011711618032775574495790907944750513959933434734821
Short name T1608
Test name
Test status
Simulation time 24422223 ps
CPU time 0.7 seconds
Started Nov 22 01:03:49 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202760 kb
Host smart-62113ac9-1a7e-4aa5-b2f8-7bb9e806fc96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84955118048146715458237535011711618032775574495790907944750513959933434734821 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 28.i2c_intr_test.84955118048146715458237535011711618032775574495790907944750513959933434734821
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.77514067883264465884152825160389605090251894564341931379045578868113217702270
Short name T1643
Test name
Test status
Simulation time 24422223 ps
CPU time 0.62 seconds
Started Nov 22 01:03:51 PM PST 23
Finished Nov 22 01:03:53 PM PST 23
Peak memory 202844 kb
Host smart-2c829147-aba5-433f-9111-7ca0bd1c1142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77514067883264465884152825160389605090251894564341931379045578868113217702270 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 29.i2c_intr_test.77514067883264465884152825160389605090251894564341931379045578868113217702270
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.76039505959325185160026638535781394555791234808749214866726269089814128107904
Short name T1591
Test name
Test status
Simulation time 64475474 ps
CPU time 0.96 seconds
Started Nov 22 01:02:54 PM PST 23
Finished Nov 22 01:02:56 PM PST 23
Peak memory 202744 kb
Host smart-a791a3c0-9788-40a4-bdb5-755b67ad011a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76039505959325185160026638535781394555791234808749214866726269089814128107904 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.76039505959325185160026638535781394555791234808749214866726269089814128107904
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.93400265347288338098314344534874603727863625013897261724421109680915893201310
Short name T1585
Test name
Test status
Simulation time 336669725 ps
CPU time 2.44 seconds
Started Nov 22 01:02:53 PM PST 23
Finished Nov 22 01:02:56 PM PST 23
Peak memory 202900 kb
Host smart-51281291-106d-4835-8565-a1e9d10fcf5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93400265347288338098314344534874603727863625013897261724421109680915893201310 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.93400265347288338098314344534874603727863625013897261724421109680915893201310
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.40189970085480553320964190070402890229578072994379536125727994232805241562160
Short name T1618
Test name
Test status
Simulation time 30047178 ps
CPU time 0.7 seconds
Started Nov 22 01:02:43 PM PST 23
Finished Nov 22 01:02:46 PM PST 23
Peak memory 202776 kb
Host smart-1ce4d472-f451-4a4f-99ee-08cbc3588892
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40189970085480553320964190070402890229578072994379536125727994232805241562160 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.40189970085480553320964190070402890229578072994379536125727994232805241562160
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.10337112842878051882088445605186745090324190191282025464999694406765927001163
Short name T1656
Test name
Test status
Simulation time 33779291 ps
CPU time 0.75 seconds
Started Nov 22 01:02:50 PM PST 23
Finished Nov 22 01:02:52 PM PST 23
Peak memory 202920 kb
Host smart-2e1f9711-2acc-4a38-8c3f-3325ab99ffec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033711284287805188208844560518674509032419
0191282025464999694406765927001163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1033711284287805188208844560
5186745090324190191282025464999694406765927001163
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.106706478154872221729832192726374919831946971575030028112375678628902053396190
Short name T1614
Test name
Test status
Simulation time 28136479 ps
CPU time 0.65 seconds
Started Nov 22 01:02:49 PM PST 23
Finished Nov 22 01:02:51 PM PST 23
Peak memory 202752 kb
Host smart-e3aa05a5-4cd0-4ac4-9af0-1a36a730345c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106706478154872221729832192726374919831946971575030028112375678628902053396190 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.106706478154872221729832192726374919831946971575030028112375678628902053396190
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.82717492076125977589953868080186847351412931653424870289971035649327555947841
Short name T1670
Test name
Test status
Simulation time 24422223 ps
CPU time 0.65 seconds
Started Nov 22 01:02:46 PM PST 23
Finished Nov 22 01:02:49 PM PST 23
Peak memory 202856 kb
Host smart-a4717d15-fb89-4ac4-abba-81e659bedf61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82717492076125977589953868080186847351412931653424870289971035649327555947841 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.i2c_intr_test.82717492076125977589953868080186847351412931653424870289971035649327555947841
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.21563191129418836292137549097372439980838413924765903127236350384843554202558
Short name T96
Test name
Test status
Simulation time 48993455 ps
CPU time 0.81 seconds
Started Nov 22 01:03:02 PM PST 23
Finished Nov 22 01:03:04 PM PST 23
Peak memory 202812 kb
Host smart-7cfca953-d7fb-4926-a0fd-11fe80a2619d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21563191129418836292137549097372439980838413924765903127236350384843554202558
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outstanding.21563191129418836292137549097372439980838413924765903127236350384843554202558
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.60886560717603611427882871253397895591965294254438474565652265696252907831237
Short name T1652
Test name
Test status
Simulation time 97278783 ps
CPU time 1.34 seconds
Started Nov 22 01:02:40 PM PST 23
Finished Nov 22 01:02:43 PM PST 23
Peak memory 203068 kb
Host smart-09232200-3786-484a-9dc7-470e2e3d334a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60886560717603611427882871253397895591965294254438474565652265696252907831237 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.i2c_tl_errors.60886560717603611427882871253397895591965294254438474565652265696252907831237
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.100321188376475869080867376760910384627835199691770255180178401452597731525985
Short name T80
Test name
Test status
Simulation time 114885785 ps
CPU time 1.29 seconds
Started Nov 22 01:02:58 PM PST 23
Finished Nov 22 01:03:01 PM PST 23
Peak memory 203016 kb
Host smart-5cd3b028-db2a-49c3-99bf-5bf8a4345ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100321188376475869080867376760910384627835199691770255180178401452597731525985 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.100321188376475869080867376760910384627835199691770255180178401452597731525985
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.88692170709156444055582164584209745935899927866174139142548842334343892345640
Short name T33
Test name
Test status
Simulation time 24422223 ps
CPU time 0.65 seconds
Started Nov 22 01:03:47 PM PST 23
Finished Nov 22 01:03:49 PM PST 23
Peak memory 202856 kb
Host smart-a26bdcb8-cc47-4cbf-808f-3ef73a2336ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88692170709156444055582164584209745935899927866174139142548842334343892345640 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 30.i2c_intr_test.88692170709156444055582164584209745935899927866174139142548842334343892345640
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.107676282088617458395478797561425742777259609332936417396371773952734086978463
Short name T108
Test name
Test status
Simulation time 24422223 ps
CPU time 0.63 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202780 kb
Host smart-4dffbc74-6097-47f0-9838-0890eb650fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107676282088617458395478797561425742777259609332936417396371773952734086978463 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 31.i2c_intr_test.107676282088617458395478797561425742777259609332936417396371773952734086978463
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.53828380445207578655531060044119780342951085360561787095437355460331462458575
Short name T1587
Test name
Test status
Simulation time 24422223 ps
CPU time 0.63 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:53 PM PST 23
Peak memory 202796 kb
Host smart-39c5e4d7-f3b6-4611-bf2b-352c58736307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53828380445207578655531060044119780342951085360561787095437355460331462458575 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 32.i2c_intr_test.53828380445207578655531060044119780342951085360561787095437355460331462458575
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.108675736186327956592247102795887151477039596786733570263651512460824980829993
Short name T111
Test name
Test status
Simulation time 24422223 ps
CPU time 0.67 seconds
Started Nov 22 01:03:49 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202756 kb
Host smart-8d21c289-e37e-429b-a144-ddb4852d9667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108675736186327956592247102795887151477039596786733570263651512460824980829993 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 33.i2c_intr_test.108675736186327956592247102795887151477039596786733570263651512460824980829993
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.103122344272199577002954193779715903356684943519380379514842511215492086179639
Short name T1606
Test name
Test status
Simulation time 24422223 ps
CPU time 0.62 seconds
Started Nov 22 01:03:55 PM PST 23
Finished Nov 22 01:03:58 PM PST 23
Peak memory 202844 kb
Host smart-c307205a-6cfc-4438-ad06-47218caf9990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103122344272199577002954193779715903356684943519380379514842511215492086179639 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 34.i2c_intr_test.103122344272199577002954193779715903356684943519380379514842511215492086179639
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.49423756454636939298828014539725053941000232202937343788333608211755210418685
Short name T1634
Test name
Test status
Simulation time 24422223 ps
CPU time 0.63 seconds
Started Nov 22 01:03:52 PM PST 23
Finished Nov 22 01:03:54 PM PST 23
Peak memory 202768 kb
Host smart-414cdd0d-7efa-449e-845e-71d813018da1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49423756454636939298828014539725053941000232202937343788333608211755210418685 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 35.i2c_intr_test.49423756454636939298828014539725053941000232202937343788333608211755210418685
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.72637762527124499698397210603803880216585174744308311695950200288069332532339
Short name T1584
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:03:52 PM PST 23
Finished Nov 22 01:03:54 PM PST 23
Peak memory 202808 kb
Host smart-9fed8d89-d4a5-477d-aa0f-46018a5dcb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72637762527124499698397210603803880216585174744308311695950200288069332532339 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 36.i2c_intr_test.72637762527124499698397210603803880216585174744308311695950200288069332532339
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.109185824895426903165330185561324856511081415186877134282262638497421447900661
Short name T125
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:03:45 PM PST 23
Finished Nov 22 01:03:46 PM PST 23
Peak memory 202860 kb
Host smart-e72fd979-1ef6-4a7b-9efb-871664ff7799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109185824895426903165330185561324856511081415186877134282262638497421447900661 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 37.i2c_intr_test.109185824895426903165330185561324856511081415186877134282262638497421447900661
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.48175471424283125777615984435314459106573517067235078706478351077903562706691
Short name T1641
Test name
Test status
Simulation time 24422223 ps
CPU time 0.62 seconds
Started Nov 22 01:03:51 PM PST 23
Finished Nov 22 01:03:54 PM PST 23
Peak memory 202844 kb
Host smart-8268efa9-5bc5-440f-9660-c1afef05e6b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48175471424283125777615984435314459106573517067235078706478351077903562706691 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 38.i2c_intr_test.48175471424283125777615984435314459106573517067235078706478351077903562706691
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.65579382824279536674016481450669863937341341201474461574834559865263266335929
Short name T139
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:03:45 PM PST 23
Finished Nov 22 01:03:46 PM PST 23
Peak memory 202756 kb
Host smart-716fe3db-1b2b-432d-ad83-5fa4e7245fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65579382824279536674016481450669863937341341201474461574834559865263266335929 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 39.i2c_intr_test.65579382824279536674016481450669863937341341201474461574834559865263266335929
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.82120893387892046284615967849771741323310654683546537667026954538751763146953
Short name T1650
Test name
Test status
Simulation time 64475474 ps
CPU time 0.91 seconds
Started Nov 22 01:03:02 PM PST 23
Finished Nov 22 01:03:04 PM PST 23
Peak memory 202776 kb
Host smart-44ef81f9-5f67-4019-a80d-4c85dc9a640d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82120893387892046284615967849771741323310654683546537667026954538751763146953 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.82120893387892046284615967849771741323310654683546537667026954538751763146953
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.90374405052433347012865147633233466479324366975023905933496146590093726292056
Short name T27
Test name
Test status
Simulation time 336669725 ps
CPU time 2.42 seconds
Started Nov 22 01:03:00 PM PST 23
Finished Nov 22 01:03:03 PM PST 23
Peak memory 202984 kb
Host smart-898e8a62-dd88-469b-a9d9-888e08f908c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90374405052433347012865147633233466479324366975023905933496146590093726292056 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.90374405052433347012865147633233466479324366975023905933496146590093726292056
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.46264022705292618909163967116420224573242853934755893734346209092082865215699
Short name T70
Test name
Test status
Simulation time 30047178 ps
CPU time 0.72 seconds
Started Nov 22 01:02:56 PM PST 23
Finished Nov 22 01:02:58 PM PST 23
Peak memory 202780 kb
Host smart-915354f2-bbf0-4201-ad63-391e3e268808
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46264022705292618909163967116420224573242853934755893734346209092082865215699 -assert nopo
stproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.46264022705292618909163967116420224573242853934755893734346209092082865215699
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.83522967338282116577408121526490919719882693004761587989249601120475045133687
Short name T1631
Test name
Test status
Simulation time 33779291 ps
CPU time 0.77 seconds
Started Nov 22 01:03:00 PM PST 23
Finished Nov 22 01:03:02 PM PST 23
Peak memory 202896 kb
Host smart-673cb8ef-69d5-403a-9cd2-903bdf2d6c68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8352296733828211657740812152649091971988269
3004761587989249601120475045133687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.8352296733828211657740812152
6490919719882693004761587989249601120475045133687
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.81655044451028349567469923850513444237579066967076030642035056255225769695329
Short name T1624
Test name
Test status
Simulation time 28136479 ps
CPU time 0.65 seconds
Started Nov 22 01:02:56 PM PST 23
Finished Nov 22 01:02:58 PM PST 23
Peak memory 202688 kb
Host smart-a1607290-5c6b-49ed-8ace-0fc49b360695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81655044451028349567469923850513444237579066967076030642035056255225769695329 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.81655044451028349567469923850513444237579066967076030642035056255225769695329
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.42450997748028698495829437963196556178825250692597473708879099128639528434382
Short name T1635
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:02:50 PM PST 23
Finished Nov 22 01:02:52 PM PST 23
Peak memory 202872 kb
Host smart-96fa538e-8b5a-404b-bbd0-d6061b4db2f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42450997748028698495829437963196556178825250692597473708879099128639528434382 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.i2c_intr_test.42450997748028698495829437963196556178825250692597473708879099128639528434382
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.51165489666959757385595606701968197797814967864006617981280095200386140121990
Short name T91
Test name
Test status
Simulation time 48993455 ps
CPU time 0.84 seconds
Started Nov 22 01:03:06 PM PST 23
Finished Nov 22 01:03:08 PM PST 23
Peak memory 202828 kb
Host smart-5cece31d-db7a-4b93-a214-8ea47013f986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51165489666959757385595606701968197797814967864006617981280095200386140121990
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outstanding.51165489666959757385595606701968197797814967864006617981280095200386140121990
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.87394259962298367992953806833893881878311848079807537754859716800741209298388
Short name T81
Test name
Test status
Simulation time 97278783 ps
CPU time 1.34 seconds
Started Nov 22 01:02:49 PM PST 23
Finished Nov 22 01:02:52 PM PST 23
Peak memory 203092 kb
Host smart-acccf82d-4e02-419a-bd19-bc06e311c37b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87394259962298367992953806833893881878311848079807537754859716800741209298388 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.i2c_tl_errors.87394259962298367992953806833893881878311848079807537754859716800741209298388
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.114773527835628304050222831989001624395991095852405107402841865905252888146187
Short name T1639
Test name
Test status
Simulation time 114885785 ps
CPU time 1.27 seconds
Started Nov 22 01:03:07 PM PST 23
Finished Nov 22 01:03:09 PM PST 23
Peak memory 202984 kb
Host smart-74cac5d5-39cd-4128-89b4-bbf7c838f090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114773527835628304050222831989001624395991095852405107402841865905252888146187 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.114773527835628304050222831989001624395991095852405107402841865905252888146187
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.70938313806981683326450693097164356894001934762049824612338442912615192947595
Short name T1586
Test name
Test status
Simulation time 24422223 ps
CPU time 0.65 seconds
Started Nov 22 01:03:45 PM PST 23
Finished Nov 22 01:03:46 PM PST 23
Peak memory 202756 kb
Host smart-0a869453-bc9f-4a69-9ec3-641417fdd9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70938313806981683326450693097164356894001934762049824612338442912615192947595 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 40.i2c_intr_test.70938313806981683326450693097164356894001934762049824612338442912615192947595
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.84172811960176040095292708000191484555381271642638251269183784205429306886754
Short name T109
Test name
Test status
Simulation time 24422223 ps
CPU time 0.61 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202824 kb
Host smart-aecb673c-494e-4e17-b733-25f9d9a70112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84172811960176040095292708000191484555381271642638251269183784205429306886754 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 41.i2c_intr_test.84172811960176040095292708000191484555381271642638251269183784205429306886754
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.83372388737558863964097461678280633887459377730479722029597527819116450331911
Short name T1662
Test name
Test status
Simulation time 24422223 ps
CPU time 0.62 seconds
Started Nov 22 01:03:47 PM PST 23
Finished Nov 22 01:03:50 PM PST 23
Peak memory 202836 kb
Host smart-95a7bd7b-274c-4863-811b-64dc5c96cc80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83372388737558863964097461678280633887459377730479722029597527819116450331911 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 42.i2c_intr_test.83372388737558863964097461678280633887459377730479722029597527819116450331911
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.89807253194154602984847577508672264493526024106093962765350659802091153543438
Short name T118
Test name
Test status
Simulation time 24422223 ps
CPU time 0.67 seconds
Started Nov 22 01:03:57 PM PST 23
Finished Nov 22 01:04:05 PM PST 23
Peak memory 202856 kb
Host smart-45bf9031-d5db-479c-8628-592582424154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89807253194154602984847577508672264493526024106093962765350659802091153543438 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 43.i2c_intr_test.89807253194154602984847577508672264493526024106093962765350659802091153543438
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.58153428085053719257414024448721962605922469658370011010859020109835960644085
Short name T133
Test name
Test status
Simulation time 24422223 ps
CPU time 0.6 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202820 kb
Host smart-94816b85-4817-4425-9749-d2f6d1ebfbdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58153428085053719257414024448721962605922469658370011010859020109835960644085 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 44.i2c_intr_test.58153428085053719257414024448721962605922469658370011010859020109835960644085
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.87407807258244568448581788786409621670561103350122037568833594285890284824601
Short name T35
Test name
Test status
Simulation time 24422223 ps
CPU time 0.62 seconds
Started Nov 22 01:03:55 PM PST 23
Finished Nov 22 01:03:58 PM PST 23
Peak memory 202832 kb
Host smart-64eba2aa-2e64-412d-be64-5e86542b966c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87407807258244568448581788786409621670561103350122037568833594285890284824601 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 45.i2c_intr_test.87407807258244568448581788786409621670561103350122037568833594285890284824601
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.23115069750865362447405771087006295378410621800809539103731943663209588943919
Short name T1605
Test name
Test status
Simulation time 24422223 ps
CPU time 0.63 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202856 kb
Host smart-75c9fbf2-d77b-4db8-8958-318ad3718e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23115069750865362447405771087006295378410621800809539103731943663209588943919 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 46.i2c_intr_test.23115069750865362447405771087006295378410621800809539103731943663209588943919
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.32827630554577558374620788968687411381889114257040728396637684957101793181341
Short name T1603
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:03:43 PM PST 23
Finished Nov 22 01:03:44 PM PST 23
Peak memory 202856 kb
Host smart-49f45b2b-273f-4f39-85de-e0088a762adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32827630554577558374620788968687411381889114257040728396637684957101793181341 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 47.i2c_intr_test.32827630554577558374620788968687411381889114257040728396637684957101793181341
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.79636640073360914993744611890290781629590356934576098708529960280350621104351
Short name T138
Test name
Test status
Simulation time 24422223 ps
CPU time 0.68 seconds
Started Nov 22 01:03:48 PM PST 23
Finished Nov 22 01:03:51 PM PST 23
Peak memory 202856 kb
Host smart-b0706cc7-0114-4283-ba13-be7da49ca882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79636640073360914993744611890290781629590356934576098708529960280350621104351 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 48.i2c_intr_test.79636640073360914993744611890290781629590356934576098708529960280350621104351
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.34395744975314298591930099780075715065333334080060845992763651773429381028130
Short name T1661
Test name
Test status
Simulation time 24422223 ps
CPU time 0.63 seconds
Started Nov 22 01:03:50 PM PST 23
Finished Nov 22 01:03:52 PM PST 23
Peak memory 202836 kb
Host smart-04dc02f6-cef6-49cc-8eaf-b5cef13c139e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34395744975314298591930099780075715065333334080060845992763651773429381028130 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 49.i2c_intr_test.34395744975314298591930099780075715065333334080060845992763651773429381028130
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.50602709109287153852416746816906452455577780136823211532440722536392917737916
Short name T77
Test name
Test status
Simulation time 33779291 ps
CPU time 0.72 seconds
Started Nov 22 01:03:03 PM PST 23
Finished Nov 22 01:03:05 PM PST 23
Peak memory 202872 kb
Host smart-d00dd55c-6b57-4881-8fe6-b24997ca98a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5060270910928715385241674681690645245557778
0136823211532440722536392917737916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.5060270910928715385241674681
6906452455577780136823211532440722536392917737916
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.92442923455117265901911514432306771271870516796866144144478765012346161961608
Short name T1669
Test name
Test status
Simulation time 28136479 ps
CPU time 0.63 seconds
Started Nov 22 01:02:55 PM PST 23
Finished Nov 22 01:02:58 PM PST 23
Peak memory 202688 kb
Host smart-8802b315-ddd0-4504-bee4-1387e4b86dfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92442923455117265901911514432306771271870516796866144144478765012346161961608 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.92442923455117265901911514432306771271870516796866144144478765012346161961608
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.81629734859710892910326659512142343370049810766088166456957611287272437148151
Short name T1594
Test name
Test status
Simulation time 24422223 ps
CPU time 0.67 seconds
Started Nov 22 01:03:01 PM PST 23
Finished Nov 22 01:03:02 PM PST 23
Peak memory 202828 kb
Host smart-a06947e7-2a9b-470b-9252-5c0e560a47cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81629734859710892910326659512142343370049810766088166456957611287272437148151 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.i2c_intr_test.81629734859710892910326659512142343370049810766088166456957611287272437148151
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.9319179720934938253869194102846640553402288152487772424733398651391709366889
Short name T92
Test name
Test status
Simulation time 48993455 ps
CPU time 0.84 seconds
Started Nov 22 01:02:50 PM PST 23
Finished Nov 22 01:02:52 PM PST 23
Peak memory 202860 kb
Host smart-1fb9fac5-1f07-4f6d-91e5-269df2a89f35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9319179720934938253869194102846640553402288152487772424733398651391709366889 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outstanding.9319179720934938253869194102846640553402288152487772424733398651391709366889
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.93483622522039437947231039823680428520362689858982913717482385099965159541504
Short name T1648
Test name
Test status
Simulation time 97278783 ps
CPU time 1.29 seconds
Started Nov 22 01:03:02 PM PST 23
Finished Nov 22 01:03:04 PM PST 23
Peak memory 203048 kb
Host smart-83aecaf6-3e23-4e20-859e-0dd7e83d182f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93483622522039437947231039823680428520362689858982913717482385099965159541504 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.i2c_tl_errors.93483622522039437947231039823680428520362689858982913717482385099965159541504
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.69467188597457520434890582672330970127655726316890146480116796405904317438841
Short name T31
Test name
Test status
Simulation time 114885785 ps
CPU time 1.26 seconds
Started Nov 22 01:02:51 PM PST 23
Finished Nov 22 01:02:53 PM PST 23
Peak memory 203072 kb
Host smart-bf80d17a-cb0d-43a1-955b-2af8553bd11e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69467188597457520434890582672330970127655726316890146480116796405904317438841 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.69467188597457520434890582672330970127655726316890146480116796405904317438841
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.32213326058288324672012896097160596533128025307119084290927669659357711251777
Short name T97
Test name
Test status
Simulation time 33779291 ps
CPU time 0.73 seconds
Started Nov 22 01:02:51 PM PST 23
Finished Nov 22 01:02:53 PM PST 23
Peak memory 202920 kb
Host smart-7ab482ef-dd27-4b83-8723-6b75b9c815b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221332605828832467201289609716059653312802
5307119084290927669659357711251777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3221332605828832467201289609
7160596533128025307119084290927669659357711251777
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.112361768548390198001102372835573134255952592657364224155363353975170490708042
Short name T1630
Test name
Test status
Simulation time 28136479 ps
CPU time 0.62 seconds
Started Nov 22 01:03:00 PM PST 23
Finished Nov 22 01:03:02 PM PST 23
Peak memory 202744 kb
Host smart-eb5520d8-cfaf-46db-b007-d0a82737165a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112361768548390198001102372835573134255952592657364224155363353975170490708042 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.112361768548390198001102372835573134255952592657364224155363353975170490708042
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.79657403574278831965359054533060736137203415617195001826263770749340195227270
Short name T1627
Test name
Test status
Simulation time 24422223 ps
CPU time 0.65 seconds
Started Nov 22 01:03:07 PM PST 23
Finished Nov 22 01:03:09 PM PST 23
Peak memory 202800 kb
Host smart-a3e81f13-1556-4763-9333-7658ff3ef0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79657403574278831965359054533060736137203415617195001826263770749340195227270 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.i2c_intr_test.79657403574278831965359054533060736137203415617195001826263770749340195227270
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.101903799134386222500983877878192573048526179779344029202292206431218539953270
Short name T93
Test name
Test status
Simulation time 48993455 ps
CPU time 0.86 seconds
Started Nov 22 01:03:06 PM PST 23
Finished Nov 22 01:03:08 PM PST 23
Peak memory 202800 kb
Host smart-26e86716-d998-44f6-b49e-c6967605d5ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101903799134386222500983877878192573048526179779344029202292206431218539953270
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outstanding.101903799134386222500983877878192573048526179779344029202292206431218539953270
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.91928021815749448690412589594587818671796197901073899786427065885479968554039
Short name T1611
Test name
Test status
Simulation time 97278783 ps
CPU time 1.35 seconds
Started Nov 22 01:02:55 PM PST 23
Finished Nov 22 01:02:58 PM PST 23
Peak memory 203096 kb
Host smart-6e126b31-f173-4bdd-8aa3-c13d9d3c04e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91928021815749448690412589594587818671796197901073899786427065885479968554039 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.i2c_tl_errors.91928021815749448690412589594587818671796197901073899786427065885479968554039
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.103834912908083350020012738163471508816737905652041415080913008666118776899467
Short name T82
Test name
Test status
Simulation time 114885785 ps
CPU time 1.36 seconds
Started Nov 22 01:03:07 PM PST 23
Finished Nov 22 01:03:10 PM PST 23
Peak memory 202984 kb
Host smart-db7d4a00-b038-4f96-9daf-c211b449c8d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103834912908083350020012738163471508816737905652041415080913008666118776899467 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.103834912908083350020012738163471508816737905652041415080913008666118776899467
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.108271030261684229864150294518896250679087614713557636288864902418562236163451
Short name T137
Test name
Test status
Simulation time 33779291 ps
CPU time 0.72 seconds
Started Nov 22 01:02:55 PM PST 23
Finished Nov 22 01:02:58 PM PST 23
Peak memory 202912 kb
Host smart-2c2fb6fe-7bf9-4271-bb2e-7fde1f2a5275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082710302616842298641502945188962506790876
14713557636288864902418562236163451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.108271030261684229864150294
518896250679087614713557636288864902418562236163451
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.19405141544106893609821982324506284107398044942802479162431613470488998963160
Short name T1659
Test name
Test status
Simulation time 28136479 ps
CPU time 0.64 seconds
Started Nov 22 01:02:49 PM PST 23
Finished Nov 22 01:02:52 PM PST 23
Peak memory 202760 kb
Host smart-75125298-6beb-4346-8f37-c74a5fd04aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19405141544106893609821982324506284107398044942802479162431613470488998963160 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.19405141544106893609821982324506284107398044942802479162431613470488998963160
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.24934215564129493125188499403793506174607917010803482108480159085036711019978
Short name T1663
Test name
Test status
Simulation time 24422223 ps
CPU time 0.68 seconds
Started Nov 22 01:02:47 PM PST 23
Finished Nov 22 01:02:49 PM PST 23
Peak memory 202840 kb
Host smart-5b8c3209-3b90-48d3-af69-ce6491ec5081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24934215564129493125188499403793506174607917010803482108480159085036711019978 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.i2c_intr_test.24934215564129493125188499403793506174607917010803482108480159085036711019978
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.89627403301885130811531592121295214682723573865874850240128900420654850540273
Short name T1633
Test name
Test status
Simulation time 48993455 ps
CPU time 0.89 seconds
Started Nov 22 01:02:52 PM PST 23
Finished Nov 22 01:02:53 PM PST 23
Peak memory 202740 kb
Host smart-c75c8fff-6461-4ab1-8d8c-f6a03e58ef94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89627403301885130811531592121295214682723573865874850240128900420654850540273
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outstanding.89627403301885130811531592121295214682723573865874850240128900420654850540273
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.95151879475668060109880715265362914984669253854131988537248508548430626869819
Short name T74
Test name
Test status
Simulation time 97278783 ps
CPU time 1.4 seconds
Started Nov 22 01:02:49 PM PST 23
Finished Nov 22 01:02:52 PM PST 23
Peak memory 203092 kb
Host smart-808bb786-171c-43fd-8bb4-2b85733757d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95151879475668060109880715265362914984669253854131988537248508548430626869819 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.i2c_tl_errors.95151879475668060109880715265362914984669253854131988537248508548430626869819
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.4790871706381872379537420536720114199241393436539923835157430415715749095642
Short name T1604
Test name
Test status
Simulation time 114885785 ps
CPU time 1.37 seconds
Started Nov 22 01:02:47 PM PST 23
Finished Nov 22 01:02:50 PM PST 23
Peak memory 203048 kb
Host smart-cb616c19-4c45-4a3b-9318-712c2650c86f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4790871706381872379537420536720114199241393436539923835157430415715749095642 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.4790871706381872379537420536720114199241393436539923835157430415715749095642
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.76089470610238435411567817065634597073278329829693640913227088878098652372692
Short name T124
Test name
Test status
Simulation time 33779291 ps
CPU time 0.72 seconds
Started Nov 22 01:02:51 PM PST 23
Finished Nov 22 01:02:53 PM PST 23
Peak memory 202908 kb
Host smart-fec4dd5a-74ef-41a5-adcb-35b861077040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7608947061023843541156781706563459707327832
9829693640913227088878098652372692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.7608947061023843541156781706
5634597073278329829693640913227088878098652372692
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.32238160390993126342464402221001376912262351227844093571519325659852031397854
Short name T1658
Test name
Test status
Simulation time 28136479 ps
CPU time 0.65 seconds
Started Nov 22 01:02:44 PM PST 23
Finished Nov 22 01:02:46 PM PST 23
Peak memory 202664 kb
Host smart-d39f2621-8394-4131-b717-1f230d13c9dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32238160390993126342464402221001376912262351227844093571519325659852031397854 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.32238160390993126342464402221001376912262351227844093571519325659852031397854
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.103049518292442072144970973726904044156991317156583889101130186412575625255654
Short name T132
Test name
Test status
Simulation time 24422223 ps
CPU time 0.63 seconds
Started Nov 22 01:02:55 PM PST 23
Finished Nov 22 01:02:58 PM PST 23
Peak memory 202788 kb
Host smart-6f2fcb73-b25d-49a7-8d01-6736d2567759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103049518292442072144970973726904044156991317156583889101130186412575625255654 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.i2c_intr_test.103049518292442072144970973726904044156991317156583889101130186412575625255654
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.101990808460280898986967779471039435211588206977324147401157460854154734096226
Short name T95
Test name
Test status
Simulation time 48993455 ps
CPU time 0.84 seconds
Started Nov 22 01:02:58 PM PST 23
Finished Nov 22 01:02:59 PM PST 23
Peak memory 202820 kb
Host smart-2058042d-8dcf-40d0-ba5b-52d0f349a2f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101990808460280898986967779471039435211588206977324147401157460854154734096226
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outstanding.101990808460280898986967779471039435211588206977324147401157460854154734096226
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.22806539284591235602812555988249020092346817282184795596792565250625887497437
Short name T1620
Test name
Test status
Simulation time 97278783 ps
CPU time 1.41 seconds
Started Nov 22 01:02:53 PM PST 23
Finished Nov 22 01:02:55 PM PST 23
Peak memory 202960 kb
Host smart-f9bb15d3-01c4-41e5-8bee-5d55df583687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22806539284591235602812555988249020092346817282184795596792565250625887497437 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.i2c_tl_errors.22806539284591235602812555988249020092346817282184795596792565250625887497437
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.31417128784614082253184741411795380665971879359857054148639074247024960913011
Short name T1647
Test name
Test status
Simulation time 114885785 ps
CPU time 1.35 seconds
Started Nov 22 01:02:53 PM PST 23
Finished Nov 22 01:02:55 PM PST 23
Peak memory 202936 kb
Host smart-bb1189ad-68ca-4c60-ab2e-988e4849f688
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31417128784614082253184741411795380665971879359857054148639074247024960913011 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.31417128784614082253184741411795380665971879359857054148639074247024960913011
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1791515719376698469617079693766539909308555413752126611802425055843694461100
Short name T119
Test name
Test status
Simulation time 33779291 ps
CPU time 0.77 seconds
Started Nov 22 01:02:49 PM PST 23
Finished Nov 22 01:02:51 PM PST 23
Peak memory 202904 kb
Host smart-421ea223-d705-4ea8-81ca-20429d125f37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791515719376698469617079693766539909308555
413752126611802425055843694461100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.17915157193766984696170796937
66539909308555413752126611802425055843694461100
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.88844539053217035893413502713014286566431342665121121578143476319292987452330
Short name T1628
Test name
Test status
Simulation time 28136479 ps
CPU time 0.63 seconds
Started Nov 22 01:02:48 PM PST 23
Finished Nov 22 01:02:50 PM PST 23
Peak memory 202764 kb
Host smart-13180c3f-f110-42ad-9666-583ab39d823f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88844539053217035893413502713014286566431342665121121578143476319292987452330 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.88844539053217035893413502713014286566431342665121121578143476319292987452330
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.58078214541915364915966963260592829556654065702946489130416628001947066733221
Short name T115
Test name
Test status
Simulation time 24422223 ps
CPU time 0.64 seconds
Started Nov 22 01:02:49 PM PST 23
Finished Nov 22 01:02:52 PM PST 23
Peak memory 202852 kb
Host smart-8e903bf1-f846-4824-8e62-0df6db087b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58078214541915364915966963260592829556654065702946489130416628001947066733221 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.i2c_intr_test.58078214541915364915966963260592829556654065702946489130416628001947066733221
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.44174879775081478541911476303567262047976284227419660315560848127296511064742
Short name T83
Test name
Test status
Simulation time 48993455 ps
CPU time 0.79 seconds
Started Nov 22 01:03:00 PM PST 23
Finished Nov 22 01:03:02 PM PST 23
Peak memory 202820 kb
Host smart-1691b04e-43e8-4895-a5fb-7b2d7a27120f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44174879775081478541911476303567262047976284227419660315560848127296511064742
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outstanding.44174879775081478541911476303567262047976284227419660315560848127296511064742
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.30892372442799015872965163391816242719621461489244892221036063794091572857168
Short name T1622
Test name
Test status
Simulation time 97278783 ps
CPU time 1.32 seconds
Started Nov 22 01:02:48 PM PST 23
Finished Nov 22 01:02:51 PM PST 23
Peak memory 203080 kb
Host smart-a2f10f18-e806-4f16-911d-cb0152b9b533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30892372442799015872965163391816242719621461489244892221036063794091572857168 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.i2c_tl_errors.30892372442799015872965163391816242719621461489244892221036063794091572857168
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.57179282726723498899468828611847387001262382374248591677337565479263263000326
Short name T1615
Test name
Test status
Simulation time 114885785 ps
CPU time 1.34 seconds
Started Nov 22 01:02:44 PM PST 23
Finished Nov 22 01:02:47 PM PST 23
Peak memory 202996 kb
Host smart-4737386b-1646-408f-be6c-414fb1a3389c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57179282726723498899468828611847387001262382374248591677337565479263263000326 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.57179282726723498899468828611847387001262382374248591677337565479263263000326
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.34397182323701446537224989536341723245576327193769794855552161804564971879716
Short name T1006
Test name
Test status
Simulation time 19975830 ps
CPU time 0.62 seconds
Started Nov 22 02:17:31 PM PST 23
Finished Nov 22 02:17:33 PM PST 23
Peak memory 202720 kb
Host smart-6c042d35-08e4-488f-9fa0-bb25fbc45d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34397182323701446537224989536341723245576327193769794855552161804564971879716 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_alert_test.34397182323701446537224989536341723245576327193769794855552161804564971879716
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.45348744139612291531447444032359932239657111297202025842524139115899368298728
Short name T548
Test name
Test status
Simulation time 74225396 ps
CPU time 1.37 seconds
Started Nov 22 02:17:45 PM PST 23
Finished Nov 22 02:17:47 PM PST 23
Peak memory 211112 kb
Host smart-fdca8141-d862-4728-8aa8-d63feb1902cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45348744139612291531447444032359932239657111297202025842524139115899368298728 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_host_error_intr.45348744139612291531447444032359932239657111297202025842524139115899368298728
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.107471972902088422510000468519973169343794117482568396841746777134891040052285
Short name T466
Test name
Test status
Simulation time 606667565 ps
CPU time 6.65 seconds
Started Nov 22 02:17:30 PM PST 23
Finished Nov 22 02:17:38 PM PST 23
Peak memory 273416 kb
Host smart-7835c3c3-ea5b-41b4-a868-205f1e284dc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107471972902088422510000468519973169343794117482568396841746777134891040052285 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.107471972902088422510000468519973169343794117482568396841746777134891040052285
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.106529199604722820447150983811515838412905060572050822172625697721067744144763
Short name T407
Test name
Test status
Simulation time 3768267272 ps
CPU time 71.87 seconds
Started Nov 22 02:18:08 PM PST 23
Finished Nov 22 02:19:21 PM PST 23
Peak memory 729484 kb
Host smart-0651dc57-65d5-44b9-a1fb-dd0ba6f7eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106529199604722820447150983811515838412905060572050822172625697721067744144763 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_host_fifo_full.106529199604722820447150983811515838412905060572050822172625697721067744144763
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.114773498314077457521859491173805710867091357059036898737839269040138825853509
Short name T1119
Test name
Test status
Simulation time 7925734012 ps
CPU time 234.8 seconds
Started Nov 22 02:17:49 PM PST 23
Finished Nov 22 02:21:44 PM PST 23
Peak memory 1271584 kb
Host smart-f6684a7b-22e7-4fa5-857b-f9e1ce8ec0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114773498314077457521859491173805710867091357059036898737839269040138825853509 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_host_fifo_overflow.114773498314077457521859491173805710867091357059036898737839269040138825853509
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.43506855643811977054486418096521936996786112941405053843301652080224296281596
Short name T656
Test name
Test status
Simulation time 209010032 ps
CPU time 0.94 seconds
Started Nov 22 02:17:40 PM PST 23
Finished Nov 22 02:17:41 PM PST 23
Peak memory 202912 kb
Host smart-095d7c6c-da98-4fe0-9ea6-07b25d7923a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43506855643811977054486418096521936996786112941405053843301652080224296281596 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.43506855643811977054486418096521936996786112941405053843301652080224296281596
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.61848208976632301265481389419248470250784945277252958399726942757944728628685
Short name T1380
Test name
Test status
Simulation time 236313385 ps
CPU time 3.81 seconds
Started Nov 22 02:17:30 PM PST 23
Finished Nov 22 02:17:35 PM PST 23
Peak memory 225464 kb
Host smart-4781e244-bd9e-4300-bda7-1f7d35700f93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61848208976632301265481389419248470250784945277252958399726942757944728628685 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.61848208976632301265481389419248470250784945277252958399726942757944728628685
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.45193386871356873251882105087529963110440853602559034754770290069397076379006
Short name T413
Test name
Test status
Simulation time 7918519784 ps
CPU time 205.4 seconds
Started Nov 22 02:17:15 PM PST 23
Finished Nov 22 02:20:43 PM PST 23
Peak memory 1310964 kb
Host smart-4948c7d8-0a4b-4ca5-bd72-d1b105533dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45193386871356873251882105087529963110440853602559034754770290069397076379006 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_host_fifo_watermark.45193386871356873251882105087529963110440853602559034754770290069397076379006
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.87781630506544196846904068875721090854896710642442338862332560416351147921680
Short name T1096
Test name
Test status
Simulation time 3754070957 ps
CPU time 53.96 seconds
Started Nov 22 02:17:29 PM PST 23
Finished Nov 22 02:18:23 PM PST 23
Peak memory 293796 kb
Host smart-596f6695-2f79-45be-a045-b8af316d0e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87781630506544196846904068875721090854896710642442338862332560416351147921680 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_host_mode_toggle.87781630506544196846904068875721090854896710642442338862332560416351147921680
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.107084117398938816730151271001240536855304891177553004272876166066484634560188
Short name T683
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:17:32 PM PST 23
Finished Nov 22 02:17:34 PM PST 23
Peak memory 202820 kb
Host smart-011dd14b-a173-4de0-b29c-52d1f4ebdb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107084117398938816730151271001240536855304891177553004272876166066484634560188 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_host_override.107084117398938816730151271001240536855304891177553004272876166066484634560188
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.9116636545117893800040240070164471836319057637459420460477669918873061288473
Short name T503
Test name
Test status
Simulation time 6830796343 ps
CPU time 65.99 seconds
Started Nov 22 02:17:17 PM PST 23
Finished Nov 22 02:18:24 PM PST 23
Peak memory 211364 kb
Host smart-68724712-5aa9-4a58-b50d-bfccd41cf4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9116636545117893800040240070164471836319057637459420460477669918873061288473 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.i2c_host_perf.9116636545117893800040240070164471836319057637459420460477669918873061288473
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_rx_oversample.106322525824037228306267118404999039563302901370486088592212662332466605353183
Short name T1512
Test name
Test status
Simulation time 3939158762 ps
CPU time 99.86 seconds
Started Nov 22 02:17:14 PM PST 23
Finished Nov 22 02:18:57 PM PST 23
Peak memory 345924 kb
Host smart-1ef639a0-467d-4e96-bf19-b56ab30c7dcc
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106322525824037228306267118404999039563302901370486088592212662332466605353183 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_rx_oversample.106322525824037228306267118404999039563302901370486088592212662332466605353183
Directory /workspace/0.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.24940456960726475125501497113519038918728170032544373556476248270591681038779
Short name T73
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.49 seconds
Started Nov 22 02:17:33 PM PST 23
Finished Nov 22 02:18:11 PM PST 23
Peak memory 299384 kb
Host smart-a0371b9f-8158-42bb-83f2-801dcc6a43cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24940456960726475125501497113519038918728170032544373556476248270591681038779 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.i2c_host_smoke.24940456960726475125501497113519038918728170032544373556476248270591681038779
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.91591691350891150198244570440564702915042211935333853313157436646510588834879
Short name T1116
Test name
Test status
Simulation time 32807463528 ps
CPU time 1048.91 seconds
Started Nov 22 02:17:49 PM PST 23
Finished Nov 22 02:35:19 PM PST 23
Peak memory 1957148 kb
Host smart-176a1e96-4b61-4194-8645-ff4376188632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91591691350891150198244570440564702915042211935333853313157436646510588834879 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_host_stress_all.91591691350891150198244570440564702915042211935333853313157436646510588834879
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.59304694695926416217135434995857780277238284094928381346646047080258532982099
Short name T965
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.32 seconds
Started Nov 22 02:17:45 PM PST 23
Finished Nov 22 02:17:59 PM PST 23
Peak memory 214148 kb
Host smart-e00bb5a5-a149-4ec2-bdf5-092736192616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59304694695926416217135434995857780277238284094928381346646047080258532982099 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_host_stretch_timeout.59304694695926416217135434995857780277238284094928381346646047080258532982099
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.102820579784157010298216141678760095866152007877901584252259277388104783066209
Short name T716
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.79 seconds
Started Nov 22 02:17:34 PM PST 23
Finished Nov 22 02:17:38 PM PST 23
Peak memory 203096 kb
Host smart-809a993c-0d8d-4c2d-af1c-2ba5168a0250
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028205797841570102982161416787
60095866152007877901584252259277388104783066209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.10282057978415701029821614
1678760095866152007877901584252259277388104783066209
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.12682739142852952622793388119667513630843277071046248403420477819224321968324
Short name T1105
Test name
Test status
Simulation time 10166144644 ps
CPU time 30.2 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:18:38 PM PST 23
Peak memory 382176 kb
Host smart-d5bec00c-5502-4b5c-a21b-c6c9cf38a7b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126827391428529526227933881196675136308432770710462
48403420477819224321968324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.12682739142852952622793388119667
513630843277071046248403420477819224321968324
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.6658886914158912483305008754274524932866018754537889610639703753578114729180
Short name T829
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.85 seconds
Started Nov 22 02:17:45 PM PST 23
Finished Nov 22 02:18:21 PM PST 23
Peak memory 463060 kb
Host smart-98035deb-4fe4-402c-a701-d96b62137d1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665888691415891248330500875427452493286601875453788
9610639703753578114729180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_tx.66588869141589124833050087542745249
32866018754537889610639703753578114729180
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.103003847813332115426494826938082623911237412461494679804859281325531867276933
Short name T905
Test name
Test status
Simulation time 825344371 ps
CPU time 2.45 seconds
Started Nov 22 02:18:08 PM PST 23
Finished Nov 22 02:18:11 PM PST 23
Peak memory 203080 kb
Host smart-521584dd-ab8b-4a6e-b04c-b395db8a5ff8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103003847813332115426494826938082623911237412461494
679804859281325531867276933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_hrst.103003847813332115426494826938082623911237412461494
679804859281325531867276933
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.46000783712073209651067538217765646411872939409657605524605376365774777001462
Short name T1448
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.3 seconds
Started Nov 22 02:17:40 PM PST 23
Finished Nov 22 02:17:45 PM PST 23
Peak memory 203752 kb
Host smart-e06c630d-a5ac-4612-9779-d131c5197fe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46000783712073209651067538217765646411872939409657
605524605376365774777001462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_smoke.46000783712073209651067538217765646411872939
409657605524605376365774777001462
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.100415991327318371080130837685434624024182521902005808220916438627994398505378
Short name T1306
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.03 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:18:32 PM PST 23
Peak memory 639292 kb
Host smart-db2db709-224d-4e99-a1ae-f8694ccd63c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10041599132731837108013083768543462402
4182521902005808220916438627994398505378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.10041599132731837108013
0837685434624024182521902005808220916438627994398505378
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.63044878044149924297842718687160867911573754354622628550800365104189507420978
Short name T733
Test name
Test status
Simulation time 834576440 ps
CPU time 3.09 seconds
Started Nov 22 02:17:33 PM PST 23
Finished Nov 22 02:17:37 PM PST 23
Peak memory 203076 kb
Host smart-3fe4515f-38a8-4b42-ba97-1f0dc1aa34e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630448780441499242978427186871608679115737543546226
28550800365104189507420978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_perf.6304487804414992429784271868716086791157375435462262
8550800365104189507420978
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.60340546282841756124721463032299872566837397531183496977614234163898825995673
Short name T553
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.3 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:18:19 PM PST 23
Peak memory 203028 kb
Host smart-125ddf95-19b8-4a68-9147-331cab25c764
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6034054628284175612472146303229987256683739753118349697761423416389882
5995673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smoke.60340546282841756124721463032299872566837397531183496977614234163898825995673
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.15215454530517038286574490219196038460552696363413832093323331410611860755547
Short name T1188
Test name
Test status
Simulation time 66540157934 ps
CPU time 1340.18 seconds
Started Nov 22 02:18:10 PM PST 23
Finished Nov 22 02:40:31 PM PST 23
Peak memory 6983556 kb
Host smart-c0b4826b-93ed-4394-9ab8-0467a5ad4108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15215454530517038286574490219196038460552696363413
832093323331410611860755547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_all.152154545305170382865744902191960384605
52696363413832093323331410611860755547
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.75599781224391916979612948439456004659707950817131422232600578286857744043845
Short name T412
Test name
Test status
Simulation time 997771563 ps
CPU time 8.74 seconds
Started Nov 22 02:18:08 PM PST 23
Finished Nov 22 02:18:17 PM PST 23
Peak memory 203080 kb
Host smart-3440372e-0161-40ab-b1aa-2d4dae21710e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7559978122439191697961294843945600465970795081713142223260057828685774
4043845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_rd.7559978122439191697961294843945600465970795081713142223260057
8286857744043845
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.32166214148595114739344933667832406480705068926719809556240377930897666776416
Short name T276
Test name
Test status
Simulation time 14461449567 ps
CPU time 81.55 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:19:30 PM PST 23
Peak memory 1542128 kb
Host smart-245856ea-95f8-48ee-b626-07eabfaceb44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216621414859511473934493366783240648070506892671980955624037793089766
6776416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_wr.3216621414859511473934493366783240648070506892671980955624037
7930897666776416
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.87267213350233352907324102588698658228154693468510376174027508094363305624501
Short name T7
Test name
Test status
Simulation time 6281818576 ps
CPU time 76.26 seconds
Started Nov 22 02:17:17 PM PST 23
Finished Nov 22 02:18:34 PM PST 23
Peak memory 930584 kb
Host smart-181dd632-ad74-4dbf-874a-dd9970ef986f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8726721335023335290732410258869865822815469346851037617402750809436330
5624501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stretch.87267213350233352907324102588698658228154693468510376174027508094363305624501
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.95440999684454008057883139433258850289736106250234966666761381979324489893209
Short name T1253
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.34 seconds
Started Nov 22 02:17:50 PM PST 23
Finished Nov 22 02:17:58 PM PST 23
Peak memory 212692 kb
Host smart-236cd732-b870-4be9-ba65-82322e2bf00a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954409996844540080578831394332588502897361062502349
66666761381979324489893209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_timeout.9544099968445400805788313943325885028973610625
0234966666761381979324489893209
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_ovf.75292457057166232155936986019824785123573944552315631401638079099975950425771
Short name T1391
Test name
Test status
Simulation time 5445414553 ps
CPU time 117.46 seconds
Started Nov 22 02:17:17 PM PST 23
Finished Nov 22 02:19:16 PM PST 23
Peak memory 406848 kb
Host smart-078b354f-d95a-426b-a1dd-38fe6e394cb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75292457057166232155936986019824785123573944552315
631401638079099975950425771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_tx_ovf.75292457057166232155936986019824785123573944552
315631401638079099975950425771
Directory /workspace/0.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.91898156915749146780965954909725909125792780125807039244301486575780959125597
Short name T1058
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.55 seconds
Started Nov 22 02:17:32 PM PST 23
Finished Nov 22 02:17:38 PM PST 23
Peak memory 205304 kb
Host smart-69c7444c-3efd-4430-82dd-96428d71a791
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918981569157491467809659549097259091257927801258070
39244301486575780959125597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_unexp_stop.918981569157491467809659549097259091257927
80125807039244301486575780959125597
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.74452353199744912951223234758511704797086882312873692353158272272572166273080
Short name T737
Test name
Test status
Simulation time 19975830 ps
CPU time 0.56 seconds
Started Nov 22 02:17:45 PM PST 23
Finished Nov 22 02:17:46 PM PST 23
Peak memory 202568 kb
Host smart-32f03ca0-a0c9-4390-b527-4c921aacf3af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74452353199744912951223234758511704797086882312873692353158272272572166273080 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_alert_test.74452353199744912951223234758511704797086882312873692353158272272572166273080
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.66750511372006450347843855295169222596824401458031316248397224767684291219798
Short name T179
Test name
Test status
Simulation time 74225396 ps
CPU time 1.36 seconds
Started Nov 22 02:17:33 PM PST 23
Finished Nov 22 02:17:36 PM PST 23
Peak memory 211244 kb
Host smart-6d2146c3-8e77-4888-bbdf-38b4461fe63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66750511372006450347843855295169222596824401458031316248397224767684291219798 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_host_error_intr.66750511372006450347843855295169222596824401458031316248397224767684291219798
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.38963143487643325329674301408198680625846616958107105629189376895425564338330
Short name T797
Test name
Test status
Simulation time 606667565 ps
CPU time 6.71 seconds
Started Nov 22 02:17:34 PM PST 23
Finished Nov 22 02:17:42 PM PST 23
Peak memory 273400 kb
Host smart-0740f8e2-5e68-4921-b969-caee2c21c533
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38963143487643325329674301408198680625846616958107105629189376895425564338330 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.38963143487643325329674301408198680625846616958107105629189376895425564338330
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.61441973441476528474224940430141932608127230362828192406770403529977228332272
Short name T746
Test name
Test status
Simulation time 3768267272 ps
CPU time 71.97 seconds
Started Nov 22 02:17:31 PM PST 23
Finished Nov 22 02:18:44 PM PST 23
Peak memory 729476 kb
Host smart-38619f17-b1b5-4fdd-b5ce-c9c55b396404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61441973441476528474224940430141932608127230362828192406770403529977228332272 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_host_fifo_full.61441973441476528474224940430141932608127230362828192406770403529977228332272
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.62697706593294520188214487914668781618102020266863940859112671959607312593113
Short name T1254
Test name
Test status
Simulation time 7925734012 ps
CPU time 239.62 seconds
Started Nov 22 02:17:45 PM PST 23
Finished Nov 22 02:21:46 PM PST 23
Peak memory 1271460 kb
Host smart-3d82a2b5-8447-4065-bdb5-172b1a00c620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62697706593294520188214487914668781618102020266863940859112671959607312593113 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.i2c_host_fifo_overflow.62697706593294520188214487914668781618102020266863940859112671959607312593113
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.33078824227464987682126729743351902707411379528140761114076067381005072255304
Short name T1345
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:18:08 PM PST 23
Finished Nov 22 02:18:09 PM PST 23
Peak memory 202884 kb
Host smart-cee69f40-2e15-48de-8204-3a7e79cf7559
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33078824227464987682126729743351902707411379528140761114076067381005072255304 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.33078824227464987682126729743351902707411379528140761114076067381005072255304
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.115642842962774650774353620580657847516210021877131077663767541207654278085251
Short name T1454
Test name
Test status
Simulation time 236313385 ps
CPU time 3.76 seconds
Started Nov 22 02:17:34 PM PST 23
Finished Nov 22 02:17:39 PM PST 23
Peak memory 225396 kb
Host smart-d72a6d2c-7c37-4ef8-a691-a2afccfea15f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115642842962774650774353620580657847516210021877131077663767541207654278085251 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.115642842962774650774353620580657847516210021877131077663767541207654278085251
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.56431616739454082396014485322773201975013465642619803193529646843813338889837
Short name T712
Test name
Test status
Simulation time 7918519784 ps
CPU time 196.45 seconds
Started Nov 22 02:17:46 PM PST 23
Finished Nov 22 02:21:03 PM PST 23
Peak memory 1310772 kb
Host smart-a3bca1fd-457e-44c3-993b-dc5a8740528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56431616739454082396014485322773201975013465642619803193529646843813338889837 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_host_fifo_watermark.56431616739454082396014485322773201975013465642619803193529646843813338889837
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.66841485693048616907019492858168824644294712078030415904546184426376804005692
Short name T1533
Test name
Test status
Simulation time 3754070957 ps
CPU time 53.15 seconds
Started Nov 22 02:17:40 PM PST 23
Finished Nov 22 02:18:34 PM PST 23
Peak memory 293740 kb
Host smart-f400aede-74a3-46d5-8208-6d8d45d4d5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66841485693048616907019492858168824644294712078030415904546184426376804005692 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_host_mode_toggle.66841485693048616907019492858168824644294712078030415904546184426376804005692
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.25882399250844879160962626549903034273135570836537443361664926866558463586032
Short name T1417
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:18:10 PM PST 23
Peak memory 202792 kb
Host smart-895847d9-52c3-4435-b3d3-b1dc2def71f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25882399250844879160962626549903034273135570836537443361664926866558463586032 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_host_override.25882399250844879160962626549903034273135570836537443361664926866558463586032
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.66589259399184855336640630058399549233981516158262745698522334661742713443709
Short name T436
Test name
Test status
Simulation time 6830796343 ps
CPU time 59.67 seconds
Started Nov 22 02:18:08 PM PST 23
Finished Nov 22 02:19:08 PM PST 23
Peak memory 211372 kb
Host smart-67cca81d-3fb4-4e01-83cf-26f4d284a19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66589259399184855336640630058399549233981516158262745698522334661742713443709 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.i2c_host_perf.66589259399184855336640630058399549233981516158262745698522334661742713443709
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_rx_oversample.50038049075408685545611155751662104194650784804252608868514190779971771858493
Short name T103
Test name
Test status
Simulation time 3939158762 ps
CPU time 109.53 seconds
Started Nov 22 02:17:33 PM PST 23
Finished Nov 22 02:19:23 PM PST 23
Peak memory 345976 kb
Host smart-136b7ca4-ae08-401f-b817-5d2163381a2b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50038049075408685545611155751662104194650784804252608868514190779971771858493 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_rx_oversample.50038049075408685545611155751662104194650784804252608868514190779971771858493
Directory /workspace/1.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.28007365664688802957920029215015576036471640184674399972717945822813305727401
Short name T1002
Test name
Test status
Simulation time 2343171530 ps
CPU time 34.23 seconds
Started Nov 22 02:17:33 PM PST 23
Finished Nov 22 02:18:09 PM PST 23
Peak memory 299388 kb
Host smart-05f03db2-ea40-47a4-8210-929580603149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28007365664688802957920029215015576036471640184674399972717945822813305727401 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.i2c_host_smoke.28007365664688802957920029215015576036471640184674399972717945822813305727401
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.57351583126384746463420388436590087168481932327516532309156581164871862589018
Short name T1427
Test name
Test status
Simulation time 32807463528 ps
CPU time 991.9 seconds
Started Nov 22 02:17:40 PM PST 23
Finished Nov 22 02:34:13 PM PST 23
Peak memory 1957152 kb
Host smart-47b8198e-3746-4477-988b-a9ec88bb3e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57351583126384746463420388436590087168481932327516532309156581164871862589018 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_host_stress_all.57351583126384746463420388436590087168481932327516532309156581164871862589018
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.40856676460511158009681804068414986567439512624237327496067835784252345382918
Short name T1273
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.33 seconds
Started Nov 22 02:17:34 PM PST 23
Finished Nov 22 02:17:48 PM PST 23
Peak memory 214096 kb
Host smart-d74396b3-3f8f-41f8-a1dd-8c5f7186be55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40856676460511158009681804068414986567439512624237327496067835784252345382918 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_host_stretch_timeout.40856676460511158009681804068414986567439512624237327496067835784252345382918
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.95818069501332486273783694549355039200471662539388246171835013429497280062018
Short name T42
Test name
Test status
Simulation time 62618346 ps
CPU time 0.84 seconds
Started Nov 22 02:17:45 PM PST 23
Finished Nov 22 02:17:47 PM PST 23
Peak memory 219824 kb
Host smart-90078573-27b0-428d-8585-584739433709
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95818069501332486273783694549355039200471662539388246171835013429497280062018 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_sec_cm.95818069501332486273783694549355039200471662539388246171835013429497280062018
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.69620873939780726506759645878391799894060803772996274346969585234571171350757
Short name T1547
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.77 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:18:11 PM PST 23
Peak memory 202852 kb
Host smart-2a78687d-933a-445d-88d0-4077f3fb150c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6962087393978072650675964587839
1799894060803772996274346969585234571171350757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.696208739397807265067596458
78391799894060803772996274346969585234571171350757
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.74346472064967616212915124390329048038613058870348340049543437020586694558858
Short name T1199
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.05 seconds
Started Nov 22 02:17:46 PM PST 23
Finished Nov 22 02:18:18 PM PST 23
Peak memory 382144 kb
Host smart-d01459ae-9961-44f5-b267-170fdbaead42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743464720649676162129151243903290480386130588703483
40049543437020586694558858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_acq.74346472064967616212915124390329
048038613058870348340049543437020586694558858
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3130974466042546914613876513723720775756972501587291102337111688016623108968
Short name T1218
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.74 seconds
Started Nov 22 02:17:41 PM PST 23
Finished Nov 22 02:18:19 PM PST 23
Peak memory 463168 kb
Host smart-a3584cc1-d43f-4be1-8f53-969609704ff9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313097446604254691461387651372372077575697250158729
1102337111688016623108968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_tx.31309744660425469146138765137237207
75756972501587291102337111688016623108968
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.54170369384435286314836229943978274884655111735663829448577984912706441920663
Short name T66
Test name
Test status
Simulation time 1417071796 ps
CPU time 3.98 seconds
Started Nov 22 02:17:31 PM PST 23
Finished Nov 22 02:17:36 PM PST 23
Peak memory 203344 kb
Host smart-21e6f991-9877-4681-828a-35a89a1ac0cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54170369384435286314836229943978274884655111735663829448577984912706441920663 -assert nop
ostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.54170369384435286314836229943978274884655111735663829448577984912706441920663
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.69529443505603903579599127844467216840716710058974199000077419831205910681709
Short name T1102
Test name
Test status
Simulation time 825344371 ps
CPU time 2.48 seconds
Started Nov 22 02:17:34 PM PST 23
Finished Nov 22 02:17:38 PM PST 23
Peak memory 203056 kb
Host smart-d2fbba65-f944-4fb9-aa26-f2f0a5cd3d5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695294435056039035795991278444672168407167100589741
99000077419831205910681709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_hrst.6952944350560390357959912784446721684071671005897419
9000077419831205910681709
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.40936109915530810805831955975774945513889949185939460494722311903338518276050
Short name T1358
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.35 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:18:14 PM PST 23
Peak memory 203816 kb
Host smart-0a75df11-0429-4243-a346-4277f9fb04ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40936109915530810805831955975774945513889949185939
460494722311903338518276050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_smoke.40936109915530810805831955975774945513889949
185939460494722311903338518276050
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.33653515259225942353050718763101363611882365778320984754989734135353993335834
Short name T252
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.51 seconds
Started Nov 22 02:17:31 PM PST 23
Finished Nov 22 02:17:53 PM PST 23
Peak memory 639248 kb
Host smart-702f5a5b-1dd4-4d52-b422-8291918d337c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33653515259225942353050718763101363611
882365778320984754989734135353993335834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.336535152592259423530507
18763101363611882365778320984754989734135353993335834
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.91875039577639234489516763263951238765736363935684868969323161671588026761394
Short name T758
Test name
Test status
Simulation time 834576440 ps
CPU time 3.05 seconds
Started Nov 22 02:17:42 PM PST 23
Finished Nov 22 02:17:45 PM PST 23
Peak memory 203004 kb
Host smart-5cfa3d10-f012-4367-b7dd-d7c6b7483e01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918750395776392344895167632639512387657363639356848
68969323161671588026761394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_perf.9187503957763923448951676326395123876573636393568486
8969323161671588026761394
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.15871515596215934158409286032495167549506139098242970768192304056394218658266
Short name T670
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.46 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:18:18 PM PST 23
Peak memory 203024 kb
Host smart-a46320d4-8b9c-4b23-a0c3-278f6cdf6e7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587151559621593415840928603249516754950613909824297076819230405639421
8658266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smoke.15871515596215934158409286032495167549506139098242970768192304056394218658266
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.73738140912134760416666536412652984303999564172639196528782164523958773453774
Short name T830
Test name
Test status
Simulation time 66540157934 ps
CPU time 1289.93 seconds
Started Nov 22 02:17:40 PM PST 23
Finished Nov 22 02:39:11 PM PST 23
Peak memory 6983624 kb
Host smart-08fcbe90-5837-4458-8328-512972895130
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73738140912134760416666536412652984303999564172639
196528782164523958773453774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_all.737381409121347604166665364126529843039
99564172639196528782164523958773453774
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.42423661395573315199630258900008834068675798161287847760106666789557375375902
Short name T1250
Test name
Test status
Simulation time 997771563 ps
CPU time 8.86 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:18:17 PM PST 23
Peak memory 203084 kb
Host smart-12c74592-c9e1-4e5d-bff7-e6eb75bfa531
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242366139557331519963025890000883406867579816128784776010666678955737
5375902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_rd.4242366139557331519963025890000883406867579816128784776010666
6789557375375902
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.56368548913146131353733332300920302985412107160670893808912160366060972374583
Short name T1074
Test name
Test status
Simulation time 14461449567 ps
CPU time 86.98 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:19:35 PM PST 23
Peak memory 1542128 kb
Host smart-7f32a24c-ed6d-4106-bbc5-d768423e7ad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5636854891314613135373333230092030298541210716067089380891216036606097
2374583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_wr.5636854891314613135373333230092030298541210716067089380891216
0366060972374583
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.54090564003892083751721343467780799882379710720441657360609725484432811030600
Short name T149
Test name
Test status
Simulation time 6281818576 ps
CPU time 78.06 seconds
Started Nov 22 02:17:35 PM PST 23
Finished Nov 22 02:18:54 PM PST 23
Peak memory 930580 kb
Host smart-422e16c6-728f-454b-9a87-8ffc874f5167
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5409056400389208375172134346778079988237971072044165736060972548443281
1030600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stretch.54090564003892083751721343467780799882379710720441657360609725484432811030600
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.26133908250533897136267138736275829409847497290256032708092508189271635761607
Short name T1436
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.48 seconds
Started Nov 22 02:17:45 PM PST 23
Finished Nov 22 02:17:53 PM PST 23
Peak memory 212488 kb
Host smart-aaa541a7-ed9f-472a-ac78-6c6ec62d5843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261339082505338971362671387362758294098474972902560
32708092508189271635761607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_timeout.2613390825053389713626713873627582940984749729
0256032708092508189271635761607
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_ovf.106870437804107063182625723195734904584614012610738069968364447841443699481212
Short name T775
Test name
Test status
Simulation time 5445414553 ps
CPU time 153.5 seconds
Started Nov 22 02:17:41 PM PST 23
Finished Nov 22 02:20:15 PM PST 23
Peak memory 406852 kb
Host smart-ebd7a036-7223-496b-b047-141754b5114d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10687043780410706318262572319573490458461401261073
8069968364447841443699481212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_tx_ovf.1068704378041070631826257231957349045846140126
10738069968364447841443699481212
Directory /workspace/1.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.60921128188369900586885966266874907975333477281311212763183930239012774839311
Short name T1150
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.5 seconds
Started Nov 22 02:17:47 PM PST 23
Finished Nov 22 02:17:53 PM PST 23
Peak memory 205292 kb
Host smart-d1dae12b-2916-442e-93e9-550f9b7094a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609211281883699005868859662668749079753334772813112
12763183930239012774839311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_unexp_stop.609211281883699005868859662668749079753334
77281311212763183930239012774839311
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_alert_test.65144259650645532275493429298846774931181403538394399536104658087648578708571
Short name T1325
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:19:52 PM PST 23
Finished Nov 22 02:19:54 PM PST 23
Peak memory 202728 kb
Host smart-735ff61e-d0c3-441f-bc08-8d01ebcf1cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65144259650645532275493429298846774931181403538394399536104658087648578708571 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_alert_test.65144259650645532275493429298846774931181403538394399536104658087648578708571
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.111123586583586652497865853151976688230080708540176040556581212436083613702603
Short name T1551
Test name
Test status
Simulation time 74225396 ps
CPU time 1.41 seconds
Started Nov 22 02:19:34 PM PST 23
Finished Nov 22 02:19:36 PM PST 23
Peak memory 211192 kb
Host smart-a693e345-3558-4fca-b707-66f9ade966b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111123586583586652497865853151976688230080708540176040556581212436083613702603 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_host_error_intr.111123586583586652497865853151976688230080708540176040556581212436083613702603
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.10959072600306393410145173592742446789804974145726266210975021740913323033307
Short name T766
Test name
Test status
Simulation time 606667565 ps
CPU time 6.71 seconds
Started Nov 22 02:19:29 PM PST 23
Finished Nov 22 02:19:38 PM PST 23
Peak memory 273320 kb
Host smart-7c68c308-8578-4d72-a5e0-9571b6832a17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10959072600306393410145173592742446789804974145726266210975021740913323033307 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.10959072600306393410145173592742446789804974145726266210975021740913323033307
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.94988507545579396235338148354942487138622420509746565396112199276429885339244
Short name T940
Test name
Test status
Simulation time 3768267272 ps
CPU time 67.88 seconds
Started Nov 22 02:19:20 PM PST 23
Finished Nov 22 02:20:29 PM PST 23
Peak memory 729224 kb
Host smart-0050bf3e-a7c4-4f97-961b-dda9af8b510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94988507545579396235338148354942487138622420509746565396112199276429885339244 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_host_fifo_full.94988507545579396235338148354942487138622420509746565396112199276429885339244
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.47983479155595629962085233664161953960919048677309085430308432850622148440880
Short name T597
Test name
Test status
Simulation time 7925734012 ps
CPU time 235.02 seconds
Started Nov 22 02:19:33 PM PST 23
Finished Nov 22 02:23:29 PM PST 23
Peak memory 1271608 kb
Host smart-c5ad8874-8e7e-432f-9ccf-3e01692239a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47983479155595629962085233664161953960919048677309085430308432850622148440880 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.i2c_host_fifo_overflow.47983479155595629962085233664161953960919048677309085430308432850622148440880
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.68101758008842671436986544492763398803852261461341011426667157242782372777372
Short name T668
Test name
Test status
Simulation time 209010032 ps
CPU time 0.96 seconds
Started Nov 22 02:19:36 PM PST 23
Finished Nov 22 02:19:38 PM PST 23
Peak memory 202912 kb
Host smart-20e4be16-d24f-47df-9dce-d98bcb0bb7ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68101758008842671436986544492763398803852261461341011426667157242782372777372 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.68101758008842671436986544492763398803852261461341011426667157242782372777372
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.35921399251597003242493201080068108542349744619908357402723057062560782966892
Short name T212
Test name
Test status
Simulation time 7918519784 ps
CPU time 202.34 seconds
Started Nov 22 02:19:33 PM PST 23
Finished Nov 22 02:22:56 PM PST 23
Peak memory 1310976 kb
Host smart-a58ad082-6817-4b06-8f2c-beee20621630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35921399251597003242493201080068108542349744619908357402723057062560782966892 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.i2c_host_fifo_watermark.35921399251597003242493201080068108542349744619908357402723057062560782966892
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.85327577796364578381902313214044999904641352368529478587180090543104250281861
Short name T919
Test name
Test status
Simulation time 3754070957 ps
CPU time 58.53 seconds
Started Nov 22 02:20:09 PM PST 23
Finished Nov 22 02:21:08 PM PST 23
Peak memory 293808 kb
Host smart-d2c6d04d-4dcb-4490-bc69-ae1b28f4e04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85327577796364578381902313214044999904641352368529478587180090543104250281861 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_host_mode_toggle.85327577796364578381902313214044999904641352368529478587180090543104250281861
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.5928699296912640281984054686341625547070352738802571196007674695673310901649
Short name T851
Test name
Test status
Simulation time 23672229 ps
CPU time 0.67 seconds
Started Nov 22 02:19:37 PM PST 23
Finished Nov 22 02:19:38 PM PST 23
Peak memory 202884 kb
Host smart-5d9b02aa-1f67-4719-8c69-74e2db241501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5928699296912640281984054686341625547070352738802571196007674695673310901649 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.i2c_host_override.5928699296912640281984054686341625547070352738802571196007674695673310901649
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.51808742747475611000893086022408436428414395116856037081568458098236938498778
Short name T1515
Test name
Test status
Simulation time 6830796343 ps
CPU time 62.9 seconds
Started Nov 22 02:19:34 PM PST 23
Finished Nov 22 02:20:37 PM PST 23
Peak memory 211304 kb
Host smart-9083a901-2e18-4122-b197-f7a046d787c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51808742747475611000893086022408436428414395116856037081568458098236938498778 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.i2c_host_perf.51808742747475611000893086022408436428414395116856037081568458098236938498778
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_rx_oversample.92833003157922189109302274036058809291474660892662152570935906864027418197954
Short name T1394
Test name
Test status
Simulation time 3939158762 ps
CPU time 114.89 seconds
Started Nov 22 02:19:32 PM PST 23
Finished Nov 22 02:21:27 PM PST 23
Peak memory 345912 kb
Host smart-6f6e8981-9412-43c9-a3a2-348d7b24062e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92833003157922189109302274036058809291474660892662152570935906864027418197954 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_rx_oversample.92833003157922189109302274036058809291474660892662152570935906864027418197954
Directory /workspace/10.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.89257018965069028251265149420518824236751384206838783606447430801939961135931
Short name T692
Test name
Test status
Simulation time 2343171530 ps
CPU time 39.7 seconds
Started Nov 22 02:19:22 PM PST 23
Finished Nov 22 02:20:07 PM PST 23
Peak memory 299416 kb
Host smart-5e76f541-b118-43b6-96f3-2246a1c9c2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89257018965069028251265149420518824236751384206838783606447430801939961135931 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.i2c_host_smoke.89257018965069028251265149420518824236751384206838783606447430801939961135931
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.70924979279657494568034046013626147059863081815804380733841414940551480189473
Short name T907
Test name
Test status
Simulation time 32807463528 ps
CPU time 1148.87 seconds
Started Nov 22 02:19:32 PM PST 23
Finished Nov 22 02:38:42 PM PST 23
Peak memory 1957096 kb
Host smart-263dcaf5-9691-4ec8-80ea-d0c24d1a43cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70924979279657494568034046013626147059863081815804380733841414940551480189473 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_host_stress_all.70924979279657494568034046013626147059863081815804380733841414940551480189473
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.59224950336437435005847130140458861697274843981844540935130644719303786555660
Short name T1386
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.28 seconds
Started Nov 22 02:19:33 PM PST 23
Finished Nov 22 02:19:47 PM PST 23
Peak memory 214216 kb
Host smart-807a5d93-1895-46c6-9124-36d41083613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59224950336437435005847130140458861697274843981844540935130644719303786555660 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_host_stretch_timeout.59224950336437435005847130140458861697274843981844540935130644719303786555660
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.14628406510131627822757859876260761278535068700336912745335270266036952813038
Short name T516
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.19 seconds
Started Nov 22 02:19:51 PM PST 23
Finished Nov 22 02:20:22 PM PST 23
Peak memory 382204 kb
Host smart-64b8ee82-824e-49a4-bd99-d554dca19b86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146284065101316278227578598762607612785350687003369
12745335270266036952813038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.1462840651013162782275785987626
0761278535068700336912745335270266036952813038
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.68753654270168073542288842762377362762383048627337505600820128236226823315592
Short name T866
Test name
Test status
Simulation time 10065199023 ps
CPU time 35.03 seconds
Started Nov 22 02:20:08 PM PST 23
Finished Nov 22 02:20:44 PM PST 23
Peak memory 461972 kb
Host smart-29d0b374-e53e-4d4b-817c-d1cf50b0d5b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687536542701680735422888427623773627623830486273375
05600820128236226823315592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_tx.687536542701680735422888427623773
62762383048627337505600820128236226823315592
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.63341959134494791558756911547842906765808358878881559531705327901283535127220
Short name T645
Test name
Test status
Simulation time 825344371 ps
CPU time 2.46 seconds
Started Nov 22 02:19:51 PM PST 23
Finished Nov 22 02:19:55 PM PST 23
Peak memory 203084 kb
Host smart-21e74a7e-ba25-4291-afa5-19ee16b0f586
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633419591344947915587569115478429067658083588788815
59531705327901283535127220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_hrst.633419591344947915587569115478429067658083588788815
59531705327901283535127220
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.57076006587721097643816651702360858805881184067328928616285395775365459740569
Short name T502
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.23 seconds
Started Nov 22 02:20:00 PM PST 23
Finished Nov 22 02:20:05 PM PST 23
Peak memory 203768 kb
Host smart-44f50120-7c0f-4b81-a017-f567caaddae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57076006587721097643816651702360858805881184067328
928616285395775365459740569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_smoke.5707600658772109764381665170236085880588118
4067328928616285395775365459740569
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.65232725015315337360473721139314575297014844417418786933796079714425500451212
Short name T223
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.72 seconds
Started Nov 22 02:20:08 PM PST 23
Finished Nov 22 02:20:33 PM PST 23
Peak memory 639244 kb
Host smart-8e273ea3-b2a7-4629-aa28-5e5ac213895e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65232725015315337360473721139314575297
014844417418786933796079714425500451212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.65232725015315337360473
721139314575297014844417418786933796079714425500451212
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.18192130268193592348461703415020218280771228112399295981276130524619467544793
Short name T1077
Test name
Test status
Simulation time 834576440 ps
CPU time 3.02 seconds
Started Nov 22 02:19:51 PM PST 23
Finished Nov 22 02:19:54 PM PST 23
Peak memory 203068 kb
Host smart-6418fd06-be01-46b8-bd44-761412b3a198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181921302681935923484617034150202182807712281123992
95981276130524619467544793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_perf.181921302681935923484617034150202182807712281123992
95981276130524619467544793
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.54986504509458539758267370754391586322825731238262483236373150956728335666165
Short name T1055
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.33 seconds
Started Nov 22 02:19:26 PM PST 23
Finished Nov 22 02:19:37 PM PST 23
Peak memory 202972 kb
Host smart-9166b13d-dd78-4ad5-8e9f-b7827ff422d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5498650450945853975826737075439158632282573123826248323637315095672833
5666165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smoke.54986504509458539758267370754391586322825731238262483236373150956728335666165
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.64126382866961664419114505500376535301886186872975180136881010249552063905828
Short name T19
Test name
Test status
Simulation time 66540157934 ps
CPU time 1443.95 seconds
Started Nov 22 02:19:57 PM PST 23
Finished Nov 22 02:44:02 PM PST 23
Peak memory 6983440 kb
Host smart-4f976236-7043-4a0f-b36e-fb13467f952c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64126382866961664419114505500376535301886186872975
180136881010249552063905828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_all.64126382866961664419114505500376535301
886186872975180136881010249552063905828
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.15998037222662748130892174681309953871972716493946555077450283750081249083924
Short name T291
Test name
Test status
Simulation time 997771563 ps
CPU time 8.89 seconds
Started Nov 22 02:19:51 PM PST 23
Finished Nov 22 02:20:01 PM PST 23
Peak memory 203048 kb
Host smart-7b495516-655a-452f-ab17-548af16f7dd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599803722266274813089217468130995387197271649394655507745028375008124
9083924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_rd.159980372226627481308921746813099538719727164939465550774502
83750081249083924
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.60485519546776186988904046016993583820657361058419870493414784230052233479819
Short name T1315
Test name
Test status
Simulation time 14461449567 ps
CPU time 79.09 seconds
Started Nov 22 02:19:51 PM PST 23
Finished Nov 22 02:21:11 PM PST 23
Peak memory 1542036 kb
Host smart-54614c59-e69c-4e2f-9323-64cbb2c1f6f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6048551954677618698890404601699358382065736105841987049341478423005223
3479819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_wr.604855195467761869889040460169935838206573610584198704934147
84230052233479819
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.109613365764613133068386919772643372516919869713212783900372310288989598296229
Short name T1088
Test name
Test status
Simulation time 6281818576 ps
CPU time 73.72 seconds
Started Nov 22 02:20:06 PM PST 23
Finished Nov 22 02:21:21 PM PST 23
Peak memory 930572 kb
Host smart-f1497b53-78ba-4789-8e18-7d458705710f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096133657646131330683869197726433725169198697132127839003723102889895
98296229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stretch.109613365764613133068386919772643372516919869713212783900372310
288989598296229
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.18365923757135743222256683391573160854032180594882327054797887263767617860783
Short name T186
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.44 seconds
Started Nov 22 02:19:52 PM PST 23
Finished Nov 22 02:20:01 PM PST 23
Peak memory 212632 kb
Host smart-b01278b1-8898-47cd-b591-717a3b3b11e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183659237571357432222566833915731608540321805948823
27054797887263767617860783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.183659237571357432222566833915731608540321805
94882327054797887263767617860783
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_ovf.35057110798916721428013286266928709351358507021092720193681232456887712121716
Short name T1564
Test name
Test status
Simulation time 5445414553 ps
CPU time 129.68 seconds
Started Nov 22 02:19:51 PM PST 23
Finished Nov 22 02:22:02 PM PST 23
Peak memory 406860 kb
Host smart-214d5fae-d3e3-4730-b132-0fe3cd3725f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35057110798916721428013286266928709351358507021092
720193681232456887712121716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_tx_ovf.3505711079891672142801328626692870935135850702
1092720193681232456887712121716
Directory /workspace/10.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/10.i2c_target_unexp_stop.108537109263702462262961776009102277884096753308574346834694347578316663082248
Short name T414
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.68 seconds
Started Nov 22 02:19:52 PM PST 23
Finished Nov 22 02:19:59 PM PST 23
Peak memory 205296 kb
Host smart-3a7d3e16-4e5e-4718-81b5-454a8c1847dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108537109263702462262961776009102277884096753308574
346834694347578316663082248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_unexp_stop.1085371092637024622629617760091022778840
96753308574346834694347578316663082248
Directory /workspace/10.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.48585305222490202845065421676755287914694273639944535749623290226553536048469
Short name T896
Test name
Test status
Simulation time 74225396 ps
CPU time 1.35 seconds
Started Nov 22 02:19:50 PM PST 23
Finished Nov 22 02:19:52 PM PST 23
Peak memory 211248 kb
Host smart-8598b3a3-8b8e-48ee-be76-1364329168c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48585305222490202845065421676755287914694273639944535749623290226553536048469 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_host_error_intr.48585305222490202845065421676755287914694273639944535749623290226553536048469
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.83053500133915032361622763098063689551668311819733408393432837680862678526162
Short name T1431
Test name
Test status
Simulation time 606667565 ps
CPU time 6.85 seconds
Started Nov 22 02:20:44 PM PST 23
Finished Nov 22 02:20:52 PM PST 23
Peak memory 273308 kb
Host smart-3ccadd09-45a7-4e6a-b9e5-cf009b592d07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83053500133915032361622763098063689551668311819733408393432837680862678526162 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.83053500133915032361622763098063689551668311819733408393432837680862678526162
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.89941443422275518823517298711711707300823202378913018900149100292735286944946
Short name T1068
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.04 seconds
Started Nov 22 02:20:07 PM PST 23
Finished Nov 22 02:21:22 PM PST 23
Peak memory 729376 kb
Host smart-73829db8-cbe4-47ef-8055-3c5eec52f4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89941443422275518823517298711711707300823202378913018900149100292735286944946 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_host_fifo_full.89941443422275518823517298711711707300823202378913018900149100292735286944946
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.113258392925139739283159955965021370335783926324056665085358862455842100997912
Short name T487
Test name
Test status
Simulation time 7925734012 ps
CPU time 251.03 seconds
Started Nov 22 02:19:52 PM PST 23
Finished Nov 22 02:24:04 PM PST 23
Peak memory 1271584 kb
Host smart-8e27f0f3-0657-413f-9d48-768cde01f000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113258392925139739283159955965021370335783926324056665085358862455842100997912 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_host_fifo_overflow.113258392925139739283159955965021370335783926324056665085358862455842100997912
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.114277003798202549144542192866708357776123738385744623789946689108505115342882
Short name T458
Test name
Test status
Simulation time 209010032 ps
CPU time 0.93 seconds
Started Nov 22 02:19:59 PM PST 23
Finished Nov 22 02:20:01 PM PST 23
Peak memory 202948 kb
Host smart-467b71ce-07e1-4a24-9954-860b93f325cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114277003798202549144542192866708357776123738385744623789946689108505115342882 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.114277003798202549144542192866708357776123738385744623789946689108505115342882
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.91431771691545992989796109652380905148786908122008100526395023374381924133904
Short name T1209
Test name
Test status
Simulation time 236313385 ps
CPU time 3.82 seconds
Started Nov 22 02:19:51 PM PST 23
Finished Nov 22 02:19:56 PM PST 23
Peak memory 225404 kb
Host smart-b23e7091-6ff8-405d-a697-d9600cd92163
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91431771691545992989796109652380905148786908122008100526395023374381924133904 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.91431771691545992989796109652380905148786908122008100526395023374381924133904
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.92163823223079157370706748406314192329411414099589718981598601947097234643694
Short name T494
Test name
Test status
Simulation time 7918519784 ps
CPU time 233.93 seconds
Started Nov 22 02:19:51 PM PST 23
Finished Nov 22 02:23:46 PM PST 23
Peak memory 1311072 kb
Host smart-56e5c49c-1e44-42cc-9268-e3ab1f5ed748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92163823223079157370706748406314192329411414099589718981598601947097234643694 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_host_fifo_watermark.92163823223079157370706748406314192329411414099589718981598601947097234643694
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.88135099260754413748124470935201874617327967616821557401977119127563271251038
Short name T1229
Test name
Test status
Simulation time 3754070957 ps
CPU time 57.81 seconds
Started Nov 22 02:20:07 PM PST 23
Finished Nov 22 02:21:06 PM PST 23
Peak memory 293708 kb
Host smart-2e511ea3-5fb7-45fc-a7fe-807d21d17855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88135099260754413748124470935201874617327967616821557401977119127563271251038 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_host_mode_toggle.88135099260754413748124470935201874617327967616821557401977119127563271251038
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.67037513665688056180420691947864294662360709697900300524180926614532834084818
Short name T1320
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:19:49 PM PST 23
Finished Nov 22 02:19:50 PM PST 23
Peak memory 202756 kb
Host smart-793467f5-b2e4-4ba1-a917-25291ff4e1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67037513665688056180420691947864294662360709697900300524180926614532834084818 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_host_override.67037513665688056180420691947864294662360709697900300524180926614532834084818
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_rx_oversample.108019876083962746862244570790011636325910444219792866414804778269671963995889
Short name T1092
Test name
Test status
Simulation time 3939158762 ps
CPU time 95.4 seconds
Started Nov 22 02:19:52 PM PST 23
Finished Nov 22 02:21:28 PM PST 23
Peak memory 346064 kb
Host smart-c488491d-0358-448d-94ab-0e87e0a2190e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108019876083962746862244570790011636325910444219792866414804778269671963995889 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_rx_oversample.108019876083962746862244570790011636325910444219792866414804778269671963995889
Directory /workspace/11.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.22183650728575099583673655797751424034554035991638425561996526308704062063372
Short name T1015
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.69 seconds
Started Nov 22 02:20:07 PM PST 23
Finished Nov 22 02:20:45 PM PST 23
Peak memory 299432 kb
Host smart-7ddbc9ff-abc8-40f9-85c8-451337bccb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22183650728575099583673655797751424034554035991638425561996526308704062063372 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.i2c_host_smoke.22183650728575099583673655797751424034554035991638425561996526308704062063372
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.63779518906701470432147992782828295711901670567644736870801872549517863201105
Short name T1355
Test name
Test status
Simulation time 32807463528 ps
CPU time 1010.85 seconds
Started Nov 22 02:20:08 PM PST 23
Finished Nov 22 02:37:00 PM PST 23
Peak memory 1957124 kb
Host smart-3de3fef5-98df-4acd-8c8b-e4454ebb17ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63779518906701470432147992782828295711901670567644736870801872549517863201105 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_host_stress_all.63779518906701470432147992782828295711901670567644736870801872549517863201105
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1279795735994348156038490072394724798745012943131670968284939595697732411748
Short name T1344
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.9 seconds
Started Nov 22 02:19:51 PM PST 23
Finished Nov 22 02:20:06 PM PST 23
Peak memory 214172 kb
Host smart-939b063a-3b1a-4619-9102-697490956700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279795735994348156038490072394724798745012943131670968284939595697732411748 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_host_stretch_timeout.1279795735994348156038490072394724798745012943131670968284939595697732411748
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.77229843687718240779319603142770083896948627455143755199266526425436305640814
Short name T1356
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.92 seconds
Started Nov 22 02:19:52 PM PST 23
Finished Nov 22 02:19:57 PM PST 23
Peak memory 203012 kb
Host smart-84a41668-203c-4cd6-bedb-b5de830b62cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7722984368771824077931960314277
0083896948627455143755199266526425436305640814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.77229843687718240779319603
142770083896948627455143755199266526425436305640814
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.48838540595652370682589806984306823079781842415788541434273208262018407633417
Short name T1181
Test name
Test status
Simulation time 10166144644 ps
CPU time 33.84 seconds
Started Nov 22 02:19:50 PM PST 23
Finished Nov 22 02:20:25 PM PST 23
Peak memory 382088 kb
Host smart-40fae7da-8a40-4969-9742-e134e812ecef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488385405956523706825898069843068230797818424157885
41434273208262018407633417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.4883854059565237068258980698430
6823079781842415788541434273208262018407633417
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.77761022614988098372629589543064286014378191362230470207758282319074139175324
Short name T750
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.87 seconds
Started Nov 22 02:19:49 PM PST 23
Finished Nov 22 02:20:24 PM PST 23
Peak memory 462148 kb
Host smart-0815396c-1400-4790-be7f-52a1b52a9083
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777610226149880983726295895430642860143781913622304
70207758282319074139175324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_tx.777610226149880983726295895430642
86014378191362230470207758282319074139175324
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.5528479666160668833848626464488585529831101853618037561422361612460706233452
Short name T324
Test name
Test status
Simulation time 825344371 ps
CPU time 2.4 seconds
Started Nov 22 02:20:10 PM PST 23
Finished Nov 22 02:20:13 PM PST 23
Peak memory 202904 kb
Host smart-64ce4a48-1018-4375-8fcb-c3dc38d32f80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552847966616066883384862646448858552983110185361803
7561422361612460706233452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_hrst.5528479666160668833848626464488585529831101853618037
561422361612460706233452
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.46007911439065232266691960458964444318270090490637263571278796950065817762325
Short name T1094
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.2 seconds
Started Nov 22 02:20:06 PM PST 23
Finished Nov 22 02:20:11 PM PST 23
Peak memory 203572 kb
Host smart-5ed9393b-0d14-4a11-866b-72a82d5d07ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46007911439065232266691960458964444318270090490637
263571278796950065817762325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.4600791143906523226669196045896444431827009
0490637263571278796950065817762325
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.12504982068107052463568126728875458345436039562406059158671944405796725428965
Short name T813
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.02 seconds
Started Nov 22 02:20:06 PM PST 23
Finished Nov 22 02:20:30 PM PST 23
Peak memory 639192 kb
Host smart-b7b7dff8-7108-4513-b9e6-5bec74eb346f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12504982068107052463568126728875458345
436039562406059158671944405796725428965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.12504982068107052463568
126728875458345436039562406059158671944405796725428965
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.95180785561503672108809974895418733155344837222754689883221319061472452032326
Short name T1230
Test name
Test status
Simulation time 834576440 ps
CPU time 3.02 seconds
Started Nov 22 02:19:52 PM PST 23
Finished Nov 22 02:19:56 PM PST 23
Peak memory 203160 kb
Host smart-20b4cab1-3471-4b78-b7ce-f1680f78ff25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951807855615036721088099748954187331553448372227546
89883221319061472452032326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_perf.951807855615036721088099748954187331553448372227546
89883221319061472452032326
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.68355213575536624506581725749748022710116912257482672962818847002841039348924
Short name T781
Test name
Test status
Simulation time 1504713936 ps
CPU time 10.07 seconds
Started Nov 22 02:20:11 PM PST 23
Finished Nov 22 02:20:22 PM PST 23
Peak memory 203056 kb
Host smart-c04f1b6c-d1dc-484e-b61f-a0e03f44e05b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6835521357553662450658172574974802271011691225748267296281884700284103
9348924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smoke.68355213575536624506581725749748022710116912257482672962818847002841039348924
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.88740893007808543037738251303999221182015265816452935476368287708763504315137
Short name T1090
Test name
Test status
Simulation time 66540157934 ps
CPU time 1400.14 seconds
Started Nov 22 02:20:06 PM PST 23
Finished Nov 22 02:43:27 PM PST 23
Peak memory 6983436 kb
Host smart-82e3b15f-9323-404e-a8b3-4ae4213b7ba2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88740893007808543037738251303999221182015265816452
935476368287708763504315137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_all.88740893007808543037738251303999221182
015265816452935476368287708763504315137
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.71898256835447598923167284347678202188687311602191693118602117680023624160381
Short name T1004
Test name
Test status
Simulation time 997771563 ps
CPU time 8.53 seconds
Started Nov 22 02:19:52 PM PST 23
Finished Nov 22 02:20:02 PM PST 23
Peak memory 203056 kb
Host smart-459d7297-2ce7-4240-91df-09cc3942e320
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7189825683544759892316728434767820218868731160219169311860211768002362
4160381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_rd.718982568354475989231672843476782021886873116021916931186021
17680023624160381
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.16889119224386169314700664216908848410917718947206707583941066784636610034899
Short name T13
Test name
Test status
Simulation time 14461449567 ps
CPU time 100.09 seconds
Started Nov 22 02:20:06 PM PST 23
Finished Nov 22 02:21:47 PM PST 23
Peak memory 1542100 kb
Host smart-e192025b-f3f0-4e99-b2d4-89cef7b2486c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688911922438616931470066421690884841091771894720670758394106678463661
0034899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_wr.168891192243861693147006642169088484109177189472067075839410
66784636610034899
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.102558353555695533832247927586180697143691119935168694785372629887405722289868
Short name T523
Test name
Test status
Simulation time 6281818576 ps
CPU time 74.91 seconds
Started Nov 22 02:20:28 PM PST 23
Finished Nov 22 02:21:43 PM PST 23
Peak memory 930496 kb
Host smart-be1acd81-0a4d-4b44-a464-7de46a43aab6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025583535556955338322479275861806971436911199351686947853726298874057
22289868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stretch.102558353555695533832247927586180697143691119935168694785372629
887405722289868
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.74512977081325090214344314661628099004360760808621025646938114224293248276225
Short name T195
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.19 seconds
Started Nov 22 02:19:50 PM PST 23
Finished Nov 22 02:19:58 PM PST 23
Peak memory 212520 kb
Host smart-a194ec21-28de-4e5a-beec-9c8e66becf98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745129770813250902143443146616280990043607608086210
25646938114224293248276225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_timeout.745129770813250902143443146616280990043607608
08621025646938114224293248276225
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_ovf.45699718568749526232249633184941266769597999179697066712790521764970597560801
Short name T1228
Test name
Test status
Simulation time 5445414553 ps
CPU time 144.01 seconds
Started Nov 22 02:20:07 PM PST 23
Finished Nov 22 02:22:32 PM PST 23
Peak memory 406748 kb
Host smart-c2e6fe65-4625-4981-9429-69115e711063
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45699718568749526232249633184941266769597999179697
066712790521764970597560801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_tx_ovf.4569971856874952623224963318494126676959799917
9697066712790521764970597560801
Directory /workspace/11.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/11.i2c_target_unexp_stop.33917382536794237908480010098449250865428838869735483309577897569529624479324
Short name T922
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.66 seconds
Started Nov 22 02:20:11 PM PST 23
Finished Nov 22 02:20:17 PM PST 23
Peak memory 205348 kb
Host smart-d14c3901-fbb8-4312-bcc2-66c7ad9a36b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339173825367942379084800100984492508654288388697354
83309577897569529624479324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_unexp_stop.33917382536794237908480010098449250865428
838869735483309577897569529624479324
Directory /workspace/11.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/12.i2c_alert_test.37231263203193213768484142136355105284238416922443702307937080863723892429151
Short name T1
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:20:07 PM PST 23
Finished Nov 22 02:20:08 PM PST 23
Peak memory 202664 kb
Host smart-8cbbc742-d5cd-4907-906f-a066774ca771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37231263203193213768484142136355105284238416922443702307937080863723892429151 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_alert_test.37231263203193213768484142136355105284238416922443702307937080863723892429151
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.101580338387759198701696636530482859293882528452486581684099073599732293620625
Short name T396
Test name
Test status
Simulation time 74225396 ps
CPU time 1.41 seconds
Started Nov 22 02:20:08 PM PST 23
Finished Nov 22 02:20:10 PM PST 23
Peak memory 211284 kb
Host smart-0d304f38-3681-4a71-8e3b-1ff89891a31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101580338387759198701696636530482859293882528452486581684099073599732293620625 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_host_error_intr.101580338387759198701696636530482859293882528452486581684099073599732293620625
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.25470924617359976298441729492978031433381732849994744844140172997298887231147
Short name T319
Test name
Test status
Simulation time 606667565 ps
CPU time 6.99 seconds
Started Nov 22 02:20:11 PM PST 23
Finished Nov 22 02:20:18 PM PST 23
Peak memory 273452 kb
Host smart-3cc271de-9a4c-404d-9131-12166de1a424
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25470924617359976298441729492978031433381732849994744844140172997298887231147 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.25470924617359976298441729492978031433381732849994744844140172997298887231147
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.14700587872771570207852265612881392394176609735590623396418446029092818849355
Short name T198
Test name
Test status
Simulation time 3768267272 ps
CPU time 75.1 seconds
Started Nov 22 02:20:43 PM PST 23
Finished Nov 22 02:21:58 PM PST 23
Peak memory 729504 kb
Host smart-d675928d-4189-45de-a2ef-0531421366db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14700587872771570207852265612881392394176609735590623396418446029092818849355 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_host_fifo_full.14700587872771570207852265612881392394176609735590623396418446029092818849355
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.7388368520336755940724017223998877519043142736047538828106789732399928942433
Short name T1261
Test name
Test status
Simulation time 7925734012 ps
CPU time 229.73 seconds
Started Nov 22 02:20:29 PM PST 23
Finished Nov 22 02:24:20 PM PST 23
Peak memory 1271640 kb
Host smart-6a7d169d-eaa1-4797-ab2f-7e53a66a3b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7388368520336755940724017223998877519043142736047538828106789732399928942433 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_host_fifo_overflow.7388368520336755940724017223998877519043142736047538828106789732399928942433
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.56266199796556204538390338994909041914421498445874779679708530620534601681941
Short name T1470
Test name
Test status
Simulation time 209010032 ps
CPU time 1.03 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:20:49 PM PST 23
Peak memory 202976 kb
Host smart-df9a9d17-1a93-43e0-96d8-ac05ff77ff50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56266199796556204538390338994909041914421498445874779679708530620534601681941 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.56266199796556204538390338994909041914421498445874779679708530620534601681941
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.50326783995698662580342653068815473651917861985851276895855635029342212054670
Short name T266
Test name
Test status
Simulation time 236313385 ps
CPU time 3.91 seconds
Started Nov 22 02:20:42 PM PST 23
Finished Nov 22 02:20:46 PM PST 23
Peak memory 225420 kb
Host smart-d7301958-2df9-458e-90bb-bc768d4853df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50326783995698662580342653068815473651917861985851276895855635029342212054670 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.50326783995698662580342653068815473651917861985851276895855635029342212054670
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.85408954707825670428680029339091424456550629747338260727965654422025888863049
Short name T908
Test name
Test status
Simulation time 7918519784 ps
CPU time 210.95 seconds
Started Nov 22 02:20:15 PM PST 23
Finished Nov 22 02:23:47 PM PST 23
Peak memory 1310960 kb
Host smart-c9d9d5f8-e485-4921-a3e7-50dadfdf8535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85408954707825670428680029339091424456550629747338260727965654422025888863049 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.i2c_host_fifo_watermark.85408954707825670428680029339091424456550629747338260727965654422025888863049
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.104928944385953693728159478792364772813671513946794247861851149499136183565558
Short name T660
Test name
Test status
Simulation time 3754070957 ps
CPU time 52.25 seconds
Started Nov 22 02:19:54 PM PST 23
Finished Nov 22 02:20:47 PM PST 23
Peak memory 293768 kb
Host smart-c5011445-0cec-42e8-b2b3-f47710f0c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104928944385953693728159478792364772813671513946794247861851149499136183565558 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_host_mode_toggle.104928944385953693728159478792364772813671513946794247861851149499136183565558
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.82347337081050965597888911945463274013016429027576146427114641364118695485815
Short name T988
Test name
Test status
Simulation time 23672229 ps
CPU time 0.67 seconds
Started Nov 22 02:20:43 PM PST 23
Finished Nov 22 02:20:44 PM PST 23
Peak memory 202808 kb
Host smart-f98c57da-4534-4f4e-9ccd-4535a68c4c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82347337081050965597888911945463274013016429027576146427114641364118695485815 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_host_override.82347337081050965597888911945463274013016429027576146427114641364118695485815
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.43486119422427858248877158040196233574862261355587272639183042025006575173380
Short name T984
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.38 seconds
Started Nov 22 02:20:45 PM PST 23
Finished Nov 22 02:21:46 PM PST 23
Peak memory 211440 kb
Host smart-655b7531-2371-41fd-add7-a64e32cf0b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43486119422427858248877158040196233574862261355587272639183042025006575173380 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.i2c_host_perf.43486119422427858248877158040196233574862261355587272639183042025006575173380
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_rx_oversample.79140668578662150893861148318981531895255709881263057025620742549078833138093
Short name T439
Test name
Test status
Simulation time 3939158762 ps
CPU time 99.13 seconds
Started Nov 22 02:20:44 PM PST 23
Finished Nov 22 02:22:24 PM PST 23
Peak memory 345944 kb
Host smart-d0a20abf-9fb6-4d19-9dcf-3b1e2fa30bd3
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79140668578662150893861148318981531895255709881263057025620742549078833138093 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_rx_oversample.79140668578662150893861148318981531895255709881263057025620742549078833138093
Directory /workspace/12.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.65342113832730071956786194910469153814875802769640444524647050998444891371069
Short name T935
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.61 seconds
Started Nov 22 02:20:07 PM PST 23
Finished Nov 22 02:20:46 PM PST 23
Peak memory 299404 kb
Host smart-f3da36ea-ec8d-4834-a9a3-3656518a96af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65342113832730071956786194910469153814875802769640444524647050998444891371069 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.i2c_host_smoke.65342113832730071956786194910469153814875802769640444524647050998444891371069
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.100859213337601189334134844828876164228554232489339359941122174006315334558692
Short name T799
Test name
Test status
Simulation time 32807463528 ps
CPU time 1052.79 seconds
Started Nov 22 02:20:43 PM PST 23
Finished Nov 22 02:38:16 PM PST 23
Peak memory 1957136 kb
Host smart-c76a8cea-63b2-42c5-aae7-ff68c3a6936e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100859213337601189334134844828876164228554232489339359941122174006315334558692 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_host_stress_all.100859213337601189334134844828876164228554232489339359941122174006315334558692
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.4053876217938339372663639835841126130332873917386790217290622885764077679000
Short name T1231
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.3 seconds
Started Nov 22 02:19:54 PM PST 23
Finished Nov 22 02:20:08 PM PST 23
Peak memory 214152 kb
Host smart-804a8332-c5be-4edb-a522-dba174bcb1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053876217938339372663639835841126130332873917386790217290622885764077679000 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.i2c_host_stretch_timeout.4053876217938339372663639835841126130332873917386790217290622885764077679000
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.98447006327043293062997197262910196454920744944873961122786430677371158046917
Short name T1035
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.71 seconds
Started Nov 22 02:20:08 PM PST 23
Finished Nov 22 02:20:13 PM PST 23
Peak memory 202780 kb
Host smart-ddcf43e3-2d13-4e12-a5df-bc55f3c6be23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9844700632704329306299719726291
0196454920744944873961122786430677371158046917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.98447006327043293062997197
262910196454920744944873961122786430677371158046917
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.34095203455687637938944922156123128518169477637125557265378916099214295927177
Short name T1219
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.99 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:21:20 PM PST 23
Peak memory 382224 kb
Host smart-eb9f966d-67f0-4f1e-bb0f-2e5bc675200d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340952034556876379389449221561231285181694776371255
57265378916099214295927177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.3409520345568763793894492215612
3128518169477637125557265378916099214295927177
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.19654199699923423730016258942020880176669595683137701965719934550723042547655
Short name T365
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.31 seconds
Started Nov 22 02:20:15 PM PST 23
Finished Nov 22 02:20:50 PM PST 23
Peak memory 462152 kb
Host smart-c238c0a1-e980-4b56-82c8-0c279eaa99fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196541996999234237300162589420208801766695956831377
01965719934550723042547655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_tx.196541996999234237300162589420208
80176669595683137701965719934550723042547655
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.57191034154671766812247241372902556665085285006596733076035734503513215137943
Short name T1287
Test name
Test status
Simulation time 825344371 ps
CPU time 2.48 seconds
Started Nov 22 02:19:55 PM PST 23
Finished Nov 22 02:19:58 PM PST 23
Peak memory 202996 kb
Host smart-e9afbb10-8cfa-4393-a1d1-eba1f93c9f8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571910341546717668122472413729025566650852850065967
33076035734503513215137943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_hrst.571910341546717668122472413729025566650852850065967
33076035734503513215137943
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.29099651850442015575931385955228755643966497293086500337403134002061628790883
Short name T939
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.27 seconds
Started Nov 22 02:20:11 PM PST 23
Finished Nov 22 02:20:16 PM PST 23
Peak memory 203728 kb
Host smart-25660369-a727-40f3-ba60-13f4a3d0b71f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29099651850442015575931385955228755643966497293086
500337403134002061628790883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_smoke.2909965185044201557593138595522875564396649
7293086500337403134002061628790883
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.19831310755279560309426289513512446158453410105204044942149335117636040774891
Short name T50
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.69 seconds
Started Nov 22 02:19:54 PM PST 23
Finished Nov 22 02:20:17 PM PST 23
Peak memory 639216 kb
Host smart-451595d4-1aa7-417a-ae35-ed7078d47978
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19831310755279560309426289513512446158
453410105204044942149335117636040774891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.19831310755279560309426
289513512446158453410105204044942149335117636040774891
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.114385228142710626605161092332508737816224770378426198029940618677175504061459
Short name T1567
Test name
Test status
Simulation time 834576440 ps
CPU time 2.96 seconds
Started Nov 22 02:20:11 PM PST 23
Finished Nov 22 02:20:15 PM PST 23
Peak memory 203072 kb
Host smart-e76cfddd-058b-4297-9c1c-eb8f1e836f37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114385228142710626605161092332508737816224770378426
198029940618677175504061459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_perf.11438522814271062660516109233250873781622477037842
6198029940618677175504061459
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.21033074499169552286188374967439397725142484655281026971043103785871181347240
Short name T201
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.44 seconds
Started Nov 22 02:20:45 PM PST 23
Finished Nov 22 02:20:56 PM PST 23
Peak memory 202916 kb
Host smart-41d5bd44-714b-48ec-aa72-873c4a9a151b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103307449916955228618837496743939772514248465528102697104310378587118
1347240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smoke.21033074499169552286188374967439397725142484655281026971043103785871181347240
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.104746409251652135902236655392954427858460841423476397728296924764042103832048
Short name T596
Test name
Test status
Simulation time 66540157934 ps
CPU time 1753.26 seconds
Started Nov 22 02:19:54 PM PST 23
Finished Nov 22 02:49:09 PM PST 23
Peak memory 6983828 kb
Host smart-179fab63-4800-47f7-bcaf-5f5989be9cfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10474640925165213590223665539295442785846084142347
6397728296924764042103832048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_all.1047464092516521359022366553929544278
58460841423476397728296924764042103832048
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.37902219604652140090379777885234951972855311802118756918764934957158393053633
Short name T287
Test name
Test status
Simulation time 997771563 ps
CPU time 8.64 seconds
Started Nov 22 02:20:43 PM PST 23
Finished Nov 22 02:20:52 PM PST 23
Peak memory 203028 kb
Host smart-d813f27b-6e55-4005-bbb2-a4b86d304ceb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790221960465214009037977788523495197285531180211875691876493495715839
3053633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_rd.379022196046521400903797778852349519728553118021187569187649
34957158393053633
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.70574511622339012185017814642920661687326840780231229767516502765370361492192
Short name T490
Test name
Test status
Simulation time 14461449567 ps
CPU time 78.36 seconds
Started Nov 22 02:20:41 PM PST 23
Finished Nov 22 02:22:00 PM PST 23
Peak memory 1542148 kb
Host smart-6ca82fe9-201e-45f5-aaf1-39e86c105a2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7057451162233901218501781464292066168732684078023122976751650276537036
1492192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_wr.705745116223390121850178146429206616873268407802312297675165
02765370361492192
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.29500200497430945556116901934539634056413785893747900299980204281349491298303
Short name T776
Test name
Test status
Simulation time 6281818576 ps
CPU time 80.91 seconds
Started Nov 22 02:20:28 PM PST 23
Finished Nov 22 02:21:50 PM PST 23
Peak memory 930528 kb
Host smart-73b18360-a165-47dc-84d5-59b947304edc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950020049743094555611690193453963405641378589374790029998020428134949
1298303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stretch.2950020049743094555611690193453963405641378589374790029998020428
1349491298303
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.71269038907550753351803276394384731880548027933542279678745323565361172414406
Short name T689
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.08 seconds
Started Nov 22 02:19:52 PM PST 23
Finished Nov 22 02:20:00 PM PST 23
Peak memory 212520 kb
Host smart-ce88f135-468f-46e8-991b-f597ad3b3379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712690389075507533518032763943847318805480279335422
79678745323565361172414406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_timeout.712690389075507533518032763943847318805480279
33542279678745323565361172414406
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_ovf.96796077315996203665798266749085202649168013177992378190323212666653059584714
Short name T652
Test name
Test status
Simulation time 5445414553 ps
CPU time 142.95 seconds
Started Nov 22 02:20:43 PM PST 23
Finished Nov 22 02:23:07 PM PST 23
Peak memory 406768 kb
Host smart-93384085-7734-4c6d-804a-28ac3781d4ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96796077315996203665798266749085202649168013177992
378190323212666653059584714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_tx_ovf.9679607731599620366579826674908520264916801317
7992378190323212666653059584714
Directory /workspace/12.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.102503864449070169206530887343475970289012994543923302962190342634921073849259
Short name T1151
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.6 seconds
Started Nov 22 02:20:44 PM PST 23
Finished Nov 22 02:20:51 PM PST 23
Peak memory 205364 kb
Host smart-ef4e4df2-5991-4e2f-9051-39520ca848a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102503864449070169206530887343475970289012994543923
302962190342634921073849259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_unexp_stop.1025038644490701692065308873434759702890
12994543923302962190342634921073849259
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.106020470005416329528155848601485935865464034926137920898270429379568084267101
Short name T558
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:20:29 PM PST 23
Finished Nov 22 02:20:31 PM PST 23
Peak memory 202596 kb
Host smart-43b276f2-56e6-477c-84ce-1f854c52e6f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106020470005416329528155848601485935865464034926137920898270429379568084267101 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 13.i2c_alert_test.106020470005416329528155848601485935865464034926137920898270429379568084267101
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.76022421337005144470688779302313423273498457886814221417279128744150913778094
Short name T1050
Test name
Test status
Simulation time 74225396 ps
CPU time 1.42 seconds
Started Nov 22 02:20:29 PM PST 23
Finished Nov 22 02:20:31 PM PST 23
Peak memory 211320 kb
Host smart-f1343891-d38d-41c1-aab8-af7a7084b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76022421337005144470688779302313423273498457886814221417279128744150913778094 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_host_error_intr.76022421337005144470688779302313423273498457886814221417279128744150913778094
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.84050538002602630051205576063927408152607113788651414585418346020568159923165
Short name T1011
Test name
Test status
Simulation time 606667565 ps
CPU time 7.04 seconds
Started Nov 22 02:20:29 PM PST 23
Finished Nov 22 02:20:36 PM PST 23
Peak memory 273488 kb
Host smart-74d1c46d-46d7-4afb-8479-fb304ff2d7a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84050538002602630051205576063927408152607113788651414585418346020568159923165 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.84050538002602630051205576063927408152607113788651414585418346020568159923165
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.99166193493947093685067228481115430399060111161384173499969568952007416570597
Short name T1312
Test name
Test status
Simulation time 3768267272 ps
CPU time 77.08 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:22:05 PM PST 23
Peak memory 729452 kb
Host smart-97f5d7b5-aabc-4208-b121-53920ae880b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99166193493947093685067228481115430399060111161384173499969568952007416570597 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_host_fifo_full.99166193493947093685067228481115430399060111161384173499969568952007416570597
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.16414402345260033524331996520100620261550798391929334021603664497553464016831
Short name T1384
Test name
Test status
Simulation time 7925734012 ps
CPU time 238.04 seconds
Started Nov 22 02:21:11 PM PST 23
Finished Nov 22 02:25:10 PM PST 23
Peak memory 1271576 kb
Host smart-7fe2ac68-d54a-4f93-8c13-5fbada653634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16414402345260033524331996520100620261550798391929334021603664497553464016831 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.i2c_host_fifo_overflow.16414402345260033524331996520100620261550798391929334021603664497553464016831
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.14943175480145849958384555023266550238783698457557473343444654972816519727514
Short name T700
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:20:30 PM PST 23
Finished Nov 22 02:20:32 PM PST 23
Peak memory 202948 kb
Host smart-dd4be95d-37c1-4720-b843-7c9c01329cb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14943175480145849958384555023266550238783698457557473343444654972816519727514 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.14943175480145849958384555023266550238783698457557473343444654972816519727514
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.58006785765868126344037011085677194808068046174649467534209647736371954051435
Short name T1013
Test name
Test status
Simulation time 236313385 ps
CPU time 3.73 seconds
Started Nov 22 02:20:30 PM PST 23
Finished Nov 22 02:20:35 PM PST 23
Peak memory 225424 kb
Host smart-3767da48-ba2a-43ad-a86b-374e0f907088
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58006785765868126344037011085677194808068046174649467534209647736371954051435 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.58006785765868126344037011085677194808068046174649467534209647736371954051435
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.8168247022549641710157024898460183341694109232726516738789295331929634738616
Short name T1331
Test name
Test status
Simulation time 7918519784 ps
CPU time 203.36 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:24:31 PM PST 23
Peak memory 1311220 kb
Host smart-0dc5dbd3-6647-45b3-903e-14779922d56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8168247022549641710157024898460183341694109232726516738789295331929634738616 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.i2c_host_fifo_watermark.8168247022549641710157024898460183341694109232726516738789295331929634738616
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.86872542843304602965517692996954191468014566933331735711848724940303861459409
Short name T260
Test name
Test status
Simulation time 3754070957 ps
CPU time 60.86 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:22:08 PM PST 23
Peak memory 293808 kb
Host smart-b34d5544-9580-483c-b095-dd5b9714c32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86872542843304602965517692996954191468014566933331735711848724940303861459409 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_host_mode_toggle.86872542843304602965517692996954191468014566933331735711848724940303861459409
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.61519509519074534064166609847027095974653543382883441622980698603679836022462
Short name T998
Test name
Test status
Simulation time 23672229 ps
CPU time 0.66 seconds
Started Nov 22 02:19:55 PM PST 23
Finished Nov 22 02:19:56 PM PST 23
Peak memory 202764 kb
Host smart-09b36358-c487-4586-91f7-d9b45aaf40bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61519509519074534064166609847027095974653543382883441622980698603679836022462 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_host_override.61519509519074534064166609847027095974653543382883441622980698603679836022462
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.54344787270781820121745182992271231273230307199722003052058257281446970944250
Short name T639
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.98 seconds
Started Nov 22 02:20:44 PM PST 23
Finished Nov 22 02:21:46 PM PST 23
Peak memory 211400 kb
Host smart-0909cb53-535c-4585-92cd-a13c565bb768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54344787270781820121745182992271231273230307199722003052058257281446970944250 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.i2c_host_perf.54344787270781820121745182992271231273230307199722003052058257281446970944250
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_rx_oversample.73311800348284836133521619801676271389019470149144851056058768919683014464917
Short name T838
Test name
Test status
Simulation time 3939158762 ps
CPU time 109.88 seconds
Started Nov 22 02:19:55 PM PST 23
Finished Nov 22 02:21:46 PM PST 23
Peak memory 345964 kb
Host smart-20f00a82-e8ab-48f3-9460-9d8c61a2498a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73311800348284836133521619801676271389019470149144851056058768919683014464917 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_rx_oversample.73311800348284836133521619801676271389019470149144851056058768919683014464917
Directory /workspace/13.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.50930336083141113053074128467178505825936017493534082436776141312792755704338
Short name T174
Test name
Test status
Simulation time 2343171530 ps
CPU time 35.71 seconds
Started Nov 22 02:20:44 PM PST 23
Finished Nov 22 02:21:20 PM PST 23
Peak memory 299436 kb
Host smart-95fa228c-a9d3-4729-997d-10df9f046289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50930336083141113053074128467178505825936017493534082436776141312792755704338 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.i2c_host_smoke.50930336083141113053074128467178505825936017493534082436776141312792755704338
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.49834271292736192176028352966385273988446581812083721838801276030286255453181
Short name T1179
Test name
Test status
Simulation time 32807463528 ps
CPU time 1027.6 seconds
Started Nov 22 02:20:30 PM PST 23
Finished Nov 22 02:37:39 PM PST 23
Peak memory 1957100 kb
Host smart-f9178eae-7946-4208-8f96-8026bb039373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49834271292736192176028352966385273988446581812083721838801276030286255453181 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_host_stress_all.49834271292736192176028352966385273988446581812083721838801276030286255453181
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.62070633279442561643748760842387373021676428354969117585722257295009063836664
Short name T1323
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.27 seconds
Started Nov 22 02:20:48 PM PST 23
Finished Nov 22 02:21:02 PM PST 23
Peak memory 214144 kb
Host smart-ad71aa75-1ead-4a66-afdc-0ded1323c201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62070633279442561643748760842387373021676428354969117585722257295009063836664 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_host_stretch_timeout.62070633279442561643748760842387373021676428354969117585722257295009063836664
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.89654995631631885534827432671636176658886447671329875515406014043027228796932
Short name T1570
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.68 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:15 PM PST 23
Peak memory 203104 kb
Host smart-1c7d5c0e-12a2-4f79-8ade-9e58d596da44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8965499563163188553482743267163
6176658886447671329875515406014043027228796932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.89654995631631885534827432
671636176658886447671329875515406014043027228796932
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.92515807528834898685188768450501733078208969185971434561305039714365122110799
Short name T410
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.95 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:21:43 PM PST 23
Peak memory 382152 kb
Host smart-9e6fc0e6-e27e-46c3-8ade-3ffb34338596
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925158075288348986851887684505017330782089691859714
34561305039714365122110799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.9251580752883489868518876845050
1733078208969185971434561305039714365122110799
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.40913730211762248729722006476969165929027626260225605680584266929378619509275
Short name T514
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.2 seconds
Started Nov 22 02:20:51 PM PST 23
Finished Nov 22 02:21:28 PM PST 23
Peak memory 461928 kb
Host smart-706b7025-142b-4faf-aed2-d65b2bc925c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409137302117622487297220064769691659290276262602256
05680584266929378619509275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_tx.409137302117622487297220064769691
65929027626260225605680584266929378619509275
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.51709630377239063125952627628207363277176428436491903370888326158323244873735
Short name T347
Test name
Test status
Simulation time 825344371 ps
CPU time 2.51 seconds
Started Nov 22 02:21:07 PM PST 23
Finished Nov 22 02:21:11 PM PST 23
Peak memory 203024 kb
Host smart-1bfd70f4-06da-400a-a0d1-02a2317c27bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517096303772390631259526276282073632771764284364919
03370888326158323244873735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_hrst.517096303772390631259526276282073632771764284364919
03370888326158323244873735
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.19655308517523062397516950714932318681825216252520955315899742519649811316
Short name T673
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.44 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:21:08 PM PST 23
Peak memory 203660 kb
Host smart-a89256a6-72db-40ff-82bf-ca68f8107080
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19655308517523062397516950714932318681825216252520
955315899742519649811316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_smoke.1965530851752306239751695071493231868182521625
2520955315899742519649811316
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.103860131299162670587789722882388329430374182539520277669334715966586809008726
Short name T333
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.92 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:29 PM PST 23
Peak memory 639264 kb
Host smart-f14a8f0c-1c34-4418-b700-96953a034bc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10386013129916267058778972288238832943
0374182539520277669334715966586809008726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1038601312991626705877
89722882388329430374182539520277669334715966586809008726
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.65906043824301687528900556095727856131137966356509650006689218127992328569160
Short name T316
Test name
Test status
Simulation time 834576440 ps
CPU time 3.03 seconds
Started Nov 22 02:21:11 PM PST 23
Finished Nov 22 02:21:15 PM PST 23
Peak memory 203064 kb
Host smart-93a1a98e-63f8-43f3-91f2-d8cdee4ae567
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659060438243016875289005560957278561311379663565096
50006689218127992328569160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_perf.659060438243016875289005560957278561311379663565096
50006689218127992328569160
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.61441469530779648744807351487433264523144459799558284887529704610022024994459
Short name T1143
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.49 seconds
Started Nov 22 02:20:14 PM PST 23
Finished Nov 22 02:20:24 PM PST 23
Peak memory 203032 kb
Host smart-bcafd982-ff03-4a28-819f-5dcda7d4c283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6144146953077964874480735148743326452314445979955828488752970461002202
4994459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smoke.61441469530779648744807351487433264523144459799558284887529704610022024994459
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.113976386085460613574961572306696763996855838620335842701452913099778482918039
Short name T1393
Test name
Test status
Simulation time 66540157934 ps
CPU time 1745.07 seconds
Started Nov 22 02:20:49 PM PST 23
Finished Nov 22 02:49:55 PM PST 23
Peak memory 6983824 kb
Host smart-1503bc3a-2339-4c45-860c-87e6a0075bf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11397638608546061357496157230669676399685583862033
5842701452913099778482918039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_all.1139763860854606135749615723066967639
96855838620335842701452913099778482918039
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.102599529009045895956250376206362498222977379097485310020493359780577672114034
Short name T2
Test name
Test status
Simulation time 997771563 ps
CPU time 8.64 seconds
Started Nov 22 02:21:01 PM PST 23
Finished Nov 22 02:21:10 PM PST 23
Peak memory 203052 kb
Host smart-d740950d-d723-4169-a63d-3348869e254f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025995290090458959562503762063624982229773790974853100204933597805776
72114034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_rd.10259952900904589595625037620636249822297737909748531002049
3359780577672114034
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.79192373949064357960314089866332134963022267325593504758119886515282143209045
Short name T1222
Test name
Test status
Simulation time 14461449567 ps
CPU time 82.52 seconds
Started Nov 22 02:20:44 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 1542020 kb
Host smart-34420790-4ac1-4a51-aa08-fd49cae3baea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7919237394906435796031408986633213496302226732559350475811988651528214
3209045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_wr.791923739490643579603140898663321349630222673255935047581198
86515282143209045
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.89925055620910727491306639099363333771581574122449738239772034185018903074847
Short name T1271
Test name
Test status
Simulation time 6281818576 ps
CPU time 73.14 seconds
Started Nov 22 02:21:01 PM PST 23
Finished Nov 22 02:22:15 PM PST 23
Peak memory 930584 kb
Host smart-e40b963a-47f2-4f23-a67b-4e9cd9043357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8992505562091072749130663909936333377158157412244973823977203418501890
3074847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stretch.8992505562091072749130663909936333377158157412244973823977203418
5018903074847
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.30396618502448615261286036982221745490137976581762001731982153536683170140114
Short name T528
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.6 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:21:15 PM PST 23
Peak memory 212488 kb
Host smart-b209bac2-4e15-4655-ab7a-4286766757ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303966185024486152612860369822217454901379765817620
01731982153536683170140114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_timeout.303966185024486152612860369822217454901379765
81762001731982153536683170140114
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_ovf.48642847721304080505017268573641265472759534048050444609744478078521657244073
Short name T725
Test name
Test status
Simulation time 5445414553 ps
CPU time 142.87 seconds
Started Nov 22 02:20:48 PM PST 23
Finished Nov 22 02:23:12 PM PST 23
Peak memory 406404 kb
Host smart-88942c54-449e-4a9f-9c26-43750edc79bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48642847721304080505017268573641265472759534048050
444609744478078521657244073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_tx_ovf.4864284772130408050501726857364126547275953404
8050444609744478078521657244073
Directory /workspace/13.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.53645728312790839470251964056199171065730667841716989074473765583081788478971
Short name T1221
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.46 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:20:54 PM PST 23
Peak memory 205232 kb
Host smart-5cfc640b-f915-4e9c-974f-9048b7162ddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536457283127908394702519640561991710657306678417169
89074473765583081788478971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_unexp_stop.53645728312790839470251964056199171065730
667841716989074473765583081788478971
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.29318304113172517840111854900943863972310349562857569682633249377948182703153
Short name T517
Test name
Test status
Simulation time 19975830 ps
CPU time 0.59 seconds
Started Nov 22 02:20:46 PM PST 23
Finished Nov 22 02:20:48 PM PST 23
Peak memory 202788 kb
Host smart-726b1ed6-87b7-4178-93d4-aa70c98bd3c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318304113172517840111854900943863972310349562857569682633249377948182703153 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_alert_test.29318304113172517840111854900943863972310349562857569682633249377948182703153
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.111187227559534494988039856052939908706400237406165747659416828024444207720820
Short name T1140
Test name
Test status
Simulation time 74225396 ps
CPU time 1.35 seconds
Started Nov 22 02:20:16 PM PST 23
Finished Nov 22 02:20:18 PM PST 23
Peak memory 211228 kb
Host smart-bcd8d67d-12ff-4f96-8a75-e70462de39da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111187227559534494988039856052939908706400237406165747659416828024444207720820 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_host_error_intr.111187227559534494988039856052939908706400237406165747659416828024444207720820
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.13707298081311743906136079453636096488404903311206912259489636048857118007721
Short name T306
Test name
Test status
Simulation time 606667565 ps
CPU time 6.53 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:11 PM PST 23
Peak memory 273356 kb
Host smart-a7b3acd5-de03-4380-87eb-549d98240c80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707298081311743906136079453636096488404903311206912259489636048857118007721 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.13707298081311743906136079453636096488404903311206912259489636048857118007721
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.51050268986254050339720709427506668643922967314264034133023366552164988116981
Short name T329
Test name
Test status
Simulation time 3768267272 ps
CPU time 72.27 seconds
Started Nov 22 02:20:30 PM PST 23
Finished Nov 22 02:21:44 PM PST 23
Peak memory 729508 kb
Host smart-eac755f0-8c9b-4d93-b098-292f3f0b1141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51050268986254050339720709427506668643922967314264034133023366552164988116981 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_host_fifo_full.51050268986254050339720709427506668643922967314264034133023366552164988116981
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.62645209579237898800813422367166243213870226923847869506780214466393745465237
Short name T300
Test name
Test status
Simulation time 7925734012 ps
CPU time 230.2 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:24:38 PM PST 23
Peak memory 1271600 kb
Host smart-30aa77e6-50e5-425c-b826-ff55076f75a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62645209579237898800813422367166243213870226923847869506780214466393745465237 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.i2c_host_fifo_overflow.62645209579237898800813422367166243213870226923847869506780214466393745465237
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.43355958304692722363584398182877738034661724051646542047638125370549674392483
Short name T763
Test name
Test status
Simulation time 209010032 ps
CPU time 0.92 seconds
Started Nov 22 02:20:44 PM PST 23
Finished Nov 22 02:20:46 PM PST 23
Peak memory 202872 kb
Host smart-603bdb1f-52b7-43e8-8361-85e1cc16ffd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43355958304692722363584398182877738034661724051646542047638125370549674392483 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.43355958304692722363584398182877738034661724051646542047638125370549674392483
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.12437007095504740811066338224559200730896939357139883558391749641393210785652
Short name T399
Test name
Test status
Simulation time 236313385 ps
CPU time 3.97 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 225504 kb
Host smart-ec76be0a-2afc-48cf-904c-6f49fcdecaa2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12437007095504740811066338224559200730896939357139883558391749641393210785652 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.12437007095504740811066338224559200730896939357139883558391749641393210785652
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.110047245033799392067099660446644575058537826547691757806169056615558479039266
Short name T332
Test name
Test status
Simulation time 7918519784 ps
CPU time 234.03 seconds
Started Nov 22 02:20:29 PM PST 23
Finished Nov 22 02:24:24 PM PST 23
Peak memory 1310976 kb
Host smart-6a6c602b-b6a8-45c7-b35c-85cfc1e7777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110047245033799392067099660446644575058537826547691757806169056615558479039266 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_host_fifo_watermark.110047245033799392067099660446644575058537826547691757806169056615558479039266
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.81140408809382762905495921212801471165142111183397227871513059409789642867425
Short name T482
Test name
Test status
Simulation time 3754070957 ps
CPU time 53.12 seconds
Started Nov 22 02:20:14 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 293724 kb
Host smart-23b42827-e1cc-4243-9bb5-e6f411686e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81140408809382762905495921212801471165142111183397227871513059409789642867425 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_host_mode_toggle.81140408809382762905495921212801471165142111183397227871513059409789642867425
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_perf.22809373004305243237104805142277480037358572718075205912929787532075516158881
Short name T433
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.11 seconds
Started Nov 22 02:20:45 PM PST 23
Finished Nov 22 02:21:46 PM PST 23
Peak memory 211312 kb
Host smart-2a4cbb7f-cbfb-44a4-8e26-2413fd682e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22809373004305243237104805142277480037358572718075205912929787532075516158881 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.i2c_host_perf.22809373004305243237104805142277480037358572718075205912929787532075516158881
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_rx_oversample.107623481607065036460611357170199130983004214389717995862428646677707801307055
Short name T1018
Test name
Test status
Simulation time 3939158762 ps
CPU time 101.21 seconds
Started Nov 22 02:20:49 PM PST 23
Finished Nov 22 02:22:31 PM PST 23
Peak memory 345936 kb
Host smart-5ec9c503-e2ab-4721-8dc7-95e25d91683e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107623481607065036460611357170199130983004214389717995862428646677707801307055 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_rx_oversample.107623481607065036460611357170199130983004214389717995862428646677707801307055
Directory /workspace/14.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.87084716950054154165380587963200802000382405381474804468428372608528806104494
Short name T613
Test name
Test status
Simulation time 2343171530 ps
CPU time 36.35 seconds
Started Nov 22 02:20:46 PM PST 23
Finished Nov 22 02:21:23 PM PST 23
Peak memory 299360 kb
Host smart-c93a0c6c-0c13-4801-b343-3050fa1bd571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87084716950054154165380587963200802000382405381474804468428372608528806104494 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.i2c_host_smoke.87084716950054154165380587963200802000382405381474804468428372608528806104494
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.15988977095564925446878531908259304922126502230732855191771954396266103631394
Short name T1481
Test name
Test status
Simulation time 32807463528 ps
CPU time 1088.69 seconds
Started Nov 22 02:20:46 PM PST 23
Finished Nov 22 02:38:56 PM PST 23
Peak memory 1957080 kb
Host smart-91d132f9-54f6-4ee2-a61b-410ef310ad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15988977095564925446878531908259304922126502230732855191771954396266103631394 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_host_stress_all.15988977095564925446878531908259304922126502230732855191771954396266103631394
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.52527867274140124201491126747941406819087748862043683694280094475983833702592
Short name T648
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.59 seconds
Started Nov 22 02:20:32 PM PST 23
Finished Nov 22 02:20:46 PM PST 23
Peak memory 214228 kb
Host smart-91c1d97b-8703-4719-bc52-393078ce1d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52527867274140124201491126747941406819087748862043683694280094475983833702592 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_host_stretch_timeout.52527867274140124201491126747941406819087748862043683694280094475983833702592
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.60527385892341332002179723860849790069230096772283200525286173932039763891209
Short name T1546
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.82 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:21:06 PM PST 23
Peak memory 203072 kb
Host smart-87f0d681-10c8-41f2-9d5e-c598e9e021d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6052738589234133200217972386084
9790069230096772283200525286173932039763891209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.60527385892341332002179723
860849790069230096772283200525286173932039763891209
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.11044322890289390775633346261903682840318848717040421631244600148373013958007
Short name T1418
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.91 seconds
Started Nov 22 02:20:33 PM PST 23
Finished Nov 22 02:21:06 PM PST 23
Peak memory 382228 kb
Host smart-51a4a0a6-1ec4-4f45-9515-e40e57f6f148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110443228902893907756333462619036828403188487170404
21631244600148373013958007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.1104432289028939077563334626190
3682840318848717040421631244600148373013958007
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.47372412935469264447309919707178671680223580103820218697705249111303276970203
Short name T980
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.11 seconds
Started Nov 22 02:20:48 PM PST 23
Finished Nov 22 02:21:25 PM PST 23
Peak memory 462068 kb
Host smart-eec78df9-1493-4ac8-b696-8674fd793246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473724129354692644473099197071786716802235801038202
18697705249111303276970203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_tx.473724129354692644473099197071786
71680223580103820218697705249111303276970203
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.63348658927770820487752782764800550892408924123024984196982798384350085118092
Short name T615
Test name
Test status
Simulation time 825344371 ps
CPU time 2.41 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:20:51 PM PST 23
Peak memory 203108 kb
Host smart-f03e8112-5b6d-42d8-9f8e-6ec26b52c891
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633486589277708204877527827648005508924089241230249
84196982798384350085118092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_hrst.633486589277708204877527827648005508924089241230249
84196982798384350085118092
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.55565209431348988746864074476107872299250453613938925375068834210920010225638
Short name T604
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.45 seconds
Started Nov 22 02:20:33 PM PST 23
Finished Nov 22 02:20:39 PM PST 23
Peak memory 203700 kb
Host smart-3cf5d69c-0e09-4b28-a9da-a2183b84ce78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55565209431348988746864074476107872299250453613938
925375068834210920010225638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_smoke.5556520943134898874686407447610787229925045
3613938925375068834210920010225638
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.80133257234310444458944201116160145490101100101881994284197249314332824773159
Short name T513
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.84 seconds
Started Nov 22 02:20:45 PM PST 23
Finished Nov 22 02:21:08 PM PST 23
Peak memory 639252 kb
Host smart-1e1004e4-883f-47c5-8c4e-599d6bc82091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80133257234310444458944201116160145490
101100101881994284197249314332824773159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.80133257234310444458944
201116160145490101100101881994284197249314332824773159
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_perf.85062431552961697034057421729776240379171723490095410016807852582968816493360
Short name T1264
Test name
Test status
Simulation time 834576440 ps
CPU time 3.18 seconds
Started Nov 22 02:20:44 PM PST 23
Finished Nov 22 02:20:47 PM PST 23
Peak memory 203044 kb
Host smart-15b26d32-f1b1-4f00-a9e2-9391850feed7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850624315529616970340574217297762403791717234900954
10016807852582968816493360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_perf.850624315529616970340574217297762403791717234900954
10016807852582968816493360
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.86988599125443211982833905303556341999044424468440199836333249082162645517243
Short name T808
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.43 seconds
Started Nov 22 02:20:46 PM PST 23
Finished Nov 22 02:20:56 PM PST 23
Peak memory 203008 kb
Host smart-7803b16f-0e09-4b1f-a295-e9488c5d5865
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8698859912544321198283390530355634199904442446844019983633324908216264
5517243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smoke.86988599125443211982833905303556341999044424468440199836333249082162645517243
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.66277518840580900560038093277383653967833571446707107602266816201160629466722
Short name T1016
Test name
Test status
Simulation time 66540157934 ps
CPU time 1460.17 seconds
Started Nov 22 02:20:44 PM PST 23
Finished Nov 22 02:45:05 PM PST 23
Peak memory 6983232 kb
Host smart-d848084c-4fec-499c-acfc-5c27edca78d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66277518840580900560038093277383653967833571446707
107602266816201160629466722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_all.66277518840580900560038093277383653967
833571446707107602266816201160629466722
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.22552550604249987084278410029391892156829885194508623037221199936448281860333
Short name T985
Test name
Test status
Simulation time 997771563 ps
CPU time 8.72 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:21:12 PM PST 23
Peak memory 202980 kb
Host smart-89dc3647-60d3-405f-ab70-4d4bfef230b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255255060424998708427841002939189215682988519450862303722119993644828
1860333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_rd.225525506042499870842784100293918921568298851945086230372211
99936448281860333
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.104564270415704053571254270538247691945111136462501756330065357103756799715907
Short name T920
Test name
Test status
Simulation time 14461449567 ps
CPU time 84.73 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:22:28 PM PST 23
Peak memory 1542020 kb
Host smart-aa9e033e-222a-4f8e-a799-c657ce7516ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045642704157040535712542705382476919451111364625017563300653571037567
99715907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_wr.10456427041570405357125427053824769194511113646250175633006
5357103756799715907
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.91429934399379886855066036602955956579381590058212527403309744442764629518750
Short name T236
Test name
Test status
Simulation time 6281818576 ps
CPU time 78.48 seconds
Started Nov 22 02:20:31 PM PST 23
Finished Nov 22 02:21:50 PM PST 23
Peak memory 930492 kb
Host smart-cd971e50-e8b4-45f3-974a-cbc82e6499cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9142993439937988685506603660295595657938159005821252740330974444276462
9518750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stretch.9142993439937988685506603660295595657938159005821252740330974444
2764629518750
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.107934870369490411013285254286810661929166421978586912996163958623720827790763
Short name T696
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.6 seconds
Started Nov 22 02:20:48 PM PST 23
Finished Nov 22 02:20:57 PM PST 23
Peak memory 212260 kb
Host smart-d2f637c0-a751-4d1f-852e-5182d98e8ada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107934870369490411013285254286810661929166421978586
912996163958623720827790763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_timeout.10793487036949041101328525428681066192916642
1978586912996163958623720827790763
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_ovf.16851087952571115586125801489057010834145972374894864347028337383496050003845
Short name T765
Test name
Test status
Simulation time 5445414553 ps
CPU time 116.97 seconds
Started Nov 22 02:20:29 PM PST 23
Finished Nov 22 02:22:27 PM PST 23
Peak memory 406716 kb
Host smart-b5fd5fce-92f0-4f23-be62-b7a3e44fa336
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16851087952571115586125801489057010834145972374894
864347028337383496050003845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_tx_ovf.1685108795257111558612580148905701083414597237
4894864347028337383496050003845
Directory /workspace/14.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.31616640248326019561561102663595089625781252841821435168878971851371541112647
Short name T1350
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.83 seconds
Started Nov 22 02:20:31 PM PST 23
Finished Nov 22 02:20:38 PM PST 23
Peak memory 205340 kb
Host smart-18db9ae1-aa10-486a-b04f-fb3902449578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316166402483260195615611026635950896257812528418214
35168878971851371541112647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_unexp_stop.31616640248326019561561102663595089625781
252841821435168878971851371541112647
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.47451908076463177356043374894023123286166906879403439234205581683851523913486
Short name T881
Test name
Test status
Simulation time 19975830 ps
CPU time 0.56 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:12 PM PST 23
Peak memory 202752 kb
Host smart-c4e08884-fcae-4202-a1e9-5029ea42659b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47451908076463177356043374894023123286166906879403439234205581683851523913486 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_alert_test.47451908076463177356043374894023123286166906879403439234205581683851523913486
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.71384577834660809848785267764124848704690004057163955590908791060422151310743
Short name T593
Test name
Test status
Simulation time 74225396 ps
CPU time 1.35 seconds
Started Nov 22 02:20:51 PM PST 23
Finished Nov 22 02:20:53 PM PST 23
Peak memory 211256 kb
Host smart-3842b37d-e23d-439d-9397-69211169b659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71384577834660809848785267764124848704690004057163955590908791060422151310743 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_host_error_intr.71384577834660809848785267764124848704690004057163955590908791060422151310743
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.10690722618833367555011829693086399495252517155366669104432286362352131179976
Short name T1200
Test name
Test status
Simulation time 606667565 ps
CPU time 6.62 seconds
Started Nov 22 02:20:34 PM PST 23
Finished Nov 22 02:20:41 PM PST 23
Peak memory 273376 kb
Host smart-585256ec-8ad3-40af-9da2-ee7a7de48833
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10690722618833367555011829693086399495252517155366669104432286362352131179976 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.10690722618833367555011829693086399495252517155366669104432286362352131179976
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.104017249749640423758034632867223951680950567553541649411636884718148741569571
Short name T977
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.44 seconds
Started Nov 22 02:20:52 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 729456 kb
Host smart-fb51d7f1-46aa-4db3-bdc9-b7fd8dc69868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104017249749640423758034632867223951680950567553541649411636884718148741569571 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_host_fifo_full.104017249749640423758034632867223951680950567553541649411636884718148741569571
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.67885808829358961112072224287870735920031176194730018124364137376027304132917
Short name T1441
Test name
Test status
Simulation time 7925734012 ps
CPU time 232.78 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:24:40 PM PST 23
Peak memory 1271580 kb
Host smart-544cd024-e034-42f6-a770-066c7bbadd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67885808829358961112072224287870735920031176194730018124364137376027304132917 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.i2c_host_fifo_overflow.67885808829358961112072224287870735920031176194730018124364137376027304132917
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.112520907495714839390875756476926406725719368927618147167135150061201623661869
Short name T419
Test name
Test status
Simulation time 209010032 ps
CPU time 0.94 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:21:05 PM PST 23
Peak memory 202900 kb
Host smart-f872d926-4a05-47f8-8d9a-805a7d212479
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112520907495714839390875756476926406725719368927618147167135150061201623661869 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.112520907495714839390875756476926406725719368927618147167135150061201623661869
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.82614287028428756587907206680916848983684156871823042507610246547574694282894
Short name T100
Test name
Test status
Simulation time 236313385 ps
CPU time 3.84 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:20:52 PM PST 23
Peak memory 225508 kb
Host smart-8fa6e715-1d2e-4963-b68a-eaadf612031e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82614287028428756587907206680916848983684156871823042507610246547574694282894 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.82614287028428756587907206680916848983684156871823042507610246547574694282894
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.37582987134991063689567806440002745736768632986615036858390656455762342782700
Short name T625
Test name
Test status
Simulation time 7918519784 ps
CPU time 209.27 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:24:17 PM PST 23
Peak memory 1311008 kb
Host smart-3f40bc0a-9be0-4b62-815b-7a4365ac3017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37582987134991063689567806440002745736768632986615036858390656455762342782700 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.i2c_host_fifo_watermark.37582987134991063689567806440002745736768632986615036858390656455762342782700
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_override.113721858920447842908030456466048647051759354041461986024684335239980717411965
Short name T893
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:20:49 PM PST 23
Peak memory 202880 kb
Host smart-12f64588-0826-467e-88ab-b5b551c328b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113721858920447842908030456466048647051759354041461986024684335239980717411965 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_host_override.113721858920447842908030456466048647051759354041461986024684335239980717411965
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2565571806727721309744146056070503132606495080407670812313623331168780999668
Short name T1397
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.61 seconds
Started Nov 22 02:20:45 PM PST 23
Finished Nov 22 02:21:46 PM PST 23
Peak memory 211372 kb
Host smart-9f3d173c-9e91-4bee-81e5-160bef58edfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565571806727721309744146056070503132606495080407670812313623331168780999668 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 15.i2c_host_perf.2565571806727721309744146056070503132606495080407670812313623331168780999668
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_rx_oversample.9967430564506087639342814428552331520415415946862332307914300193882990928163
Short name T1542
Test name
Test status
Simulation time 3939158762 ps
CPU time 103.53 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:22:32 PM PST 23
Peak memory 345992 kb
Host smart-85631a4d-b378-4155-a001-b16577a43b79
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9967430564506087639342814428552331520415415946862332307914300193882990928163 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_rx_oversample.9967430564506087639342814428552331520415415946862332307914300193882990928163
Directory /workspace/15.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.49674608776898840686831228164861043163678200718783048395128324398216644904884
Short name T647
Test name
Test status
Simulation time 2343171530 ps
CPU time 34.04 seconds
Started Nov 22 02:20:45 PM PST 23
Finished Nov 22 02:21:20 PM PST 23
Peak memory 299232 kb
Host smart-a1f6678f-6cd2-4c2e-8bb2-9ce93f657f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49674608776898840686831228164861043163678200718783048395128324398216644904884 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.i2c_host_smoke.49674608776898840686831228164861043163678200718783048395128324398216644904884
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.25149738161008224201611114947411985691705874867189276197963488720300630925758
Short name T849
Test name
Test status
Simulation time 32807463528 ps
CPU time 1034.47 seconds
Started Nov 22 02:21:01 PM PST 23
Finished Nov 22 02:38:17 PM PST 23
Peak memory 1956944 kb
Host smart-0a4a4df3-1622-49db-95ce-8d265c0e298f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25149738161008224201611114947411985691705874867189276197963488720300630925758 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_host_stress_all.25149738161008224201611114947411985691705874867189276197963488720300630925758
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.33541561165022866075239683712966758809852336864541221833296518973741410167870
Short name T913
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.52 seconds
Started Nov 22 02:21:01 PM PST 23
Finished Nov 22 02:21:16 PM PST 23
Peak memory 214164 kb
Host smart-5851380b-1ac5-400e-8510-0331d3757522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33541561165022866075239683712966758809852336864541221833296518973741410167870 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_host_stretch_timeout.33541561165022866075239683712966758809852336864541221833296518973741410167870
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.11043426269010718172375404479953460702247331209805970618556594809607327986454
Short name T1373
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.82 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:21:19 PM PST 23
Peak memory 202956 kb
Host smart-e913b4ee-a675-47d4-958c-1087ad159650
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104342626901071817237540447995
3460702247331209805970618556594809607327986454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.11043426269010718172375404
479953460702247331209805970618556594809607327986454
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.64085540057092440560823656257185260939891205490346300677003402542071506428978
Short name T551
Test name
Test status
Simulation time 10166144644 ps
CPU time 30.91 seconds
Started Nov 22 02:20:51 PM PST 23
Finished Nov 22 02:21:23 PM PST 23
Peak memory 382176 kb
Host smart-d87d6bfd-fa0d-4457-af87-c925eb91671f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640855400570924405608236562571852609398912054903463
00677003402542071506428978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.6408554005709244056082365625718
5260939891205490346300677003402542071506428978
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.52101428256371808175489578143452300127210846376595498325352074225626721262651
Short name T430
Test name
Test status
Simulation time 10065199023 ps
CPU time 35.69 seconds
Started Nov 22 02:20:50 PM PST 23
Finished Nov 22 02:21:27 PM PST 23
Peak memory 462116 kb
Host smart-d243060d-ba09-4bc3-b282-1ced72a3257e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521014282563718081754895781434523001272108463765954
98325352074225626721262651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_tx.521014282563718081754895781434523
00127210846376595498325352074225626721262651
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.30706141126727162648447885422060236542415502728249083105535925893344092318365
Short name T576
Test name
Test status
Simulation time 825344371 ps
CPU time 2.53 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:08 PM PST 23
Peak memory 203016 kb
Host smart-0ebc8e96-cdea-4dde-a3b9-fc1c21adae78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307061411267271626484478854220602365424155027282490
83105535925893344092318365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_hrst.307061411267271626484478854220602365424155027282490
83105535925893344092318365
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.101779541862544015018650886385195546907543901593557936117117820045056739833904
Short name T884
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.25 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:16 PM PST 23
Peak memory 203696 kb
Host smart-947eada7-1f3f-4da6-811b-bf8e5730f74e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10177954186254401501865088638519554690754390159355
7936117117820045056739833904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_smoke.101779541862544015018650886385195546907543
901593557936117117820045056739833904
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.90086379281164754473155717428699217620665019029723501391667225630771644591785
Short name T545
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.29 seconds
Started Nov 22 02:20:51 PM PST 23
Finished Nov 22 02:21:16 PM PST 23
Peak memory 639188 kb
Host smart-12c9b966-62df-4481-ac16-9eb1d774ce94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90086379281164754473155717428699217620
665019029723501391667225630771644591785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.90086379281164754473155
717428699217620665019029723501391667225630771644591785
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.104149482892290916539521475149903830670208112704164515657035617158381636758380
Short name T144
Test name
Test status
Simulation time 834576440 ps
CPU time 2.97 seconds
Started Nov 22 02:21:13 PM PST 23
Finished Nov 22 02:21:17 PM PST 23
Peak memory 202980 kb
Host smart-0994600e-b21b-44cf-bd57-03c1736bf66d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104149482892290916539521475149903830670208112704164
515657035617158381636758380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_perf.10414948289229091653952147514990383067020811270416
4515657035617158381636758380
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.76150793601251891293004528432954494919460801650319008257689453978086116685296
Short name T1108
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.43 seconds
Started Nov 22 02:21:00 PM PST 23
Finished Nov 22 02:21:10 PM PST 23
Peak memory 203044 kb
Host smart-e68584b4-1935-4fdb-92b6-1e7ae29e103e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7615079360125189129300452843295449491946080165031900825768945397808611
6685296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smoke.76150793601251891293004528432954494919460801650319008257689453978086116685296
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.37608084397799146622971897860077996150591531570963693743620455026161768897632
Short name T151
Test name
Test status
Simulation time 997771563 ps
CPU time 8.82 seconds
Started Nov 22 02:21:13 PM PST 23
Finished Nov 22 02:21:23 PM PST 23
Peak memory 203048 kb
Host smart-b9e9059e-1e1c-4e52-b555-fda98d78148f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760808439779914662297189786007799615059153157096369374362045502616176
8897632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_rd.376080843977991466229718978600779961505915315709636937436204
55026161768897632
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.47793002834235686971791261128467943676225184900440418408626463077630061881989
Short name T1186
Test name
Test status
Simulation time 14461449567 ps
CPU time 94.69 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:22:38 PM PST 23
Peak memory 1542232 kb
Host smart-8d0999de-e03d-46d8-bb89-1afa51220337
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4779300283423568697179126112846794367622518490044041840862646307763006
1881989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_wr.477930028342356869717912611284679436762251849004404184086264
63077630061881989
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.16321379663683011938668758921298823176769660920541894641442339625626675725264
Short name T568
Test name
Test status
Simulation time 6281818576 ps
CPU time 83.06 seconds
Started Nov 22 02:20:48 PM PST 23
Finished Nov 22 02:22:12 PM PST 23
Peak memory 930496 kb
Host smart-31974694-a4f6-4883-956e-e5a34c3442c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632137966368301193866875892129882317676966092054189464144233962562667
5725264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stretch.1632137966368301193866875892129882317676966092054189464144233962
5626675725264
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.14760005727055997984707232766915904056186272495627234214322908737814533512782
Short name T1154
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.32 seconds
Started Nov 22 02:20:46 PM PST 23
Finished Nov 22 02:20:54 PM PST 23
Peak memory 212660 kb
Host smart-9302695c-9430-4c39-b50b-9762e165398d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147600057270559979847072327669159040561862724956272
34214322908737814533512782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_timeout.147600057270559979847072327669159040561862724
95627234214322908737814533512782
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_ovf.51199567666664204530660146028812061493410733601200747773644455863031508601574
Short name T756
Test name
Test status
Simulation time 5445414553 ps
CPU time 124.06 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:23:15 PM PST 23
Peak memory 406836 kb
Host smart-fe4ba44a-9b89-4b33-9b13-9dd1e7ec8e6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51199567666664204530660146028812061493410733601200
747773644455863031508601574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_tx_ovf.5119956766666420453066014602881206149341073360
1200747773644455863031508601574
Directory /workspace/15.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.13724626333094939597974788367682236391878484253356673468809429139975387392972
Short name T607
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.53 seconds
Started Nov 22 02:21:01 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 205252 kb
Host smart-59826a49-7a8e-416c-9c8a-660965143865
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137246263330949395979747883676822363918784842533566
73468809429139975387392972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_unexp_stop.13724626333094939597974788367682236391878
484253356673468809429139975387392972
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.21923075808901173567475205450230518804264597967868136426241204158074929083936
Short name T875
Test name
Test status
Simulation time 19975830 ps
CPU time 0.62 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:21:08 PM PST 23
Peak memory 202776 kb
Host smart-278dcc52-da4b-4d82-a252-6e99bc543f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923075808901173567475205450230518804264597967868136426241204158074929083936 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_alert_test.21923075808901173567475205450230518804264597967868136426241204158074929083936
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.56932830830247048187266251891726457246045496628523116570891657159846229049947
Short name T1187
Test name
Test status
Simulation time 74225396 ps
CPU time 1.38 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:21:09 PM PST 23
Peak memory 211072 kb
Host smart-821e3305-f4cb-444b-b7b5-ecaad4c01e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56932830830247048187266251891726457246045496628523116570891657159846229049947 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_host_error_intr.56932830830247048187266251891726457246045496628523116570891657159846229049947
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.82855933234188744008679253943438922356917861600801759362334389617315314227501
Short name T227
Test name
Test status
Simulation time 606667565 ps
CPU time 6.74 seconds
Started Nov 22 02:20:50 PM PST 23
Finished Nov 22 02:20:57 PM PST 23
Peak memory 273316 kb
Host smart-c0c85137-9dfa-494c-9287-d6a2b85f6d13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82855933234188744008679253943438922356917861600801759362334389617315314227501 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.82855933234188744008679253943438922356917861600801759362334389617315314227501
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.70402578607457068338545420355761536536263038389963806815628278657478401277131
Short name T1541
Test name
Test status
Simulation time 3768267272 ps
CPU time 71.86 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:22:24 PM PST 23
Peak memory 729444 kb
Host smart-c74b50ca-9e0d-4b34-80a0-892a72461405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70402578607457068338545420355761536536263038389963806815628278657478401277131 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_host_fifo_full.70402578607457068338545420355761536536263038389963806815628278657478401277131
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.25621880653582519469917273099003277043876675195381842977731495353404131692607
Short name T1137
Test name
Test status
Simulation time 7925734012 ps
CPU time 227.16 seconds
Started Nov 22 02:20:48 PM PST 23
Finished Nov 22 02:24:36 PM PST 23
Peak memory 1271656 kb
Host smart-4732207c-c49e-4bf7-be13-b4894dffd974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25621880653582519469917273099003277043876675195381842977731495353404131692607 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.i2c_host_fifo_overflow.25621880653582519469917273099003277043876675195381842977731495353404131692607
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.23377303060672051311915728279635672687676144795104422489253402873847886942932
Short name T1224
Test name
Test status
Simulation time 209010032 ps
CPU time 0.94 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 202964 kb
Host smart-ebb202a9-444c-44bd-be12-1436cd7813b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23377303060672051311915728279635672687676144795104422489253402873847886942932 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.23377303060672051311915728279635672687676144795104422489253402873847886942932
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.106296043512058570329344641782132596238119357702264731804967711847340627990011
Short name T620
Test name
Test status
Simulation time 236313385 ps
CPU time 3.78 seconds
Started Nov 22 02:20:30 PM PST 23
Finished Nov 22 02:20:35 PM PST 23
Peak memory 225460 kb
Host smart-1db61967-1ce7-4850-a22b-0d545dbc34bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106296043512058570329344641782132596238119357702264731804967711847340627990011 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.106296043512058570329344641782132596238119357702264731804967711847340627990011
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.77951189136968395098195159955462360143913359950813216829612328005156562090260
Short name T1033
Test name
Test status
Simulation time 7918519784 ps
CPU time 206.67 seconds
Started Nov 22 02:21:12 PM PST 23
Finished Nov 22 02:24:39 PM PST 23
Peak memory 1310968 kb
Host smart-825467a8-a3e2-45ad-b7c9-473c1750342a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77951189136968395098195159955462360143913359950813216829612328005156562090260 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.i2c_host_fifo_watermark.77951189136968395098195159955462360143913359950813216829612328005156562090260
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.77364458752205133293253293219188171654219106786134571266067531619073008319002
Short name T637
Test name
Test status
Simulation time 3754070957 ps
CPU time 51.22 seconds
Started Nov 22 02:20:49 PM PST 23
Finished Nov 22 02:21:41 PM PST 23
Peak memory 293784 kb
Host smart-338bd3cc-2910-4010-b2b6-1a8bff3404c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77364458752205133293253293219188171654219106786134571266067531619073008319002 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_host_mode_toggle.77364458752205133293253293219188171654219106786134571266067531619073008319002
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.81542833858377556325194024295939500766906050583964437732528889980070069774515
Short name T533
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:12 PM PST 23
Peak memory 202512 kb
Host smart-e86d7b1d-d052-4256-a424-4972118c0f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81542833858377556325194024295939500766906050583964437732528889980070069774515 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_host_override.81542833858377556325194024295939500766906050583964437732528889980070069774515
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.97880142791900815536066302469218499898280604321536936542848771217851447302280
Short name T1488
Test name
Test status
Simulation time 6830796343 ps
CPU time 61.48 seconds
Started Nov 22 02:20:33 PM PST 23
Finished Nov 22 02:21:35 PM PST 23
Peak memory 211348 kb
Host smart-7714e444-ff2c-4a34-89a1-16eca5c60e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97880142791900815536066302469218499898280604321536936542848771217851447302280 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.i2c_host_perf.97880142791900815536066302469218499898280604321536936542848771217851447302280
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_rx_oversample.73012487669163896393967118000633773220700189598856697983738469624265604475010
Short name T1568
Test name
Test status
Simulation time 3939158762 ps
CPU time 98.3 seconds
Started Nov 22 02:21:12 PM PST 23
Finished Nov 22 02:22:51 PM PST 23
Peak memory 345900 kb
Host smart-14bb346a-85c7-4ada-905a-954f50d0a223
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73012487669163896393967118000633773220700189598856697983738469624265604475010 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_rx_oversample.73012487669163896393967118000633773220700189598856697983738469624265604475010
Directory /workspace/16.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.78601598974098725519943562638844525113404310202306314613252075779890121936399
Short name T1278
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.77 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:43 PM PST 23
Peak memory 299436 kb
Host smart-d4718a30-a0d5-4e94-a86f-9c7e101a0a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78601598974098725519943562638844525113404310202306314613252075779890121936399 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.i2c_host_smoke.78601598974098725519943562638844525113404310202306314613252075779890121936399
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.48558246983342059276076343111867342119793957756254666310188327441551725242945
Short name T233
Test name
Test status
Simulation time 32807463528 ps
CPU time 1024.6 seconds
Started Nov 22 02:20:57 PM PST 23
Finished Nov 22 02:38:03 PM PST 23
Peak memory 1956584 kb
Host smart-7fb80bfd-8c54-49e3-b2fe-e6215a97f038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48558246983342059276076343111867342119793957756254666310188327441551725242945 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_host_stress_all.48558246983342059276076343111867342119793957756254666310188327441551725242945
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.54784864636549736680090210774404820119961878321097245659206573133376168505172
Short name T1098
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.62 seconds
Started Nov 22 02:21:05 PM PST 23
Finished Nov 22 02:21:20 PM PST 23
Peak memory 214172 kb
Host smart-8b93ef8e-9cb8-47dc-9b99-d3a5001ffc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54784864636549736680090210774404820119961878321097245659206573133376168505172 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_host_stretch_timeout.54784864636549736680090210774404820119961878321097245659206573133376168505172
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.8454986709894375207896501593131204078728384237419944669906429319405103295170
Short name T571
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.82 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:09 PM PST 23
Peak memory 203036 kb
Host smart-e8f8125f-6476-4be3-b3e4-aca6c0fe16b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8454986709894375207896501593131
204078728384237419944669906429319405103295170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.845498670989437520789650159
3131204078728384237419944669906429319405103295170
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.12064939258963166470692751668219566345476209682261528606018209195550536185813
Short name T560
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.55 seconds
Started Nov 22 02:20:54 PM PST 23
Finished Nov 22 02:21:27 PM PST 23
Peak memory 382224 kb
Host smart-301b7db4-83e8-4b2d-848d-e47c46c87488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120649392589631664706927516682195663454762096822615
28606018209195550536185813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.1206493925896316647069275166821
9566345476209682261528606018209195550536185813
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.72361716810521579922899698241105377361897508526096316535999296314510394460277
Short name T654
Test name
Test status
Simulation time 825344371 ps
CPU time 2.42 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 202960 kb
Host smart-5963619b-97ca-44f5-a75e-b40297988fdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723617168105215799228996982411053773618975085260963
16535999296314510394460277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_hrst.723617168105215799228996982411053773618975085260963
16535999296314510394460277
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.109911950982079292953553800100952200163831998547612364706028932075195432943877
Short name T384
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.19 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 203748 kb
Host smart-a5e1b19a-3eac-47d1-a00e-bb8d27a6ec7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10991195098207929295355380010095220016383199854761
2364706028932075195432943877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_smoke.109911950982079292953553800100952200163831
998547612364706028932075195432943877
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.72273776070260064254351657647825215644163378981920998349945516080282963968073
Short name T925
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.71 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:28 PM PST 23
Peak memory 639160 kb
Host smart-44686b86-b3ab-4ec2-9139-39eb7cb3d0b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72273776070260064254351657647825215644
163378981920998349945516080282963968073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.72273776070260064254351
657647825215644163378981920998349945516080282963968073
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.77526052287399485254989711290937050431806125040608948940673035116830263772737
Short name T391
Test name
Test status
Simulation time 834576440 ps
CPU time 3.1 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:21:06 PM PST 23
Peak memory 202908 kb
Host smart-203f2965-6bff-46fa-b156-a50a83c21ebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775260522873994852549897112909370504318061250406089
48940673035116830263772737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_perf.775260522873994852549897112909370504318061250406089
48940673035116830263772737
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.60774459694574512280991366498245904420292566976718178399748989167492749914530
Short name T1462
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.1 seconds
Started Nov 22 02:20:50 PM PST 23
Finished Nov 22 02:21:00 PM PST 23
Peak memory 203016 kb
Host smart-1bc5514f-b01a-4fc6-9241-d24b6601248d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6077445969457451228099136649824590442029256697671817839974898916749274
9914530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smoke.60774459694574512280991366498245904420292566976718178399748989167492749914530
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.23501387918055574680344194756604399643858730134864493534840532341301154738300
Short name T1426
Test name
Test status
Simulation time 66540157934 ps
CPU time 1482.76 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:45:49 PM PST 23
Peak memory 6983388 kb
Host smart-1a7ef67f-e0c5-49cd-a50f-888ba0db7d3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23501387918055574680344194756604399643858730134864
493534840532341301154738300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_all.23501387918055574680344194756604399643
858730134864493534840532341301154738300
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.99902177446087200043333680284737335122416511576978867916301151917569341508534
Short name T1390
Test name
Test status
Simulation time 997771563 ps
CPU time 8.92 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:15 PM PST 23
Peak memory 203048 kb
Host smart-2c415016-ca7d-4f14-9f2d-20db02ae2718
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9990217744608720004333368028473733512241651157697886791630115191756934
1508534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_rd.999021774460872000433336802847373351224165115769788679163011
51917569341508534
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.25556891039354635012381011982231275115206692043979837399084449228345059971021
Short name T1494
Test name
Test status
Simulation time 14461449567 ps
CPU time 90.26 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 1542080 kb
Host smart-6371c93f-a0d5-4723-9e1b-36a0046aea9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555689103935463501238101198223127511520669204397983739908444922834505
9971021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_wr.255568910393546350123810119822312751152066920439798373990844
49228345059971021
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.11178481731330980610581621655365513111333191264653195704818586438352853287278
Short name T415
Test name
Test status
Simulation time 6281818576 ps
CPU time 79.35 seconds
Started Nov 22 02:20:51 PM PST 23
Finished Nov 22 02:22:10 PM PST 23
Peak memory 930604 kb
Host smart-3a6c1f7c-d24e-4b43-862c-345841ac929d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117848173133098061058162165536551311133319126465319570481858643835285
3287278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stretch.1117848173133098061058162165536551311133319126465319570481858643
8352853287278
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.19874867975542001075062789527449021791930800186926034885040043071288075938216
Short name T590
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.32 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:21:10 PM PST 23
Peak memory 212748 kb
Host smart-4d1a5980-7828-467f-abee-18cc8aec0eff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198748679755420010750627895274490217919308001869260
34885040043071288075938216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_timeout.198748679755420010750627895274490217919308001
86926034885040043071288075938216
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_ovf.97771063620917328875954639958320653397668354616399460116724061916092433394461
Short name T1211
Test name
Test status
Simulation time 5445414553 ps
CPU time 123.45 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:23:13 PM PST 23
Peak memory 406752 kb
Host smart-09f31f96-611f-41bf-80e2-66299450fcb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97771063620917328875954639958320653397668354616399
460116724061916092433394461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_tx_ovf.9777106362091732887595463995832065339766835461
6399460116724061916092433394461
Directory /workspace/16.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.71943702196998591181223094165498636588743463983766625368556886344982469095970
Short name T841
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.68 seconds
Started Nov 22 02:20:50 PM PST 23
Finished Nov 22 02:20:57 PM PST 23
Peak memory 205252 kb
Host smart-f95bc861-6f26-432d-9c2b-49fe021db7a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719437021969985911812230941654986365887434639837666
25368556886344982469095970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_unexp_stop.71943702196998591181223094165498636588743
463983766625368556886344982469095970
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.99525380119465228310092164954119098536930671837197414530007092184117375120546
Short name T658
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:21:08 PM PST 23
Peak memory 202652 kb
Host smart-dc7fb422-ed00-48c1-8b91-350a4861b5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99525380119465228310092164954119098536930671837197414530007092184117375120546 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_alert_test.99525380119465228310092164954119098536930671837197414530007092184117375120546
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.26688815625306708224085739556525330097000531768484030313321354919639126362825
Short name T305
Test name
Test status
Simulation time 74225396 ps
CPU time 1.43 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:13 PM PST 23
Peak memory 211248 kb
Host smart-6793ca33-ed5c-4583-968b-71a70b98eb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26688815625306708224085739556525330097000531768484030313321354919639126362825 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_host_error_intr.26688815625306708224085739556525330097000531768484030313321354919639126362825
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.110181678633377112493197641423007645461696628869665604879551489806880172979908
Short name T1442
Test name
Test status
Simulation time 606667565 ps
CPU time 6.7 seconds
Started Nov 22 02:20:51 PM PST 23
Finished Nov 22 02:20:58 PM PST 23
Peak memory 273352 kb
Host smart-0a37eec5-d9f6-4aa6-926d-0e18fa87c9f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110181678633377112493197641423007645461696628869665604879551489806880172979908 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.110181678633377112493197641423007645461696628869665604879551489806880172979908
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.28310675493971437203534261901910679242167356465068079892176336679404660203087
Short name T467
Test name
Test status
Simulation time 3768267272 ps
CPU time 70.9 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 729488 kb
Host smart-a4ef59e9-2139-4f2b-9168-f5fb52fdae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28310675493971437203534261901910679242167356465068079892176336679404660203087 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_host_fifo_full.28310675493971437203534261901910679242167356465068079892176336679404660203087
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.30971982573661473939501580232371269925768253934764972211556459775693849384780
Short name T465
Test name
Test status
Simulation time 7925734012 ps
CPU time 228.7 seconds
Started Nov 22 02:20:51 PM PST 23
Finished Nov 22 02:24:41 PM PST 23
Peak memory 1271532 kb
Host smart-184b8fce-2fff-4c56-a9fe-69f7e3c20233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30971982573661473939501580232371269925768253934764972211556459775693849384780 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.i2c_host_fifo_overflow.30971982573661473939501580232371269925768253934764972211556459775693849384780
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.36266681802872149595099996967884667547246097797138724046183568190237104845197
Short name T1530
Test name
Test status
Simulation time 209010032 ps
CPU time 0.92 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:12 PM PST 23
Peak memory 202672 kb
Host smart-2aee0259-bf02-4105-bc39-488cf950396f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36266681802872149595099996967884667547246097797138724046183568190237104845197 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.36266681802872149595099996967884667547246097797138724046183568190237104845197
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.80735378254403727588509642328959015856415810822681062972264001217321896633392
Short name T71
Test name
Test status
Simulation time 236313385 ps
CPU time 3.91 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:21:11 PM PST 23
Peak memory 225560 kb
Host smart-83461b92-795c-460a-b6b3-80560a049f56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80735378254403727588509642328959015856415810822681062972264001217321896633392 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.80735378254403727588509642328959015856415810822681062972264001217321896633392
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.104687728995607730117456121717797220455216670084872954188515477576448414708734
Short name T1026
Test name
Test status
Simulation time 7918519784 ps
CPU time 244.82 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:25:09 PM PST 23
Peak memory 1310992 kb
Host smart-6838f1c1-6d25-41c0-9ee7-9a6014a6d4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104687728995607730117456121717797220455216670084872954188515477576448414708734 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_host_fifo_watermark.104687728995607730117456121717797220455216670084872954188515477576448414708734
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.83356937462635168973959636423555966261932731360924481357367634616746357082216
Short name T58
Test name
Test status
Simulation time 3754070957 ps
CPU time 52.86 seconds
Started Nov 22 02:20:57 PM PST 23
Finished Nov 22 02:21:51 PM PST 23
Peak memory 293660 kb
Host smart-05f4edb3-f833-4ab3-b908-bee970120de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83356937462635168973959636423555966261932731360924481357367634616746357082216 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_host_mode_toggle.83356937462635168973959636423555966261932731360924481357367634616746357082216
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.94295287931839352457163054522107518339038943378286720456181478225592618470676
Short name T1558
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:21:01 PM PST 23
Finished Nov 22 02:21:03 PM PST 23
Peak memory 202868 kb
Host smart-0c399298-5e7c-41e6-a9f9-991f98246f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94295287931839352457163054522107518339038943378286720456181478225592618470676 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_host_override.94295287931839352457163054522107518339038943378286720456181478225592618470676
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.72610322630261050433996002182822540102481422484494082104107355307471308359448
Short name T1372
Test name
Test status
Simulation time 6830796343 ps
CPU time 61.65 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:22:08 PM PST 23
Peak memory 211304 kb
Host smart-1d3a5769-f879-463b-a266-bed8c7ed0824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72610322630261050433996002182822540102481422484494082104107355307471308359448 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.i2c_host_perf.72610322630261050433996002182822540102481422484494082104107355307471308359448
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_rx_oversample.64567534312113905437598751906247720770557885058449311934377645405906571322193
Short name T1192
Test name
Test status
Simulation time 3939158762 ps
CPU time 104.69 seconds
Started Nov 22 02:20:47 PM PST 23
Finished Nov 22 02:22:33 PM PST 23
Peak memory 345972 kb
Host smart-96c8f2ee-9a4b-4950-abb6-b7899e9ee685
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64567534312113905437598751906247720770557885058449311934377645405906571322193 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_rx_oversample.64567534312113905437598751906247720770557885058449311934377645405906571322193
Directory /workspace/17.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.114890774085914769998017698766230280479904597902117377976961706016617641424076
Short name T1225
Test name
Test status
Simulation time 2343171530 ps
CPU time 38.24 seconds
Started Nov 22 02:20:50 PM PST 23
Finished Nov 22 02:21:29 PM PST 23
Peak memory 299344 kb
Host smart-db768ab7-fc55-498d-86f6-d5c63face272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114890774085914769998017698766230280479904597902117377976961706016617641424076 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.i2c_host_smoke.114890774085914769998017698766230280479904597902117377976961706016617641424076
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.93645844313540344056235920319952672969329583804088589121319133110359389372716
Short name T556
Test name
Test status
Simulation time 32807463528 ps
CPU time 1123.72 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:39:52 PM PST 23
Peak memory 1957056 kb
Host smart-9ad59131-dfb1-4c78-8907-5456aaa5bd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93645844313540344056235920319952672969329583804088589121319133110359389372716 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_host_stress_all.93645844313540344056235920319952672969329583804088589121319133110359389372716
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.43961114037212575448361237076062856377643822630602290221561991399755359324776
Short name T1115
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.79 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:21:17 PM PST 23
Peak memory 214180 kb
Host smart-a3a03b33-1415-457a-800f-7e74a98c6f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43961114037212575448361237076062856377643822630602290221561991399755359324776 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_host_stretch_timeout.43961114037212575448361237076062856377643822630602290221561991399755359324776
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.88456067996027436902604349743422592218050222083352416952244252399286170214346
Short name T1319
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.84 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:21:08 PM PST 23
Peak memory 203016 kb
Host smart-2362e570-e5ec-43f5-b01e-cff86e44b800
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8845606799602743690260434974342
2592218050222083352416952244252399286170214346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.88456067996027436902604349
743422592218050222083352416952244252399286170214346
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.9033112259029898665605994144893420317670071532325185556080053619424319765292
Short name T918
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.22 seconds
Started Nov 22 02:21:05 PM PST 23
Finished Nov 22 02:21:39 PM PST 23
Peak memory 382164 kb
Host smart-923309b4-7118-4e97-806d-2e3b4ff8f4e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903311225902989866560599414489342031767007153232518
5556080053619424319765292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.90331122590298986656059941448934
20317670071532325185556080053619424319765292
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.35867255601607732483591355535831448720358054764704478016018176351186547607644
Short name T997
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.14 seconds
Started Nov 22 02:20:54 PM PST 23
Finished Nov 22 02:21:31 PM PST 23
Peak memory 462212 kb
Host smart-60a42e72-12b3-44d2-aee0-cdbe9b52eaa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358672556016077324835913555358314487203580547647044
78016018176351186547607644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_tx.358672556016077324835913555358314
48720358054764704478016018176351186547607644
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.21133260810871164910807797282106533649802030734379589048244257066603872239682
Short name T825
Test name
Test status
Simulation time 825344371 ps
CPU time 2.55 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:21:05 PM PST 23
Peak memory 202992 kb
Host smart-c49c118c-8076-48f3-9901-80faf2c49962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211332608108711649108077972821065336498020307343795
89048244257066603872239682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_hrst.211332608108711649108077972821065336498020307343795
89048244257066603872239682
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.5308258376136323012808999897153104628233881130044687599135607071107065790423
Short name T1523
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.27 seconds
Started Nov 22 02:21:02 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 203576 kb
Host smart-82b75764-aa91-4e04-99a6-e5de9638520b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53082583761363230128089998971531046282338811300446
87599135607071107065790423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_smoke.53082583761363230128089998971531046282338811
30044687599135607071107065790423
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.43053974578139638968883347963158475935617056416576895812915373514787948213847
Short name T1534
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.76 seconds
Started Nov 22 02:21:13 PM PST 23
Finished Nov 22 02:21:36 PM PST 23
Peak memory 639172 kb
Host smart-2f12d7a4-388f-427a-90a8-db349480a829
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43053974578139638968883347963158475935
617056416576895812915373514787948213847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.43053974578139638968883
347963158475935617056416576895812915373514787948213847
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.104935498999048993057571358972140764776537949594287873036671354603553431416797
Short name T675
Test name
Test status
Simulation time 834576440 ps
CPU time 2.96 seconds
Started Nov 22 02:20:52 PM PST 23
Finished Nov 22 02:20:56 PM PST 23
Peak memory 202840 kb
Host smart-54dd45e6-1556-405f-8f5b-5c3cf6d4ce44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104935498999048993057571358972140764776537949594287
873036671354603553431416797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_perf.10493549899904899305757135897214076477653794959428
7873036671354603553431416797
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.103644409577188837022921915146718026957491730277566749368572388703899802305225
Short name T176
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.58 seconds
Started Nov 22 02:21:05 PM PST 23
Finished Nov 22 02:21:16 PM PST 23
Peak memory 202940 kb
Host smart-60a3a17f-84f1-43a9-a1d8-11b7708cae53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036444095771888370229219151467180269574917302775667493685723887038998
02305225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smoke.103644409577188837022921915146718026957491730277566749368572388703899802305225
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.104569197589479181154647943794436634154566471577386113191114734502772251424757
Short name T795
Test name
Test status
Simulation time 66540157934 ps
CPU time 1409.64 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:44:39 PM PST 23
Peak memory 6983872 kb
Host smart-f3f0b949-1070-4a0f-bfb9-561c348b8517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10456919758947918115464794379443663415456647157738
6113191114734502772251424757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_all.1045691975894791811546479437944366341
54566471577386113191114734502772251424757
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.111943568899149487031787090990214133612981160893721729911246808568383720333141
Short name T377
Test name
Test status
Simulation time 997771563 ps
CPU time 8.67 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:21:18 PM PST 23
Peak memory 202984 kb
Host smart-37b22e6a-cf95-4770-ac7f-3137fc8fe3d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119435688991494870317870909902141336129811608937217299112468085683837
20333141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_rd.11194356889914948703178709099021413361298116089372172991124
6808568383720333141
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.34770035779680769464070325781336915567780329849028199966639952069722389146075
Short name T1240
Test name
Test status
Simulation time 14461449567 ps
CPU time 81.7 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:22:28 PM PST 23
Peak memory 1542112 kb
Host smart-58e9dd5b-3cc4-4348-b3cd-15d7f7430b22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477003577968076946407032578133691556778032984902819996663995206972238
9146075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_wr.347700357796807694640703257813369155677803298490281999666399
52069722389146075
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.103484139113122729400003622281226205051241187839559327941199438248804745780990
Short name T1133
Test name
Test status
Simulation time 6281818576 ps
CPU time 74.6 seconds
Started Nov 22 02:21:07 PM PST 23
Finished Nov 22 02:22:23 PM PST 23
Peak memory 930628 kb
Host smart-89c7d580-98d2-4510-ac01-eeddc0548d95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034841391131227294000036222812262050512411878395593279411994382488047
45780990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stretch.103484139113122729400003622281226205051241187839559327941199438
248804745780990
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.94454664353498034610727054440834067898315082664792953859029129204883600649850
Short name T1241
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.32 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:21:18 PM PST 23
Peak memory 212664 kb
Host smart-a0e5f66d-ce95-48c9-b624-f39db97a45a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944546643534980346107270544408340678983150826647929
53859029129204883600649850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_timeout.944546643534980346107270544408340678983150826
64792953859029129204883600649850
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_ovf.86456072277575606759611266735931530923374766382189457532472655954629186738492
Short name T1445
Test name
Test status
Simulation time 5445414553 ps
CPU time 133.42 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:23:17 PM PST 23
Peak memory 406820 kb
Host smart-fcbe2c67-2210-4a19-8f6b-70d8c9b28c7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86456072277575606759611266735931530923374766382189
457532472655954629186738492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_tx_ovf.8645607227757560675961126673593153092337476638
2189457532472655954629186738492
Directory /workspace/17.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.59917048162056610953647375909498277968743881365267274388917809117246282376252
Short name T1283
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.84 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:21:15 PM PST 23
Peak memory 205308 kb
Host smart-87588ee3-5d02-4ac9-ae91-976510d8d665
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599170481620566109536473759094982779687438813652672
74388917809117246282376252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_unexp_stop.59917048162056610953647375909498277968743
881365267274388917809117246282376252
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_alert_test.79813497613883479812479566695833528571901444657190044283921857342766007215368
Short name T1203
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:21:09 PM PST 23
Peak memory 202800 kb
Host smart-6fae91cf-fc88-4593-a102-05627764ffa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79813497613883479812479566695833528571901444657190044283921857342766007215368 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_alert_test.79813497613883479812479566695833528571901444657190044283921857342766007215368
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.14832077925224865291977469180106528720412490959356819549023876554801541524791
Short name T728
Test name
Test status
Simulation time 74225396 ps
CPU time 1.35 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:21:12 PM PST 23
Peak memory 211232 kb
Host smart-d3702e2b-5c3b-425a-b2fa-1e4ecb153ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14832077925224865291977469180106528720412490959356819549023876554801541524791 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_host_error_intr.14832077925224865291977469180106528720412490959356819549023876554801541524791
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.22644536045216378104117113649150560516661046573674179022157059239781770584025
Short name T5
Test name
Test status
Simulation time 606667565 ps
CPU time 6.7 seconds
Started Nov 22 02:20:57 PM PST 23
Finished Nov 22 02:21:05 PM PST 23
Peak memory 272716 kb
Host smart-59e87182-b65d-455d-81c4-7f26f255f9e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22644536045216378104117113649150560516661046573674179022157059239781770584025 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.22644536045216378104117113649150560516661046573674179022157059239781770584025
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.87547487179588924856153133321891110381995753851584879266068943179706028615130
Short name T1149
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.74 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:22:26 PM PST 23
Peak memory 729508 kb
Host smart-ecd24908-740b-48a5-9fa9-72aa2a17f2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87547487179588924856153133321891110381995753851584879266068943179706028615130 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_host_fifo_full.87547487179588924856153133321891110381995753851584879266068943179706028615130
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.37809767785511174374991527101813038686414202966087929348521274966383699230943
Short name T1497
Test name
Test status
Simulation time 7925734012 ps
CPU time 215.56 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:24:46 PM PST 23
Peak memory 1271492 kb
Host smart-cb3ad5b1-3773-40bd-9723-9535c8839496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37809767785511174374991527101813038686414202966087929348521274966383699230943 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.i2c_host_fifo_overflow.37809767785511174374991527101813038686414202966087929348521274966383699230943
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.18227869868523957862480672770399846228747295001164161846844634730257592322064
Short name T519
Test name
Test status
Simulation time 236313385 ps
CPU time 3.73 seconds
Started Nov 22 02:21:07 PM PST 23
Finished Nov 22 02:21:12 PM PST 23
Peak memory 225572 kb
Host smart-b191f41a-4674-470c-acc3-a056d4983da4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18227869868523957862480672770399846228747295001164161846844634730257592322064 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.18227869868523957862480672770399846228747295001164161846844634730257592322064
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.97289440197515310979917917595350719062457037872805998659391321113018692879743
Short name T358
Test name
Test status
Simulation time 7918519784 ps
CPU time 207.92 seconds
Started Nov 22 02:21:07 PM PST 23
Finished Nov 22 02:24:36 PM PST 23
Peak memory 1310968 kb
Host smart-c24e5436-dfad-49c3-afc1-0b742f4510b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97289440197515310979917917595350719062457037872805998659391321113018692879743 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.i2c_host_fifo_watermark.97289440197515310979917917595350719062457037872805998659391321113018692879743
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.41165378988640892493692212836137282507984341937683549909995306899407429722512
Short name T294
Test name
Test status
Simulation time 3754070957 ps
CPU time 55.43 seconds
Started Nov 22 02:21:13 PM PST 23
Finished Nov 22 02:22:10 PM PST 23
Peak memory 293728 kb
Host smart-fb946732-95c0-4d7c-869b-a48fac39efe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41165378988640892493692212836137282507984341937683549909995306899407429722512 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_host_mode_toggle.41165378988640892493692212836137282507984341937683549909995306899407429722512
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2551479708369131327852093861737371322997871928738260368550575266147100694907
Short name T1563
Test name
Test status
Simulation time 23672229 ps
CPU time 0.66 seconds
Started Nov 22 02:20:57 PM PST 23
Finished Nov 22 02:20:59 PM PST 23
Peak memory 202144 kb
Host smart-88c6565b-a2fb-483c-a707-c66e2c1d45ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551479708369131327852093861737371322997871928738260368550575266147100694907 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_host_override.2551479708369131327852093861737371322997871928738260368550575266147100694907
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.76979943828582622080810127290229271929709220085716418946650416892834838255147
Short name T945
Test name
Test status
Simulation time 6830796343 ps
CPU time 62.62 seconds
Started Nov 22 02:21:01 PM PST 23
Finished Nov 22 02:22:05 PM PST 23
Peak memory 211324 kb
Host smart-2575bb8d-df95-4f95-b096-54dbc8fe9b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76979943828582622080810127290229271929709220085716418946650416892834838255147 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.i2c_host_perf.76979943828582622080810127290229271929709220085716418946650416892834838255147
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_rx_oversample.114903404748375071923810945587689941383009127273240866264173610476573928694662
Short name T924
Test name
Test status
Simulation time 3939158762 ps
CPU time 101.08 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:22:48 PM PST 23
Peak memory 345880 kb
Host smart-05ba971d-4a18-4369-bb02-1d94b7d4f3e5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114903404748375071923810945587689941383009127273240866264173610476573928694662 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_rx_oversample.114903404748375071923810945587689941383009127273240866264173610476573928694662
Directory /workspace/18.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.54647462104812979293279460424230085649506589185486973985160640764989216322612
Short name T390
Test name
Test status
Simulation time 2343171530 ps
CPU time 41.34 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 299440 kb
Host smart-3eff2e46-9bb2-4e0c-8b63-5cf259c11b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54647462104812979293279460424230085649506589185486973985160640764989216322612 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.i2c_host_smoke.54647462104812979293279460424230085649506589185486973985160640764989216322612
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.77372800648726800449557071821938440962726106828800085642560903645819170523143
Short name T969
Test name
Test status
Simulation time 32807463528 ps
CPU time 1197.65 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:41:03 PM PST 23
Peak memory 1957040 kb
Host smart-58e75035-d1ba-4082-96f3-8b737efa2d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77372800648726800449557071821938440962726106828800085642560903645819170523143 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_host_stress_all.77372800648726800449557071821938440962726106828800085642560903645819170523143
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.105841247168972954282926202102457422496095802906030607329683206333812361261696
Short name T1091
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.53 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:25 PM PST 23
Peak memory 213940 kb
Host smart-1fdbf06e-a358-4f73-9830-bce40b06bbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105841247168972954282926202102457422496095802906030607329683206333812361261696 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_host_stretch_timeout.105841247168972954282926202102457422496095802906030607329683206333812361261696
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.6295090049978256024716031416000566326290257249848089933926790983836325271125
Short name T352
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.91 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:21:20 PM PST 23
Peak memory 202956 kb
Host smart-1603fc0a-4819-4d01-8ea0-ee221f7599a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6295090049978256024716031416000
566326290257249848089933926790983836325271125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.629509004997825602471603141
6000566326290257249848089933926790983836325271125
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.68709771447238719584805770587828419385045390773548295358669696147005185490123
Short name T773
Test name
Test status
Simulation time 10166144644 ps
CPU time 30.97 seconds
Started Nov 22 02:21:12 PM PST 23
Finished Nov 22 02:21:44 PM PST 23
Peak memory 382232 kb
Host smart-b87b1d17-37f5-4db6-bd85-d1e1f5d46825
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687097714472387195848057705878284193850453907735482
95358669696147005185490123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.6870977144723871958480577058782
8419385045390773548295358669696147005185490123
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.74315009838912961990638030800934135196170921364021517731286101621223363733129
Short name T1339
Test name
Test status
Simulation time 10065199023 ps
CPU time 38.63 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:50 PM PST 23
Peak memory 461808 kb
Host smart-ffdeddce-f6bb-4032-976e-046831cc684a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743150098389129619906380308009341351961709213640215
17731286101621223363733129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_tx.743150098389129619906380308009341
35196170921364021517731286101621223363733129
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.104436000025681549069078950042715339172850903347495355670202420927819843960588
Short name T1423
Test name
Test status
Simulation time 825344371 ps
CPU time 2.46 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:21:12 PM PST 23
Peak memory 203088 kb
Host smart-88f0bf09-aef3-4145-98ab-bb98b0bfa870
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104436000025681549069078950042715339172850903347495
355670202420927819843960588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_hrst.10443600002568154906907895004271533917285090334749
5355670202420927819843960588
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.86814713656337457414969414129329384572486205522026437707980441308314540678267
Short name T1019
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.52 seconds
Started Nov 22 02:21:03 PM PST 23
Finished Nov 22 02:21:09 PM PST 23
Peak memory 203824 kb
Host smart-12aafc80-d01f-4d34-9b59-36d448b61085
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86814713656337457414969414129329384572486205522026
437707980441308314540678267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_smoke.8681471365633745741496941412932938457248620
5522026437707980441308314540678267
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.93037881838061205052386053696062798812308816371356964049235408923813791733525
Short name T843
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.92 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:21:34 PM PST 23
Peak memory 639204 kb
Host smart-085bd65d-eb32-433b-bdfd-589052aae4f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93037881838061205052386053696062798812
308816371356964049235408923813791733525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.93037881838061205052386
053696062798812308816371356964049235408923813791733525
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.100410049983565302007640670479746235589560300247200081520903009556702702653455
Short name T448
Test name
Test status
Simulation time 834576440 ps
CPU time 3.08 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:08 PM PST 23
Peak memory 203068 kb
Host smart-e6f49a22-f51a-41fb-8c00-4a53628f3455
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100410049983565302007640670479746235589560300247200
081520903009556702702653455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_perf.10041004998356530200764067047974623558956030024720
0081520903009556702702653455
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.44608850543873691084194420421817776403796343214255318682794751950102686969119
Short name T562
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.34 seconds
Started Nov 22 02:21:05 PM PST 23
Finished Nov 22 02:21:15 PM PST 23
Peak memory 202924 kb
Host smart-56a55d9c-1a34-4d13-abf2-f1af6b98d877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4460885054387369108419442042181777640379634321425531868279475195010268
6969119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smoke.44608850543873691084194420421817776403796343214255318682794751950102686969119
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.1808620919972667876011395038352465983717460673273415033796324632007683450390
Short name T745
Test name
Test status
Simulation time 66540157934 ps
CPU time 1469.21 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:45:40 PM PST 23
Peak memory 6983548 kb
Host smart-f9c19f58-fe49-4546-be51-67a906c7428a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18086209199726678760113950383524659837174606732734
15033796324632007683450390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_all.180862091997266787601139503835246598371
7460673273415033796324632007683450390
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.37618634886073010365299173137258279380350430746286193275713494902059731600524
Short name T460
Test name
Test status
Simulation time 997771563 ps
CPU time 8.93 seconds
Started Nov 22 02:21:01 PM PST 23
Finished Nov 22 02:21:11 PM PST 23
Peak memory 202896 kb
Host smart-ed43194f-bd48-4636-adf7-ea7554f3d1dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761863488607301036529917313725827938035043074628619327571349490205973
1600524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_rd.376186348860730103652991731372582793803504307462861932757134
94902059731600524
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.32755239662153175920178631797457951048456424779586330697847196706474764244497
Short name T735
Test name
Test status
Simulation time 14461449567 ps
CPU time 81.6 seconds
Started Nov 22 02:21:05 PM PST 23
Finished Nov 22 02:22:28 PM PST 23
Peak memory 1542036 kb
Host smart-f6744bcc-0c77-4a9e-85dc-1dac0116ee1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275523966215317592017863179745795104845642477958633069784719670647476
4244497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_wr.327552396621531759201786317974579510484564247795863306978471
96706474764244497
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.66889929388697060360574120295374799415430126330517476749826478328586746443558
Short name T421
Test name
Test status
Simulation time 6281818576 ps
CPU time 86.18 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:22:42 PM PST 23
Peak memory 930472 kb
Host smart-023f4f07-0624-4767-9a2c-846e13350c78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6688992938869706036057412029537479941543012633051747674982647832858674
6443558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stretch.6688992938869706036057412029537479941543012633051747674982647832
8586746443558
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.29561824846124983076292344683274052812424615128205224299883416985866111387536
Short name T411
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.88 seconds
Started Nov 22 02:21:04 PM PST 23
Finished Nov 22 02:21:14 PM PST 23
Peak memory 212612 kb
Host smart-4e0844ad-274c-483c-8d6d-6039bace8aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295618248461249830762923446832740528124246151282052
24299883416985866111387536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_timeout.295618248461249830762923446832740528124246151
28205224299883416985866111387536
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_ovf.102999839244803181564312890859866196973347560510010409470729705899983699593419
Short name T1459
Test name
Test status
Simulation time 5445414553 ps
CPU time 114.53 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:23:02 PM PST 23
Peak memory 406824 kb
Host smart-598f49e1-dfdf-48b5-881e-87f7dbe5def0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10299983924480318156431289085986619697334756051001
0409470729705899983699593419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_tx_ovf.102999839244803181564312890859866196973347560
510010409470729705899983699593419
Directory /workspace/18.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.111206036890926653257837994299377263507725634819240505237750627347871927261382
Short name T764
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.56 seconds
Started Nov 22 02:21:05 PM PST 23
Finished Nov 22 02:21:12 PM PST 23
Peak memory 205364 kb
Host smart-342db729-bae5-41ab-a4a9-469883e2c5bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111206036890926653257837994299377263507725634819240
505237750627347871927261382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_unexp_stop.1112060368909266532578379942993772635077
25634819240505237750627347871927261382
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.8943595575772094076610523281272384219282158095661627833546497623600835376482
Short name T836
Test name
Test status
Simulation time 19975830 ps
CPU time 0.61 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:21:10 PM PST 23
Peak memory 202596 kb
Host smart-27ee9dc8-fdfa-43d8-bd6d-4f93cb2c59d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8943595575772094076610523281272384219282158095661627833546497623600835376482 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_alert_test.8943595575772094076610523281272384219282158095661627833546497623600835376482
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.87915988106739086402276618478495599388456966414343180695961270589631094723523
Short name T335
Test name
Test status
Simulation time 74225396 ps
CPU time 1.31 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:21:16 PM PST 23
Peak memory 211084 kb
Host smart-9f2f566a-659b-4a8e-bbfc-d55f29971698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87915988106739086402276618478495599388456966414343180695961270589631094723523 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_host_error_intr.87915988106739086402276618478495599388456966414343180695961270589631094723523
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.41851479041682772017599397472859311687206426997741783699981079531530340939488
Short name T1204
Test name
Test status
Simulation time 606667565 ps
CPU time 6.87 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:21:22 PM PST 23
Peak memory 273284 kb
Host smart-7ad73b2c-d526-4c3b-84d7-4dc463f8ce32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41851479041682772017599397472859311687206426997741783699981079531530340939488 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.41851479041682772017599397472859311687206426997741783699981079531530340939488
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.61646081627675870318376274447143913402352608098944047485973825058088987564967
Short name T235
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.93 seconds
Started Nov 22 02:21:06 PM PST 23
Finished Nov 22 02:22:23 PM PST 23
Peak memory 729428 kb
Host smart-b4bb02cb-ec4d-4e48-92d6-91e2dbb05592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61646081627675870318376274447143913402352608098944047485973825058088987564967 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_host_fifo_full.61646081627675870318376274447143913402352608098944047485973825058088987564967
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.104179649816477773782721245562535790813372284388759938472831426373252160864964
Short name T432
Test name
Test status
Simulation time 7925734012 ps
CPU time 268.22 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:25:39 PM PST 23
Peak memory 1271512 kb
Host smart-81854523-e64b-4f33-a7a5-29d8e269e74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104179649816477773782721245562535790813372284388759938472831426373252160864964 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.i2c_host_fifo_overflow.104179649816477773782721245562535790813372284388759938472831426373252160864964
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.62101459651941150925948219337812376656107157186122317709742633546828169937115
Short name T688
Test name
Test status
Simulation time 209010032 ps
CPU time 0.94 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:21:11 PM PST 23
Peak memory 202888 kb
Host smart-6f1f326c-0431-4523-8bc4-d166fef75849
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62101459651941150925948219337812376656107157186122317709742633546828169937115 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.62101459651941150925948219337812376656107157186122317709742633546828169937115
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.32784058896965614574495197553824074873087634169891541555253222697508000247275
Short name T1083
Test name
Test status
Simulation time 236313385 ps
CPU time 3.78 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:21:13 PM PST 23
Peak memory 225456 kb
Host smart-4860ec96-c8d1-4dd5-b89d-0bd745e4a0d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32784058896965614574495197553824074873087634169891541555253222697508000247275 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.32784058896965614574495197553824074873087634169891541555253222697508000247275
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.53902694155281003155817933759568241390150622049145902787746015216086133960280
Short name T822
Test name
Test status
Simulation time 7918519784 ps
CPU time 199.89 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:24:31 PM PST 23
Peak memory 1310888 kb
Host smart-cd6665e0-b9e4-45b2-a8fa-899c3ff09335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53902694155281003155817933759568241390150622049145902787746015216086133960280 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.i2c_host_fifo_watermark.53902694155281003155817933759568241390150622049145902787746015216086133960280
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.95678283556234084559372980441191621970517638001894215611444971900595061697676
Short name T1030
Test name
Test status
Simulation time 3754070957 ps
CPU time 52.27 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:22:08 PM PST 23
Peak memory 293560 kb
Host smart-0eb48e70-62e2-463d-831b-ce742c868251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95678283556234084559372980441191621970517638001894215611444971900595061697676 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_host_mode_toggle.95678283556234084559372980441191621970517638001894215611444971900595061697676
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.4903477625823559805910018450196006324507943152352507420677666485441605907759
Short name T1252
Test name
Test status
Simulation time 23672229 ps
CPU time 0.61 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:21:10 PM PST 23
Peak memory 202808 kb
Host smart-6b0a749f-2c66-402f-b4fa-74d733997294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4903477625823559805910018450196006324507943152352507420677666485441605907759 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_host_override.4903477625823559805910018450196006324507943152352507420677666485441605907759
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.82190639272193468539626511015074535320259785815589537521634095895087188905275
Short name T508
Test name
Test status
Simulation time 6830796343 ps
CPU time 62.44 seconds
Started Nov 22 02:21:11 PM PST 23
Finished Nov 22 02:22:15 PM PST 23
Peak memory 211360 kb
Host smart-cfb688f7-b797-46a6-ae18-902e3336bfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82190639272193468539626511015074535320259785815589537521634095895087188905275 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.i2c_host_perf.82190639272193468539626511015074535320259785815589537521634095895087188905275
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_rx_oversample.102382105705400236372755660633989898659382497525815739967731902278880560537735
Short name T1193
Test name
Test status
Simulation time 3939158762 ps
CPU time 124.4 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:23:14 PM PST 23
Peak memory 345924 kb
Host smart-3d4e69a0-9705-4314-b661-47e89f3b83e1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102382105705400236372755660633989898659382497525815739967731902278880560537735 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_rx_oversample.102382105705400236372755660633989898659382497525815739967731902278880560537735
Directory /workspace/19.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.33112890150365369725220822681611565243494419047193851848318786783607382480475
Short name T1286
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.83 seconds
Started Nov 22 02:21:13 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 299312 kb
Host smart-2c6e962a-c3cd-4e7e-8f47-5a3f3a9a3f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33112890150365369725220822681611565243494419047193851848318786783607382480475 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.i2c_host_smoke.33112890150365369725220822681611565243494419047193851848318786783607382480475
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.35990701354546273475049130646443567734197959528717808292711460519009691880542
Short name T1023
Test name
Test status
Simulation time 32807463528 ps
CPU time 1038.97 seconds
Started Nov 22 02:21:11 PM PST 23
Finished Nov 22 02:38:31 PM PST 23
Peak memory 1957076 kb
Host smart-b62284c5-e964-4d1a-844f-dbe9b941ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35990701354546273475049130646443567734197959528717808292711460519009691880542 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_host_stress_all.35990701354546273475049130646443567734197959528717808292711460519009691880542
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.23514355075813447686087054370321487085111748364563525618657895659446769867066
Short name T272
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.42 seconds
Started Nov 22 02:21:08 PM PST 23
Finished Nov 22 02:21:22 PM PST 23
Peak memory 214140 kb
Host smart-369c9ef5-2076-46a4-93df-f59050a54ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23514355075813447686087054370321487085111748364563525618657895659446769867066 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_host_stretch_timeout.23514355075813447686087054370321487085111748364563525618657895659446769867066
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.107845092574806954510020666523056748644842861254504792574636429503531804229140
Short name T995
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.79 seconds
Started Nov 22 02:21:11 PM PST 23
Finished Nov 22 02:21:16 PM PST 23
Peak memory 203028 kb
Host smart-fd3da8b7-71ba-46e7-9eaa-11e4cdc9572f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078450925748069545100206665230
56748644842861254504792574636429503531804229140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1078450925748069545100206
66523056748644842861254504792574636429503531804229140
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.60772138732443171815777109296639854640621501391034613495983046737203906980473
Short name T389
Test name
Test status
Simulation time 10166144644 ps
CPU time 31 seconds
Started Nov 22 02:21:13 PM PST 23
Finished Nov 22 02:21:44 PM PST 23
Peak memory 382152 kb
Host smart-d36dc74a-f32b-4497-a88c-ae623cecf949
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607721387324431718157771092966398546406215013910346
13495983046737203906980473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.6077213873244317181577710929663
9854640621501391034613495983046737203906980473
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.62627226081900967224940829454974521470805383028506842354220980218446653365459
Short name T1456
Test name
Test status
Simulation time 10065199023 ps
CPU time 37.85 seconds
Started Nov 22 02:21:13 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 461928 kb
Host smart-f083a66e-db16-4c8e-8ac4-045f35387573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626272260819009672249408294549745214708053830285068
42354220980218446653365459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_tx.626272260819009672249408294549745
21470805383028506842354220980218446653365459
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.42841130202934349891440052847450952053322930975679943267524514489334914646278
Short name T274
Test name
Test status
Simulation time 825344371 ps
CPU time 2.38 seconds
Started Nov 22 02:21:18 PM PST 23
Finished Nov 22 02:21:21 PM PST 23
Peak memory 202988 kb
Host smart-4daeb326-8f37-4fa3-bec9-1acd573f91ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428411302029343498914400528474509520533229309756799
43267524514489334914646278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.428411302029343498914400528474509520533229309756799
43267524514489334914646278
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.102118597524278255063718996577201449871430380547443380359768363626202243051227
Short name T993
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.25 seconds
Started Nov 22 02:21:05 PM PST 23
Finished Nov 22 02:21:11 PM PST 23
Peak memory 203464 kb
Host smart-680b935c-1dfa-4bdb-ba60-3c4aeb0fd9a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10211859752427825506371899657720144987143038054744
3380359768363626202243051227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_smoke.102118597524278255063718996577201449871430
380547443380359768363626202243051227
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.28192676164295149688648495283032368880337426050160966372065734969141239467573
Short name T326
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.43 seconds
Started Nov 22 02:21:10 PM PST 23
Finished Nov 22 02:21:33 PM PST 23
Peak memory 639144 kb
Host smart-cc7280e7-ed53-483a-85fd-58128b2703e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28192676164295149688648495283032368880
337426050160966372065734969141239467573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.28192676164295149688648
495283032368880337426050160966372065734969141239467573
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.34846005082086980281707288358712346898906435236905138522514386970714714365029
Short name T534
Test name
Test status
Simulation time 834576440 ps
CPU time 3.06 seconds
Started Nov 22 02:21:16 PM PST 23
Finished Nov 22 02:21:20 PM PST 23
Peak memory 203016 kb
Host smart-9cba95d7-2c36-4f64-a0de-83b6bbfaf330
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348460050820869802817072883587123468989064352369051
38522514386970714714365029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_perf.348460050820869802817072883587123468989064352369051
38522514386970714714365029
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.99588841192569610553364724940834239628715410829645245751186383993472269229071
Short name T784
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.58 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:21:25 PM PST 23
Peak memory 202800 kb
Host smart-8ab4ce5f-53c1-447a-847b-5baf927637d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9958884119256961055336472494083423962871541082964524575118638399347226
9229071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smoke.99588841192569610553364724940834239628715410829645245751186383993472269229071
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.107052522256627461450776441492174871564750462661723177137416536120202495673175
Short name T617
Test name
Test status
Simulation time 66540157934 ps
CPU time 1326.53 seconds
Started Nov 22 02:21:12 PM PST 23
Finished Nov 22 02:43:20 PM PST 23
Peak memory 6983760 kb
Host smart-f6a9285f-2fe7-400b-85f3-5659a670ec93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705252225662746145077644149217487156475046266172
3177137416536120202495673175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_all.1070525222566274614507764414921748715
64750462661723177137416536120202495673175
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.45051699465513474750240571043462320779242010193018807136013468862781592601466
Short name T1267
Test name
Test status
Simulation time 997771563 ps
CPU time 8.57 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:21:25 PM PST 23
Peak memory 202796 kb
Host smart-5e640ac7-a342-4323-98e1-6f2477dd6872
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4505169946551347475024057104346232077924201019301880713601346886278159
2601466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_rd.450516994655134747502405710434623207792420101930188071360134
68862781592601466
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.4254649134351420524436201400309033459004105296638873898254727662067303458538
Short name T234
Test name
Test status
Simulation time 14461449567 ps
CPU time 81.42 seconds
Started Nov 22 02:21:12 PM PST 23
Finished Nov 22 02:22:34 PM PST 23
Peak memory 1542076 kb
Host smart-eb285c48-3f17-4ff2-9f62-ee19476ba46c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254649134351420524436201400309033459004105296638873898254727662067303
458538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_wr.4254649134351420524436201400309033459004105296638873898254727
662067303458538
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.95037876512037119231381457433996442593500294773753731006906263478736718606920
Short name T1284
Test name
Test status
Simulation time 6281818576 ps
CPU time 81.7 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:22:33 PM PST 23
Peak memory 930328 kb
Host smart-bc6daf55-2b21-4303-bdd3-15e547316292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9503787651203711923138145743399644259350029477375373100690626347873671
8606920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stretch.9503787651203711923138145743399644259350029477375373100690626347
8736718606920
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.10055674343952017986801716341796352838661901923615300881760043233630910327212
Short name T341
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.4 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:21:18 PM PST 23
Peak memory 211660 kb
Host smart-abf62e82-158a-445f-b9cb-c0b8d25e601f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100556743439520179868017163417963528386619019236153
00881760043233630910327212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_timeout.100556743439520179868017163417963528386619019
23615300881760043233630910327212
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_ovf.1839258756465847008480032350382915564074117749309627614194738419753192471298
Short name T444
Test name
Test status
Simulation time 5445414553 ps
CPU time 116.24 seconds
Started Nov 22 02:21:12 PM PST 23
Finished Nov 22 02:23:09 PM PST 23
Peak memory 406756 kb
Host smart-cf1995d3-3c16-455b-b92a-b8c9bdba51ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18392587564658470084800323503829155640741177493096
27614194738419753192471298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_tx_ovf.18392587564658470084800323503829155640741177493
09627614194738419753192471298
Directory /workspace/19.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.63013329125100161326369448485851281306871915637557170713749018963966814181008
Short name T464
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.41 seconds
Started Nov 22 02:21:14 PM PST 23
Finished Nov 22 02:21:21 PM PST 23
Peak memory 205156 kb
Host smart-f5e69b57-01b9-482a-ae0e-3c3d2c7f3854
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630133291251001613263694484858512813068719156375571
70713749018963966814181008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_unexp_stop.63013329125100161326369448485851281306871
915637557170713749018963966814181008
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.77510349514168312628450292272739725093233859227525390350749006026177708026499
Short name T1208
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:18:19 PM PST 23
Finished Nov 22 02:18:20 PM PST 23
Peak memory 202788 kb
Host smart-b5788a5d-4be2-464d-ac48-672431d209c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77510349514168312628450292272739725093233859227525390350749006026177708026499 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_alert_test.77510349514168312628450292272739725093233859227525390350749006026177708026499
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.85367858804793890313743951172810232767332146117418651680832608527502086961750
Short name T1257
Test name
Test status
Simulation time 74225396 ps
CPU time 1.32 seconds
Started Nov 22 02:17:44 PM PST 23
Finished Nov 22 02:17:47 PM PST 23
Peak memory 211040 kb
Host smart-018f511a-e78b-49bd-ab40-b1590800a102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85367858804793890313743951172810232767332146117418651680832608527502086961750 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_host_error_intr.85367858804793890313743951172810232767332146117418651680832608527502086961750
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.64881781311780164848297773599530619269204437015297346503008634904733148527540
Short name T855
Test name
Test status
Simulation time 606667565 ps
CPU time 6.91 seconds
Started Nov 22 02:18:08 PM PST 23
Finished Nov 22 02:18:16 PM PST 23
Peak memory 273440 kb
Host smart-264aa929-a7df-403b-be98-f0fe08e08464
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64881781311780164848297773599530619269204437015297346503008634904733148527540 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.64881781311780164848297773599530619269204437015297346503008634904733148527540
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.102878297847193594308995499503809745899376401339234741793262587939780687921716
Short name T1044
Test name
Test status
Simulation time 3768267272 ps
CPU time 70.62 seconds
Started Nov 22 02:18:17 PM PST 23
Finished Nov 22 02:19:29 PM PST 23
Peak memory 729328 kb
Host smart-f062c3ff-c3ef-404f-bfb7-c22db2d5eabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102878297847193594308995499503809745899376401339234741793262587939780687921716 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_host_fifo_full.102878297847193594308995499503809745899376401339234741793262587939780687921716
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.79859317700781070341345260924971549682841292535149732746621564598571035587992
Short name T1410
Test name
Test status
Simulation time 7925734012 ps
CPU time 247.04 seconds
Started Nov 22 02:18:35 PM PST 23
Finished Nov 22 02:22:43 PM PST 23
Peak memory 1271600 kb
Host smart-d9c778b2-2b5f-4ee9-a544-8fd2ce7dddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79859317700781070341345260924971549682841292535149732746621564598571035587992 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.i2c_host_fifo_overflow.79859317700781070341345260924971549682841292535149732746621564598571035587992
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.80507412239669255834684903994534189711550640396345925524133030958619030222991
Short name T923
Test name
Test status
Simulation time 209010032 ps
CPU time 0.98 seconds
Started Nov 22 02:18:17 PM PST 23
Finished Nov 22 02:18:19 PM PST 23
Peak memory 202772 kb
Host smart-1594e3b6-3ade-498f-b3c2-110d53baca24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80507412239669255834684903994534189711550640396345925524133030958619030222991 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.80507412239669255834684903994534189711550640396345925524133030958619030222991
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.23618476424161207529261622745351351548899154482640992291347255295798176195326
Short name T200
Test name
Test status
Simulation time 236313385 ps
CPU time 3.73 seconds
Started Nov 22 02:18:33 PM PST 23
Finished Nov 22 02:18:38 PM PST 23
Peak memory 225480 kb
Host smart-ab6e7175-0ed7-4e3d-b600-069e7055a8e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23618476424161207529261622745351351548899154482640992291347255295798176195326 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.23618476424161207529261622745351351548899154482640992291347255295798176195326
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.98626273633453627571472312858675276160828876873046784062759145630496072370888
Short name T1110
Test name
Test status
Simulation time 7918519784 ps
CPU time 214.91 seconds
Started Nov 22 02:17:46 PM PST 23
Finished Nov 22 02:21:21 PM PST 23
Peak memory 1310788 kb
Host smart-5a120eda-7af4-4a05-ab63-80e993f9ec27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98626273633453627571472312858675276160828876873046784062759145630496072370888 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.i2c_host_fifo_watermark.98626273633453627571472312858675276160828876873046784062759145630496072370888
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.27831748537386538179594356893073881111078856068942890650979176773559814337164
Short name T1371
Test name
Test status
Simulation time 3754070957 ps
CPU time 53 seconds
Started Nov 22 02:18:13 PM PST 23
Finished Nov 22 02:19:06 PM PST 23
Peak memory 293748 kb
Host smart-806abb6c-b6b0-4c48-8eb0-59762c92bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27831748537386538179594356893073881111078856068942890650979176773559814337164 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_host_mode_toggle.27831748537386538179594356893073881111078856068942890650979176773559814337164
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.75237356168628295961766131718194642617634872319211119636914627352440907502307
Short name T1282
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:17:46 PM PST 23
Finished Nov 22 02:17:47 PM PST 23
Peak memory 202748 kb
Host smart-61e74744-cd53-4cdc-b31e-bfb96ac6e11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75237356168628295961766131718194642617634872319211119636914627352440907502307 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_host_override.75237356168628295961766131718194642617634872319211119636914627352440907502307
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.37055185603833212855572482739694680600289560284233458721548461839394156304011
Short name T557
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.2 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:19:10 PM PST 23
Peak memory 211460 kb
Host smart-28015785-0df0-41e0-ae52-faad98610e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37055185603833212855572482739694680600289560284233458721548461839394156304011 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.i2c_host_perf.37055185603833212855572482739694680600289560284233458721548461839394156304011
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_rx_oversample.21568703553542178266465561370318035099739604043996495190164481689854255647844
Short name T739
Test name
Test status
Simulation time 3939158762 ps
CPU time 106.06 seconds
Started Nov 22 02:17:43 PM PST 23
Finished Nov 22 02:19:30 PM PST 23
Peak memory 345752 kb
Host smart-132eae84-94d5-4a21-bf5d-af6754394e86
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21568703553542178266465561370318035099739604043996495190164481689854255647844 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_rx_oversample.21568703553542178266465561370318035099739604043996495190164481689854255647844
Directory /workspace/2.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.110445762113951921851753449914707440021375038053357052511119995663112070092930
Short name T543
Test name
Test status
Simulation time 2343171530 ps
CPU time 35.86 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:18:43 PM PST 23
Peak memory 299344 kb
Host smart-08c3c638-9f0a-494e-955d-70f3837bca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110445762113951921851753449914707440021375038053357052511119995663112070092930 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.i2c_host_smoke.110445762113951921851753449914707440021375038053357052511119995663112070092930
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.97200671415557161762519764190278101974621743914228366371073473321189495084294
Short name T640
Test name
Test status
Simulation time 32807463528 ps
CPU time 907.27 seconds
Started Nov 22 02:17:43 PM PST 23
Finished Nov 22 02:32:51 PM PST 23
Peak memory 1956904 kb
Host smart-6e603ecc-589f-4b1a-aadf-d5588cdb3927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97200671415557161762519764190278101974621743914228366371073473321189495084294 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_host_stress_all.97200671415557161762519764190278101974621743914228366371073473321189495084294
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.104927983857782582947281174042395273582744806433173081910799071485636380735190
Short name T832
Test name
Test status
Simulation time 1466624971 ps
CPU time 12.87 seconds
Started Nov 22 02:17:44 PM PST 23
Finished Nov 22 02:17:58 PM PST 23
Peak memory 213992 kb
Host smart-ba2830a2-1510-4b2c-9280-3a16958e3ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104927983857782582947281174042395273582744806433173081910799071485636380735190 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_host_stretch_timeout.104927983857782582947281174042395273582744806433173081910799071485636380735190
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.68794376488182979164057311117311099778945922773571037296760029600048562805282
Short name T40
Test name
Test status
Simulation time 62618346 ps
CPU time 0.83 seconds
Started Nov 22 02:18:44 PM PST 23
Finished Nov 22 02:18:45 PM PST 23
Peak memory 219660 kb
Host smart-6a856a21-3766-445d-9742-fc964f1883cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68794376488182979164057311117311099778945922773571037296760029600048562805282 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_sec_cm.68794376488182979164057311117311099778945922773571037296760029600048562805282
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.90916576398963972225144189178508464880840687576107675677003310991191364858537
Short name T1042
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.64 seconds
Started Nov 22 02:18:21 PM PST 23
Finished Nov 22 02:18:25 PM PST 23
Peak memory 202760 kb
Host smart-407160cf-7431-445d-913e-731dbd17a706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9091657639896397222514418917850
8464880840687576107675677003310991191364858537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.909165763989639722251441891
78508464880840687576107675677003310991191364858537
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.114633812240987352330762005020568831989798757092626459440088502790662083280081
Short name T1139
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.36 seconds
Started Nov 22 02:18:10 PM PST 23
Finished Nov 22 02:18:43 PM PST 23
Peak memory 382120 kb
Host smart-89b9a17b-ac78-4fc1-8e16-006ec5adbee5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114633812240987352330762005020568831989798757092626
459440088502790662083280081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.1146338122409873523307620050205
68831989798757092626459440088502790662083280081
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.105275775355651007653020501569231949131359657877626549511176068419443758262129
Short name T1147
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.86 seconds
Started Nov 22 02:17:44 PM PST 23
Finished Nov 22 02:18:19 PM PST 23
Peak memory 461932 kb
Host smart-780d8d61-3ad2-4105-abed-417281395705
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105275775355651007653020501569231949131359657877626
549511176068419443758262129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_tx.105275775355651007653020501569231
949131359657877626549511176068419443758262129
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.8021297473697725637249094394717948192310652603976274443454303710477733897965
Short name T783
Test name
Test status
Simulation time 825344371 ps
CPU time 2.5 seconds
Started Nov 22 02:18:33 PM PST 23
Finished Nov 22 02:18:37 PM PST 23
Peak memory 203048 kb
Host smart-a137cbd5-e6fb-4cdd-939d-9e56a89027aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802129747369772563724909439471794819231065260397627
4443454303710477733897965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_hrst.80212974736977256372490943947179481923106526039762744
43454303710477733897965
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.20443556440441670864036527141894018132490280586483761160391053402748214217806
Short name T641
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.13 seconds
Started Nov 22 02:18:08 PM PST 23
Finished Nov 22 02:18:13 PM PST 23
Peak memory 203712 kb
Host smart-bd0ef3c8-a629-4572-97ce-7ed86f646993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443556440441670864036527141894018132490280586483
761160391053402748214217806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.20443556440441670864036527141894018132490280
586483761160391053402748214217806
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.61284071548853205923571232957326082601802215777885446783078265298515967760152
Short name T426
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.72 seconds
Started Nov 22 02:18:20 PM PST 23
Finished Nov 22 02:18:43 PM PST 23
Peak memory 638972 kb
Host smart-708a1bc1-313c-4f9d-9667-c89c826b1507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61284071548853205923571232957326082601
802215777885446783078265298515967760152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.612840715488532059235712
32957326082601802215777885446783078265298515967760152
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.92241885009343228358721543067455469452295462044914179068036825061571468208941
Short name T250
Test name
Test status
Simulation time 834576440 ps
CPU time 3.05 seconds
Started Nov 22 02:18:34 PM PST 23
Finished Nov 22 02:18:38 PM PST 23
Peak memory 202992 kb
Host smart-6ead9099-0fd5-4383-89e9-06ab2cc1ea41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922418850093432283587215430674554694522954620449141
79068036825061571468208941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_perf.9224188500934322835872154306745546945229546204491417
9068036825061571468208941
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.97311688799930665009490218249865798621203843016382405536888720981191008536233
Short name T1572
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.43 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:18:20 PM PST 23
Peak memory 202924 kb
Host smart-0bc36adf-2682-4d70-a821-965c0bcd9afe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9731168879993066500949021824986579862120384301638240553688872098119100
8536233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smoke.97311688799930665009490218249865798621203843016382405536888720981191008536233
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.39753134385750063064996816663405001105119813876895144441686779678575089947141
Short name T989
Test name
Test status
Simulation time 66540157934 ps
CPU time 1659.05 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:45:50 PM PST 23
Peak memory 6983608 kb
Host smart-52c53e33-0ebe-4774-80da-2bdfbcc97a7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39753134385750063064996816663405001105119813876895
144441686779678575089947141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_all.397531343857500630649968166634050011051
19813876895144441686779678575089947141
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.58225268050827855353046265136025336211802917564158664759775160309554332657666
Short name T1297
Test name
Test status
Simulation time 997771563 ps
CPU time 8.3 seconds
Started Nov 22 02:17:44 PM PST 23
Finished Nov 22 02:17:53 PM PST 23
Peak memory 202840 kb
Host smart-d7c5fc4c-82db-4932-945f-ccdbd21591cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5822526805082785535304626513602533621180291756415866475977516030955433
2657666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_rd.5822526805082785535304626513602533621180291756415866475977516
0309554332657666
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.51542796500276363810482557716870694774146571093175008080635728901141608416918
Short name T1571
Test name
Test status
Simulation time 14461449567 ps
CPU time 89.99 seconds
Started Nov 22 02:18:18 PM PST 23
Finished Nov 22 02:19:49 PM PST 23
Peak memory 1541560 kb
Host smart-7cdec393-ffe7-4f0b-92a6-dac95c95a8a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5154279650027636381048255771687069477414657109317500808063572890114160
8416918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_wr.5154279650027636381048255771687069477414657109317500808063572
8901141608416918
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.79068113686769080876113706878971386661184189705305861319425375892336531510
Short name T382
Test name
Test status
Simulation time 6281818576 ps
CPU time 73.2 seconds
Started Nov 22 02:18:18 PM PST 23
Finished Nov 22 02:19:32 PM PST 23
Peak memory 930236 kb
Host smart-32357f31-ac04-425d-b5d1-0fdf7142603a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7906811368676908087611370687897138666118418970530586131942537589233653
1510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stretch.79068113686769080876113706878971386661184189705305861319425375892336531510
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.85173699624111937193860530561515398607047974379677349365149158659303755973018
Short name T1064
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.78 seconds
Started Nov 22 02:18:07 PM PST 23
Finished Nov 22 02:18:15 PM PST 23
Peak memory 212580 kb
Host smart-9d3e920f-c3b3-4de2-8ee9-f21d05040a17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851736996241119371938605305615153986070479743796773
49365149158659303755973018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_timeout.8517369962411193719386053056151539860704797437
9677349365149158659303755973018
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_ovf.16829285380717925795692910156793078135181674327383804671864631974763782933976
Short name T526
Test name
Test status
Simulation time 5445414553 ps
CPU time 116.28 seconds
Started Nov 22 02:18:33 PM PST 23
Finished Nov 22 02:20:30 PM PST 23
Peak memory 406812 kb
Host smart-288a0c80-59fb-4452-afad-e5ba29a65d42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16829285380717925795692910156793078135181674327383
804671864631974763782933976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_tx_ovf.16829285380717925795692910156793078135181674327
383804671864631974763782933976
Directory /workspace/2.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.55306586752523473918494729255800791315232396137269123688995998326758311244350
Short name T961
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.46 seconds
Started Nov 22 02:17:44 PM PST 23
Finished Nov 22 02:17:51 PM PST 23
Peak memory 205072 kb
Host smart-5b08ed52-201c-497e-ba78-2cebd6ccedd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553065867525234739184947292558007913152323961372691
23688995998326758311244350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_unexp_stop.553065867525234739184947292558007913152323
96137269123688995998326758311244350
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.98001316616055241281448625019246623060605011726151675249326641110045332819925
Short name T453
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:12 PM PST 23
Peak memory 202684 kb
Host smart-8f22bbdc-7956-4a7d-b2c1-abf26a02ed8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98001316616055241281448625019246623060605011726151675249326641110045332819925 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_alert_test.98001316616055241281448625019246623060605011726151675249326641110045332819925
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.63341294712932372229386593491091437641749021014084954296089116985724606885308
Short name T1148
Test name
Test status
Simulation time 74225396 ps
CPU time 1.38 seconds
Started Nov 22 02:21:15 PM PST 23
Finished Nov 22 02:21:18 PM PST 23
Peak memory 211312 kb
Host smart-92a59c42-5a74-40c6-9008-d9dcd74cf9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63341294712932372229386593491091437641749021014084954296089116985724606885308 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_host_error_intr.63341294712932372229386593491091437641749021014084954296089116985724606885308
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.57093585246263242128444753014299499794731594868377222243251024052801766558432
Short name T175
Test name
Test status
Simulation time 606667565 ps
CPU time 6.59 seconds
Started Nov 22 02:21:18 PM PST 23
Finished Nov 22 02:21:25 PM PST 23
Peak memory 273296 kb
Host smart-7bb7a964-4157-43f4-be96-018fad9cb514
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57093585246263242128444753014299499794731594868377222243251024052801766558432 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.57093585246263242128444753014299499794731594868377222243251024052801766558432
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2888398681115246958752912258887626184364822978160360387343915020904161125234
Short name T1407
Test name
Test status
Simulation time 3768267272 ps
CPU time 69.47 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:22:20 PM PST 23
Peak memory 729328 kb
Host smart-d3a4559f-6765-4925-9f50-19cdc301c5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888398681115246958752912258887626184364822978160360387343915020904161125234 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_host_fifo_full.2888398681115246958752912258887626184364822978160360387343915020904161125234
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.56421605017339233556927757776844225552342878487402987294684863494989638385072
Short name T473
Test name
Test status
Simulation time 7925734012 ps
CPU time 251.35 seconds
Started Nov 22 02:21:18 PM PST 23
Finished Nov 22 02:25:30 PM PST 23
Peak memory 1271496 kb
Host smart-48df0d10-45e8-4381-b5d7-8f68dbc7e9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56421605017339233556927757776844225552342878487402987294684863494989638385072 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.i2c_host_fifo_overflow.56421605017339233556927757776844225552342878487402987294684863494989638385072
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.95858553063281546264587981632155904107239369870218566370296293777868982823731
Short name T1507
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:21:12 PM PST 23
Finished Nov 22 02:21:14 PM PST 23
Peak memory 202912 kb
Host smart-ec0db245-40a8-46d8-b46e-470f6623429c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95858553063281546264587981632155904107239369870218566370296293777868982823731 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.95858553063281546264587981632155904107239369870218566370296293777868982823731
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.77643653173393698845432590086484874898989689902226055565679906119491081388923
Short name T751
Test name
Test status
Simulation time 236313385 ps
CPU time 3.83 seconds
Started Nov 22 02:21:15 PM PST 23
Finished Nov 22 02:21:20 PM PST 23
Peak memory 225560 kb
Host smart-602d8c70-e50b-48b9-a280-46cb4b63d611
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77643653173393698845432590086484874898989689902226055565679906119491081388923 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.77643653173393698845432590086484874898989689902226055565679906119491081388923
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.93253501931161051938894460320963165149621582286967583435052833488528169952059
Short name T1555
Test name
Test status
Simulation time 7918519784 ps
CPU time 205.48 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:24:36 PM PST 23
Peak memory 1310828 kb
Host smart-8f16eb5a-26a3-4f81-9db5-9d764adcbd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93253501931161051938894460320963165149621582286967583435052833488528169952059 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_host_fifo_watermark.93253501931161051938894460320963165149621582286967583435052833488528169952059
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.16407741478681483443516352454447028052755146290713759340857904771466911982586
Short name T1576
Test name
Test status
Simulation time 3754070957 ps
CPU time 52.15 seconds
Started Nov 22 02:22:00 PM PST 23
Finished Nov 22 02:22:58 PM PST 23
Peak memory 293796 kb
Host smart-e4997a61-c5be-4e25-bf2e-7289b6379c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16407741478681483443516352454447028052755146290713759340857904771466911982586 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_host_mode_toggle.16407741478681483443516352454447028052755146290713759340857904771466911982586
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.80558357629472509321270100839124584198843225599159948647048621584678573838047
Short name T1313
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:21:11 PM PST 23
Finished Nov 22 02:21:13 PM PST 23
Peak memory 202572 kb
Host smart-67acf690-2605-4696-8acf-1de16726a673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80558357629472509321270100839124584198843225599159948647048621584678573838047 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_host_override.80558357629472509321270100839124584198843225599159948647048621584678573838047
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.36148263136773658029530384994421282759602093038280461481652927265332132927150
Short name T353
Test name
Test status
Simulation time 6830796343 ps
CPU time 57.43 seconds
Started Nov 22 02:21:09 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 211188 kb
Host smart-2be056b0-a3be-4268-a86e-d1a17c8498fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36148263136773658029530384994421282759602093038280461481652927265332132927150 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.i2c_host_perf.36148263136773658029530384994421282759602093038280461481652927265332132927150
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_rx_oversample.11075611360105249155657321208277512734981475855381441870982728525238913663792
Short name T1408
Test name
Test status
Simulation time 3939158762 ps
CPU time 116.73 seconds
Started Nov 22 02:21:18 PM PST 23
Finished Nov 22 02:23:15 PM PST 23
Peak memory 345860 kb
Host smart-ca500db4-024b-448b-9163-e193ffd1645d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11075611360105249155657321208277512734981475855381441870982728525238913663792 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_rx_oversample.11075611360105249155657321208277512734981475855381441870982728525238913663792
Directory /workspace/20.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.23385326092529942070871152862778353642064869327448251940067291497940693341810
Short name T242
Test name
Test status
Simulation time 2343171530 ps
CPU time 36.39 seconds
Started Nov 22 02:21:18 PM PST 23
Finished Nov 22 02:21:55 PM PST 23
Peak memory 299324 kb
Host smart-10c0b069-e4df-4af2-8cf6-b4ec3369bbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23385326092529942070871152862778353642064869327448251940067291497940693341810 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.i2c_host_smoke.23385326092529942070871152862778353642064869327448251940067291497940693341810
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.17607164600794405978461239416880171811599712784487263156088842074085577351894
Short name T861
Test name
Test status
Simulation time 32807463528 ps
CPU time 1043.74 seconds
Started Nov 22 02:21:47 PM PST 23
Finished Nov 22 02:39:11 PM PST 23
Peak memory 1957116 kb
Host smart-5f4cbb12-43a7-41d2-83cb-06e0e3181eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17607164600794405978461239416880171811599712784487263156088842074085577351894 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_host_stress_all.17607164600794405978461239416880171811599712784487263156088842074085577351894
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.10458729846288669620179000272427094276556391346148197081898968486605475168203
Short name T187
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.29 seconds
Started Nov 22 02:21:18 PM PST 23
Finished Nov 22 02:21:32 PM PST 23
Peak memory 214104 kb
Host smart-be2c0fb1-e12d-43e0-bf92-b218dd86e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10458729846288669620179000272427094276556391346148197081898968486605475168203 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_host_stretch_timeout.10458729846288669620179000272427094276556391346148197081898968486605475168203
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.47053343689855045791995080522376607183159203835836933210335961631913490960016
Short name T402
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.85 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 202984 kb
Host smart-db3ce41c-108d-4eef-9f10-edeb84270672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4705334368985504579199508052237
6607183159203835836933210335961631913490960016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.47053343689855045791995080
522376607183159203835836933210335961631913490960016
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.21248761058251531598512944656248742317824561494826424756756460535966065627264
Short name T685
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.3 seconds
Started Nov 22 02:21:29 PM PST 23
Finished Nov 22 02:22:01 PM PST 23
Peak memory 382176 kb
Host smart-15b9029b-0f5f-4cd3-b4c4-b5705f640128
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212487610582515315985129446562487423178245614948264
24756756460535966065627264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.2124876105825153159851294465624
8742317824561494826424756756460535966065627264
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.51486490992793962655316800486680729917121162189951357172150177716912714218254
Short name T835
Test name
Test status
Simulation time 10065199023 ps
CPU time 35.4 seconds
Started Nov 22 02:21:31 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 462132 kb
Host smart-a5b92805-8f94-4cdf-aa64-7441064408f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514864909927939626553168004866807299171211621899513
57172150177716912714218254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_tx.514864909927939626553168004866807
29917121162189951357172150177716912714218254
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.41211563512462571652981948248442923805864756177105798541683070038493203430908
Short name T616
Test name
Test status
Simulation time 825344371 ps
CPU time 2.43 seconds
Started Nov 22 02:21:29 PM PST 23
Finished Nov 22 02:21:32 PM PST 23
Peak memory 203172 kb
Host smart-29c14ff8-dec8-4bb8-94d4-bf95fb4b34aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412115635124625716529819482484429238058647561771057
98541683070038493203430908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_hrst.412115635124625716529819482484429238058647561771057
98541683070038493203430908
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.47661661796360133690763953660309309965565004085617808708760221436062076158477
Short name T468
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.23 seconds
Started Nov 22 02:21:42 PM PST 23
Finished Nov 22 02:21:47 PM PST 23
Peak memory 203736 kb
Host smart-bff4486d-159a-4810-a394-5555d116be8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47661661796360133690763953660309309965565004085617
808708760221436062076158477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.4766166179636013369076395366030930996556500
4085617808708760221436062076158477
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2727104091952455303678752983882362911851100042426694899380231037502591872526
Short name T1129
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.97 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:22:10 PM PST 23
Peak memory 639196 kb
Host smart-6be6eec9-9049-46a7-ad1b-50b1324677ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27271040919524553036787529838823629118
51100042426694899380231037502591872526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.272710409195245530367875
2983882362911851100042426694899380231037502591872526
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_perf.99514088625444386891928941529099758895766655261884685836136791157320096636574
Short name T895
Test name
Test status
Simulation time 834576440 ps
CPU time 3.13 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:22:09 PM PST 23
Peak memory 202984 kb
Host smart-dc90ce47-25df-4a5c-ac51-af14b69c2755
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995140886254443868919289415290997588957666552618846
85836136791157320096636574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_perf.995140886254443868919289415290997588957666552618846
85836136791157320096636574
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.81706778351564575632596640595865548334929165522215963931758580895252650759724
Short name T856
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.71 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:22:16 PM PST 23
Peak memory 203032 kb
Host smart-50eda1bd-f701-406c-98ce-71f1b8ce664e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8170677835156457563259664059586554833492916552221596393175858089525265
0759724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smoke.81706778351564575632596640595865548334929165522215963931758580895252650759724
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.23713814138625903648555966220249281857343351021239578559773632128305760280756
Short name T1046
Test name
Test status
Simulation time 66540157934 ps
CPU time 1481.31 seconds
Started Nov 22 02:21:33 PM PST 23
Finished Nov 22 02:46:15 PM PST 23
Peak memory 6983228 kb
Host smart-9c467ca3-7395-4daf-9270-d5c1a56da5d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23713814138625903648555966220249281857343351021239
578559773632128305760280756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_all.23713814138625903648555966220249281857
343351021239578559773632128305760280756
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.96288331486156259738231685189689916988538467439972545308423962497855776294041
Short name T1079
Test name
Test status
Simulation time 997771563 ps
CPU time 9.1 seconds
Started Nov 22 02:21:44 PM PST 23
Finished Nov 22 02:21:54 PM PST 23
Peak memory 203076 kb
Host smart-6cdf4390-578a-4458-8289-7bd3d9604129
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9628833148615625973823168518968991698853846743997254530842396249785577
6294041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_rd.962883314861562597382316851896899169885384674399725453084239
62497855776294041
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.78654908560386935518555753092047546877186919730038078247723464657893974632630
Short name T1348
Test name
Test status
Simulation time 14461449567 ps
CPU time 84.66 seconds
Started Nov 22 02:21:50 PM PST 23
Finished Nov 22 02:23:16 PM PST 23
Peak memory 1541856 kb
Host smart-05174467-cb83-46f5-8000-81f1d2156aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7865490856038693551855575309204754687718691973003807824772346465789397
4632630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_wr.786549085603869355185557530920475468771869197300380782477234
64657893974632630
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.52738025801180467250344781044183276935220949371811980698883747359475432833205
Short name T744
Test name
Test status
Simulation time 6281818576 ps
CPU time 78.78 seconds
Started Nov 22 02:22:10 PM PST 23
Finished Nov 22 02:23:32 PM PST 23
Peak memory 930472 kb
Host smart-4353c457-fb7b-42a4-ac35-28515d687a89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5273802580118046725034478104418327693522094937181198069888374735947543
2833205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stretch.5273802580118046725034478104418327693522094937181198069888374735
9475432833205
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.73518309609657840558540613159641813980755247948416397483738516811474102280757
Short name T338
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.3 seconds
Started Nov 22 02:21:44 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 212608 kb
Host smart-8bd83fac-bce7-493f-8390-e96dd960710f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735183096096578405585406131596418139807552479484163
97483738516811474102280757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_timeout.735183096096578405585406131596418139807552479
48416397483738516811474102280757
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_ovf.21670297718978128800360930206934647762940578342125029624266203281072938376953
Short name T1508
Test name
Test status
Simulation time 5445414553 ps
CPU time 115.14 seconds
Started Nov 22 02:21:25 PM PST 23
Finished Nov 22 02:23:21 PM PST 23
Peak memory 406852 kb
Host smart-a79400e0-0d56-469f-9829-a33528541867
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670297718978128800360930206934647762940578342125
029624266203281072938376953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_tx_ovf.2167029771897812880036093020693464776294057834
2125029624266203281072938376953
Directory /workspace/20.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.101031548145654891655883611799621236314506444077061936578553844359968857243085
Short name T1338
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.48 seconds
Started Nov 22 02:21:44 PM PST 23
Finished Nov 22 02:21:51 PM PST 23
Peak memory 205296 kb
Host smart-896a6116-1d4e-4656-aaf0-2ac7267f0cd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101031548145654891655883611799621236314506444077061
936578553844359968857243085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_unexp_stop.1010315481456548916558836117996212363145
06444077061936578553844359968857243085
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.52288261615032974523470212004742370582349692693769065320835783071924580461166
Short name T228
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:22:06 PM PST 23
Peak memory 202592 kb
Host smart-25f73e4e-7960-480c-955a-a6610dd62f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52288261615032974523470212004742370582349692693769065320835783071924580461166 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_alert_test.52288261615032974523470212004742370582349692693769065320835783071924580461166
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.64662547748210172505290150677096515667012416106987247916214388394250895567032
Short name T1493
Test name
Test status
Simulation time 74225396 ps
CPU time 1.4 seconds
Started Nov 22 02:21:26 PM PST 23
Finished Nov 22 02:21:28 PM PST 23
Peak memory 211264 kb
Host smart-5db6bca4-08a4-44bb-b6d4-20a7609cb66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64662547748210172505290150677096515667012416106987247916214388394250895567032 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_host_error_intr.64662547748210172505290150677096515667012416106987247916214388394250895567032
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.115545529603928097214810705450001540785911750033575588168420877665326336230699
Short name T521
Test name
Test status
Simulation time 606667565 ps
CPU time 6.7 seconds
Started Nov 22 02:21:28 PM PST 23
Finished Nov 22 02:21:36 PM PST 23
Peak memory 273372 kb
Host smart-6d9575c7-4ad5-4ce1-b3a3-1c0c6b8b7582
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115545529603928097214810705450001540785911750033575588168420877665326336230699 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.115545529603928097214810705450001540785911750033575588168420877665326336230699
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.42004678781017450377523908927944317703275390430042406123885345869789954112866
Short name T711
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.04 seconds
Started Nov 22 02:21:28 PM PST 23
Finished Nov 22 02:22:42 PM PST 23
Peak memory 729496 kb
Host smart-596a2332-3070-4817-b5c5-3b0d813b6cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42004678781017450377523908927944317703275390430042406123885345869789954112866 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_host_fifo_full.42004678781017450377523908927944317703275390430042406123885345869789954112866
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.71938615006376051218991614925314623096857049894435466063201684188110011200434
Short name T1274
Test name
Test status
Simulation time 7925734012 ps
CPU time 242.26 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:26:08 PM PST 23
Peak memory 1271580 kb
Host smart-43070f61-d8cb-4e26-991a-836c742b2d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71938615006376051218991614925314623096857049894435466063201684188110011200434 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.i2c_host_fifo_overflow.71938615006376051218991614925314623096857049894435466063201684188110011200434
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.69629396481803172231285017515284367287794061659661832213976551930890689936949
Short name T868
Test name
Test status
Simulation time 209010032 ps
CPU time 0.98 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:13 PM PST 23
Peak memory 202880 kb
Host smart-21dc11da-4c23-4281-a8f5-c0eedd52f790
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69629396481803172231285017515284367287794061659661832213976551930890689936949 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.69629396481803172231285017515284367287794061659661832213976551930890689936949
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.14017558485453115343118552293572979178682438040050705387506111093654912120980
Short name T364
Test name
Test status
Simulation time 236313385 ps
CPU time 3.68 seconds
Started Nov 22 02:21:44 PM PST 23
Finished Nov 22 02:21:49 PM PST 23
Peak memory 225404 kb
Host smart-8fd0303b-efcd-4cf8-9c22-6bdf666d0ff4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14017558485453115343118552293572979178682438040050705387506111093654912120980 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.14017558485453115343118552293572979178682438040050705387506111093654912120980
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.50982801450870424928049945721593211331506714287910140374616463080420522266191
Short name T833
Test name
Test status
Simulation time 7918519784 ps
CPU time 207.37 seconds
Started Nov 22 02:21:31 PM PST 23
Finished Nov 22 02:24:59 PM PST 23
Peak memory 1310884 kb
Host smart-6c21ba8c-4566-4831-b2f9-f51471641f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50982801450870424928049945721593211331506714287910140374616463080420522266191 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_host_fifo_watermark.50982801450870424928049945721593211331506714287910140374616463080420522266191
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.56294855423779326274187567166509182881250808017895994977426043701082834620230
Short name T511
Test name
Test status
Simulation time 3754070957 ps
CPU time 51.26 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:22:57 PM PST 23
Peak memory 293680 kb
Host smart-81825e4c-b1e3-4e63-bb4e-8a7b897ae8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56294855423779326274187567166509182881250808017895994977426043701082834620230 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_host_mode_toggle.56294855423779326274187567166509182881250808017895994977426043701082834620230
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.101864001696575930639946061453281918349073389218603571321291924342089385180337
Short name T691
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:21:49 PM PST 23
Peak memory 202880 kb
Host smart-ba740e91-37a3-43a4-ae15-3514eac1aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101864001696575930639946061453281918349073389218603571321291924342089385180337 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_host_override.101864001696575930639946061453281918349073389218603571321291924342089385180337
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.63563839602755426560367610986053288101849125629621614849342693263303567929156
Short name T359
Test name
Test status
Simulation time 6830796343 ps
CPU time 62.91 seconds
Started Nov 22 02:21:50 PM PST 23
Finished Nov 22 02:22:54 PM PST 23
Peak memory 210648 kb
Host smart-bc68ef63-8bc5-4b9b-856f-50eef2a9d307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63563839602755426560367610986053288101849125629621614849342693263303567929156 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.i2c_host_perf.63563839602755426560367610986053288101849125629621614849342693263303567929156
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.109222822073715557647746499918823049648123262295958559280051971231795641884996
Short name T449
Test name
Test status
Simulation time 2343171530 ps
CPU time 33.16 seconds
Started Nov 22 02:21:45 PM PST 23
Finished Nov 22 02:22:19 PM PST 23
Peak memory 299448 kb
Host smart-695867a4-0cdd-4fa4-a36a-480e161ea6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109222822073715557647746499918823049648123262295958559280051971231795641884996 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.i2c_host_smoke.109222822073715557647746499918823049648123262295958559280051971231795641884996
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.62422202045698303857314456667347526467442539617330152960946248284111204301568
Short name T1565
Test name
Test status
Simulation time 32807463528 ps
CPU time 1111.39 seconds
Started Nov 22 02:21:42 PM PST 23
Finished Nov 22 02:40:15 PM PST 23
Peak memory 1957128 kb
Host smart-08f4714c-c7b5-447e-8319-a621c950edfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62422202045698303857314456667347526467442539617330152960946248284111204301568 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_host_stress_all.62422202045698303857314456667347526467442539617330152960946248284111204301568
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.28689781958053008243138077048914403519236499252137563883573599364515750644558
Short name T191
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.29 seconds
Started Nov 22 02:21:47 PM PST 23
Finished Nov 22 02:22:01 PM PST 23
Peak memory 214168 kb
Host smart-997bc410-e50d-421e-9094-d7bf9979ee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28689781958053008243138077048914403519236499252137563883573599364515750644558 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_host_stretch_timeout.28689781958053008243138077048914403519236499252137563883573599364515750644558
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.100341232940614405307238826140914211511113071479115089521166371508212491805645
Short name T1059
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.91 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:22:10 PM PST 23
Peak memory 202992 kb
Host smart-1b361c56-c892-49f4-9051-3255a652bbb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003412329406144053072388261409
14211511113071479115089521166371508212491805645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1003412329406144053072388
26140914211511113071479115089521166371508212491805645
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.73177072421981992072379457537580656957971970265230177494935086977843659060139
Short name T172
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.26 seconds
Started Nov 22 02:21:32 PM PST 23
Finished Nov 22 02:22:04 PM PST 23
Peak memory 382208 kb
Host smart-b3d368c2-a641-43a6-9056-e4cee7e9babc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731770724219819920723794575375806569579719702652301
77494935086977843659060139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.7317707242198199207237945753758
0656957971970265230177494935086977843659060139
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.106796662599589411055589307924912262798728238248604644427045507724215631661708
Short name T564
Test name
Test status
Simulation time 10065199023 ps
CPU time 35.7 seconds
Started Nov 22 02:21:29 PM PST 23
Finished Nov 22 02:22:06 PM PST 23
Peak memory 462096 kb
Host smart-b5ae2d10-2d78-4784-980f-0e12fe735e58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106796662599589411055589307924912262798728238248604
644427045507724215631661708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_tx.10679666259958941105558930792491
2262798728238248604644427045507724215631661708
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.11584330382471568748007593839377155054055095607615086432530557285078948348809
Short name T1213
Test name
Test status
Simulation time 825344371 ps
CPU time 2.48 seconds
Started Nov 22 02:21:49 PM PST 23
Finished Nov 22 02:21:53 PM PST 23
Peak memory 202796 kb
Host smart-ccc3a949-0b0d-4b7f-9fa3-ee49a5337b84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115843303824715687480075938393771550540550956076150
86432530557285078948348809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_hrst.115843303824715687480075938393771550540550956076150
86432530557285078948348809
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.22869079685422496674201649512760781400679077959355451040343600907685905911131
Short name T267
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.19 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 203724 kb
Host smart-8ba6087d-3c11-434d-b48b-6c092b7df652
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22869079685422496674201649512760781400679077959355
451040343600907685905911131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.2286907968542249667420164951276078140067907
7959355451040343600907685905911131
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.61386940389884464229291658129448106418707450760637106075566487954141993878441
Short name T743
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.3 seconds
Started Nov 22 02:21:25 PM PST 23
Finished Nov 22 02:21:47 PM PST 23
Peak memory 639156 kb
Host smart-b66804e5-95a3-4d5b-a416-139a2f07eb68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61386940389884464229291658129448106418
707450760637106075566487954141993878441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.61386940389884464229291
658129448106418707450760637106075566487954141993878441
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.50022625040534742168480605271594950848566919064840095902686839965038948279091
Short name T951
Test name
Test status
Simulation time 834576440 ps
CPU time 3.01 seconds
Started Nov 22 02:21:43 PM PST 23
Finished Nov 22 02:21:47 PM PST 23
Peak memory 203052 kb
Host smart-1712a284-655d-4f69-b7b8-77ce58c11a71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500226250405347421684806052715949508485669190648400
95902686839965038948279091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_perf.500226250405347421684806052715949508485669190648400
95902686839965038948279091
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.33474972612362049173950979552469025566041301893608856606827212717242600404932
Short name T1351
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.88 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:21:59 PM PST 23
Peak memory 203056 kb
Host smart-abb30dbc-a00b-462e-a46e-34c3bb56833b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347497261236204917395097955246902556604130189360885660682721271724260
0404932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smoke.33474972612362049173950979552469025566041301893608856606827212717242600404932
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.93619377242332123092917388717719669380432676548616576931416638254828824172538
Short name T1017
Test name
Test status
Simulation time 66540157934 ps
CPU time 1479.65 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:46:51 PM PST 23
Peak memory 6983392 kb
Host smart-2aa30386-9228-4d69-b4bd-d77698e5da91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93619377242332123092917388717719669380432676548616
576931416638254828824172538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_all.93619377242332123092917388717719669380
432676548616576931416638254828824172538
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.103939022857126624439437456851287030338737686823851157270978847708713216834325
Short name T1071
Test name
Test status
Simulation time 997771563 ps
CPU time 8.54 seconds
Started Nov 22 02:21:45 PM PST 23
Finished Nov 22 02:21:55 PM PST 23
Peak memory 203088 kb
Host smart-00d92b9f-1c96-47a1-a4e2-3fb31e9ca23e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039390228571266244394374568512870303387376868238511572709788477087132
16834325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_rd.10393902285712662443943745685128703033873768682385115727097
8847708713216834325
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.89610546322910608119334833664037326674934671370633881396215029225428684598365
Short name T944
Test name
Test status
Simulation time 14461449567 ps
CPU time 84.11 seconds
Started Nov 22 02:21:45 PM PST 23
Finished Nov 22 02:23:10 PM PST 23
Peak memory 1542104 kb
Host smart-1337469f-fd5b-4d36-b4a6-288528dbc3d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8961054632291060811933483366403732667493467137063388139621502922542868
4598365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_wr.896105463229106081193348336640373266749346713706338813962150
29225428684598365
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.5344184034818027815917589646617522507325657462975268191812308851053025747233
Short name T1335
Test name
Test status
Simulation time 6281818576 ps
CPU time 72.54 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:23:18 PM PST 23
Peak memory 930600 kb
Host smart-382d5f85-5b3b-473d-8859-ead4a933e25f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5344184034818027815917589646617522507325657462975268191812308851053025
747233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stretch.5344184034818027815917589646617522507325657462975268191812308851053025747233
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.81781440100715481711778013313648320998468621410160330483883049124928927485820
Short name T1138
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.54 seconds
Started Nov 22 02:21:27 PM PST 23
Finished Nov 22 02:21:35 PM PST 23
Peak memory 212616 kb
Host smart-f7fc55d7-0e17-483f-afe7-e2e7c9659e71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817814401007154817117780133136483209984686214101603
30483883049124928927485820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_timeout.817814401007154817117780133136483209984686214
10160330483883049124928927485820
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_ovf.69923082645324267210550146946741844081305648108715751652993706502797342844622
Short name T1043
Test name
Test status
Simulation time 5445414553 ps
CPU time 140.4 seconds
Started Nov 22 02:21:44 PM PST 23
Finished Nov 22 02:24:05 PM PST 23
Peak memory 406648 kb
Host smart-5ddf86bc-9a4e-430b-b7a0-757e3ece3a60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69923082645324267210550146946741844081305648108715
751652993706502797342844622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_tx_ovf.6992308264532426721055014694674184408130564810
8715751652993706502797342844622
Directory /workspace/21.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.96885489011370527878077219246081501308877408005550329819546386985611522947028
Short name T1346
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.57 seconds
Started Nov 22 02:21:47 PM PST 23
Finished Nov 22 02:21:54 PM PST 23
Peak memory 205376 kb
Host smart-5c6b2dd2-f022-4e45-b07b-663618ade900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968854890113705278780772192460815013088774080055503
29819546386985611522947028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_unexp_stop.96885489011370527878077219246081501308877
408005550329819546386985611522947028
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.107930977186281247703418111720192182071108319575819691944934128575883367226907
Short name T1451
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:13 PM PST 23
Peak memory 202692 kb
Host smart-567eab17-a278-4304-9551-04aa9a78e6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107930977186281247703418111720192182071108319575819691944934128575883367226907 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_alert_test.107930977186281247703418111720192182071108319575819691944934128575883367226907
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.49983259604396212061533639972118324516725659958025836320318517164790046322184
Short name T1479
Test name
Test status
Simulation time 74225396 ps
CPU time 1.42 seconds
Started Nov 22 02:21:45 PM PST 23
Finished Nov 22 02:21:47 PM PST 23
Peak memory 211312 kb
Host smart-d9a5d6f1-e494-49a7-a2ab-6caa411388ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49983259604396212061533639972118324516725659958025836320318517164790046322184 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_host_error_intr.49983259604396212061533639972118324516725659958025836320318517164790046322184
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1005938822298672025766725875614621183082092729123989135284114953796574563964
Short name T1498
Test name
Test status
Simulation time 606667565 ps
CPU time 6.49 seconds
Started Nov 22 02:21:28 PM PST 23
Finished Nov 22 02:21:35 PM PST 23
Peak memory 273220 kb
Host smart-bf344118-9a61-4029-942c-835f0389666c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005938822298672025766725875614621183082092729123989135284114953796574563964 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.1005938822298672025766725875614621183082092729123989135284114953796574563964
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.111980592366860755829604209336795150880556643188196088976721465043864125724684
Short name T626
Test name
Test status
Simulation time 3768267272 ps
CPU time 75 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:23:22 PM PST 23
Peak memory 729596 kb
Host smart-517aca56-667b-423c-89ee-071fa5d7fcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111980592366860755829604209336795150880556643188196088976721465043864125724684 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_host_fifo_full.111980592366860755829604209336795150880556643188196088976721465043864125724684
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.112894534905543289135317027202436899650307175984250764163409796204644519227959
Short name T199
Test name
Test status
Simulation time 7925734012 ps
CPU time 270.22 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:26:36 PM PST 23
Peak memory 1271536 kb
Host smart-497c4522-f234-43ed-923d-de1c7144ceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112894534905543289135317027202436899650307175984250764163409796204644519227959 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.i2c_host_fifo_overflow.112894534905543289135317027202436899650307175984250764163409796204644519227959
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2361175854556532370032093887055012328382987150698883850538454888746529175119
Short name T211
Test name
Test status
Simulation time 209010032 ps
CPU time 0.94 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:21:48 PM PST 23
Peak memory 202860 kb
Host smart-d68f5bb6-52e4-4d7a-8a82-51fb731b4e26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361175854556532370032093887055012328382987150698883850538454888746529175119 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.2361175854556532370032093887055012328382987150698883850538454888746529175119
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.59512589467460417535493975886919325258948844283442864129094453847597878038886
Short name T1251
Test name
Test status
Simulation time 236313385 ps
CPU time 3.96 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 225524 kb
Host smart-e8d52ebc-2c2b-49c5-98dd-4acf44cb5778
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59512589467460417535493975886919325258948844283442864129094453847597878038886 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.59512589467460417535493975886919325258948844283442864129094453847597878038886
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.77300010762991698104107048673947305680425957966945385829872903924676735550719
Short name T717
Test name
Test status
Simulation time 7918519784 ps
CPU time 201.68 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:25:33 PM PST 23
Peak memory 1310712 kb
Host smart-f45e6fd2-384b-4469-9f9e-e524719bce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77300010762991698104107048673947305680425957966945385829872903924676735550719 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.i2c_host_fifo_watermark.77300010762991698104107048673947305680425957966945385829872903924676735550719
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.102735157579704766262655844696432251667797209346038733113210313752189755034595
Short name T612
Test name
Test status
Simulation time 3754070957 ps
CPU time 55.81 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:23:07 PM PST 23
Peak memory 293772 kb
Host smart-dcdd58c6-99c9-4b9f-92c4-611134cfbfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102735157579704766262655844696432251667797209346038733113210313752189755034595 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.i2c_host_mode_toggle.102735157579704766262655844696432251667797209346038733113210313752189755034595
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.57229137249525334103308878079393219227380271168487476495388139185759487796254
Short name T1525
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:13 PM PST 23
Peak memory 202900 kb
Host smart-6901a952-0f1a-4be8-a65b-fccb3357d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57229137249525334103308878079393219227380271168487476495388139185759487796254 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_host_override.57229137249525334103308878079393219227380271168487476495388139185759487796254
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.108599215809545415347488735474600563593531725364562686593041857768223689616846
Short name T812
Test name
Test status
Simulation time 6830796343 ps
CPU time 58.28 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:22:47 PM PST 23
Peak memory 211372 kb
Host smart-ea8d5482-7624-41a6-ab61-d4f23be18cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108599215809545415347488735474600563593531725364562686593041857768223689616846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.i2c_host_perf.108599215809545415347488735474600563593531725364562686593041857768223689616846
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_rx_oversample.26549336992864697518343232147798163200732750811639194321629413083590935477367
Short name T328
Test name
Test status
Simulation time 3939158762 ps
CPU time 100.35 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:23:29 PM PST 23
Peak memory 345960 kb
Host smart-ce6ab5ab-77c2-4a49-9294-5092b44ba31c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26549336992864697518343232147798163200732750811639194321629413083590935477367 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_rx_oversample.26549336992864697518343232147798163200732750811639194321629413083590935477367
Directory /workspace/22.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.115777323322289499792602549834006684957464093947980395098162057025626958890078
Short name T701
Test name
Test status
Simulation time 2343171530 ps
CPU time 38.49 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:50 PM PST 23
Peak memory 299320 kb
Host smart-bbeef4b0-5dff-4303-a2bd-15971c70d6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115777323322289499792602549834006684957464093947980395098162057025626958890078 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.i2c_host_smoke.115777323322289499792602549834006684957464093947980395098162057025626958890078
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.95637717457528646871044110660362465468810296761072423124736800060929482793043
Short name T1189
Test name
Test status
Simulation time 32807463528 ps
CPU time 1086.56 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:39:53 PM PST 23
Peak memory 1957060 kb
Host smart-e464995e-c87c-44ac-bdb8-92b9f6c6f9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95637717457528646871044110660362465468810296761072423124736800060929482793043 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_host_stress_all.95637717457528646871044110660362465468810296761072423124736800060929482793043
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.27262989806398962774411560884100764667379400865296314779824326540891377489418
Short name T982
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.09 seconds
Started Nov 22 02:21:47 PM PST 23
Finished Nov 22 02:22:01 PM PST 23
Peak memory 214176 kb
Host smart-3f3f809b-9701-4fed-9949-60ed3df8a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27262989806398962774411560884100764667379400865296314779824326540891377489418 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_host_stretch_timeout.27262989806398962774411560884100764667379400865296314779824326540891377489418
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.31903929800867581118327186951230333560796584720860763682832665143079696272714
Short name T509
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.82 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:21:51 PM PST 23
Peak memory 202960 kb
Host smart-375a20d5-90d7-4839-b200-8b28b4003a46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190392980086758111832718695123
0333560796584720860763682832665143079696272714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.31903929800867581118327186
951230333560796584720860763682832665143079696272714
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.32252337526355570479477414406646995020913257733497372470684674011992898095845
Short name T1343
Test name
Test status
Simulation time 10166144644 ps
CPU time 30.96 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:22:17 PM PST 23
Peak memory 382128 kb
Host smart-6f58c9ac-fdae-4cec-b3aa-0174ea224f43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322523375263555704794774144066469950209132577334973
72470684674011992898095845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.3225233752635557047947741440664
6995020913257733497372470684674011992898095845
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.43361164875648010935598389841275226082220762609771041786533372585549897258880
Short name T806
Test name
Test status
Simulation time 10065199023 ps
CPU time 37.57 seconds
Started Nov 22 02:21:47 PM PST 23
Finished Nov 22 02:22:26 PM PST 23
Peak memory 462064 kb
Host smart-aaf313df-e098-4a38-b245-79e6bf845394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433611648756480109355983898412752260822207626097710
41786533372585549897258880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_tx.433611648756480109355983898412752
26082220762609771041786533372585549897258880
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.26436456248668018492336276093635878953001915204562671106689861288815577390583
Short name T538
Test name
Test status
Simulation time 825344371 ps
CPU time 2.47 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 202984 kb
Host smart-b8ebfa57-67ec-416f-88b7-e4e0b351a285
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264364562486680184923362760936358789530019152045626
71106689861288815577390583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_hrst.264364562486680184923362760936358789530019152045626
71106689861288815577390583
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.114431201122453511947036087285388625043828197791062172343617326536439648060481
Short name T1164
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.25 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:17 PM PST 23
Peak memory 203708 kb
Host smart-d1d7f4e8-a5b7-4f2d-a89f-c12fedf424fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11443120112245351194703608728538862504382819779106
2172343617326536439648060481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_smoke.114431201122453511947036087285388625043828
197791062172343617326536439648060481
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.56042647276020291202442689346800579930960493661518224983049576081571356306754
Short name T1024
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.62 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:22:08 PM PST 23
Peak memory 639152 kb
Host smart-fa9c49ee-9fbd-4d41-8527-9466533edf92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56042647276020291202442689346800579930
960493661518224983049576081571356306754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.56042647276020291202442
689346800579930960493661518224983049576081571356306754
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.98475315830533682846198606515813786578682699030768343351945772742791063398937
Short name T380
Test name
Test status
Simulation time 834576440 ps
CPU time 3.12 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:15 PM PST 23
Peak memory 203036 kb
Host smart-72d62287-9a12-437c-9b71-1f1d5ae08219
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984753158305336828461986065158137865786826990307683
43351945772742791063398937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_perf.984753158305336828461986065158137865786826990307683
43351945772742791063398937
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.35944120110513494692131044392927620690152538334430167022691599354449164965061
Short name T845
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.68 seconds
Started Nov 22 02:21:47 PM PST 23
Finished Nov 22 02:21:57 PM PST 23
Peak memory 202916 kb
Host smart-bbe2a5a1-ac3e-442a-9b0b-df72db051fbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594412011051349469213104439292762069015253833443016702269159935444916
4965061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smoke.35944120110513494692131044392927620690152538334430167022691599354449164965061
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.73676962761525971416488360000323433832185820631978043974004516287716538824246
Short name T167
Test name
Test status
Simulation time 66540157934 ps
CPU time 1583.84 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:48:11 PM PST 23
Peak memory 6983412 kb
Host smart-e94ace79-1687-4198-b79f-f7632801e038
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73676962761525971416488360000323433832185820631978
043974004516287716538824246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_all.73676962761525971416488360000323433832
185820631978043974004516287716538824246
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.15456719738558862878841436302140358962030105829998708796578181172917965997069
Short name T510
Test name
Test status
Simulation time 997771563 ps
CPU time 8.67 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:20 PM PST 23
Peak memory 202992 kb
Host smart-b31da52c-912e-460e-848d-ebe775ee54fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545671973855886287884143630214035896203010582999870879657818117291796
5997069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_rd.154567197385588628788414363021403589620301058299987087965781
81172917965997069
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.7389626501248964294561935222280522046256937892537852762056786780675952433277
Short name T1227
Test name
Test status
Simulation time 14461449567 ps
CPU time 85.09 seconds
Started Nov 22 02:22:11 PM PST 23
Finished Nov 22 02:23:39 PM PST 23
Peak memory 1542096 kb
Host smart-d14959fb-dae0-43d0-a47b-1f13dfc07eed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7389626501248964294561935222280522046256937892537852762056786780675952
433277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_wr.7389626501248964294561935222280522046256937892537852762056786
780675952433277
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.52225402812814098231206506223696500274926807207839387589708592271178489190130
Short name T154
Test name
Test status
Simulation time 6281818576 ps
CPU time 80.28 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:23:26 PM PST 23
Peak memory 930552 kb
Host smart-52a3c946-01e8-4cd2-a1a3-f5df6c6dc83c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5222540281281409823120650622369650027492680720783938758970859227117848
9190130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stretch.5222540281281409823120650622369650027492680720783938758970859227
1178489190130
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.106014030836301620247042221595533288499954478465472949308535435846736372919627
Short name T462
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.31 seconds
Started Nov 22 02:21:45 PM PST 23
Finished Nov 22 02:21:53 PM PST 23
Peak memory 212664 kb
Host smart-5cc04004-7bea-4863-9260-76084bba4780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106014030836301620247042221595533288499954478465472
949308535435846736372919627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_timeout.10601403083630162024704222159553328849995447
8465472949308535435846736372919627
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_ovf.1275125852365938270809386660173834620268164059739147156469131232188504190323
Short name T1039
Test name
Test status
Simulation time 5445414553 ps
CPU time 153.69 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:24:39 PM PST 23
Peak memory 406832 kb
Host smart-d3fc74f3-0c48-4175-9d06-a84cbb1afa8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12751258523659382708093866601738346202681640597391
47156469131232188504190323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_tx_ovf.12751258523659382708093866601738346202681640597
39147156469131232188504190323
Directory /workspace/22.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.43359384983007464372297782900846375850869642388201052771492139500187917394618
Short name T190
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.53 seconds
Started Nov 22 02:21:49 PM PST 23
Finished Nov 22 02:21:55 PM PST 23
Peak memory 205232 kb
Host smart-52bc5e7f-39b5-4137-b3f8-a2a3aead876c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433593849830074643722977829008463758508696423882010
52771492139500187917394618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_unexp_stop.43359384983007464372297782900846375850869
642388201052771492139500187917394618
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.100657072522994445574913288890002059754325188417911972632391242810857599931009
Short name T1539
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:12 PM PST 23
Peak memory 202716 kb
Host smart-3c5cb995-15b7-4021-9dac-12e047a30f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100657072522994445574913288890002059754325188417911972632391242810857599931009 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_alert_test.100657072522994445574913288890002059754325188417911972632391242810857599931009
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.100666372121650888756052619467973852031973550437322392336031319210545271949739
Short name T964
Test name
Test status
Simulation time 74225396 ps
CPU time 1.34 seconds
Started Nov 22 02:21:45 PM PST 23
Finished Nov 22 02:21:47 PM PST 23
Peak memory 211304 kb
Host smart-3ccd0100-1abc-431b-bea4-a4a063defe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100666372121650888756052619467973852031973550437322392336031319210545271949739 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_host_error_intr.100666372121650888756052619467973852031973550437322392336031319210545271949739
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.72337759220585538929481922442298582299418509390393064566119990372079095387939
Short name T1322
Test name
Test status
Simulation time 606667565 ps
CPU time 6.82 seconds
Started Nov 22 02:21:47 PM PST 23
Finished Nov 22 02:21:54 PM PST 23
Peak memory 273300 kb
Host smart-a1d50b6f-795a-43f9-a2cf-6a30a6f0902a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72337759220585538929481922442298582299418509390393064566119990372079095387939 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.72337759220585538929481922442298582299418509390393064566119990372079095387939
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.70584727740352283793617286605038997885132236206963216187850463220064254283451
Short name T853
Test name
Test status
Simulation time 3768267272 ps
CPU time 72.81 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:23:20 PM PST 23
Peak memory 729508 kb
Host smart-18e8623f-a4f3-4e08-9c2a-828175cf7602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70584727740352283793617286605038997885132236206963216187850463220064254283451 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_host_fifo_full.70584727740352283793617286605038997885132236206963216187850463220064254283451
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.75522639855058089228700913364182519458174911337535189578727954533334767629889
Short name T1207
Test name
Test status
Simulation time 209010032 ps
CPU time 0.99 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:22:08 PM PST 23
Peak memory 202796 kb
Host smart-ea9937e6-49b1-4141-895b-71547e77dbdc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75522639855058089228700913364182519458174911337535189578727954533334767629889 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.75522639855058089228700913364182519458174911337535189578727954533334767629889
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.115293875805366979251361681828503770833673874754780654029542742601707321990023
Short name T777
Test name
Test status
Simulation time 236313385 ps
CPU time 3.74 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 225548 kb
Host smart-5478d91a-478a-4132-a3a8-dff0777cabba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115293875805366979251361681828503770833673874754780654029542742601707321990023 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.115293875805366979251361681828503770833673874754780654029542742601707321990023
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.31926295573745801699992234873504702101678721516915740651585596346755505788351
Short name T736
Test name
Test status
Simulation time 7918519784 ps
CPU time 203.99 seconds
Started Nov 22 02:21:47 PM PST 23
Finished Nov 22 02:25:12 PM PST 23
Peak memory 1310924 kb
Host smart-5de92ea9-6a10-4f23-882e-f9762692d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31926295573745801699992234873504702101678721516915740651585596346755505788351 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.i2c_host_fifo_watermark.31926295573745801699992234873504702101678721516915740651585596346755505788351
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.64841079210220118367338130893300852899058954296250920893799428271466341608737
Short name T258
Test name
Test status
Simulation time 3754070957 ps
CPU time 50.78 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:22:38 PM PST 23
Peak memory 293804 kb
Host smart-120bef64-e424-481e-b587-086bf90cfc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64841079210220118367338130893300852899058954296250920893799428271466341608737 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_host_mode_toggle.64841079210220118367338130893300852899058954296250920893799428271466341608737
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.54341121224799389004190448550285007166387914116145558445912337000495577356537
Short name T253
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:21:49 PM PST 23
Finished Nov 22 02:21:50 PM PST 23
Peak memory 202752 kb
Host smart-79a60eb7-098e-4412-ad83-7634314683b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54341121224799389004190448550285007166387914116145558445912337000495577356537 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_host_override.54341121224799389004190448550285007166387914116145558445912337000495577356537
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.52664997548376944235093631554547743002562071074861881924391136057102897305145
Short name T983
Test name
Test status
Simulation time 6830796343 ps
CPU time 61.67 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:22:48 PM PST 23
Peak memory 211324 kb
Host smart-c14a061a-1d18-4b46-8472-283388bf7eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52664997548376944235093631554547743002562071074861881924391136057102897305145 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.i2c_host_perf.52664997548376944235093631554547743002562071074861881924391136057102897305145
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_rx_oversample.41125874466263226316130001626028132566291813427388718460890599404299451833346
Short name T1113
Test name
Test status
Simulation time 3939158762 ps
CPU time 101.75 seconds
Started Nov 22 02:21:46 PM PST 23
Finished Nov 22 02:23:29 PM PST 23
Peak memory 345928 kb
Host smart-498ee2fb-6773-4009-94e6-cfee4bf514ab
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41125874466263226316130001626028132566291813427388718460890599404299451833346 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_rx_oversample.41125874466263226316130001626028132566291813427388718460890599404299451833346
Directory /workspace/23.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.106746455418508861190485887549714927390075387120175159591950531804259458647855
Short name T296
Test name
Test status
Simulation time 2343171530 ps
CPU time 36 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:22:42 PM PST 23
Peak memory 299360 kb
Host smart-64d00554-2149-4f7b-9346-85265337f7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106746455418508861190485887549714927390075387120175159591950531804259458647855 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.i2c_host_smoke.106746455418508861190485887549714927390075387120175159591950531804259458647855
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.90181218935944749965201075525476939621204743468791141203330860825776755699124
Short name T375
Test name
Test status
Simulation time 32807463528 ps
CPU time 1091.07 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:40:17 PM PST 23
Peak memory 1956944 kb
Host smart-299661cf-082b-4098-814c-7f471e5c9371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90181218935944749965201075525476939621204743468791141203330860825776755699124 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_host_stress_all.90181218935944749965201075525476939621204743468791141203330860825776755699124
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.67963606310064791703215130568273984091228168616522699827538399405218487458444
Short name T889
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.59 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:22:20 PM PST 23
Peak memory 214164 kb
Host smart-85baaf90-6dd2-4421-b4b6-a5a701fd96f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67963606310064791703215130568273984091228168616522699827538399405218487458444 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_host_stretch_timeout.67963606310064791703215130568273984091228168616522699827538399405218487458444
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.26228894343351827098064464673890680288451841809930397027239447408670923670677
Short name T860
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.81 seconds
Started Nov 22 02:22:10 PM PST 23
Finished Nov 22 02:22:17 PM PST 23
Peak memory 202956 kb
Host smart-46f87ac9-463e-40b6-8a89-9ad07f73d6f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622889434335182709806446467389
0680288451841809930397027239447408670923670677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.26228894343351827098064464
673890680288451841809930397027239447408670923670677
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.80690238514657027459909060329879863499282223551364817690419983821726893267937
Short name T279
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.36 seconds
Started Nov 22 02:21:50 PM PST 23
Finished Nov 22 02:22:22 PM PST 23
Peak memory 382168 kb
Host smart-b37eda0b-4aed-43c6-970c-6bf9dca8d2b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806902385146570274599090603298798634992822235513648
17690419983821726893267937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.8069023851465702745990906032987
9863499282223551364817690419983821726893267937
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.93942361328475357220321651705391336495011353632821572792202856754433522825893
Short name T363
Test name
Test status
Simulation time 10065199023 ps
CPU time 35.79 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:46 PM PST 23
Peak memory 462148 kb
Host smart-9de7cf08-5785-44fb-ba69-1e7749aeef79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939423613284753572203216517053913364950113536328215
72792202856754433522825893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_tx.939423613284753572203216517053913
36495011353632821572792202856754433522825893
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.23744838103836467698192634992453869644476549330984105394615564741075755104300
Short name T863
Test name
Test status
Simulation time 825344371 ps
CPU time 2.52 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:21:51 PM PST 23
Peak memory 203060 kb
Host smart-52a1e2c3-2d86-408d-ae86-895a3b1aa517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237448381038364676981926349924538696444765493309841
05394615564741075755104300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_hrst.237448381038364676981926349924538696444765493309841
05394615564741075755104300
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.56123614100125685987177290260841401350831407457618254876977400465279390808951
Short name T1559
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.22 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:22:10 PM PST 23
Peak memory 203732 kb
Host smart-540926d5-ccc5-44e3-ac2d-52a6049582dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56123614100125685987177290260841401350831407457618
254876977400465279390808951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_smoke.5612361410012568598717729026084140135083140
7457618254876977400465279390808951
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.41620857448768467155937138570028001384660287548385279687454242945547785253410
Short name T107
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.74 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:22:10 PM PST 23
Peak memory 639216 kb
Host smart-ca99ea6a-af28-4c5e-801f-04e4280a4904
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41620857448768467155937138570028001384
660287548385279687454242945547785253410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.41620857448768467155937
138570028001384660287548385279687454242945547785253410
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.39405639768650062703791395719669105534100822150302873298274955380756363465147
Short name T1158
Test name
Test status
Simulation time 834576440 ps
CPU time 2.95 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 203020 kb
Host smart-60a2eaa0-b025-4c3a-ba1a-b14cb4f14698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394056397686500627037913957196691055341008221503028
73298274955380756363465147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_perf.394056397686500627037913957196691055341008221503028
73298274955380756363465147
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.3766822543717944741955349649344497211299177326374613306163917147481713249410
Short name T1191
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.47 seconds
Started Nov 22 02:21:49 PM PST 23
Finished Nov 22 02:21:59 PM PST 23
Peak memory 203008 kb
Host smart-fa0c5683-680b-47da-a8fc-bef5458d0d69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766822543717944741955349649344497211299177326374613306163917147481713
249410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smoke.3766822543717944741955349649344497211299177326374613306163917147481713249410
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.44724056199251775873896992413066433167035470174827604468380114876494949526508
Short name T1303
Test name
Test status
Simulation time 66540157934 ps
CPU time 1520.41 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:47:32 PM PST 23
Peak memory 6983408 kb
Host smart-2acbc20b-7aaf-4ed7-803e-eb5544c6e981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44724056199251775873896992413066433167035470174827
604468380114876494949526508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_all.44724056199251775873896992413066433167
035470174827604468380114876494949526508
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.16848105124250226508279924059773767065099342164310185211481891549748641518772
Short name T1066
Test name
Test status
Simulation time 997771563 ps
CPU time 8.59 seconds
Started Nov 22 02:21:45 PM PST 23
Finished Nov 22 02:21:54 PM PST 23
Peak memory 203052 kb
Host smart-084f0d77-dc8e-4731-97a1-1cb28253d5fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684810512425022650827992405977376706509934216431018521148189154974864
1518772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_rd.168481051242502265082799240597737670650993421643101852114818
91549748641518772
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.39547317242423091370001304894097461736734738139472610950112139378407744987965
Short name T954
Test name
Test status
Simulation time 14461449567 ps
CPU time 81.4 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:23:34 PM PST 23
Peak memory 1542084 kb
Host smart-84e2a2a6-06ab-4572-b484-3bf1ddbebe51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954731724242309137000130489409746173673473813947261095011213937840774
4987965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_wr.395473172424230913700013048940974617367347381394726109501121
39378407744987965
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.54117835867827823972533299936367889293813015803197509436718111291000633756890
Short name T163
Test name
Test status
Simulation time 6281818576 ps
CPU time 76.67 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:23:27 PM PST 23
Peak memory 930576 kb
Host smart-a616bf86-419a-494f-bd71-c0e3064aac17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5411783586782782397253329993636788929381301580319750943671811129100063
3756890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stretch.5411783586782782397253329993636788929381301580319750943671811129
1000633756890
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.82698311973282995949760957944671014256256444649332147076096106451162974665490
Short name T385
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.42 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:20 PM PST 23
Peak memory 212624 kb
Host smart-f7ebe678-4a7a-42f7-8bbc-6c5baac6a7fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826983119732829959497609579446710142562564446493321
47076096106451162974665490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_timeout.826983119732829959497609579446710142562564446
49332147076096106451162974665490
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_ovf.53032279097588298851609490971924226216348161746456165479180496445556721794296
Short name T1579
Test name
Test status
Simulation time 5445414553 ps
CPU time 118.53 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:24:04 PM PST 23
Peak memory 406788 kb
Host smart-f48e9de0-ac71-4cdb-8458-b8b5247f8223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53032279097588298851609490971924226216348161746456
165479180496445556721794296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_tx_ovf.5303227909758829885160949097192422621634816174
6456165479180496445556721794296
Directory /workspace/23.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.104227975702042534234811554428950646283373542894027809636875352746319878389273
Short name T1041
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.64 seconds
Started Nov 22 02:21:53 PM PST 23
Finished Nov 22 02:21:59 PM PST 23
Peak memory 205196 kb
Host smart-62d15e13-7516-4718-85b6-f69851e43924
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104227975702042534234811554428950646283373542894027
809636875352746319878389273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_unexp_stop.1042279757020425342348115544289506462833
73542894027809636875352746319878389273
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.48373316585449794087790634676241138670404077333767604301354201518033469124076
Short name T540
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:22:11 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 202544 kb
Host smart-9af58293-dd3d-4533-bb76-0d6dd623f974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48373316585449794087790634676241138670404077333767604301354201518033469124076 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_alert_test.48373316585449794087790634676241138670404077333767604301354201518033469124076
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.47376654256655073339973695418895494790958408993284588228944182426093135090724
Short name T831
Test name
Test status
Simulation time 74225396 ps
CPU time 1.34 seconds
Started Nov 22 02:21:54 PM PST 23
Finished Nov 22 02:21:57 PM PST 23
Peak memory 211164 kb
Host smart-409ad38a-e0ed-4eac-9c64-6ca889e1a5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47376654256655073339973695418895494790958408993284588228944182426093135090724 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_host_error_intr.47376654256655073339973695418895494790958408993284588228944182426093135090724
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.20330420162826438416147190320127314297396606804935760050534948009243008609549
Short name T649
Test name
Test status
Simulation time 606667565 ps
CPU time 6.92 seconds
Started Nov 22 02:21:51 PM PST 23
Finished Nov 22 02:21:58 PM PST 23
Peak memory 273344 kb
Host smart-22c6cd60-2695-40eb-99b1-3ac90fd53325
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20330420162826438416147190320127314297396606804935760050534948009243008609549 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.20330420162826438416147190320127314297396606804935760050534948009243008609549
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.23210108150085990936350142087976451658069252137589285216532533878091562264467
Short name T259
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.91 seconds
Started Nov 22 02:21:49 PM PST 23
Finished Nov 22 02:23:04 PM PST 23
Peak memory 729540 kb
Host smart-ac02c77d-800c-4221-abc6-ef97ad8d01b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23210108150085990936350142087976451658069252137589285216532533878091562264467 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_host_fifo_full.23210108150085990936350142087976451658069252137589285216532533878091562264467
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.65631467174710112454129762741747374900492564861912949933598406519541571462542
Short name T492
Test name
Test status
Simulation time 7925734012 ps
CPU time 265.42 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:26:36 PM PST 23
Peak memory 1271532 kb
Host smart-c3fac58d-9f05-4598-937f-d276e2fde397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65631467174710112454129762741747374900492564861912949933598406519541571462542 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.i2c_host_fifo_overflow.65631467174710112454129762741747374900492564861912949933598406519541571462542
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.49554538752287958958912058764136308983442970507360109637983268233891576629363
Short name T64
Test name
Test status
Simulation time 209010032 ps
CPU time 0.97 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 202852 kb
Host smart-875fb735-2055-48a6-a5c5-f3cd26a8e53b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49554538752287958958912058764136308983442970507360109637983268233891576629363 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.49554538752287958958912058764136308983442970507360109637983268233891576629363
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.56381740958008910771790826275854179545814410117892576628377974565096836967653
Short name T286
Test name
Test status
Simulation time 236313385 ps
CPU time 3.74 seconds
Started Nov 22 02:21:54 PM PST 23
Finished Nov 22 02:22:00 PM PST 23
Peak memory 225372 kb
Host smart-8e3411c6-5e65-403c-a1db-b8be05db651a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56381740958008910771790826275854179545814410117892576628377974565096836967653 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.56381740958008910771790826275854179545814410117892576628377974565096836967653
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.69560389559123743026593875427663213448520264569546953532729587037169935562382
Short name T1054
Test name
Test status
Simulation time 7918519784 ps
CPU time 203.74 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:25:32 PM PST 23
Peak memory 1310712 kb
Host smart-86b3a142-0864-4f5f-ac83-8d1e4f1a5ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69560389559123743026593875427663213448520264569546953532729587037169935562382 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.i2c_host_fifo_watermark.69560389559123743026593875427663213448520264569546953532729587037169935562382
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.104570917287422385478925033780603989823824353857721227144874574437351260538438
Short name T651
Test name
Test status
Simulation time 3754070957 ps
CPU time 56.69 seconds
Started Nov 22 02:22:10 PM PST 23
Finished Nov 22 02:23:10 PM PST 23
Peak memory 293664 kb
Host smart-cdfbc512-5300-40b0-8db6-9e95361e8ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104570917287422385478925033780603989823824353857721227144874574437351260538438 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.i2c_host_mode_toggle.104570917287422385478925033780603989823824353857721227144874574437351260538438
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.81705735053830162605155358299769591364584866187329020190020889292639897332359
Short name T20
Test name
Test status
Simulation time 23672229 ps
CPU time 0.61 seconds
Started Nov 22 02:21:50 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 202548 kb
Host smart-7c0be20c-5651-4f16-9319-c7e1d99a97b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81705735053830162605155358299769591364584866187329020190020889292639897332359 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_host_override.81705735053830162605155358299769591364584866187329020190020889292639897332359
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.11321073073157680426915205501179046030222577584980606292850360348885966184223
Short name T666
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.45 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:23:07 PM PST 23
Peak memory 211244 kb
Host smart-8169bd80-8c87-4a9c-8cf4-85b4e969e71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11321073073157680426915205501179046030222577584980606292850360348885966184223 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.i2c_host_perf.11321073073157680426915205501179046030222577584980606292850360348885966184223
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_rx_oversample.101632282619110436607342802547188489962110697725889105549616958787296146315558
Short name T1513
Test name
Test status
Simulation time 3939158762 ps
CPU time 101.96 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:23:48 PM PST 23
Peak memory 345972 kb
Host smart-3e29a5a8-db15-43a1-9a3f-fddaba575cc6
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101632282619110436607342802547188489962110697725889105549616958787296146315558 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_rx_oversample.101632282619110436607342802547188489962110697725889105549616958787296146315558
Directory /workspace/24.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.55117239312354149931663078914585079559396668581812308511770463721664607770764
Short name T1475
Test name
Test status
Simulation time 2343171530 ps
CPU time 35.76 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:47 PM PST 23
Peak memory 299428 kb
Host smart-2b59aac0-5b8d-4bb1-b229-e69c4f1bb679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55117239312354149931663078914585079559396668581812308511770463721664607770764 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.i2c_host_smoke.55117239312354149931663078914585079559396668581812308511770463721664607770764
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.66870097285197715887024162037193931049071088053916022575292421548439856533728
Short name T325
Test name
Test status
Simulation time 32807463528 ps
CPU time 1057.51 seconds
Started Nov 22 02:22:09 PM PST 23
Finished Nov 22 02:39:51 PM PST 23
Peak memory 1957092 kb
Host smart-cd3a381c-284a-4067-8d0f-cc5493d416b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66870097285197715887024162037193931049071088053916022575292421548439856533728 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_host_stress_all.66870097285197715887024162037193931049071088053916022575292421548439856533728
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.65880013804080179775358087824778225460608419455965584643957582648922877968747
Short name T815
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.25 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:26 PM PST 23
Peak memory 214168 kb
Host smart-3be6de26-5444-4bbc-bfd4-1a7314e77d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65880013804080179775358087824778225460608419455965584643957582648922877968747 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_host_stretch_timeout.65880013804080179775358087824778225460608419455965584643957582648922877968747
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.88640907000946287596975276610792646782940241581953176776778211035178450182689
Short name T441
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.91 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:16 PM PST 23
Peak memory 203024 kb
Host smart-cc05dd55-565f-4676-ba77-cfc199e39454
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8864090700094628759697527661079
2646782940241581953176776778211035178450182689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.88640907000946287596975276
610792646782940241581953176776778211035178450182689
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.36594496026388939434376857555665168618841631517880506354584399748560320354987
Short name T906
Test name
Test status
Simulation time 10166144644 ps
CPU time 34.37 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:46 PM PST 23
Peak memory 382180 kb
Host smart-14d2c687-8bab-4788-8371-3eb5ebefc082
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365944960263889394343768575556651686188416315178805
06354584399748560320354987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.3659449602638893943437685755566
5168618841631517880506354584399748560320354987
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.113655194589909422879819198556294128675591506336604810304942997978698526035169
Short name T1205
Test name
Test status
Simulation time 10065199023 ps
CPU time 37.56 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:50 PM PST 23
Peak memory 462044 kb
Host smart-3990275c-ba6d-44eb-8f37-db10bca924f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113655194589909422879819198556294128675591506336604
810304942997978698526035169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_tx.11365519458990942287981919855629
4128675591506336604810304942997978698526035169
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.113684176171446209521784804264576604028041642924921389020754628315304284216311
Short name T1000
Test name
Test status
Simulation time 825344371 ps
CPU time 2.39 seconds
Started Nov 22 02:22:16 PM PST 23
Finished Nov 22 02:22:20 PM PST 23
Peak memory 202920 kb
Host smart-aa64158a-7da2-4a3e-810a-5bbe180541d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113684176171446209521784804264576604028041642924921
389020754628315304284216311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_hrst.11368417617144620952178480426457660402804164292492
1389020754628315304284216311
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.36212146058373946992847010605122522299269272537921075710828828757971090549231
Short name T520
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.17 seconds
Started Nov 22 02:22:16 PM PST 23
Finished Nov 22 02:22:21 PM PST 23
Peak memory 203588 kb
Host smart-611f57fa-e0ea-4ca3-b964-808dfb0149cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212146058373946992847010605122522299269272537921
075710828828757971090549231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_smoke.3621214605837394699284701060512252229926927
2537921075710828828757971090549231
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.33333172496254707239295860154713832205915910792466757417078362632970533702418
Short name T1029
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.02 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 639168 kb
Host smart-39146edc-d84f-43f8-b3cc-9d3707e277c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33333172496254707239295860154713832205
915910792466757417078362632970533702418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.33333172496254707239295
860154713832205915910792466757417078362632970533702418
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.73733940377585901055788347069178786887832536049306985668366091251050548721285
Short name T1052
Test name
Test status
Simulation time 834576440 ps
CPU time 3.03 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 203028 kb
Host smart-00a4ecf3-a6d2-4a10-8cbc-8952e2150cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737339403775859010557883470691787868878325360493069
85668366091251050548721285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_perf.737339403775859010557883470691787868878325360493069
85668366091251050548721285
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.7913669620579682667353009456416895357676776759286989319256625755670829635758
Short name T601
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.55 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:20 PM PST 23
Peak memory 203016 kb
Host smart-72ea337d-be7c-4e06-87f4-36e60039567b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7913669620579682667353009456416895357676776759286989319256625755670829
635758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smoke.7913669620579682667353009456416895357676776759286989319256625755670829635758
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.7847593066320513612944555551803113802454079512065841134081589492416278668264
Short name T801
Test name
Test status
Simulation time 66540157934 ps
CPU time 1333.92 seconds
Started Nov 22 02:21:50 PM PST 23
Finished Nov 22 02:44:05 PM PST 23
Peak memory 6983540 kb
Host smart-79911cd3-086f-46c2-9744-01ec69603c60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78475930663205136129445555518031138024540795120658
41134081589492416278668264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_all.784759306632051361294455555180311380245
4079512065841134081589492416278668264
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.84476143391914156801124104082821387926719350779556811480860893789524887131718
Short name T261
Test name
Test status
Simulation time 997771563 ps
CPU time 8.71 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:22:15 PM PST 23
Peak memory 203076 kb
Host smart-c7211728-df18-4532-a887-c23d91d33d6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8447614339191415680112410408282138792671935077955681148086089378952488
7131718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_rd.844761433919141568011241040828213879267193507795568114808608
93789524887131718
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.90123636058843663487477880453360876786526052967968641698589319529819327617091
Short name T1270
Test name
Test status
Simulation time 14461449567 ps
CPU time 86.04 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:23:38 PM PST 23
Peak memory 1542140 kb
Host smart-e1c0b590-07c2-4c39-9702-baecc2d77505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9012363605884366348747788045336087678652605296796864169858931952981932
7617091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_wr.901236360588436634874778804533608767865260529679686416985893
19529819327617091
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.7457682081748887231815389777259138584301117640288164919062856559474502181123
Short name T1159
Test name
Test status
Simulation time 6281818576 ps
CPU time 78.46 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:23:31 PM PST 23
Peak memory 930652 kb
Host smart-ed199f53-496d-43ed-9790-79b204d8c148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7457682081748887231815389777259138584301117640288164919062856559474502
181123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stretch.7457682081748887231815389777259138584301117640288164919062856559474502181123
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.15062700216329972421128913232503504521877068441960170261987618023106606393449
Short name T362
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.28 seconds
Started Nov 22 02:22:20 PM PST 23
Finished Nov 22 02:22:34 PM PST 23
Peak memory 212516 kb
Host smart-ae133742-8dc1-4d79-bed5-8290de35de38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150627002163299724211289132325035045218770684419601
70261987618023106606393449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_timeout.150627002163299724211289132325035045218770684
41960170261987618023106606393449
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_ovf.33209590635118785830219240211053861988026991316743467624967813029012771292484
Short name T790
Test name
Test status
Simulation time 5445414553 ps
CPU time 107.64 seconds
Started Nov 22 02:22:10 PM PST 23
Finished Nov 22 02:24:01 PM PST 23
Peak memory 406532 kb
Host smart-473177f2-ab05-4459-8774-f3670d71aaaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33209590635118785830219240211053861988026991316743
467624967813029012771292484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_tx_ovf.3320959063511878583021924021105386198802699131
6743467624967813029012771292484
Directory /workspace/24.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.21971633361509796208666571891164269460809111715042263730111830086834972038851
Short name T1520
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.41 seconds
Started Nov 22 02:22:20 PM PST 23
Finished Nov 22 02:22:34 PM PST 23
Peak memory 205200 kb
Host smart-0f710a8a-49d6-41d9-9de6-5383031ac2e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219716333615097962086665718911642694608091117150422
63730111830086834972038851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_unexp_stop.21971633361509796208666571891164269460809
111715042263730111830086834972038851
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.53267219510651623402313238544581222515012007796097674810625017345581337862514
Short name T1217
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:22:11 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 202484 kb
Host smart-9b355c21-563a-4e5b-bd7b-4f4566043d01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53267219510651623402313238544581222515012007796097674810625017345581337862514 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_alert_test.53267219510651623402313238544581222515012007796097674810625017345581337862514
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.81131261354981021207375997265661507697791088002876175223310411341811529341838
Short name T840
Test name
Test status
Simulation time 74225396 ps
CPU time 1.38 seconds
Started Nov 22 02:21:53 PM PST 23
Finished Nov 22 02:21:55 PM PST 23
Peak memory 211164 kb
Host smart-f41caa3c-d725-42c0-8433-19d349d5bbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81131261354981021207375997265661507697791088002876175223310411341811529341838 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_host_error_intr.81131261354981021207375997265661507697791088002876175223310411341811529341838
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.28101546673483443742377074448158347805072087220420191004869997060397865563544
Short name T973
Test name
Test status
Simulation time 606667565 ps
CPU time 6.78 seconds
Started Nov 22 02:21:50 PM PST 23
Finished Nov 22 02:21:58 PM PST 23
Peak memory 273356 kb
Host smart-6f388153-1ab9-433e-9d20-10ba9679868d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28101546673483443742377074448158347805072087220420191004869997060397865563544 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.28101546673483443742377074448158347805072087220420191004869997060397865563544
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.73746061779379355281539245688220216274884877883181383308993387768361084453872
Short name T608
Test name
Test status
Simulation time 3768267272 ps
CPU time 77.11 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:23:25 PM PST 23
Peak memory 729352 kb
Host smart-971302ed-d9e7-4764-b7a8-f1f84e0d821d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73746061779379355281539245688220216274884877883181383308993387768361084453872 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_host_fifo_full.73746061779379355281539245688220216274884877883181383308993387768361084453872
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.31462517934268795019535014737905997655097675082013121912571723970402292156502
Short name T661
Test name
Test status
Simulation time 7925734012 ps
CPU time 217.39 seconds
Started Nov 22 02:21:50 PM PST 23
Finished Nov 22 02:25:29 PM PST 23
Peak memory 1271544 kb
Host smart-fd9aa8ab-addb-42b4-b0ed-8b89d823c6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31462517934268795019535014737905997655097675082013121912571723970402292156502 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.i2c_host_fifo_overflow.31462517934268795019535014737905997655097675082013121912571723970402292156502
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.5538637335674777673033253004502634828258245083821351291369520929514227867980
Short name T423
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:21:50 PM PST 23
Finished Nov 22 02:21:52 PM PST 23
Peak memory 202908 kb
Host smart-01d8d312-38e2-4018-82fb-b5c31a4654e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5538637335674777673033253004502634828258245083821351291369520929514227867980 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.5538637335674777673033253004502634828258245083821351291369520929514227867980
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.106233856142891699407745350101323810651608808722021097388284731129853317737043
Short name T871
Test name
Test status
Simulation time 236313385 ps
CPU time 3.9 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:15 PM PST 23
Peak memory 225480 kb
Host smart-55a51c40-caee-4346-b3db-8f3ffe2a3c29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106233856142891699407745350101323810651608808722021097388284731129853317737043 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.106233856142891699407745350101323810651608808722021097388284731129853317737043
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.105968299579032992744041841803825380010678861730704717555830819078188009487106
Short name T959
Test name
Test status
Simulation time 7918519784 ps
CPU time 225.36 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:25:51 PM PST 23
Peak memory 1311012 kb
Host smart-41a690b1-2697-4964-9b89-16866257b44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105968299579032992744041841803825380010678861730704717555830819078188009487106 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_host_fifo_watermark.105968299579032992744041841803825380010678861730704717555830819078188009487106
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.42514523390897338090694604467367203947224820400450296762279015902086093796924
Short name T1111
Test name
Test status
Simulation time 3754070957 ps
CPU time 50.17 seconds
Started Nov 22 02:22:20 PM PST 23
Finished Nov 22 02:23:17 PM PST 23
Peak memory 293628 kb
Host smart-2a0111e9-1abc-4b19-9fc7-71e5ec613205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42514523390897338090694604467367203947224820400450296762279015902086093796924 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_host_mode_toggle.42514523390897338090694604467367203947224820400450296762279015902086093796924
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.60487755315219969290323151468262646465251979846491968558736539127957885677896
Short name T900
Test name
Test status
Simulation time 23672229 ps
CPU time 0.68 seconds
Started Nov 22 02:22:11 PM PST 23
Finished Nov 22 02:22:15 PM PST 23
Peak memory 202804 kb
Host smart-a7ead43e-cc99-4230-9cf2-4ede7f27d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60487755315219969290323151468262646465251979846491968558736539127957885677896 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_host_override.60487755315219969290323151468262646465251979846491968558736539127957885677896
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.115248612003378603981306018287689004500217436046012188319703182040191210848902
Short name T60
Test name
Test status
Simulation time 6830796343 ps
CPU time 59.25 seconds
Started Nov 22 02:22:17 PM PST 23
Finished Nov 22 02:23:19 PM PST 23
Peak memory 211332 kb
Host smart-622c11fe-4ac7-4a6c-ac26-b7e8beb3f8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115248612003378603981306018287689004500217436046012188319703182040191210848902 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.i2c_host_perf.115248612003378603981306018287689004500217436046012188319703182040191210848902
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_rx_oversample.60914824366471282137298546977723965010323303672162414931044355780903247245368
Short name T459
Test name
Test status
Simulation time 3939158762 ps
CPU time 103.84 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:23:33 PM PST 23
Peak memory 345952 kb
Host smart-521a2e25-a230-47d0-b2b2-fc2ed48092ec
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60914824366471282137298546977723965010323303672162414931044355780903247245368 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_rx_oversample.60914824366471282137298546977723965010323303672162414931044355780903247245368
Directory /workspace/25.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.68776163995672435479022340631587786254461915211411815133088201077828246477965
Short name T265
Test name
Test status
Simulation time 2343171530 ps
CPU time 35.6 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:48 PM PST 23
Peak memory 299208 kb
Host smart-efe743fd-4b30-4e82-b56d-13b2a817b64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68776163995672435479022340631587786254461915211411815133088201077828246477965 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.i2c_host_smoke.68776163995672435479022340631587786254461915211411815133088201077828246477965
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.69778391306216022257281350344277190638486003067033021163603758805143192718060
Short name T740
Test name
Test status
Simulation time 32807463528 ps
CPU time 1012.53 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:39:06 PM PST 23
Peak memory 1957068 kb
Host smart-10681ecc-3229-4cb5-820b-2ffe533018be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69778391306216022257281350344277190638486003067033021163603758805143192718060 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_host_stress_all.69778391306216022257281350344277190638486003067033021163603758805143192718060
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.32200516361131665444239444831280127341738222538549688186947037486129883287291
Short name T1382
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.83 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:22:19 PM PST 23
Peak memory 214160 kb
Host smart-808b8199-db0d-436d-8e26-00d2131d3b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32200516361131665444239444831280127341738222538549688186947037486129883287291 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_host_stretch_timeout.32200516361131665444239444831280127341738222538549688186947037486129883287291
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.72886779315730621340017983306161125235999715617115937632901200379860422716825
Short name T839
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.83 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:22:10 PM PST 23
Peak memory 202996 kb
Host smart-ad99c107-3662-4f5d-8db1-4bcf22e6398f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7288677931573062134001798330616
1125235999715617115937632901200379860422716825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.72886779315730621340017983
306161125235999715617115937632901200379860422716825
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.21807427346419634405021550850312746381763183333230755837670754330376226978572
Short name T727
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.59 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:43 PM PST 23
Peak memory 382236 kb
Host smart-af84b5cf-8977-4a9f-8061-d1c717e7d06f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218074273464196344050215508503127463817631833332307
55837670754330376226978572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.2180742734641963440502155085031
2746381763183333230755837670754330376226978572
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.46841223699338296349834981682135218881663945110930645415190669338969006636563
Short name T1501
Test name
Test status
Simulation time 10065199023 ps
CPU time 37.46 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:22:45 PM PST 23
Peak memory 462132 kb
Host smart-495ae199-7aee-4d44-babf-0521b346368a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468412236993382963498349816821352188816639451109306
45415190669338969006636563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_tx.468412236993382963498349816821352
18881663945110930645415190669338969006636563
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.107158149607231266938770842531466467175868872046631339234400613262274712659525
Short name T793
Test name
Test status
Simulation time 825344371 ps
CPU time 2.43 seconds
Started Nov 22 02:22:17 PM PST 23
Finished Nov 22 02:22:22 PM PST 23
Peak memory 203044 kb
Host smart-c4c2b80f-c1e7-43af-b43e-e5d1e5cde4e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107158149607231266938770842531466467175868872046631
339234400613262274712659525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_hrst.10715814960723126693877084253146646717586887204663
1339234400613262274712659525
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.59178538340498709225338719634843725825510287373605112516573467555486155078583
Short name T481
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.4 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:17 PM PST 23
Peak memory 203728 kb
Host smart-f029bb08-0d2c-4726-aa30-9e7e3a76b609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59178538340498709225338719634843725825510287373605
112516573467555486155078583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_smoke.5917853834049870922533871963484372582551028
7373605112516573467555486155078583
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.45473822650135661833506720801611851262477588465778118203268712744805006011443
Short name T1167
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.96 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:22:30 PM PST 23
Peak memory 639252 kb
Host smart-d199453d-cc6d-47ed-ac61-a3999d538cdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45473822650135661833506720801611851262
477588465778118203268712744805006011443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.45473822650135661833506
720801611851262477588465778118203268712744805006011443
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.87745270993423634273330362449075887459913531928116967949935222345525113557741
Short name T479
Test name
Test status
Simulation time 834576440 ps
CPU time 2.98 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 202976 kb
Host smart-f2aa78e3-ffec-454d-8f6a-a62561986aaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877452709934236342733303624490758874599135319281169
67949935222345525113557741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_perf.877452709934236342733303624490758874599135319281169
67949935222345525113557741
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.41918248940383799222331647483885023810654116237781633805066859018350516926355
Short name T1131
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.42 seconds
Started Nov 22 02:22:12 PM PST 23
Finished Nov 22 02:22:24 PM PST 23
Peak memory 202488 kb
Host smart-3af5937a-594a-4c9d-bd76-ba82d948544e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191824894038379922233164748388502381065411623778163380506685901835051
6926355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smoke.41918248940383799222331647483885023810654116237781633805066859018350516926355
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.15530534132116614098688869041395292066279004507454950920937277264387054929625
Short name T1163
Test name
Test status
Simulation time 66540157934 ps
CPU time 1386.28 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:45:18 PM PST 23
Peak memory 6983344 kb
Host smart-355b3f17-ed38-4b8d-a122-38ad76d2b8c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15530534132116614098688869041395292066279004507454
950920937277264387054929625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_all.15530534132116614098688869041395292066
279004507454950920937277264387054929625
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.8689806049079997154079328505019853083385087482419661820166303521193679919663
Short name T1529
Test name
Test status
Simulation time 997771563 ps
CPU time 8.55 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:22 PM PST 23
Peak memory 203028 kb
Host smart-a0f5c962-69f8-4b15-9747-4775601c6a43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8689806049079997154079328505019853083385087482419661820166303521193679
919663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_rd.8689806049079997154079328505019853083385087482419661820166303
521193679919663
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.12536208984254781148844704082351471222338414216493687034846608947285435914371
Short name T1499
Test name
Test status
Simulation time 14461449567 ps
CPU time 89.65 seconds
Started Nov 22 02:21:47 PM PST 23
Finished Nov 22 02:23:17 PM PST 23
Peak memory 1542148 kb
Host smart-def87085-910f-4726-bbd8-7610c0e1559d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253620898425478114884470408235147122233841421649368703484660894728543
5914371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_wr.125362089842547811488447040823514712223384142164936870348466
08947285435914371
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.44555378939104734567771566803264468244360634964737660878153599422107327138219
Short name T575
Test name
Test status
Simulation time 6281818576 ps
CPU time 75.84 seconds
Started Nov 22 02:21:54 PM PST 23
Finished Nov 22 02:23:11 PM PST 23
Peak memory 930448 kb
Host smart-cc9490c8-c1f3-4d03-9bbe-eaedb04b24ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4455537893910473456777156680326446824436063496473766087815359942210732
7138219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stretch.4455537893910473456777156680326446824436063496473766087815359942
2107327138219
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.45659054261944103926593395895113385441532252051534725369395280566735276311710
Short name T506
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.11 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:18 PM PST 23
Peak memory 212660 kb
Host smart-9d4b7d51-1120-4302-b86a-206852196d58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456590542619441039265933958951133854415322520515347
25369395280566735276311710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_timeout.456590542619441039265933958951133854415322520
51534725369395280566735276311710
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_ovf.71902434317556755070904781643631515198818370438877637187236972506934138682585
Short name T249
Test name
Test status
Simulation time 5445414553 ps
CPU time 118.32 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:24:05 PM PST 23
Peak memory 406852 kb
Host smart-ac0fd8cd-f24d-4649-8154-5fd47230c5e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71902434317556755070904781643631515198818370438877
637187236972506934138682585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_tx_ovf.7190243431755675507090478164363151519881837043
8877637187236972506934138682585
Directory /workspace/25.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.31515708433842387105146528872817117900063266363270427978820290570944393250752
Short name T1212
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.42 seconds
Started Nov 22 02:21:48 PM PST 23
Finished Nov 22 02:21:54 PM PST 23
Peak memory 205380 kb
Host smart-735e477a-2e29-4925-86e7-15783357657f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315157084338423871051465288728171179000632663632704
27978820290570944393250752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_unexp_stop.31515708433842387105146528872817117900063
266363270427978820290570944393250752
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.62358230035037802171678098213875806789602075734765597572137880741479775864587
Short name T1583
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:22:10 PM PST 23
Peak memory 202800 kb
Host smart-0a843f03-dedd-488f-92e6-54e667c0297a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62358230035037802171678098213875806789602075734765597572137880741479775864587 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_alert_test.62358230035037802171678098213875806789602075734765597572137880741479775864587
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.48119010236126934143675048772714083110165021825618796819714129991830488283774
Short name T330
Test name
Test status
Simulation time 74225396 ps
CPU time 1.38 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 211276 kb
Host smart-dd0b0b97-3e36-426f-bd76-0b1bd2a42d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48119010236126934143675048772714083110165021825618796819714129991830488283774 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_host_error_intr.48119010236126934143675048772714083110165021825618796819714129991830488283774
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.104933636407340928301118858979579486740567457902895808060269669746897614065029
Short name T981
Test name
Test status
Simulation time 606667565 ps
CPU time 6.6 seconds
Started Nov 22 02:22:11 PM PST 23
Finished Nov 22 02:22:21 PM PST 23
Peak memory 273300 kb
Host smart-9e4364d3-4da2-4a86-a777-9497107afaa7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104933636407340928301118858979579486740567457902895808060269669746897614065029 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.104933636407340928301118858979579486740567457902895808060269669746897614065029
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.66376220526904785269888078921603147302008869027877214909279055354895341681755
Short name T1118
Test name
Test status
Simulation time 3768267272 ps
CPU time 71.91 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:23:22 PM PST 23
Peak memory 729492 kb
Host smart-a55a5e5d-4845-4d76-a7d3-bda079f891c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66376220526904785269888078921603147302008869027877214909279055354895341681755 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_host_fifo_full.66376220526904785269888078921603147302008869027877214909279055354895341681755
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.37946695623069617482239994535985173116976591779801910119330075858580924631659
Short name T1363
Test name
Test status
Simulation time 7925734012 ps
CPU time 223.3 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:25:56 PM PST 23
Peak memory 1271536 kb
Host smart-344e1e43-b77c-42dd-963f-970bdfdf57bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37946695623069617482239994535985173116976591779801910119330075858580924631659 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.i2c_host_fifo_overflow.37946695623069617482239994535985173116976591779801910119330075858580924631659
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.326324068042719381064770267005646376622180278167022237057742169569375851309
Short name T898
Test name
Test status
Simulation time 209010032 ps
CPU time 0.96 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:22:09 PM PST 23
Peak memory 202908 kb
Host smart-1ffb71cc-64d1-40cc-be1a-949002aca374
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326324068042719381064770267005646376622180278167022237057742169569375851309 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.326324068042719381064770267005646376622180278167022237057742169569375851309
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.6704523523419252987390041350324669870440067393424708897840655648251369267784
Short name T1122
Test name
Test status
Simulation time 236313385 ps
CPU time 3.87 seconds
Started Nov 22 02:22:06 PM PST 23
Finished Nov 22 02:22:15 PM PST 23
Peak memory 225512 kb
Host smart-2b2be54d-685e-46aa-a7fd-36c4a372951f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6704523523419252987390041350324669870440067393424708897840655648251369267784 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.6704523523419252987390041350324669870440067393424708897840655648251369267784
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.76135114900550154024283522024133556431854776941031108117226411250792038025620
Short name T754
Test name
Test status
Simulation time 7918519784 ps
CPU time 201.44 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:25:34 PM PST 23
Peak memory 1310920 kb
Host smart-9bd7ffcd-57c5-46e1-b4ee-2a2bdaaf4784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76135114900550154024283522024133556431854776941031108117226411250792038025620 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.i2c_host_fifo_watermark.76135114900550154024283522024133556431854776941031108117226411250792038025620
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.57027763506568806923898654073177863511401323686729036240060849876336782686823
Short name T882
Test name
Test status
Simulation time 3754070957 ps
CPU time 55.21 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:23:03 PM PST 23
Peak memory 293788 kb
Host smart-3df19f7f-5252-4c11-9996-1fa6799a4551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57027763506568806923898654073177863511401323686729036240060849876336782686823 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_host_mode_toggle.57027763506568806923898654073177863511401323686729036240060849876336782686823
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.8920420516721664063379642862489010755354346893859648170652814935098038265488
Short name T1107
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 202840 kb
Host smart-ee9c9a99-0111-4111-868d-b1e382dd2d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8920420516721664063379642862489010755354346893859648170652814935098038265488 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_host_override.8920420516721664063379642862489010755354346893859648170652814935098038265488
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.12399437359974816102861362068058734930744625235880792139334932535245935927112
Short name T1429
Test name
Test status
Simulation time 6830796343 ps
CPU time 59.66 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:23:05 PM PST 23
Peak memory 211272 kb
Host smart-81b947f3-1888-4948-8256-19c3baa681c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12399437359974816102861362068058734930744625235880792139334932535245935927112 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.i2c_host_perf.12399437359974816102861362068058734930744625235880792139334932535245935927112
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_rx_oversample.79443374600233188443360141417264790278654529287842237457800486811154628609372
Short name T693
Test name
Test status
Simulation time 3939158762 ps
CPU time 96.58 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:23:49 PM PST 23
Peak memory 345960 kb
Host smart-524c8d1b-f8d5-4d73-bef2-2d0a66ca6dbb
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79443374600233188443360141417264790278654529287842237457800486811154628609372 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_rx_oversample.79443374600233188443360141417264790278654529287842237457800486811154628609372
Directory /workspace/26.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.98010444862106922804263449295872457867771439084991451747480421090419232521354
Short name T1036
Test name
Test status
Simulation time 2343171530 ps
CPU time 38.48 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:22:44 PM PST 23
Peak memory 299288 kb
Host smart-c439d6b3-2ae0-4f03-83ce-9897891ab53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98010444862106922804263449295872457867771439084991451747480421090419232521354 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.i2c_host_smoke.98010444862106922804263449295872457867771439084991451747480421090419232521354
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.22523355689580408400011323289793269037334276672515201758610024968852872554847
Short name T1522
Test name
Test status
Simulation time 32807463528 ps
CPU time 1058.76 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:39:45 PM PST 23
Peak memory 1957052 kb
Host smart-1b5482bb-3aa0-442e-8705-eeaa0ace738f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22523355689580408400011323289793269037334276672515201758610024968852872554847 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_host_stress_all.22523355689580408400011323289793269037334276672515201758610024968852872554847
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.62261452088125215991660481115060715906677557912193788910333066573813531276367
Short name T1399
Test name
Test status
Simulation time 1466624971 ps
CPU time 12.97 seconds
Started Nov 22 02:22:16 PM PST 23
Finished Nov 22 02:22:30 PM PST 23
Peak memory 214040 kb
Host smart-63efa3cc-5718-4b34-8e20-dd739131dcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62261452088125215991660481115060715906677557912193788910333066573813531276367 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_host_stretch_timeout.62261452088125215991660481115060715906677557912193788910333066573813531276367
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.92845063515446074990877844947109438587576531450412749218005244841897563353098
Short name T1458
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.77 seconds
Started Nov 22 02:22:11 PM PST 23
Finished Nov 22 02:22:18 PM PST 23
Peak memory 203024 kb
Host smart-1841c9de-2ae5-4f91-83e1-e0f1f24e9406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9284506351544607499087784494710
9438587576531450412749218005244841897563353098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.92845063515446074990877844
947109438587576531450412749218005244841897563353098
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3358820362425553676392418608111247840013541872826165726449394084358349563668
Short name T268
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.14 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:44 PM PST 23
Peak memory 382244 kb
Host smart-d56a41d5-46a4-4a85-91ed-9f3745a55ef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335882036242555367639241860811124784001354187282616
5726449394084358349563668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.33588203624255536763924186081112
47840013541872826165726449394084358349563668
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.51076653636525792702558784056876973367407812991921956864910442897435483862148
Short name T1455
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.89 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:22:41 PM PST 23
Peak memory 462120 kb
Host smart-09dc6234-1a2a-460f-8e57-e5f52d05aaff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510766536365257927025587840568769733674078129919219
56864910442897435483862148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_tx.510766536365257927025587840568769
73367407812991921956864910442897435483862148
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.39858749445042220687256648648729894896679480341115697819380847003629800923646
Short name T976
Test name
Test status
Simulation time 825344371 ps
CPU time 2.47 seconds
Started Nov 22 02:22:12 PM PST 23
Finished Nov 22 02:22:17 PM PST 23
Peak memory 202664 kb
Host smart-067d9aa0-769b-487d-8b3a-79aa33b47f3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398587494450422206872566486487298948966794803411156
97819380847003629800923646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_hrst.398587494450422206872566486487298948966794803411156
97819380847003629800923646
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.56108481221496308473095025044985376255655357776396380878610330909410298178323
Short name T1354
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.1 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:22:12 PM PST 23
Peak memory 203560 kb
Host smart-2b451543-7fa9-4794-9de4-aa19eb0e0ada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56108481221496308473095025044985376255655357776396
380878610330909410298178323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_smoke.5610848122149630847309502504498537625565535
7776396380878610330909410298178323
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.950128717266350237985541855388022541786228153115416961176784698852435834581
Short name T1048
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.51 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:22:27 PM PST 23
Peak memory 639112 kb
Host smart-e40b0a0e-595b-4d7e-98df-de162a05bc48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95012871726635023798554185538802254178
6228153115416961176784698852435834581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.9501287172663502379855418
55388022541786228153115416961176784698852435834581
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.104195415284236005306390913187312683492061165898433978278875723682890391040717
Short name T703
Test name
Test status
Simulation time 834576440 ps
CPU time 2.99 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:16 PM PST 23
Peak memory 203068 kb
Host smart-89a7ce60-c2da-48af-9f97-b4b14b7b1f16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104195415284236005306390913187312683492061165898433
978278875723682890391040717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_perf.10419541528423600530639091318731268349206116589843
3978278875723682890391040717
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.34015992085249526376351211416255807131176783730265359381134077106354704178938
Short name T687
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.35 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:22:16 PM PST 23
Peak memory 202976 kb
Host smart-0d6a2b79-3fad-498b-9c31-98650021d253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401599208524952637635121141625580713117678373026535938113407710635470
4178938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smoke.34015992085249526376351211416255807131176783730265359381134077106354704178938
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.38682924175669824350870121134561229671098083204165194226413295049977699801278
Short name T1190
Test name
Test status
Simulation time 66540157934 ps
CPU time 1708.86 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:50:37 PM PST 23
Peak memory 6983436 kb
Host smart-9766398f-3027-4bb4-b920-bc0af6f11b6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38682924175669824350870121134561229671098083204165
194226413295049977699801278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_all.38682924175669824350870121134561229671
098083204165194226413295049977699801278
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.14372000131267624284850553151909323487812331937484947616357427808734100329118
Short name T970
Test name
Test status
Simulation time 997771563 ps
CPU time 8.68 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:22 PM PST 23
Peak memory 202840 kb
Host smart-fa1caf8b-b772-4366-a606-499de60e954f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437200013126762428485055315190932348781233193748494761635742780873410
0329118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_rd.143720001312676242848505531519093234878123319374849476163574
27808734100329118
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.71554227133516310418950512784919220602375096151186832345726317688026676536217
Short name T594
Test name
Test status
Simulation time 14461449567 ps
CPU time 80.45 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:23:26 PM PST 23
Peak memory 1542148 kb
Host smart-692fc98a-eeb0-4351-bfa6-d53a05ecf5fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7155422713351631041895051278491922060237509615118683234572631768802667
6536217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_wr.715542271335163104189505127849192206023750961511868323457263
17688026676536217
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.87242510360834022032183310295960352826663536732922542429454242554661068240750
Short name T1424
Test name
Test status
Simulation time 6281818576 ps
CPU time 76.38 seconds
Started Nov 22 02:22:01 PM PST 23
Finished Nov 22 02:23:22 PM PST 23
Peak memory 930468 kb
Host smart-b5b50d85-ed71-4f87-8bf9-68519ed3ffc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8724251036083402203218331029596035282666353673292254242945424255466106
8240750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stretch.8724251036083402203218331029596035282666353673292254242945424255
4661068240750
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.53235598811490476792311385510071388517522614224362375922322694300884783234289
Short name T600
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.57 seconds
Started Nov 22 02:22:02 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 212600 kb
Host smart-49ee8031-5cdb-44bb-acc2-f44481a15bf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532355988114904767923113855100713885175226142243623
75922322694300884783234289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_timeout.532355988114904767923113855100713885175226142
24362375922322694300884783234289
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.57976988263762909723477017397294648243603055344204756995582515151990664848686
Short name T196
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.5 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:16 PM PST 23
Peak memory 205364 kb
Host smart-274e7e65-8d94-48f5-9c00-6bbeaf804b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579769882637629097234770173972946482436030553442047
56995582515151990664848686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_unexp_stop.57976988263762909723477017397294648243603
055344204756995582515151990664848686
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.40636351210707345146625200910229977898208317475106745758792728000611156342352
Short name T1243
Test name
Test status
Simulation time 19975830 ps
CPU time 0.56 seconds
Started Nov 22 02:22:20 PM PST 23
Finished Nov 22 02:22:29 PM PST 23
Peak memory 202588 kb
Host smart-7ced0520-7bd3-48df-abd5-5345014012e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40636351210707345146625200910229977898208317475106745758792728000611156342352 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_alert_test.40636351210707345146625200910229977898208317475106745758792728000611156342352
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.74691416073039198810109649616389942980483184000134122761343152861276264096574
Short name T914
Test name
Test status
Simulation time 74225396 ps
CPU time 1.35 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:12 PM PST 23
Peak memory 211304 kb
Host smart-93a9134b-9412-460f-baec-e062bad7cff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74691416073039198810109649616389942980483184000134122761343152861276264096574 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_host_error_intr.74691416073039198810109649616389942980483184000134122761343152861276264096574
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.18764791375180138595428495476571081343901528548400696955406931356505271264365
Short name T1540
Test name
Test status
Simulation time 606667565 ps
CPU time 6.72 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:20 PM PST 23
Peak memory 273376 kb
Host smart-f228b721-58ca-4b60-89d5-580c80dbd549
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18764791375180138595428495476571081343901528548400696955406931356505271264365 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.18764791375180138595428495476571081343901528548400696955406931356505271264365
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.98695816187851913182061312543015128106750868404265513773589765274038853312660
Short name T14
Test name
Test status
Simulation time 3768267272 ps
CPU time 76.74 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:23:27 PM PST 23
Peak memory 729452 kb
Host smart-9548fb46-a139-4705-8300-dafe78e7e202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98695816187851913182061312543015128106750868404265513773589765274038853312660 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_host_fifo_full.98695816187851913182061312543015128106750868404265513773589765274038853312660
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.109957039615885330551928076137138132634779476559098605441966547669736486388687
Short name T872
Test name
Test status
Simulation time 7925734012 ps
CPU time 216.24 seconds
Started Nov 22 02:22:16 PM PST 23
Finished Nov 22 02:25:54 PM PST 23
Peak memory 1271432 kb
Host smart-f73179f3-7e35-4072-a0a1-eadec27079d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109957039615885330551928076137138132634779476559098605441966547669736486388687 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_host_fifo_overflow.109957039615885330551928076137138132634779476559098605441966547669736486388687
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.23572898111316563024213017789380875519836167447857685148482492202820480585660
Short name T772
Test name
Test status
Simulation time 209010032 ps
CPU time 0.92 seconds
Started Nov 22 02:22:16 PM PST 23
Finished Nov 22 02:22:18 PM PST 23
Peak memory 202784 kb
Host smart-f90e70e4-f494-40ca-98dc-912079856b85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23572898111316563024213017789380875519836167447857685148482492202820480585660 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.23572898111316563024213017789380875519836167447857685148482492202820480585660
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.35653650009191057374869588196024417703432503619579062668153780893814926504215
Short name T322
Test name
Test status
Simulation time 236313385 ps
CPU time 3.72 seconds
Started Nov 22 02:22:12 PM PST 23
Finished Nov 22 02:22:18 PM PST 23
Peak memory 225416 kb
Host smart-52eaaff8-583f-40eb-b96c-beca768f557a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35653650009191057374869588196024417703432503619579062668153780893814926504215 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.35653650009191057374869588196024417703432503619579062668153780893814926504215
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.16925946472332144391703389647123740038240007833511818158643710491060265797182
Short name T786
Test name
Test status
Simulation time 7918519784 ps
CPU time 227.37 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:26:00 PM PST 23
Peak memory 1310884 kb
Host smart-2ad44152-c40c-4f21-a070-d588b4c5b0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16925946472332144391703389647123740038240007833511818158643710491060265797182 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_host_fifo_watermark.16925946472332144391703389647123740038240007833511818158643710491060265797182
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.10778401251223827079141632792048805628444283095094506484021733033872494749174
Short name T461
Test name
Test status
Simulation time 3754070957 ps
CPU time 55.62 seconds
Started Nov 22 02:22:10 PM PST 23
Finished Nov 22 02:23:09 PM PST 23
Peak memory 293716 kb
Host smart-4cfb1b91-4435-4a1a-9609-3559e7bdf991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10778401251223827079141632792048805628444283095094506484021733033872494749174 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_host_mode_toggle.10778401251223827079141632792048805628444283095094506484021733033872494749174
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.80266742204655523529109949239437783108538091497333976753651488561435996215493
Short name T1169
Test name
Test status
Simulation time 23672229 ps
CPU time 0.65 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:22:07 PM PST 23
Peak memory 202884 kb
Host smart-ee8f9541-b3ec-4490-a185-1e0439ad0798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80266742204655523529109949239437783108538091497333976753651488561435996215493 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_host_override.80266742204655523529109949239437783108538091497333976753651488561435996215493
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.111933959427669384373462714861973035964749727975253073880833951954010610437955
Short name T1238
Test name
Test status
Simulation time 6830796343 ps
CPU time 57.53 seconds
Started Nov 22 02:22:10 PM PST 23
Finished Nov 22 02:23:11 PM PST 23
Peak memory 211144 kb
Host smart-cc507839-9f54-474e-9815-7738b38f68f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111933959427669384373462714861973035964749727975253073880833951954010610437955 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.i2c_host_perf.111933959427669384373462714861973035964749727975253073880833951954010610437955
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_rx_oversample.86891773596136355557684871540715350342696148075034441451453433160860154197516
Short name T738
Test name
Test status
Simulation time 3939158762 ps
CPU time 112.05 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:23:58 PM PST 23
Peak memory 345972 kb
Host smart-2af97be5-8835-4eea-a837-94a399d6f21f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86891773596136355557684871540715350342696148075034441451453433160860154197516 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_rx_oversample.86891773596136355557684871540715350342696148075034441451453433160860154197516
Directory /workspace/27.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.109687337222973860234310263074301738617967760975588105407199056388326027682624
Short name T1526
Test name
Test status
Simulation time 2343171530 ps
CPU time 36.45 seconds
Started Nov 22 02:22:03 PM PST 23
Finished Nov 22 02:22:42 PM PST 23
Peak memory 299384 kb
Host smart-46d34a33-cb1d-460e-adac-a2330eee3a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109687337222973860234310263074301738617967760975588105407199056388326027682624 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.i2c_host_smoke.109687337222973860234310263074301738617967760975588105407199056388326027682624
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.2592789789824197473525210010000463726413541667486913843267239526210720314559
Short name T1549
Test name
Test status
Simulation time 32807463528 ps
CPU time 1039.26 seconds
Started Nov 22 02:22:11 PM PST 23
Finished Nov 22 02:39:33 PM PST 23
Peak memory 1957188 kb
Host smart-d6f64e65-8258-4ffd-89b7-2dbc8ad341b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592789789824197473525210010000463726413541667486913843267239526210720314559 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_host_stress_all.2592789789824197473525210010000463726413541667486913843267239526210720314559
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.30902452356221979168145590467244677209916963881181898008909980007494160059953
Short name T1321
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.54 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:26 PM PST 23
Peak memory 214236 kb
Host smart-58af6400-3953-46e6-abdb-35e6fbd96869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30902452356221979168145590467244677209916963881181898008909980007494160059953 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_host_stretch_timeout.30902452356221979168145590467244677209916963881181898008909980007494160059953
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.45241907002080327702581332057435817941400807259498495047805917649568161723070
Short name T224
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.92 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:15 PM PST 23
Peak memory 203020 kb
Host smart-001b476b-e050-485d-8bd8-530f36ad34ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4524190700208032770258133205743
5817941400807259498495047805917649568161723070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.45241907002080327702581332
057435817941400807259498495047805917649568161723070
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.85219985468189377332976189975607434116784387363347143221128309022282703561443
Short name T208
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.86 seconds
Started Nov 22 02:22:17 PM PST 23
Finished Nov 22 02:22:51 PM PST 23
Peak memory 382200 kb
Host smart-6357d682-d4f5-4078-9ea0-223ca86a0d48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852199854681893773329761899756074341167843873633471
43221128309022282703561443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.8521998546818937733297618997560
7434116784387363347143221128309022282703561443
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.32273194448210521655658846299561981184798623068494015416630220017206225011825
Short name T929
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.71 seconds
Started Nov 22 02:22:10 PM PST 23
Finished Nov 22 02:22:48 PM PST 23
Peak memory 462060 kb
Host smart-b8c2822f-ee26-4c41-8364-133280d8f008
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322731944482105216556588462995619811847986230684940
15416630220017206225011825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_tx.322731944482105216556588462995619
81184798623068494015416630220017206225011825
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.55136905557446246567651040892357107611759181328610111865735946731544369433149
Short name T805
Test name
Test status
Simulation time 825344371 ps
CPU time 2.41 seconds
Started Nov 22 02:22:09 PM PST 23
Finished Nov 22 02:22:16 PM PST 23
Peak memory 203056 kb
Host smart-06d6f6af-768e-45c3-8467-3f07c3056aa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551369055574462465676510408923571076117591813286101
11865735946731544369433149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_hrst.551369055574462465676510408923571076117591813286101
11865735946731544369433149
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.98318268867943218935841289046502926045211394867333810808565567307895994871126
Short name T1291
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.07 seconds
Started Nov 22 02:22:17 PM PST 23
Finished Nov 22 02:22:23 PM PST 23
Peak memory 203696 kb
Host smart-20e3ef24-2cdb-4249-91ff-702fc467c36f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98318268867943218935841289046502926045211394867333
810808565567307895994871126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_smoke.9831826886794321893584128904650292604521139
4867333810808565567307895994871126
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.102770596093561933955003825302503530531675682109117180344315579017277455560426
Short name T819
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.39 seconds
Started Nov 22 02:22:20 PM PST 23
Finished Nov 22 02:22:48 PM PST 23
Peak memory 639096 kb
Host smart-0db1960e-bddd-48fa-8c8b-e1f7e8a7be00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10277059609356193395500382530250353053
1675682109117180344315579017277455560426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1027705960935619339550
03825302503530531675682109117180344315579017277455560426
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.90338012672697796433208070469737920949897156602100627407466401745843979868295
Short name T1420
Test name
Test status
Simulation time 834576440 ps
CPU time 3.08 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:16 PM PST 23
Peak memory 202980 kb
Host smart-f88597d9-5eec-4b60-9858-da06787b1dd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903380126726977964332080704697379209498971566021006
27407466401745843979868295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_perf.903380126726977964332080704697379209498971566021006
27407466401745843979868295
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.39990311665431620799562882578023745747644647950019560647972110565398778141562
Short name T915
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.34 seconds
Started Nov 22 02:22:04 PM PST 23
Finished Nov 22 02:22:19 PM PST 23
Peak memory 202964 kb
Host smart-e5f221e1-bdb8-4577-8e94-f67fcaf5df9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999031166543162079956288257802374574764464795001956064797211056539877
8141562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smoke.39990311665431620799562882578023745747644647950019560647972110565398778141562
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.45007394303642421013549584487838341953088720235507720599808819205609887130273
Short name T499
Test name
Test status
Simulation time 66540157934 ps
CPU time 1300.63 seconds
Started Nov 22 02:22:20 PM PST 23
Finished Nov 22 02:44:10 PM PST 23
Peak memory 6983272 kb
Host smart-5f72b099-4213-4690-9ecf-bbc2a745ff5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45007394303642421013549584487838341953088720235507
720599808819205609887130273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_all.45007394303642421013549584487838341953
088720235507720599808819205609887130273
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.105224491593915466095627114568910720850744176850725343638545585030496536570656
Short name T1202
Test name
Test status
Simulation time 997771563 ps
CPU time 8.6 seconds
Started Nov 22 02:22:16 PM PST 23
Finished Nov 22 02:22:26 PM PST 23
Peak memory 203012 kb
Host smart-0431517a-1b8a-4ee4-8245-2da33c2073c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052244915939154660956271145689107208507441768507253436385455850304965
36570656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_rd.10522449159391546609562711456891072085074417685072534363854
5585030496536570656
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.36048521240125285416721183207280113100657816137066554198262892690681535825954
Short name T243
Test name
Test status
Simulation time 14461449567 ps
CPU time 86.79 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:23:38 PM PST 23
Peak memory 1542140 kb
Host smart-129727f5-0c69-44d0-84f1-4ba1c7007ea0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604852124012528541672118320728011310065781613706655419826289269068153
5825954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_wr.360485212401252854167211832072801131006578161370665541982628
92690681535825954
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.101428156036784892789695887924557874015290476881076680626487308224337823185044
Short name T346
Test name
Test status
Simulation time 6281818576 ps
CPU time 76.7 seconds
Started Nov 22 02:22:17 PM PST 23
Finished Nov 22 02:23:36 PM PST 23
Peak memory 930556 kb
Host smart-63bb5a9d-8639-4317-8513-527adfa3cc76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014281560367848927896958879245578740152904768810766806264873082243378
23185044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stretch.101428156036784892789695887924557874015290476881076680626487308
224337823185044
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.111032405404024136825041698863963042108989427408843025784666069945756023433601
Short name T1062
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.58 seconds
Started Nov 22 02:22:05 PM PST 23
Finished Nov 22 02:22:18 PM PST 23
Peak memory 212604 kb
Host smart-38c0c60d-5298-4cfb-8b64-668662fcaa4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111032405404024136825041698863963042108989427408843
025784666069945756023433601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_timeout.11103240540402413682504169886396304210898942
7408843025784666069945756023433601
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_ovf.49941129924215866182761613323156672738461761281973455284730058849296263512029
Short name T442
Test name
Test status
Simulation time 5445414553 ps
CPU time 126.19 seconds
Started Nov 22 02:22:12 PM PST 23
Finished Nov 22 02:24:20 PM PST 23
Peak memory 406664 kb
Host smart-0cae5215-0dd6-4583-b5a5-d0f6beffb2bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49941129924215866182761613323156672738461761281973
455284730058849296263512029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_tx_ovf.4994112992421586618276161332315667273846176128
1973455284730058849296263512029
Directory /workspace/27.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.97235750816464285161472826384491208733335325427583716739470087401657303092087
Short name T707
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.6 seconds
Started Nov 22 02:22:20 PM PST 23
Finished Nov 22 02:22:34 PM PST 23
Peak memory 205196 kb
Host smart-49a001f8-11e9-4876-8032-d296e641d9af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972357508164642851614728263844912087333353254275837
16739470087401657303092087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_unexp_stop.97235750816464285161472826384491208733335
325427583716739470087401657303092087
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/28.i2c_alert_test.59821396321098247134657244409709333739688698761414032543821364771460606083214
Short name T157
Test name
Test status
Simulation time 19975830 ps
CPU time 0.59 seconds
Started Nov 22 02:23:01 PM PST 23
Finished Nov 22 02:23:03 PM PST 23
Peak memory 202700 kb
Host smart-ff2be078-fa58-438f-b2f0-56c3c783223f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59821396321098247134657244409709333739688698761414032543821364771460606083214 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_alert_test.59821396321098247134657244409709333739688698761414032543821364771460606083214
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.71727541317364342051838145944574869057770052588883687791660758148900785980138
Short name T565
Test name
Test status
Simulation time 74225396 ps
CPU time 1.4 seconds
Started Nov 22 02:22:07 PM PST 23
Finished Nov 22 02:22:14 PM PST 23
Peak memory 211392 kb
Host smart-c1acccac-fd19-4e66-8dc9-eea7e97db1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71727541317364342051838145944574869057770052588883687791660758148900785980138 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_host_error_intr.71727541317364342051838145944574869057770052588883687791660758148900785980138
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.115113851596070590272194947684694048980362167268020719749578614425133644835982
Short name T1194
Test name
Test status
Simulation time 606667565 ps
CPU time 6.54 seconds
Started Nov 22 02:22:12 PM PST 23
Finished Nov 22 02:22:21 PM PST 23
Peak memory 273124 kb
Host smart-352bb425-8df4-41cb-9653-05dee718e642
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115113851596070590272194947684694048980362167268020719749578614425133644835982 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.115113851596070590272194947684694048980362167268020719749578614425133644835982
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.46224082484153244313423286035387901947623326489844677196445447009888966542421
Short name T823
Test name
Test status
Simulation time 3768267272 ps
CPU time 70.32 seconds
Started Nov 22 02:22:13 PM PST 23
Finished Nov 22 02:23:26 PM PST 23
Peak memory 729580 kb
Host smart-114b0864-6bc7-470e-a9df-8210ad045b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46224082484153244313423286035387901947623326489844677196445447009888966542421 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_host_fifo_full.46224082484153244313423286035387901947623326489844677196445447009888966542421
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.26841106216215255096198548685211484312075070174391472164908151868138797649378
Short name T741
Test name
Test status
Simulation time 7925734012 ps
CPU time 212.85 seconds
Started Nov 22 02:22:11 PM PST 23
Finished Nov 22 02:25:46 PM PST 23
Peak memory 1271300 kb
Host smart-a870ffae-b28e-4994-b756-f594b3369914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26841106216215255096198548685211484312075070174391472164908151868138797649378 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.i2c_host_fifo_overflow.26841106216215255096198548685211484312075070174391472164908151868138797649378
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.98361652495325638481317905083950565159557779682677385282712509929512234894526
Short name T301
Test name
Test status
Simulation time 209010032 ps
CPU time 0.91 seconds
Started Nov 22 02:22:22 PM PST 23
Finished Nov 22 02:22:30 PM PST 23
Peak memory 202832 kb
Host smart-4b02f72e-c7e9-4b08-9e8e-9140a9291970
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98361652495325638481317905083950565159557779682677385282712509929512234894526 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.98361652495325638481317905083950565159557779682677385282712509929512234894526
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.27218449534952285346809925395537642479864347308945060719245613146172084028246
Short name T1065
Test name
Test status
Simulation time 236313385 ps
CPU time 3.65 seconds
Started Nov 22 02:22:22 PM PST 23
Finished Nov 22 02:22:32 PM PST 23
Peak memory 225424 kb
Host smart-d44c5e24-a54e-47e0-a86d-afccea2af706
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27218449534952285346809925395537642479864347308945060719245613146172084028246 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.27218449534952285346809925395537642479864347308945060719245613146172084028246
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.24779856512774381790487421622733443643976994392835809936071002446508314642379
Short name T869
Test name
Test status
Simulation time 7918519784 ps
CPU time 217.22 seconds
Started Nov 22 02:22:23 PM PST 23
Finished Nov 22 02:26:06 PM PST 23
Peak memory 1310896 kb
Host smart-d569f0a7-924c-4754-bb3f-e2d75a2c30d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24779856512774381790487421622733443643976994392835809936071002446508314642379 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_host_fifo_watermark.24779856512774381790487421622733443643976994392835809936071002446508314642379
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.96423512701290692767321871285419299018737896248694927427893304944309792698715
Short name T1233
Test name
Test status
Simulation time 3754070957 ps
CPU time 57.63 seconds
Started Nov 22 02:22:26 PM PST 23
Finished Nov 22 02:23:29 PM PST 23
Peak memory 293720 kb
Host smart-435bc7ed-289e-418e-9e13-e01a2e63ce0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96423512701290692767321871285419299018737896248694927427893304944309792698715 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_host_mode_toggle.96423512701290692767321871285419299018737896248694927427893304944309792698715
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.103290840713861111820314970931684020987023322473714667280368859737864970219778
Short name T762
Test name
Test status
Simulation time 23672229 ps
CPU time 0.61 seconds
Started Nov 22 02:22:21 PM PST 23
Finished Nov 22 02:22:29 PM PST 23
Peak memory 202700 kb
Host smart-9fb2b12a-6903-4e18-aefd-60f78e9400f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103290840713861111820314970931684020987023322473714667280368859737864970219778 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_host_override.103290840713861111820314970931684020987023322473714667280368859737864970219778
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.3490235867096734017092628369640008370767089840977300185329081421934493215856
Short name T361
Test name
Test status
Simulation time 6830796343 ps
CPU time 58.53 seconds
Started Nov 22 02:22:22 PM PST 23
Finished Nov 22 02:23:27 PM PST 23
Peak memory 211256 kb
Host smart-2c312173-01ec-402c-bdf2-e5fc52a15ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490235867096734017092628369640008370767089840977300185329081421934493215856 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.i2c_host_perf.3490235867096734017092628369640008370767089840977300185329081421934493215856
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_rx_oversample.79692426238195938737009635649732259199718268876095329576850781819301331133932
Short name T956
Test name
Test status
Simulation time 3939158762 ps
CPU time 84.92 seconds
Started Nov 22 02:22:21 PM PST 23
Finished Nov 22 02:23:54 PM PST 23
Peak memory 345788 kb
Host smart-056053b2-60f1-49ac-8efc-75cb5babb147
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79692426238195938737009635649732259199718268876095329576850781819301331133932 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_rx_oversample.79692426238195938737009635649732259199718268876095329576850781819301331133932
Directory /workspace/28.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.15376336865330956941900864953734028474263792580778498865143828154842356692801
Short name T1340
Test name
Test status
Simulation time 2343171530 ps
CPU time 38.44 seconds
Started Nov 22 02:22:09 PM PST 23
Finished Nov 22 02:22:52 PM PST 23
Peak memory 299432 kb
Host smart-3bc389c4-7cf7-483b-8e77-101d13160d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15376336865330956941900864953734028474263792580778498865143828154842356692801 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.i2c_host_smoke.15376336865330956941900864953734028474263792580778498865143828154842356692801
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.22667282572032581710700299818595430412682739749084238683919267970782458951075
Short name T1206
Test name
Test status
Simulation time 32807463528 ps
CPU time 1030.97 seconds
Started Nov 22 02:22:09 PM PST 23
Finished Nov 22 02:39:24 PM PST 23
Peak memory 1957112 kb
Host smart-694c4925-3349-4e2b-8ad6-8817418612a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22667282572032581710700299818595430412682739749084238683919267970782458951075 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_host_stress_all.22667282572032581710700299818595430412682739749084238683919267970782458951075
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3379015970844456496447718338517962063305108916083999810843086420195471155304
Short name T512
Test name
Test status
Simulation time 1466624971 ps
CPU time 12.75 seconds
Started Nov 22 02:22:22 PM PST 23
Finished Nov 22 02:22:41 PM PST 23
Peak memory 214116 kb
Host smart-c72952ce-93f8-43c7-9024-a647353d1625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379015970844456496447718338517962063305108916083999810843086420195471155304 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_host_stretch_timeout.3379015970844456496447718338517962063305108916083999810843086420195471155304
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.79651428913504097255636671351600550360455962401034355205655668063180428993492
Short name T62
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.79 seconds
Started Nov 22 02:22:22 PM PST 23
Finished Nov 22 02:22:33 PM PST 23
Peak memory 203004 kb
Host smart-904da084-0a02-4c85-850e-da1db0ec323a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7965142891350409725563667135160
0550360455962401034355205655668063180428993492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.79651428913504097255636671
351600550360455962401034355205655668063180428993492
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.103980484235353059440348684158636309450284611913212326007238618538651701580615
Short name T1334
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.19 seconds
Started Nov 22 02:22:21 PM PST 23
Finished Nov 22 02:23:00 PM PST 23
Peak memory 382160 kb
Host smart-f5e2597d-d44e-40ad-b4f0-eb57433a883f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103980484235353059440348684158636309450284611913212
326007238618538651701580615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.103980484235353059440348684158
636309450284611913212326007238618538651701580615
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.70656244146651419576411124702498453411641754980527971650906901351605834153487
Short name T400
Test name
Test status
Simulation time 10065199023 ps
CPU time 37.08 seconds
Started Nov 22 02:22:09 PM PST 23
Finished Nov 22 02:22:50 PM PST 23
Peak memory 461832 kb
Host smart-8fae4fe8-6738-4b99-8505-c91b92435899
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706562441466514195764111247024984534116417549805279
71650906901351605834153487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_tx.706562441466514195764111247024984
53411641754980527971650906901351605834153487
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.32770506688582147305329116104117030894745002905232282772204084719321582659725
Short name T1232
Test name
Test status
Simulation time 825344371 ps
CPU time 2.4 seconds
Started Nov 22 02:22:12 PM PST 23
Finished Nov 22 02:22:17 PM PST 23
Peak memory 203152 kb
Host smart-1f74f24e-ec4f-41c1-9fde-629151225494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327705066885821473053291161041170308947450029052322
82772204084719321582659725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_hrst.327705066885821473053291161041170308947450029052322
82772204084719321582659725
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.6460167475884022759562431418985590979718669442545081443385918359300118679682
Short name T49
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.21 seconds
Started Nov 22 02:22:09 PM PST 23
Finished Nov 22 02:22:17 PM PST 23
Peak memory 203432 kb
Host smart-d524ae27-b795-4dfc-9d49-a6ecd9506204
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64601674758840227595624314189855909797186694425450
81443385918359300118679682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_smoke.64601674758840227595624314189855909797186694
42545081443385918359300118679682
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.54319848178746969576523874195842916745377647247304496408355597863762747426217
Short name T527
Test name
Test status
Simulation time 5106060125 ps
CPU time 20.35 seconds
Started Nov 22 02:22:21 PM PST 23
Finished Nov 22 02:22:49 PM PST 23
Peak memory 638276 kb
Host smart-5342f92b-7934-4506-a5a6-d94bb724dea5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54319848178746969576523874195842916745
377647247304496408355597863762747426217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.54319848178746969576523
874195842916745377647247304496408355597863762747426217
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.11137810455750411040778627959618974005047962625228275755073941719360738155069
Short name T166
Test name
Test status
Simulation time 834576440 ps
CPU time 2.93 seconds
Started Nov 22 02:22:12 PM PST 23
Finished Nov 22 02:22:18 PM PST 23
Peak memory 203140 kb
Host smart-4e12e45c-ea4c-4b77-973f-f287dd22f5ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111378104557504110407786279596189740050479626252282
75755073941719360738155069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_perf.111378104557504110407786279596189740050479626252282
75755073941719360738155069
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.98703879298298712331417174411342192045746463094644315617377907415161458469308
Short name T379
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.39 seconds
Started Nov 22 02:22:08 PM PST 23
Finished Nov 22 02:22:23 PM PST 23
Peak memory 203000 kb
Host smart-e091b1bc-036a-410e-8c8d-de35e372c133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9870387929829871233141717441134219204574646309464431561737790741516145
8469308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smoke.98703879298298712331417174411342192045746463094644315617377907415161458469308
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.41453163699436346404660968354193258094997946446642840560837558077608703628297
Short name T572
Test name
Test status
Simulation time 66540157934 ps
CPU time 1914.29 seconds
Started Nov 22 02:22:10 PM PST 23
Finished Nov 22 02:54:08 PM PST 23
Peak memory 6983120 kb
Host smart-16711e64-74e2-479b-8b11-b80a0ea67ed6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41453163699436346404660968354193258094997946446642
840560837558077608703628297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_all.41453163699436346404660968354193258094
997946446642840560837558077608703628297
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.64939774660497633903259719125892002725013673704699502488854489564900295700497
Short name T1145
Test name
Test status
Simulation time 997771563 ps
CPU time 8.84 seconds
Started Nov 22 02:22:13 PM PST 23
Finished Nov 22 02:22:24 PM PST 23
Peak memory 203144 kb
Host smart-aec30246-04ce-4459-906b-d1989ea4fac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6493977466049763390325971912589200272501367370469950248885448956490029
5700497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_rd.649397746604976339032597191258920027250136737046995024888544
89564900295700497
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.65865226717039271250274878526655238877559580507578760910112956002561863994268
Short name T1248
Test name
Test status
Simulation time 14461449567 ps
CPU time 91.49 seconds
Started Nov 22 02:22:19 PM PST 23
Finished Nov 22 02:23:57 PM PST 23
Peak memory 1541976 kb
Host smart-5cbf90c9-5cab-493d-bfab-9269583dce0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6586522671703927125027487852665523887755958050757876091011295600256186
3994268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_wr.658652267170392712502748785266552388775595805075787609101129
56002561863994268
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.115763081720702152564747632780831955210205481213700987511392756772072093398619
Short name T679
Test name
Test status
Simulation time 6281818576 ps
CPU time 76.39 seconds
Started Nov 22 02:22:23 PM PST 23
Finished Nov 22 02:23:45 PM PST 23
Peak memory 930484 kb
Host smart-d36552aa-30c3-4506-98f4-1373a8cb74df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157630817207021525647476327808319552102054812137009875113927567720720
93398619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stretch.115763081720702152564747632780831955210205481213700987511392756
772072093398619
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.6416275793209138080631236356643128963015836044215109980791428164005070992485
Short name T595
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.38 seconds
Started Nov 22 02:22:13 PM PST 23
Finished Nov 22 02:22:23 PM PST 23
Peak memory 212748 kb
Host smart-1275ca51-b250-407f-aaf4-2c2984da5be6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641627579320913808063123635664312896301583604421510
9980791428164005070992485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_timeout.6416275793209138080631236356643128963015836044
215109980791428164005070992485
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_ovf.105081455188120913980716871666109725065955717510777539597368130184977452248728
Short name T366
Test name
Test status
Simulation time 5445414553 ps
CPU time 113.25 seconds
Started Nov 22 02:22:21 PM PST 23
Finished Nov 22 02:24:22 PM PST 23
Peak memory 406756 kb
Host smart-4f876db9-f1bc-45fe-88dd-277dbd9ffbc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10508145518812091398071687166610972506595571751077
7539597368130184977452248728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_tx_ovf.105081455188120913980716871666109725065955717
510777539597368130184977452248728
Directory /workspace/28.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.98410524668694113704165214316167565040697477155455099211471444993077319294853
Short name T237
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.41 seconds
Started Nov 22 02:22:22 PM PST 23
Finished Nov 22 02:22:34 PM PST 23
Peak memory 205264 kb
Host smart-f98282c1-d844-459b-ba4d-cfcf359355d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984105246686941137041652143161675650406974771554550
99211471444993077319294853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_unexp_stop.98410524668694113704165214316167565040697
477155455099211471444993077319294853
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.12419860157976946369706183212464577561978011901023601427225011585850037983449
Short name T1121
Test name
Test status
Simulation time 19975830 ps
CPU time 0.63 seconds
Started Nov 22 02:22:43 PM PST 23
Finished Nov 22 02:22:44 PM PST 23
Peak memory 202756 kb
Host smart-e6e24380-d9a4-4ca3-a77e-11a9abe476eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12419860157976946369706183212464577561978011901023601427225011585850037983449 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_alert_test.12419860157976946369706183212464577561978011901023601427225011585850037983449
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.115697055542042193219058530513137395885578577018003961433908897759377555271692
Short name T401
Test name
Test status
Simulation time 74225396 ps
CPU time 1.36 seconds
Started Nov 22 02:23:02 PM PST 23
Finished Nov 22 02:23:04 PM PST 23
Peak memory 211244 kb
Host smart-33b289c4-6f1e-44e6-8de4-99f12ce0e62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115697055542042193219058530513137395885578577018003961433908897759377555271692 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_host_error_intr.115697055542042193219058530513137395885578577018003961433908897759377555271692
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.59576620474533316584234928563253208076829727109025488972781629461490200528679
Short name T311
Test name
Test status
Simulation time 606667565 ps
CPU time 6.65 seconds
Started Nov 22 02:22:43 PM PST 23
Finished Nov 22 02:22:50 PM PST 23
Peak memory 273408 kb
Host smart-b684d0dd-e464-4825-8844-bb85934cbd66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59576620474533316584234928563253208076829727109025488972781629461490200528679 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.59576620474533316584234928563253208076829727109025488972781629461490200528679
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.63909950597116727541910473334958825652830896423141363042255245427516597878034
Short name T165
Test name
Test status
Simulation time 3768267272 ps
CPU time 76.84 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:24:40 PM PST 23
Peak memory 729436 kb
Host smart-1e16bf24-da1c-4205-a433-c1e043ddf9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63909950597116727541910473334958825652830896423141363042255245427516597878034 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_host_fifo_full.63909950597116727541910473334958825652830896423141363042255245427516597878034
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.80370159049376304603284400356949979155970882153966884045836969071007743180195
Short name T779
Test name
Test status
Simulation time 7925734012 ps
CPU time 217.59 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:27:01 PM PST 23
Peak memory 1271620 kb
Host smart-27612088-cbeb-4469-83af-25b81467a7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80370159049376304603284400356949979155970882153966884045836969071007743180195 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.i2c_host_fifo_overflow.80370159049376304603284400356949979155970882153966884045836969071007743180195
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.106878426333741922997686198492208311079042042770539106856389272644667786249478
Short name T1438
Test name
Test status
Simulation time 209010032 ps
CPU time 1 seconds
Started Nov 22 02:23:01 PM PST 23
Finished Nov 22 02:23:03 PM PST 23
Peak memory 202900 kb
Host smart-bb25de90-978a-406f-baf8-47df94fa80bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106878426333741922997686198492208311079042042770539106856389272644667786249478 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.106878426333741922997686198492208311079042042770539106856389272644667786249478
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.49787871309845951718799750760156560001976926784759732804390016687181272085357
Short name T496
Test name
Test status
Simulation time 236313385 ps
CPU time 3.92 seconds
Started Nov 22 02:22:27 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 225500 kb
Host smart-bf13055d-d071-410b-bb30-8b3b0474ff56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49787871309845951718799750760156560001976926784759732804390016687181272085357 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.49787871309845951718799750760156560001976926784759732804390016687181272085357
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.27958967278405253545831430531138076429003345613782643651053158404454631104462
Short name T469
Test name
Test status
Simulation time 7918519784 ps
CPU time 222.22 seconds
Started Nov 22 02:22:29 PM PST 23
Finished Nov 22 02:26:15 PM PST 23
Peak memory 1311016 kb
Host smart-bca012bd-fd68-41d8-89d6-a995d1103409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27958967278405253545831430531138076429003345613782643651053158404454631104462 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_host_fifo_watermark.27958967278405253545831430531138076429003345613782643651053158404454631104462
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.50117389137693015062413236534455917160170317016115025345080175119589950387232
Short name T1214
Test name
Test status
Simulation time 3754070957 ps
CPU time 55.84 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:24:19 PM PST 23
Peak memory 293636 kb
Host smart-2c310027-86da-4c4f-a020-79a66f0bbc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50117389137693015062413236534455917160170317016115025345080175119589950387232 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_host_mode_toggle.50117389137693015062413236534455917160170317016115025345080175119589950387232
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.75013866703475863149473579624801705594159604929413387304406296904859513848881
Short name T1389
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:23:03 PM PST 23
Finished Nov 22 02:23:05 PM PST 23
Peak memory 202880 kb
Host smart-c0cee155-c4dd-40c4-b8e1-3d2bf7b0cfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75013866703475863149473579624801705594159604929413387304406296904859513848881 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_host_override.75013866703475863149473579624801705594159604929413387304406296904859513848881
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.34588579322584081376969396006001101813434719803996787167774908758242312567101
Short name T1239
Test name
Test status
Simulation time 6830796343 ps
CPU time 62.98 seconds
Started Nov 22 02:22:44 PM PST 23
Finished Nov 22 02:23:48 PM PST 23
Peak memory 211360 kb
Host smart-4673606c-8cea-4829-bbfb-6ee333ce0167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34588579322584081376969396006001101813434719803996787167774908758242312567101 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.i2c_host_perf.34588579322584081376969396006001101813434719803996787167774908758242312567101
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_rx_oversample.20988842606345683821336528903154111282420521281123508627813671313082834454118
Short name T1290
Test name
Test status
Simulation time 3939158762 ps
CPU time 101.57 seconds
Started Nov 22 02:22:25 PM PST 23
Finished Nov 22 02:24:11 PM PST 23
Peak memory 345784 kb
Host smart-363a2f37-93e2-4de2-9df8-27ad801e4e1a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20988842606345683821336528903154111282420521281123508627813671313082834454118 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_rx_oversample.20988842606345683821336528903154111282420521281123508627813671313082834454118
Directory /workspace/29.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.82176296725846570272904954663710116260294796563489816566647731608861056448364
Short name T1045
Test name
Test status
Simulation time 2343171530 ps
CPU time 36.01 seconds
Started Nov 22 02:22:30 PM PST 23
Finished Nov 22 02:23:09 PM PST 23
Peak memory 299424 kb
Host smart-973c1d68-eeda-4196-be65-9ac7bce1f25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82176296725846570272904954663710116260294796563489816566647731608861056448364 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.i2c_host_smoke.82176296725846570272904954663710116260294796563489816566647731608861056448364
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.90652308347199443490824435620160821763547383626320512506802335717267309438919
Short name T398
Test name
Test status
Simulation time 32807463528 ps
CPU time 1184.43 seconds
Started Nov 22 02:23:02 PM PST 23
Finished Nov 22 02:42:47 PM PST 23
Peak memory 1957084 kb
Host smart-e7a4f5de-0dcc-4a68-a29f-f09856ef724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90652308347199443490824435620160821763547383626320512506802335717267309438919 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_host_stress_all.90652308347199443490824435620160821763547383626320512506802335717267309438919
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.1874790280887316990962701444471419666503423688026891193148818262010668533799
Short name T624
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.35 seconds
Started Nov 22 02:23:01 PM PST 23
Finished Nov 22 02:23:15 PM PST 23
Peak memory 214236 kb
Host smart-9c9a155a-0916-4393-bc08-df1b47c7f822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874790280887316990962701444471419666503423688026891193148818262010668533799 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_host_stretch_timeout.1874790280887316990962701444471419666503423688026891193148818262010668533799
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.37936789661215234802547328625826395981418775962665864078895158216236641757012
Short name T424
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.7 seconds
Started Nov 22 02:23:19 PM PST 23
Finished Nov 22 02:23:25 PM PST 23
Peak memory 203040 kb
Host smart-5327d62c-1a1e-4408-98cb-935798dac034
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793678966121523480254732862582
6395981418775962665864078895158216236641757012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.37936789661215234802547328
625826395981418775962665864078895158216236641757012
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.75410621407474531803488706581185072874605609703375089491379853611646680091354
Short name T587
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.84 seconds
Started Nov 22 02:23:19 PM PST 23
Finished Nov 22 02:23:53 PM PST 23
Peak memory 382120 kb
Host smart-51355eda-e598-4321-88a2-a666c5187f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754106214074745318034887065811850728746056097033750
89491379853611646680091354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_acq.7541062140747453180348870658118
5072874605609703375089491379853611646680091354
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.85021954299010672444111181500784166253656807467977716120251854189857422974674
Short name T621
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.29 seconds
Started Nov 22 02:22:27 PM PST 23
Finished Nov 22 02:23:06 PM PST 23
Peak memory 462084 kb
Host smart-b55880dd-dbe8-406f-b90c-896a79ea202e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850219542990106724441111815007841662536568074679777
16120251854189857422974674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_tx.850219542990106724441111815007841
66253656807467977716120251854189857422974674
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.23207467640639513114135607470121726836469092291534743745665690745119224969723
Short name T1477
Test name
Test status
Simulation time 825344371 ps
CPU time 2.46 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:23:25 PM PST 23
Peak memory 202996 kb
Host smart-618fd5b9-3087-400b-8642-d7689eb349c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232074676406395131141356074701217268364690922915347
43745665690745119224969723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_hrst.232074676406395131141356074701217268364690922915347
43745665690745119224969723
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.12511004395292675403421088874751880972562467161511156799907106035422803559003
Short name T180
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.37 seconds
Started Nov 22 02:23:17 PM PST 23
Finished Nov 22 02:23:22 PM PST 23
Peak memory 203732 kb
Host smart-bee550c9-ce44-4a5f-b28a-ff7f94c59c41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12511004395292675403421088874751880972562467161511
156799907106035422803559003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.1251100439529267540342108887475188097256246
7161511156799907106035422803559003
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.105260352756525183123293428277889411993472654779249153979355789910180990793301
Short name T713
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.94 seconds
Started Nov 22 02:22:27 PM PST 23
Finished Nov 22 02:22:57 PM PST 23
Peak memory 639164 kb
Host smart-1b15d47f-5fff-4df7-be06-6d104da4451d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526035275652518312329342827788941199
3472654779249153979355789910180990793301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1052603527565251831232
93428277889411993472654779249153979355789910180990793301
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.35223736720447208373386406245047708764434674977957115421718472331610522688161
Short name T554
Test name
Test status
Simulation time 834576440 ps
CPU time 3.04 seconds
Started Nov 22 02:22:27 PM PST 23
Finished Nov 22 02:22:35 PM PST 23
Peak memory 203040 kb
Host smart-ad0e8896-e9a2-4469-ae7f-7e4810f6c623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352237367204472083733864062450477087644346749779571
15421718472331610522688161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_perf.352237367204472083733864062450477087644346749779571
15421718472331610522688161
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.68653632326836471709177195459327904300254152772040202466265124153760978847275
Short name T769
Test name
Test status
Simulation time 1504713936 ps
CPU time 10.06 seconds
Started Nov 22 02:22:30 PM PST 23
Finished Nov 22 02:22:43 PM PST 23
Peak memory 203016 kb
Host smart-a4db37ef-a41c-4627-904c-eea94c7fab62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6865363232683647170917719545932790430025415277204020246626512415376097
8847275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smoke.68653632326836471709177195459327904300254152772040202466265124153760978847275
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.64945623569861689339604323312489141215192575022323861005898786950966751396423
Short name T11
Test name
Test status
Simulation time 66540157934 ps
CPU time 1427.89 seconds
Started Nov 22 02:22:30 PM PST 23
Finished Nov 22 02:46:21 PM PST 23
Peak memory 6983424 kb
Host smart-216fbe55-de4f-4ad1-89aa-b9d83162c095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64945623569861689339604323312489141215192575022323
861005898786950966751396423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_all.64945623569861689339604323312489141215
192575022323861005898786950966751396423
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.11888828859145208986792969035940116652497428824295310157469212635290793440881
Short name T1136
Test name
Test status
Simulation time 997771563 ps
CPU time 8.81 seconds
Started Nov 22 02:23:19 PM PST 23
Finished Nov 22 02:23:29 PM PST 23
Peak memory 202980 kb
Host smart-7baba100-8ce6-4b7e-a0e8-7bf9b0075327
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188882885914520898679296903594011665249742882429531015746921263529079
3440881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_rd.118888288591452089867929690359401166524974288242953101574692
12635290793440881
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.93014150694702435776117598010564547640904413820692335706013948462217025013056
Short name T684
Test name
Test status
Simulation time 14461449567 ps
CPU time 79.21 seconds
Started Nov 22 02:22:27 PM PST 23
Finished Nov 22 02:23:51 PM PST 23
Peak memory 1542048 kb
Host smart-04f4e113-0fdc-49ab-b878-1792beb727b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9301415069470243577611759801056454764090441382069233570601394846221702
5013056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_wr.930141506947024357761175980105645476409044138206923357060139
48462217025013056
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.12474693072807141210834251273664842191250894143950884129881653920635476436872
Short name T406
Test name
Test status
Simulation time 6281818576 ps
CPU time 78.47 seconds
Started Nov 22 02:22:28 PM PST 23
Finished Nov 22 02:23:51 PM PST 23
Peak memory 930492 kb
Host smart-506a2ed8-ed30-457a-8a44-3c208fb05694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247469307280714121083425127366484219125089414395088412988165392063547
6436872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stretch.1247469307280714121083425127366484219125089414395088412988165392
0635476436872
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.25755981728830434140479825536835231209789264562591712616459385105388774268823
Short name T1333
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.23 seconds
Started Nov 22 02:22:32 PM PST 23
Finished Nov 22 02:22:41 PM PST 23
Peak memory 212584 kb
Host smart-884d8642-7f3d-48b3-b803-c1e77fb4d354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257559817288304341404798255368352312097892645625917
12616459385105388774268823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_timeout.257559817288304341404798255368352312097892645
62591712616459385105388774268823
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_ovf.4563052999300330761851555631711537029550954685281743302242779460501226156683
Short name T23
Test name
Test status
Simulation time 5445414553 ps
CPU time 118.35 seconds
Started Nov 22 02:23:02 PM PST 23
Finished Nov 22 02:25:01 PM PST 23
Peak memory 406852 kb
Host smart-deff7a19-4910-4ecd-8904-ae55d2eb02d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45630529993003307618515556317115370295509546852817
43302242779460501226156683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_tx_ovf.45630529993003307618515556317115370295509546852
81743302242779460501226156683
Directory /workspace/29.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.77532597967209212816398629072490514789319569411115010483564720465890487618179
Short name T1141
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.38 seconds
Started Nov 22 02:23:01 PM PST 23
Finished Nov 22 02:23:07 PM PST 23
Peak memory 205340 kb
Host smart-58164bf2-b23e-42a7-8b1a-85017e45d5fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775325979672092128163986290724905147893195694111150
10483564720465890487618179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_unexp_stop.77532597967209212816398629072490514789319
569411115010483564720465890487618179
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.91101756468096980884665733168383148343203854272724127098624986251239824985710
Short name T1069
Test name
Test status
Simulation time 19975830 ps
CPU time 0.56 seconds
Started Nov 22 02:18:19 PM PST 23
Finished Nov 22 02:18:20 PM PST 23
Peak memory 202728 kb
Host smart-4ae642e1-5e46-4483-b184-958dd2f8d31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91101756468096980884665733168383148343203854272724127098624986251239824985710 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_alert_test.91101756468096980884665733168383148343203854272724127098624986251239824985710
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.113084485468325966956503232540979856001023544821131980365097792702008101964623
Short name T659
Test name
Test status
Simulation time 74225396 ps
CPU time 1.36 seconds
Started Nov 22 02:18:31 PM PST 23
Finished Nov 22 02:18:33 PM PST 23
Peak memory 211308 kb
Host smart-afb7cb34-7f84-4058-8016-d13f16701ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113084485468325966956503232540979856001023544821131980365097792702008101964623 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_host_error_intr.113084485468325966956503232540979856001023544821131980365097792702008101964623
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.27303372851576334475221795292004800119137950733669554697711495714534150035933
Short name T1561
Test name
Test status
Simulation time 606667565 ps
CPU time 7.01 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:18:16 PM PST 23
Peak memory 273120 kb
Host smart-43197c85-8c87-4ef4-ba9e-02a2ec6cfba4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27303372851576334475221795292004800119137950733669554697711495714534150035933 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.27303372851576334475221795292004800119137950733669554697711495714534150035933
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.87340434936348166293638195764028411118344920294563365299038708414406919341079
Short name T289
Test name
Test status
Simulation time 3768267272 ps
CPU time 72.88 seconds
Started Nov 22 02:18:37 PM PST 23
Finished Nov 22 02:19:50 PM PST 23
Peak memory 729460 kb
Host smart-2cb11a01-9192-4a41-9c15-eb19de5fb1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87340434936348166293638195764028411118344920294563365299038708414406919341079 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_host_fifo_full.87340434936348166293638195764028411118344920294563365299038708414406919341079
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.143988865152306836644033122308245423126117959192918752247098877359584923987
Short name T631
Test name
Test status
Simulation time 7925734012 ps
CPU time 226.8 seconds
Started Nov 22 02:18:36 PM PST 23
Finished Nov 22 02:22:24 PM PST 23
Peak memory 1271684 kb
Host smart-20217082-08ca-44ef-9adb-fcf9d1620215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143988865152306836644033122308245423126117959192918752247098877359584923987 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_host_fifo_overflow.143988865152306836644033122308245423126117959192918752247098877359584923987
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.10696465593367588891008835884326885710668391951064863966777098174158446830167
Short name T1032
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:18:36 PM PST 23
Finished Nov 22 02:18:38 PM PST 23
Peak memory 202952 kb
Host smart-79b89cae-886c-402a-84fd-56e96dc7a212
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10696465593367588891008835884326885710668391951064863966777098174158446830167 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.10696465593367588891008835884326885710668391951064863966777098174158446830167
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.64301445775270886867212223703096215348418193960750652974528061234483667545006
Short name T850
Test name
Test status
Simulation time 236313385 ps
CPU time 3.79 seconds
Started Nov 22 02:18:32 PM PST 23
Finished Nov 22 02:18:37 PM PST 23
Peak memory 225440 kb
Host smart-5ceaa234-bfc8-4f37-af1a-0e95d40f6489
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64301445775270886867212223703096215348418193960750652974528061234483667545006 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.64301445775270886867212223703096215348418193960750652974528061234483667545006
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.101286177462520774874220858529857489778468899618235920246950697892147193980124
Short name T256
Test name
Test status
Simulation time 7918519784 ps
CPU time 206.16 seconds
Started Nov 22 02:18:33 PM PST 23
Finished Nov 22 02:21:59 PM PST 23
Peak memory 1310856 kb
Host smart-1847fecd-506c-45c3-aee6-460e27f2544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101286177462520774874220858529857489778468899618235920246950697892147193980124 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_host_fifo_watermark.101286177462520774874220858529857489778468899618235920246950697892147193980124
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.104639544496123802211416254729064969930951012346062239195668262759686693855050
Short name T185
Test name
Test status
Simulation time 3754070957 ps
CPU time 49.63 seconds
Started Nov 22 02:18:36 PM PST 23
Finished Nov 22 02:19:27 PM PST 23
Peak memory 293796 kb
Host smart-2247e620-87e7-40b2-98b9-c4d92f5e16da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104639544496123802211416254729064969930951012346062239195668262759686693855050 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_host_mode_toggle.104639544496123802211416254729064969930951012346062239195668262759686693855050
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.100383253394733931248863907963357710809700960777938930555894188990490547943265
Short name T1135
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:18:18 PM PST 23
Finished Nov 22 02:18:20 PM PST 23
Peak memory 202200 kb
Host smart-a8f29577-7129-4834-9151-b83e5049cd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100383253394733931248863907963357710809700960777938930555894188990490547943265 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_host_override.100383253394733931248863907963357710809700960777938930555894188990490547943265
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.49347384688321758486587432836436582073746184753904389155333811775002717373220
Short name T45
Test name
Test status
Simulation time 6830796343 ps
CPU time 63.1 seconds
Started Nov 22 02:18:22 PM PST 23
Finished Nov 22 02:19:26 PM PST 23
Peak memory 211404 kb
Host smart-cf9af1a1-f30e-4b32-9d8e-48445be27c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49347384688321758486587432836436582073746184753904389155333811775002717373220 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.i2c_host_perf.49347384688321758486587432836436582073746184753904389155333811775002717373220
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_rx_oversample.666192746363043081202042506556163844037244186132266116068164410372890307787
Short name T331
Test name
Test status
Simulation time 3939158762 ps
CPU time 123.73 seconds
Started Nov 22 02:18:32 PM PST 23
Finished Nov 22 02:20:36 PM PST 23
Peak memory 345916 kb
Host smart-dbe1da45-0fcd-42e2-bf55-15ab929eef54
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666192746363043081202042506556163844037244186132266116068164410372890307787 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_rx_oversample.666192746363043081202042506556163844037244186132266116068164410372890307787
Directory /workspace/3.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.57695023088015670237791945792245764367895192568618157125755968427504048493937
Short name T952
Test name
Test status
Simulation time 2343171530 ps
CPU time 36.75 seconds
Started Nov 22 02:18:05 PM PST 23
Finished Nov 22 02:18:43 PM PST 23
Peak memory 299428 kb
Host smart-d176aa2e-4ada-4f3f-aeee-c3539e6bffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57695023088015670237791945792245764367895192568618157125755968427504048493937 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.i2c_host_smoke.57695023088015670237791945792245764367895192568618157125755968427504048493937
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.92530556926917741516059560312569560058219482908574304113830353846328794526719
Short name T936
Test name
Test status
Simulation time 32807463528 ps
CPU time 1033.7 seconds
Started Nov 22 02:18:17 PM PST 23
Finished Nov 22 02:35:32 PM PST 23
Peak memory 1956980 kb
Host smart-2fa827bb-876d-4ce6-beee-3c927b57c941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92530556926917741516059560312569560058219482908574304113830353846328794526719 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_host_stress_all.92530556926917741516059560312569560058219482908574304113830353846328794526719
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.43156138508998553528379239103686401036757675226545632932539966575269108979388
Short name T189
Test name
Test status
Simulation time 1466624971 ps
CPU time 14 seconds
Started Nov 22 02:18:36 PM PST 23
Finished Nov 22 02:18:51 PM PST 23
Peak memory 214156 kb
Host smart-f3651587-c83a-4877-9415-650c8e78d9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43156138508998553528379239103686401036757675226545632932539966575269108979388 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_host_stretch_timeout.43156138508998553528379239103686401036757675226545632932539966575269108979388
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.72745966579253092079358901369019253469647842707432563644246324306334585419930
Short name T41
Test name
Test status
Simulation time 62618346 ps
CPU time 0.85 seconds
Started Nov 22 02:18:34 PM PST 23
Finished Nov 22 02:18:36 PM PST 23
Peak memory 219984 kb
Host smart-d21d6ab2-ae2d-4d23-ba30-0e9262941aef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72745966579253092079358901369019253469647842707432563644246324306334585419930 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_sec_cm.72745966579253092079358901369019253469647842707432563644246324306334585419930
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.9646861361652368105386848175908049047442548640840472729398009463014421755719
Short name T899
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.78 seconds
Started Nov 22 02:18:35 PM PST 23
Finished Nov 22 02:18:40 PM PST 23
Peak memory 203012 kb
Host smart-f4b1de34-4989-4847-9ed1-ef90c18e3051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9646861361652368105386848175908
049047442548640840472729398009463014421755719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.9646861361652368105386848175
908049047442548640840472729398009463014421755719
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.96024155043204339549531382372777278340528010207558687756719244973434020175266
Short name T1084
Test name
Test status
Simulation time 10166144644 ps
CPU time 29.36 seconds
Started Nov 22 02:18:35 PM PST 23
Finished Nov 22 02:19:05 PM PST 23
Peak memory 382256 kb
Host smart-dcecb43e-1cc5-48a3-b442-27e3788c4a37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960241550432043395495313823727772783405280102075586
87756719244973434020175266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.96024155043204339549531382372777
278340528010207558687756719244973434020175266
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.15271066328281460003849138175808461161179344584120756677783230527933045646281
Short name T254
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.23 seconds
Started Nov 22 02:18:33 PM PST 23
Finished Nov 22 02:19:08 PM PST 23
Peak memory 463160 kb
Host smart-99aeb634-6e88-4576-9b2f-38c349460d0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152710663282814600038491381758084611611793445841207
56677783230527933045646281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_tx.1527106632828146000384913817580846
1161179344584120756677783230527933045646281
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.74920140063458740171344239734693567249125929469014464258469004484240135009245
Short name T1466
Test name
Test status
Simulation time 825344371 ps
CPU time 2.4 seconds
Started Nov 22 02:18:19 PM PST 23
Finished Nov 22 02:18:22 PM PST 23
Peak memory 203080 kb
Host smart-7a4c8d4b-c9b0-4d84-88ce-c063a74a8d37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749201400634587401713442397346935672491259294690144
64258469004484240135009245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_hrst.7492014006345874017134423973469356724912592946901446
4258469004484240135009245
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.69084188251309684521032625269194471983999696685414319979856800266494595573388
Short name T255
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.11 seconds
Started Nov 22 02:18:21 PM PST 23
Finished Nov 22 02:18:25 PM PST 23
Peak memory 203368 kb
Host smart-e6956d73-a112-4009-847e-fe529a76c62b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69084188251309684521032625269194471983999696685414
319979856800266494595573388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.69084188251309684521032625269194471983999696
685414319979856800266494595573388
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.29486861643356496486734346551493776766596821195847600374257831308871066277604
Short name T1076
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.43 seconds
Started Nov 22 02:18:22 PM PST 23
Finished Nov 22 02:18:44 PM PST 23
Peak memory 638976 kb
Host smart-8f10a0aa-679e-4d75-8d5b-a8e306ea0d62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29486861643356496486734346551493776766
596821195847600374257831308871066277604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.294868616433564964867343
46551493776766596821195847600374257831308871066277604
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.56516391675437260958829453719466564603656458036591621090210054269927964696283
Short name T846
Test name
Test status
Simulation time 834576440 ps
CPU time 3.01 seconds
Started Nov 22 02:18:10 PM PST 23
Finished Nov 22 02:18:14 PM PST 23
Peak memory 203036 kb
Host smart-b3e8d06e-7fd4-47d7-a342-326e4d3a02aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565163916754372609588294537194665646036564580365916
21090210054269927964696283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_perf.5651639167543726095882945371946656460365645803659162
1090210054269927964696283
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.65685708154657909016853407047651507066946955789983621771727478667805671583600
Short name T463
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.58 seconds
Started Nov 22 02:18:37 PM PST 23
Finished Nov 22 02:18:47 PM PST 23
Peak memory 202980 kb
Host smart-21bf8fb6-364d-402c-b801-1da815f69f67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6568570815465790901685340704765150706694695578998362177172747866780567
1583600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smoke.65685708154657909016853407047651507066946955789983621771727478667805671583600
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.2224697892372391624750120788172638378412696700403346385676948769916758225270
Short name T643
Test name
Test status
Simulation time 66540157934 ps
CPU time 1653.05 seconds
Started Nov 22 02:18:34 PM PST 23
Finished Nov 22 02:46:08 PM PST 23
Peak memory 6983628 kb
Host smart-2a9b0508-b656-4310-9685-0f85ffdb7ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22246978923723916247501207881726383784126967004033
46385676948769916758225270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_all.2224697892372391624750120788172638378412
696700403346385676948769916758225270
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.73274147139470700840927509062577308400180981575023500015816176147142751281653
Short name T957
Test name
Test status
Simulation time 997771563 ps
CPU time 8.8 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:18:18 PM PST 23
Peak memory 202796 kb
Host smart-f37752a1-16f2-46b8-a614-f711bfe7de7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7327414713947070084092750906257730840018098157502350001581617614714275
1281653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_rd.7327414713947070084092750906257730840018098157502350001581617
6147142751281653
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.48563219930543495883568394043587526444015825824576458859904071429824387435603
Short name T589
Test name
Test status
Simulation time 14461449567 ps
CPU time 89.15 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:19:39 PM PST 23
Peak memory 1542100 kb
Host smart-c59b69b2-1d0b-4f9d-bad6-68d1c51e6869
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4856321993054349588356839404358752644401582582457645885990407142982438
7435603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_wr.4856321993054349588356839404358752644401582582457645885990407
1429824387435603
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.103708875593967321049174028693626029464322738602861161541840316750242850051010
Short name T302
Test name
Test status
Simulation time 6281818576 ps
CPU time 71.89 seconds
Started Nov 22 02:18:37 PM PST 23
Finished Nov 22 02:19:50 PM PST 23
Peak memory 930588 kb
Host smart-7d8a27ab-c59c-481f-b8f0-d5f6b6d91229
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037088755939673210491740286936260294643227386028611615418403167502428
50051010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stretch.1037088755939673210491740286936260294643227386028611615418403167
50242850051010
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.58875573981572463720089892072910803744392240140248544900392672549799876176728
Short name T445
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.38 seconds
Started Nov 22 02:18:18 PM PST 23
Finished Nov 22 02:18:26 PM PST 23
Peak memory 212496 kb
Host smart-137c5796-c8a7-4225-aa48-486c4f3fa4c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588755739815724637200898920729108037443922401402485
44900392672549799876176728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_timeout.5887557398157246372008989207291080374439224014
0248544900392672549799876176728
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_ovf.49685703877302635767749355224098638920605507244197157751150166826147618659162
Short name T1403
Test name
Test status
Simulation time 5445414553 ps
CPU time 124.25 seconds
Started Nov 22 02:18:19 PM PST 23
Finished Nov 22 02:20:23 PM PST 23
Peak memory 406776 kb
Host smart-0910a1f1-10cd-45fc-89d6-45d7d5b11206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49685703877302635767749355224098638920605507244197
157751150166826147618659162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_tx_ovf.49685703877302635767749355224098638920605507244
197157751150166826147618659162
Directory /workspace/3.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.77029534968660680271302200676495586663408953088237239723159865869636248512168
Short name T295
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.7 seconds
Started Nov 22 02:18:08 PM PST 23
Finished Nov 22 02:18:15 PM PST 23
Peak memory 205328 kb
Host smart-0a8ba850-ac9f-418a-a327-3ed11a864aec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770295349686606802713022006764955866634089530882372
39723159865869636248512168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_unexp_stop.770295349686606802713022006764955866634089
53088237239723159865869636248512168
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.92743679739532782065568955487574938522504172055244656441220496738682170368169
Short name T653
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:22:30 PM PST 23
Finished Nov 22 02:22:33 PM PST 23
Peak memory 202644 kb
Host smart-1cc5f7c6-c71b-417d-8cf0-ef0a9cf331b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92743679739532782065568955487574938522504172055244656441220496738682170368169 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_alert_test.92743679739532782065568955487574938522504172055244656441220496738682170368169
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.58133162018095774471051940482007885809327651414653414041641236060092919330406
Short name T699
Test name
Test status
Simulation time 74225396 ps
CPU time 1.36 seconds
Started Nov 22 02:23:17 PM PST 23
Finished Nov 22 02:23:19 PM PST 23
Peak memory 211308 kb
Host smart-ea6f39d4-8add-42a5-b901-9a57decaad4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58133162018095774471051940482007885809327651414653414041641236060092919330406 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_host_error_intr.58133162018095774471051940482007885809327651414653414041641236060092919330406
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.68422814983787602902323694176283039679021175854080243342894775702216778627495
Short name T778
Test name
Test status
Simulation time 606667565 ps
CPU time 6.93 seconds
Started Nov 22 02:22:27 PM PST 23
Finished Nov 22 02:22:39 PM PST 23
Peak memory 273440 kb
Host smart-faa34c1b-5534-47d6-b362-a847d4ef1d40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68422814983787602902323694176283039679021175854080243342894775702216778627495 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.68422814983787602902323694176283039679021175854080243342894775702216778627495
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.114192994195314982261955330320098331856019724676201079818415979505228818418844
Short name T664
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.14 seconds
Started Nov 22 02:22:42 PM PST 23
Finished Nov 22 02:23:57 PM PST 23
Peak memory 729500 kb
Host smart-9599ef3a-a1d9-48a0-86ed-1c1b14e115c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114192994195314982261955330320098331856019724676201079818415979505228818418844 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_host_fifo_full.114192994195314982261955330320098331856019724676201079818415979505228818418844
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.61659503088739110296422975891283969971446490109031007267556762320791124835198
Short name T996
Test name
Test status
Simulation time 7925734012 ps
CPU time 216.26 seconds
Started Nov 22 02:22:28 PM PST 23
Finished Nov 22 02:26:09 PM PST 23
Peak memory 1271544 kb
Host smart-3b51629b-9e21-4beb-87e1-f71ee8aa392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61659503088739110296422975891283969971446490109031007267556762320791124835198 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.i2c_host_fifo_overflow.61659503088739110296422975891283969971446490109031007267556762320791124835198
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.84586343522333988452169833562512207326790853714985309633464641080683944600052
Short name T351
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:22:27 PM PST 23
Finished Nov 22 02:22:33 PM PST 23
Peak memory 202944 kb
Host smart-22ad0854-9e9f-47d0-a83b-70ae6a8d135f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84586343522333988452169833562512207326790853714985309633464641080683944600052 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.84586343522333988452169833562512207326790853714985309633464641080683944600052
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.5763506432808082739531482650103091323471285256453143066876803685407082996564
Short name T715
Test name
Test status
Simulation time 236313385 ps
CPU time 4.03 seconds
Started Nov 22 02:22:29 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 225460 kb
Host smart-e5f757f7-43e7-4889-a15f-eb5dce50dc0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5763506432808082739531482650103091323471285256453143066876803685407082996564 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.5763506432808082739531482650103091323471285256453143066876803685407082996564
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.49149168932459260021318990615066084800041563781706742055141042619716034707191
Short name T1244
Test name
Test status
Simulation time 7918519784 ps
CPU time 189.11 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:26:30 PM PST 23
Peak memory 1311052 kb
Host smart-0ff9ef3d-d4cc-492a-830d-040d273225e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49149168932459260021318990615066084800041563781706742055141042619716034707191 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_host_fifo_watermark.49149168932459260021318990615066084800041563781706742055141042619716034707191
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.98177112124372072369231702334643644029471424046580731987165138118517102895694
Short name T1538
Test name
Test status
Simulation time 3754070957 ps
CPU time 49.55 seconds
Started Nov 22 02:23:19 PM PST 23
Finished Nov 22 02:24:10 PM PST 23
Peak memory 293880 kb
Host smart-2ce353f6-e8c5-43d9-9c07-a9e63f8e2a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98177112124372072369231702334643644029471424046580731987165138118517102895694 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_host_mode_toggle.98177112124372072369231702334643644029471424046580731987165138118517102895694
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.25127060838647896295704755232992271344679799543563218277019424436276794446227
Short name T1272
Test name
Test status
Simulation time 23672229 ps
CPU time 0.67 seconds
Started Nov 22 02:22:29 PM PST 23
Finished Nov 22 02:22:33 PM PST 23
Peak memory 202916 kb
Host smart-75abfa75-a2da-4390-8775-d98dddd9d869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25127060838647896295704755232992271344679799543563218277019424436276794446227 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_host_override.25127060838647896295704755232992271344679799543563218277019424436276794446227
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.115461558864615676022849998372590756751539987033839944003261871382749998242172
Short name T1183
Test name
Test status
Simulation time 6830796343 ps
CPU time 62.17 seconds
Started Nov 22 02:23:02 PM PST 23
Finished Nov 22 02:24:05 PM PST 23
Peak memory 211304 kb
Host smart-872046ac-88cd-4191-8e9c-394f76202243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115461558864615676022849998372590756751539987033839944003261871382749998242172 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.i2c_host_perf.115461558864615676022849998372590756751539987033839944003261871382749998242172
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_rx_oversample.25583874294566833459565247118762981469970158750895293685501491076294372190982
Short name T690
Test name
Test status
Simulation time 3939158762 ps
CPU time 98.63 seconds
Started Nov 22 02:22:33 PM PST 23
Finished Nov 22 02:24:13 PM PST 23
Peak memory 345860 kb
Host smart-d73c1228-41e0-414a-b813-654b7add512e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25583874294566833459565247118762981469970158750895293685501491076294372190982 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_rx_oversample.25583874294566833459565247118762981469970158750895293685501491076294372190982
Directory /workspace/30.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.19015844950992827486783799202734554551523424816279356294451421174080472944415
Short name T958
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.01 seconds
Started Nov 22 02:23:17 PM PST 23
Finished Nov 22 02:23:55 PM PST 23
Peak memory 299276 kb
Host smart-0fb1a410-37a8-47a0-8146-ec5be18aa12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19015844950992827486783799202734554551523424816279356294451421174080472944415 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.i2c_host_smoke.19015844950992827486783799202734554551523424816279356294451421174080472944415
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.74402069501971012015186157338928408813326479197076752062034529288157323236229
Short name T1246
Test name
Test status
Simulation time 32807463528 ps
CPU time 1219.61 seconds
Started Nov 22 02:22:27 PM PST 23
Finished Nov 22 02:42:52 PM PST 23
Peak memory 1957024 kb
Host smart-cd8bf23b-936e-4e49-8bad-889f3774de9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74402069501971012015186157338928408813326479197076752062034529288157323236229 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_host_stress_all.74402069501971012015186157338928408813326479197076752062034529288157323236229
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.64244894601332937435095786728737425890820930195260733413640698473585396864716
Short name T1028
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.03 seconds
Started Nov 22 02:23:01 PM PST 23
Finished Nov 22 02:23:15 PM PST 23
Peak memory 214160 kb
Host smart-81ff9364-ce3e-4f5a-8746-b80b97ef1f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64244894601332937435095786728737425890820930195260733413640698473585396864716 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_host_stretch_timeout.64244894601332937435095786728737425890820930195260733413640698473585396864716
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.73247733893576936514392612147183030370953075509608749940236841488472867489761
Short name T342
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.83 seconds
Started Nov 22 02:22:46 PM PST 23
Finished Nov 22 02:22:51 PM PST 23
Peak memory 202920 kb
Host smart-ce41cafb-b225-4090-9410-ed1bd6206323
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7324773389357693651439261214718
3030370953075509608749940236841488472867489761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.73247733893576936514392612
147183030370953075509608749940236841488472867489761
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.73189209848134143672513910147770650627513234220892882144701847543706821895914
Short name T1304
Test name
Test status
Simulation time 10166144644 ps
CPU time 33.68 seconds
Started Nov 22 02:23:18 PM PST 23
Finished Nov 22 02:23:53 PM PST 23
Peak memory 382196 kb
Host smart-78afffab-c0fd-4956-b639-06dd124520e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731892098481341436725139101477706506275132342208928
82144701847543706821895914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.7318920984813414367251391014777
0650627513234220892882144701847543706821895914
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.80525110825628848191865078553780695887567644741244248844648181029213717304570
Short name T730
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.05 seconds
Started Nov 22 02:22:46 PM PST 23
Finished Nov 22 02:23:23 PM PST 23
Peak memory 462072 kb
Host smart-20d6adc1-46fe-4a66-9639-725c2c84bde1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805251108256288481918650785537806958875676447412442
48844648181029213717304570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_tx.805251108256288481918650785537806
95887567644741244248844648181029213717304570
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.83054616334019778511440303735450085883435273533539887082576877348809552608902
Short name T1112
Test name
Test status
Simulation time 825344371 ps
CPU time 2.42 seconds
Started Nov 22 02:22:46 PM PST 23
Finished Nov 22 02:22:50 PM PST 23
Peak memory 203056 kb
Host smart-dbfb86fe-f3a6-46df-b3ed-6c09d47324aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830546163340197785114403037354500858834352735335398
87082576877348809552608902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_hrst.830546163340197785114403037354500858834352735335398
87082576877348809552608902
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.89743631299656670457919572845699446597705293446426904252140502369882466044635
Short name T1009
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.5 seconds
Started Nov 22 02:22:31 PM PST 23
Finished Nov 22 02:22:37 PM PST 23
Peak memory 203676 kb
Host smart-1c512986-0670-4881-b278-594223ce76b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89743631299656670457919572845699446597705293446426
904252140502369882466044635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.8974363129965667045791957284569944659770529
3446426904252140502369882466044635
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.8300486317375459429077226825824291598961120324952389906303913259995186405320
Short name T532
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.08 seconds
Started Nov 22 02:23:00 PM PST 23
Finished Nov 22 02:23:23 PM PST 23
Peak memory 639180 kb
Host smart-a9a7d4b8-b933-4518-8136-7793f7c5e35d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83004863173754594290772268258242915989
61120324952389906303913259995186405320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.830048631737545942907722
6825824291598961120324952389906303913259995186405320
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.59360421688975978937751020300170719145209422495640713360469375370789168338872
Short name T1460
Test name
Test status
Simulation time 834576440 ps
CPU time 2.95 seconds
Started Nov 22 02:22:31 PM PST 23
Finished Nov 22 02:22:36 PM PST 23
Peak memory 202996 kb
Host smart-5814cfe0-d370-44da-8571-daa32dea7a2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593604216889759789377510203001707191452094224956407
13360469375370789168338872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_perf.593604216889759789377510203001707191452094224956407
13360469375370789168338872
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.82497617020453660181915664320482711211130206500496572821202887577883885380786
Short name T837
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.56 seconds
Started Nov 22 02:23:19 PM PST 23
Finished Nov 22 02:23:30 PM PST 23
Peak memory 203016 kb
Host smart-5eed4f71-590d-438e-960e-706f4d2c759e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8249761702045366018191566432048271121113020650049657282120288757788388
5380786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smoke.82497617020453660181915664320482711211130206500496572821202887577883885380786
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.79256155752078159537614031350288872913679337974038166786729203847326308697399
Short name T1324
Test name
Test status
Simulation time 66540157934 ps
CPU time 1562.64 seconds
Started Nov 22 02:23:02 PM PST 23
Finished Nov 22 02:49:06 PM PST 23
Peak memory 6983448 kb
Host smart-d3c04cb2-922a-4db1-96c8-7289079fa701
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79256155752078159537614031350288872913679337974038
166786729203847326308697399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_all.79256155752078159537614031350288872913
679337974038166786729203847326308697399
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.33621196990449812483507599629982822619405596685690795823638917276739125922231
Short name T598
Test name
Test status
Simulation time 997771563 ps
CPU time 8.41 seconds
Started Nov 22 02:22:29 PM PST 23
Finished Nov 22 02:22:41 PM PST 23
Peak memory 203068 kb
Host smart-38496f21-b9fb-47b4-a629-5863e855e833
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362119699044981248350759962998282261940559668569079582363891727673912
5922231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_rd.336211969904498124835075996299828226194055966856907958236389
17276739125922231
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.112386415777002408953750261442458990763997714007792259422037956531081946061281
Short name T378
Test name
Test status
Simulation time 14461449567 ps
CPU time 80.46 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:24:43 PM PST 23
Peak memory 1542104 kb
Host smart-d18f9d57-32f8-480f-8be8-aa6140bbc473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123864157770024089537502614424589907639977140077922594220379565310819
46061281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_wr.11238641577700240895375026144245899076399771400779225942203
7956531081946061281
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3087950440256667761777986617917772896762637557326814433166560642095093269180
Short name T1040
Test name
Test status
Simulation time 6281818576 ps
CPU time 74.77 seconds
Started Nov 22 02:22:50 PM PST 23
Finished Nov 22 02:24:06 PM PST 23
Peak memory 930504 kb
Host smart-42c58346-a7f5-442e-a35c-8b66d2dff12d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087950440256667761777986617917772896762637557326814433166560642095093
269180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stretch.3087950440256667761777986617917772896762637557326814433166560642095093269180
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.23089337362836006633924392650042023085228916837357212340847313832740070668886
Short name T317
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.24 seconds
Started Nov 22 02:23:18 PM PST 23
Finished Nov 22 02:23:27 PM PST 23
Peak memory 212652 kb
Host smart-155abcab-e915-4f26-b9b0-52ba77810ff8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230893373628360066339243926500420230852289168373572
12340847313832740070668886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_timeout.230893373628360066339243926500420230852289168
37357212340847313832740070668886
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_ovf.8184825439072475083842146521024376109008093616923819251931218965723533873610
Short name T1031
Test name
Test status
Simulation time 5445414553 ps
CPU time 131.14 seconds
Started Nov 22 02:23:19 PM PST 23
Finished Nov 22 02:25:31 PM PST 23
Peak memory 406732 kb
Host smart-31041b60-65b5-4f23-bd99-dc268456be7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81848254390724750838421465210243761090080936169238
19251931218965723533873610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_tx_ovf.81848254390724750838421465210243761090080936169
23819251931218965723533873610
Directory /workspace/30.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.100718622708103764712920824589898922436514622707072117892546414397988380470779
Short name T197
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.47 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:23:28 PM PST 23
Peak memory 205260 kb
Host smart-d081bf58-9c32-41c4-89e5-dbbb516bcb76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100718622708103764712920824589898922436514622707072
117892546414397988380470779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_unexp_stop.1007186227081037647129208245898989224365
14622707072117892546414397988380470779
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.42801956489262501879726523079405456872389530839392480895625543180632724497828
Short name T355
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:23:19 PM PST 23
Finished Nov 22 02:23:22 PM PST 23
Peak memory 202744 kb
Host smart-875694eb-d07c-46a0-9ee8-d6578bd4923c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42801956489262501879726523079405456872389530839392480895625543180632724497828 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_alert_test.42801956489262501879726523079405456872389530839392480895625543180632724497828
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.64285597246011559420404270486947954444787656600248661931343831650910106147389
Short name T665
Test name
Test status
Simulation time 74225396 ps
CPU time 1.35 seconds
Started Nov 22 02:23:01 PM PST 23
Finished Nov 22 02:23:03 PM PST 23
Peak memory 211264 kb
Host smart-3da5c713-6fd4-4589-b2e6-131141448916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64285597246011559420404270486947954444787656600248661931343831650910106147389 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_host_error_intr.64285597246011559420404270486947954444787656600248661931343831650910106147389
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.11677801459848341266082376580415844026439834522300234630562534389514353988359
Short name T1056
Test name
Test status
Simulation time 606667565 ps
CPU time 6.7 seconds
Started Nov 22 02:23:18 PM PST 23
Finished Nov 22 02:23:25 PM PST 23
Peak memory 273524 kb
Host smart-0eaebf91-fb08-4b7b-86d0-d09f6e15757b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11677801459848341266082376580415844026439834522300234630562534389514353988359 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.11677801459848341266082376580415844026439834522300234630562534389514353988359
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.101204920920929116577455115270940775283069109901961997674699970869171781438641
Short name T304
Test name
Test status
Simulation time 3768267272 ps
CPU time 71.44 seconds
Started Nov 22 02:23:21 PM PST 23
Finished Nov 22 02:24:35 PM PST 23
Peak memory 729332 kb
Host smart-2e575535-6b10-4b97-91f4-7954f81bedb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101204920920929116577455115270940775283069109901961997674699970869171781438641 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_host_fifo_full.101204920920929116577455115270940775283069109901961997674699970869171781438641
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.52392787940759981386000005258244759646707146146810578478019454527575027474529
Short name T1256
Test name
Test status
Simulation time 7925734012 ps
CPU time 223.93 seconds
Started Nov 22 02:22:39 PM PST 23
Finished Nov 22 02:26:24 PM PST 23
Peak memory 1271580 kb
Host smart-363b953c-7015-445b-919e-dbf9bf946fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52392787940759981386000005258244759646707146146810578478019454527575027474529 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.i2c_host_fifo_overflow.52392787940759981386000005258244759646707146146810578478019454527575027474529
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.62395432815294714525464930613375664542314199981111349735210489240921185826413
Short name T541
Test name
Test status
Simulation time 209010032 ps
CPU time 0.96 seconds
Started Nov 22 02:22:39 PM PST 23
Finished Nov 22 02:22:40 PM PST 23
Peak memory 202668 kb
Host smart-eb2fe4dd-c078-4617-8cff-684291993775
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62395432815294714525464930613375664542314199981111349735210489240921185826413 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.62395432815294714525464930613375664542314199981111349735210489240921185826413
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.84833697269219483388568234161134714060730288456395741072431559442821094149052
Short name T1307
Test name
Test status
Simulation time 236313385 ps
CPU time 3.78 seconds
Started Nov 22 02:23:17 PM PST 23
Finished Nov 22 02:23:22 PM PST 23
Peak memory 225524 kb
Host smart-f5251e71-7506-4d05-aa4e-10a01add2613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84833697269219483388568234161134714060730288456395741072431559442821094149052 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.84833697269219483388568234161134714060730288456395741072431559442821094149052
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.33274920557259011551712583632960702881705941366197704895174821051291679551029
Short name T206
Test name
Test status
Simulation time 7918519784 ps
CPU time 210.79 seconds
Started Nov 22 02:22:31 PM PST 23
Finished Nov 22 02:26:04 PM PST 23
Peak memory 1310904 kb
Host smart-54f9d712-c624-46f4-829f-9e7f60003132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33274920557259011551712583632960702881705941366197704895174821051291679551029 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.i2c_host_fifo_watermark.33274920557259011551712583632960702881705941366197704895174821051291679551029
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.114824888799439720409298946456527315013525151579649033598147193666954862890120
Short name T678
Test name
Test status
Simulation time 3754070957 ps
CPU time 51.25 seconds
Started Nov 22 02:23:03 PM PST 23
Finished Nov 22 02:23:55 PM PST 23
Peak memory 293780 kb
Host smart-152b3b87-15e8-4b5b-92c8-b30aa6011811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114824888799439720409298946456527315013525151579649033598147193666954862890120 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.i2c_host_mode_toggle.114824888799439720409298946456527315013525151579649033598147193666954862890120
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.80647834732088605353135480789207158439840069640677595818537957811575901842690
Short name T774
Test name
Test status
Simulation time 23672229 ps
CPU time 0.61 seconds
Started Nov 22 02:22:45 PM PST 23
Finished Nov 22 02:22:47 PM PST 23
Peak memory 202704 kb
Host smart-aff6ae5a-756f-4eef-9111-c2226914575b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80647834732088605353135480789207158439840069640677595818537957811575901842690 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_host_override.80647834732088605353135480789207158439840069640677595818537957811575901842690
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.68648567122518465524919254130927895347053388625518165060566918378104984453511
Short name T1492
Test name
Test status
Simulation time 6830796343 ps
CPU time 61.08 seconds
Started Nov 22 02:23:18 PM PST 23
Finished Nov 22 02:24:20 PM PST 23
Peak memory 211276 kb
Host smart-e6cbde33-82e0-4e1e-b0f3-a08b2aa61019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68648567122518465524919254130927895347053388625518165060566918378104984453511 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.i2c_host_perf.68648567122518465524919254130927895347053388625518165060566918378104984453511
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_rx_oversample.105374662724483233857749354439419476902235493495654475422970898605993209561827
Short name T344
Test name
Test status
Simulation time 3939158762 ps
CPU time 99.17 seconds
Started Nov 22 02:22:48 PM PST 23
Finished Nov 22 02:24:28 PM PST 23
Peak memory 345968 kb
Host smart-24a8430b-2dd1-49d3-b786-a4bc9e0281b8
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105374662724483233857749354439419476902235493495654475422970898605993209561827 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_rx_oversample.105374662724483233857749354439419476902235493495654475422970898605993209561827
Directory /workspace/31.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.48745482618625010395539114752869426632133517303622589255530992256891406316578
Short name T747
Test name
Test status
Simulation time 2343171530 ps
CPU time 38.39 seconds
Started Nov 22 02:22:33 PM PST 23
Finished Nov 22 02:23:12 PM PST 23
Peak memory 299312 kb
Host smart-ac68df06-f192-46a4-aeaa-343ba2bd9583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48745482618625010395539114752869426632133517303622589255530992256891406316578 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.i2c_host_smoke.48745482618625010395539114752869426632133517303622589255530992256891406316578
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.111896219514545157285239928351993145966777494586956375718689399387681413824514
Short name T1161
Test name
Test status
Simulation time 32807463528 ps
CPU time 987.37 seconds
Started Nov 22 02:22:28 PM PST 23
Finished Nov 22 02:39:00 PM PST 23
Peak memory 1956976 kb
Host smart-2dc9a464-ec7c-44aa-8a23-3bfc8d4855c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111896219514545157285239928351993145966777494586956375718689399387681413824514 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_host_stress_all.111896219514545157285239928351993145966777494586956375718689399387681413824514
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.96827291195617694165705356754573874003762903270127257692473644417615976758725
Short name T1063
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.66 seconds
Started Nov 22 02:22:37 PM PST 23
Finished Nov 22 02:22:51 PM PST 23
Peak memory 214028 kb
Host smart-537dbf5f-bc26-4074-842d-66462e2d04be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96827291195617694165705356754573874003762903270127257692473644417615976758725 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_host_stretch_timeout.96827291195617694165705356754573874003762903270127257692473644417615976758725
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.13121226835844690486622165935779968070327937559493054904167889387576270316431
Short name T870
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.68 seconds
Started Nov 22 02:23:19 PM PST 23
Finished Nov 22 02:23:24 PM PST 23
Peak memory 203036 kb
Host smart-04fd529b-4dbc-4654-93cf-d1e6a473424e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312122683584469048662216593577
9968070327937559493054904167889387576270316431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.13121226835844690486622165
935779968070327937559493054904167889387576270316431
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.69040550537980031347605349775904029609304095565090954193811650423169286775030
Short name T1329
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.16 seconds
Started Nov 22 02:23:03 PM PST 23
Finished Nov 22 02:23:36 PM PST 23
Peak memory 382164 kb
Host smart-fa144878-d2e2-4b0e-a2d0-cb5a3396392b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690405505379800313476053497759040296093040955650909
54193811650423169286775030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.6904055053798003134760534977590
4029609304095565090954193811650423169286775030
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.105951908411077464232211674293787758582319499979985687275139654325516952690836
Short name T1467
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.61 seconds
Started Nov 22 02:23:33 PM PST 23
Finished Nov 22 02:24:10 PM PST 23
Peak memory 462120 kb
Host smart-b3126dad-2899-4e02-a772-d67f1f8864d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105951908411077464232211674293787758582319499979985
687275139654325516952690836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_tx.10595190841107746423221167429378
7758582319499979985687275139654325516952690836
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.114350155336855546300090349326266026188704432226407856462440712920517581020094
Short name T655
Test name
Test status
Simulation time 825344371 ps
CPU time 2.5 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:23:25 PM PST 23
Peak memory 203076 kb
Host smart-5b9b77a9-3f6f-4d00-9054-820aa5afac7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114350155336855546300090349326266026188704432226407
856462440712920517581020094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_hrst.11435015533685554630009034932626602618870443222640
7856462440712920517581020094
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.78716021766486884249293578362918689335755574248926758845332672791001880485212
Short name T343
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.28 seconds
Started Nov 22 02:22:46 PM PST 23
Finished Nov 22 02:22:51 PM PST 23
Peak memory 203728 kb
Host smart-e9608421-dc03-4d80-a13c-8b42fb932474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78716021766486884249293578362918689335755574248926
758845332672791001880485212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.7871602176648688424929357836291868933575557
4248926758845332672791001880485212
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.111771018217346968574510380710110945604390131834526539130640122299228969583242
Short name T1215
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.46 seconds
Started Nov 22 02:23:18 PM PST 23
Finished Nov 22 02:23:43 PM PST 23
Peak memory 639192 kb
Host smart-936fa2e3-4902-4dbf-b378-17b036b66d07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11177101821734696857451038071011094560
4390131834526539130640122299228969583242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1117710182173469685745
10380710110945604390131834526539130640122299228969583242
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_perf.81628612408024238510285961066567527932012492276115793012151389268895219772633
Short name T143
Test name
Test status
Simulation time 834576440 ps
CPU time 2.98 seconds
Started Nov 22 02:23:21 PM PST 23
Finished Nov 22 02:23:27 PM PST 23
Peak memory 202976 kb
Host smart-566324e4-b318-41a8-95d6-076f7352b842
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816286124080242385102859610665675279320124922761157
93012151389268895219772633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_perf.816286124080242385102859610665675279320124922761157
93012151389268895219772633
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.91491849170802651176028542406097349873093843161186081398854353801903486226366
Short name T170
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.78 seconds
Started Nov 22 02:23:00 PM PST 23
Finished Nov 22 02:23:11 PM PST 23
Peak memory 202988 kb
Host smart-3f66d311-0ab0-447c-99d9-71ca1cd3e1ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9149184917080265117602854240609734987309384316118608139885435380190348
6226366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smoke.91491849170802651176028542406097349873093843161186081398854353801903486226366
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.100842941240933533740562175861514040318706640823817508865834660168033313709755
Short name T1185
Test name
Test status
Simulation time 66540157934 ps
CPU time 1745.21 seconds
Started Nov 22 02:23:06 PM PST 23
Finished Nov 22 02:52:13 PM PST 23
Peak memory 6983832 kb
Host smart-2640eae1-7300-4a8e-8a94-a7575899ff92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10084294124093353374056217586151404031870664082381
7508865834660168033313709755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_all.1008429412409335337405621758615140403
18706640823817508865834660168033313709755
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1872084892103798086769604317186870312716026764975816721631924485791794955644
Short name T1005
Test name
Test status
Simulation time 997771563 ps
CPU time 8.76 seconds
Started Nov 22 02:22:48 PM PST 23
Finished Nov 22 02:22:57 PM PST 23
Peak memory 203064 kb
Host smart-364193e9-2ae7-4d5e-9ebd-78168b1f445a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872084892103798086769604317186870312716026764975816721631924485791794
955644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_rd.1872084892103798086769604317186870312716026764975816721631924
485791794955644
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.47886306421580059653199430623266371340483866254686367897408788513977950603629
Short name T178
Test name
Test status
Simulation time 14461449567 ps
CPU time 86.9 seconds
Started Nov 22 02:23:17 PM PST 23
Finished Nov 22 02:24:45 PM PST 23
Peak memory 1542088 kb
Host smart-9d189346-8475-4b7e-be0d-d457fcae45f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4788630642158005965319943062326637134048386625468636789740878851397795
0603629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_wr.478863064215800596531994306232663713404838662546863678974087
88513977950603629
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.98215659735955598306002220195818067483489549060969272723074103470359223735852
Short name T862
Test name
Test status
Simulation time 6281818576 ps
CPU time 76.02 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:24:39 PM PST 23
Peak memory 930484 kb
Host smart-98ad1423-6534-424a-aa0f-479322e60547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9821565973595559830600222019581806748348954906096927272307410347035922
3735852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stretch.9821565973595559830600222019581806748348954906096927272307410347
0359223735852
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.4666147987798943804832568159771043984362642122365829136906517075025885698053
Short name T681
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.46 seconds
Started Nov 22 02:23:01 PM PST 23
Finished Nov 22 02:23:09 PM PST 23
Peak memory 212512 kb
Host smart-a8ea73f4-8f3c-4470-ba74-4e6429c76202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466614798779894380483256815977104398436264212236582
9136906517075025885698053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_timeout.4666147987798943804832568159771043984362642122
365829136906517075025885698053
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_ovf.86328741168886941909183232138705285650637809258541034788952735946580522063874
Short name T824
Test name
Test status
Simulation time 5445414553 ps
CPU time 133.71 seconds
Started Nov 22 02:23:18 PM PST 23
Finished Nov 22 02:25:33 PM PST 23
Peak memory 406796 kb
Host smart-1a8c300f-69df-4a0c-b98e-26cf7128aca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86328741168886941909183232138705285650637809258541
034788952735946580522063874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_tx_ovf.8632874116888694190918323213870528565063780925
8541034788952735946580522063874
Directory /workspace/31.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.66772113608794557752625379687755141610979746743004270326983013030707215854101
Short name T1432
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.74 seconds
Started Nov 22 02:22:47 PM PST 23
Finished Nov 22 02:22:53 PM PST 23
Peak memory 205240 kb
Host smart-72a88616-d923-416a-88b0-757272e23190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667721136087945577526253796877551416109797467430042
70326983013030707215854101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_unexp_stop.66772113608794557752625379687755141610979
746743004270326983013030707215854101
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.17245213651864865986372047985224427171358870709787732321347310003123544304499
Short name T931
Test name
Test status
Simulation time 19975830 ps
CPU time 0.6 seconds
Started Nov 22 02:36:17 PM PST 23
Finished Nov 22 02:36:19 PM PST 23
Peak memory 202772 kb
Host smart-62381267-849e-481e-a276-7b68b3bc874b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245213651864865986372047985224427171358870709787732321347310003123544304499 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_alert_test.17245213651864865986372047985224427171358870709787732321347310003123544304499
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.101011497343182149024879191022156831411711170647468937736593096042799815915736
Short name T1008
Test name
Test status
Simulation time 74225396 ps
CPU time 1.35 seconds
Started Nov 22 02:35:46 PM PST 23
Finished Nov 22 02:35:48 PM PST 23
Peak memory 211252 kb
Host smart-159961cc-ba5b-4865-aa44-6adb5b37ea63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101011497343182149024879191022156831411711170647468937736593096042799815915736 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_host_error_intr.101011497343182149024879191022156831411711170647468937736593096042799815915736
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.44893172560410184574021260924323639715765098840201766563884840788660899611557
Short name T320
Test name
Test status
Simulation time 606667565 ps
CPU time 6.74 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:23:30 PM PST 23
Peak memory 273284 kb
Host smart-a1435115-0a31-42a9-ba2a-1cfc3e7abe77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44893172560410184574021260924323639715765098840201766563884840788660899611557 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.44893172560410184574021260924323639715765098840201766563884840788660899611557
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.43595678708554092851413216515277573483123278163393108319270205702971307147445
Short name T257
Test name
Test status
Simulation time 3768267272 ps
CPU time 72.47 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:24:34 PM PST 23
Peak memory 729484 kb
Host smart-6c852ece-f7a8-48f2-a839-17b500e23078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43595678708554092851413216515277573483123278163393108319270205702971307147445 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_host_fifo_full.43595678708554092851413216515277573483123278163393108319270205702971307147445
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.96577119413672957645236333982984337556191469287301786852434273247721345521560
Short name T314
Test name
Test status
Simulation time 7925734012 ps
CPU time 221.59 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:27:04 PM PST 23
Peak memory 1271540 kb
Host smart-e80f7551-d02b-4bd8-979a-04c98a2532a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96577119413672957645236333982984337556191469287301786852434273247721345521560 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.i2c_host_fifo_overflow.96577119413672957645236333982984337556191469287301786852434273247721345521560
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.43888578430446162470197332618671150894295451866960491815112287382456461960484
Short name T757
Test name
Test status
Simulation time 209010032 ps
CPU time 0.97 seconds
Started Nov 22 02:23:03 PM PST 23
Finished Nov 22 02:23:05 PM PST 23
Peak memory 202892 kb
Host smart-3483553e-8f29-478e-9ab7-c1f5be2c32be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43888578430446162470197332618671150894295451866960491815112287382456461960484 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.43888578430446162470197332618671150894295451866960491815112287382456461960484
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.61483469655247076341155361476039197631726228665331161857860708389676847143902
Short name T298
Test name
Test status
Simulation time 236313385 ps
CPU time 3.73 seconds
Started Nov 22 02:23:03 PM PST 23
Finished Nov 22 02:23:08 PM PST 23
Peak memory 225488 kb
Host smart-7e57b692-994d-4ae7-8fdd-bf70381e2a90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61483469655247076341155361476039197631726228665331161857860708389676847143902 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.61483469655247076341155361476039197631726228665331161857860708389676847143902
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.60849935794077734700407340507857640403355686713417051471943700208113046133354
Short name T1578
Test name
Test status
Simulation time 7918519784 ps
CPU time 212.95 seconds
Started Nov 22 02:23:19 PM PST 23
Finished Nov 22 02:26:54 PM PST 23
Peak memory 1310956 kb
Host smart-ae77eb61-9b50-4af1-8c5d-d5e28a09b216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60849935794077734700407340507857640403355686713417051471943700208113046133354 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.i2c_host_fifo_watermark.60849935794077734700407340507857640403355686713417051471943700208113046133354
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.102683718307533992598543476346058398363066428444743087872066132877867775849782
Short name T650
Test name
Test status
Simulation time 3754070957 ps
CPU time 48.56 seconds
Started Nov 22 02:36:17 PM PST 23
Finished Nov 22 02:37:06 PM PST 23
Peak memory 293672 kb
Host smart-145a6545-096d-4114-8e57-1d508b44a5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102683718307533992598543476346058398363066428444743087872066132877867775849782 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_host_mode_toggle.102683718307533992598543476346058398363066428444743087872066132877867775849782
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.74709183449133120219689277307044157422463878214430086081427865771797452531942
Short name T339
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:23:24 PM PST 23
Peak memory 202916 kb
Host smart-fef6985e-f981-4f68-9349-7fd138634611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74709183449133120219689277307044157422463878214430086081427865771797452531942 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_host_override.74709183449133120219689277307044157422463878214430086081427865771797452531942
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.96938803583123476872729927048094724036183544226075035880904298229581740924587
Short name T1316
Test name
Test status
Simulation time 6830796343 ps
CPU time 59.63 seconds
Started Nov 22 02:23:03 PM PST 23
Finished Nov 22 02:24:04 PM PST 23
Peak memory 211192 kb
Host smart-75bb3297-ae5d-4fe0-a0bc-fe9128d54bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96938803583123476872729927048094724036183544226075035880904298229581740924587 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.i2c_host_perf.96938803583123476872729927048094724036183544226075035880904298229581740924587
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_rx_oversample.16892127283938264453441584712486777495054820527907840409422475985899697496511
Short name T1175
Test name
Test status
Simulation time 3939158762 ps
CPU time 116.05 seconds
Started Nov 22 02:23:20 PM PST 23
Finished Nov 22 02:25:18 PM PST 23
Peak memory 345960 kb
Host smart-54fca340-84cb-4e1f-8e8f-921c6f7cc6ae
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16892127283938264453441584712486777495054820527907840409422475985899697496511 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_rx_oversample.16892127283938264453441584712486777495054820527907840409422475985899697496511
Directory /workspace/32.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.87114213566247369403206131674397404944842640018304120493490857580407542997492
Short name T213
Test name
Test status
Simulation time 2343171530 ps
CPU time 35.03 seconds
Started Nov 22 02:23:03 PM PST 23
Finished Nov 22 02:23:38 PM PST 23
Peak memory 299348 kb
Host smart-49d1ed10-5fb0-4ea4-87d5-c72b53b9e37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87114213566247369403206131674397404944842640018304120493490857580407542997492 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.i2c_host_smoke.87114213566247369403206131674397404944842640018304120493490857580407542997492
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.44261838236022354511880102864368011691497148872226532672034972129099539571857
Short name T963
Test name
Test status
Simulation time 32807463528 ps
CPU time 1172.23 seconds
Started Nov 22 02:35:48 PM PST 23
Finished Nov 22 02:55:21 PM PST 23
Peak memory 1957160 kb
Host smart-bbd0219c-ce35-4bcb-bec6-c853055dd724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44261838236022354511880102864368011691497148872226532672034972129099539571857 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_host_stress_all.44261838236022354511880102864368011691497148872226532672034972129099539571857
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.104360220512476764549225633228162720058758769118291850000872836019268537567174
Short name T1401
Test name
Test status
Simulation time 1466624971 ps
CPU time 14.42 seconds
Started Nov 22 02:35:48 PM PST 23
Finished Nov 22 02:36:03 PM PST 23
Peak memory 214248 kb
Host smart-7459e7ad-fc94-40c2-b14a-55de1ff92dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104360220512476764549225633228162720058758769118291850000872836019268537567174 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_host_stretch_timeout.104360220512476764549225633228162720058758769118291850000872836019268537567174
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.92825809795923851166307111898935058567867082725530383731309772223315969922775
Short name T1562
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.98 seconds
Started Nov 22 02:36:17 PM PST 23
Finished Nov 22 02:36:22 PM PST 23
Peak memory 203084 kb
Host smart-0f7a4e0f-27df-4b2f-b0ba-905e80b2b565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9282580979592385116630711189893
5058567867082725530383731309772223315969922775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.92825809795923851166307111
898935058567867082725530383731309772223315969922775
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.11592164614725129794568283273397329325257454687482909274586018022495740524657
Short name T694
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.13 seconds
Started Nov 22 02:36:16 PM PST 23
Finished Nov 22 02:36:47 PM PST 23
Peak memory 382268 kb
Host smart-c1a286e1-526f-40cf-9676-e6c39bc5832d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115921646147251297945682832733973293252574546874829
09274586018022495740524657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.1159216461472512979456828327339
7329325257454687482909274586018022495740524657
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.70008419929778155851877377452023638693813886871368098803073129690584060326996
Short name T1223
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.15 seconds
Started Nov 22 02:36:15 PM PST 23
Finished Nov 22 02:36:52 PM PST 23
Peak memory 462184 kb
Host smart-6fcc20fc-27cf-4f5f-aeab-f29a595dad00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700084199297781558518773774520236386938138868713680
98803073129690584060326996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_tx.700084199297781558518773774520236
38693813886871368098803073129690584060326996
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.52683473955627428378345055170796271190943455128692346579599309504922057575363
Short name T1514
Test name
Test status
Simulation time 825344371 ps
CPU time 2.42 seconds
Started Nov 22 02:36:29 PM PST 23
Finished Nov 22 02:36:32 PM PST 23
Peak memory 203016 kb
Host smart-ef2a4142-0567-439b-9cf6-bd3edb131ceb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526834739556274283783450551707962711909434551286923
46579599309504922057575363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_hrst.526834739556274283783450551707962711909434551286923
46579599309504922057575363
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.14150909274359002333375963275999008700266205374949921683585639849021737342155
Short name T1337
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.42 seconds
Started Nov 22 02:36:15 PM PST 23
Finished Nov 22 02:36:20 PM PST 23
Peak memory 203784 kb
Host smart-6925c7b3-f68a-4e13-aae7-309d516e2ec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14150909274359002333375963275999008700266205374949
921683585639849021737342155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_smoke.1415090927435900233337596327599900870026620
5374949921683585639849021737342155
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.37259716471643269295188272392707198349191210072473159632838758476375024137129
Short name T425
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.87 seconds
Started Nov 22 02:36:03 PM PST 23
Finished Nov 22 02:36:27 PM PST 23
Peak memory 639272 kb
Host smart-23552197-be52-461f-9dec-d9f1852f0de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37259716471643269295188272392707198349
191210072473159632838758476375024137129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.37259716471643269295188
272392707198349191210072473159632838758476375024137129
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.9676990018020550751777948039013160205503954594399389240965278386618416730347
Short name T710
Test name
Test status
Simulation time 834576440 ps
CPU time 2.98 seconds
Started Nov 22 02:36:04 PM PST 23
Finished Nov 22 02:36:08 PM PST 23
Peak memory 203060 kb
Host smart-7d628116-28df-4363-bb74-b84cd0c52dcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967699001802055075177794803901316020550395459439938
9240965278386618416730347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_perf.9676990018020550751777948039013160205503954594399389
240965278386618416730347
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.50534080865530332383528136546595267900264997015340540522002329357376414526500
Short name T816
Test name
Test status
Simulation time 1504713936 ps
CPU time 8.99 seconds
Started Nov 22 02:36:02 PM PST 23
Finished Nov 22 02:36:12 PM PST 23
Peak memory 203044 kb
Host smart-e06f012e-7df7-46b2-a30e-63523164b98a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5053408086553033238352813654659526790026499701534054052200232935737641
4526500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smoke.50534080865530332383528136546595267900264997015340540522002329357376414526500
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.57221053824587617737135235113530125566109518864208742956907880043653138473163
Short name T229
Test name
Test status
Simulation time 66540157934 ps
CPU time 1663.21 seconds
Started Nov 22 02:36:15 PM PST 23
Finished Nov 22 03:03:59 PM PST 23
Peak memory 6983444 kb
Host smart-504c7513-99b2-4ea8-86e1-f1b2fcf0fad3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57221053824587617737135235113530125566109518864208
742956907880043653138473163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_all.57221053824587617737135235113530125566
109518864208742956907880043653138473163
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.7803955127289381686638593202709549403304452336157550210382162006247383588546
Short name T1503
Test name
Test status
Simulation time 997771563 ps
CPU time 8.16 seconds
Started Nov 22 02:36:03 PM PST 23
Finished Nov 22 02:36:12 PM PST 23
Peak memory 203068 kb
Host smart-ec9d0b7c-7ce1-47fa-a6c7-c66ee68b8c11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7803955127289381686638593202709549403304452336157550210382162006247383
588546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_rd.7803955127289381686638593202709549403304452336157550210382162
006247383588546
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.86190609336083811792878594136177874969094017562629268233898691007258757106111
Short name T393
Test name
Test status
Simulation time 14461449567 ps
CPU time 89.5 seconds
Started Nov 22 02:36:17 PM PST 23
Finished Nov 22 02:37:47 PM PST 23
Peak memory 1542156 kb
Host smart-d520ac55-7518-41f8-8f68-f4cd00bfef2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8619060933608381179287859413617787496909401756262926823389869100725875
7106111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_wr.861906093360838117928785941361778749690940175626292682338986
91007258757106111
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.94450585675273122641955447285220223079516239417348480564491972485835280929719
Short name T606
Test name
Test status
Simulation time 6281818576 ps
CPU time 73.1 seconds
Started Nov 22 02:36:02 PM PST 23
Finished Nov 22 02:37:16 PM PST 23
Peak memory 930636 kb
Host smart-a1366e17-0627-49dc-b20e-fc7b1b1db191
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9445058567527312264195544728522022307951623941734848056449197248583528
0929719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stretch.9445058567527312264195544728522022307951623941734848056449197248
5835280929719
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3525976273324642615070460899516097054545608936043547018414738963936363072171
Short name T705
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.78 seconds
Started Nov 22 02:36:04 PM PST 23
Finished Nov 22 02:36:12 PM PST 23
Peak memory 212636 kb
Host smart-2a65424e-1bd4-46a3-b548-93ace8dca7d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352597627332464261507046089951609705454560893604354
7018414738963936363072171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_timeout.3525976273324642615070460899516097054545608936
043547018414738963936363072171
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_ovf.98281406155238100112387600489184949041038777153887956516656015884241754777217
Short name T1434
Test name
Test status
Simulation time 5445414553 ps
CPU time 160.18 seconds
Started Nov 22 02:36:15 PM PST 23
Finished Nov 22 02:38:56 PM PST 23
Peak memory 406880 kb
Host smart-00224d57-1234-441b-af95-be34e8c96609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98281406155238100112387600489184949041038777153887
956516656015884241754777217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_tx_ovf.9828140615523810011238760048918494904103877715
3887956516656015884241754777217
Directory /workspace/32.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.61366822364859256461326537749662568533100090933660613079315603242621968445567
Short name T569
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.7 seconds
Started Nov 22 02:36:02 PM PST 23
Finished Nov 22 02:36:08 PM PST 23
Peak memory 205364 kb
Host smart-defc05b0-2db0-41ee-954e-c587211caaaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613668223648592564613265377496625685331000909336606
13079315603242621968445567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_unexp_stop.61366822364859256461326537749662568533100
090933660613079315603242621968445567
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.19118470320943573208838487183370323596120648679043514955223677902413179561439
Short name T955
Test name
Test status
Simulation time 19975830 ps
CPU time 0.56 seconds
Started Nov 22 02:36:44 PM PST 23
Finished Nov 22 02:36:45 PM PST 23
Peak memory 202816 kb
Host smart-04ececdf-f763-478a-840c-84b6b247df08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19118470320943573208838487183370323596120648679043514955223677902413179561439 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_alert_test.19118470320943573208838487183370323596120648679043514955223677902413179561439
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.77310601925055353357656543381609992476988424803064364036602486204248575639611
Short name T152
Test name
Test status
Simulation time 74225396 ps
CPU time 1.39 seconds
Started Nov 22 02:36:44 PM PST 23
Finished Nov 22 02:36:46 PM PST 23
Peak memory 211372 kb
Host smart-e7e96910-721c-4942-b02b-930bf7bd3bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77310601925055353357656543381609992476988424803064364036602486204248575639611 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_host_error_intr.77310601925055353357656543381609992476988424803064364036602486204248575639611
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.97524344618545208616720493546979183806094332823856566614732319615248262172227
Short name T1235
Test name
Test status
Simulation time 606667565 ps
CPU time 6.32 seconds
Started Nov 22 02:36:16 PM PST 23
Finished Nov 22 02:36:23 PM PST 23
Peak memory 273288 kb
Host smart-0b8368cc-5abb-4c14-9cb1-54e3c545026e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97524344618545208616720493546979183806094332823856566614732319615248262172227 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.97524344618545208616720493546979183806094332823856566614732319615248262172227
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.24769678647812681075231288433427950314248400254384200863738828631051840261986
Short name T244
Test name
Test status
Simulation time 3768267272 ps
CPU time 73.82 seconds
Started Nov 22 02:36:13 PM PST 23
Finished Nov 22 02:37:27 PM PST 23
Peak memory 729460 kb
Host smart-3344a82f-6798-4421-ae40-1851da123d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24769678647812681075231288433427950314248400254384200863738828631051840261986 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_host_fifo_full.24769678647812681075231288433427950314248400254384200863738828631051840261986
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.59416162552540162573178032649172646917220880909302294325307230870084246508455
Short name T1220
Test name
Test status
Simulation time 7925734012 ps
CPU time 207.27 seconds
Started Nov 22 02:36:15 PM PST 23
Finished Nov 22 02:39:43 PM PST 23
Peak memory 1271444 kb
Host smart-f1c84cc4-6fa7-4773-98ef-8acfea7c61ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59416162552540162573178032649172646917220880909302294325307230870084246508455 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.i2c_host_fifo_overflow.59416162552540162573178032649172646917220880909302294325307230870084246508455
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.56557870085007022379297340506647194243919617844745355901476772088341418190350
Short name T299
Test name
Test status
Simulation time 209010032 ps
CPU time 0.94 seconds
Started Nov 22 02:36:16 PM PST 23
Finished Nov 22 02:36:17 PM PST 23
Peak memory 202964 kb
Host smart-b66765d9-94ac-4b99-8df2-c3d4f4703091
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56557870085007022379297340506647194243919617844745355901476772088341418190350 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.56557870085007022379297340506647194243919617844745355901476772088341418190350
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.30642189936623712918487373921582834743594039743011648999487840998945969030541
Short name T635
Test name
Test status
Simulation time 236313385 ps
CPU time 3.93 seconds
Started Nov 22 02:36:18 PM PST 23
Finished Nov 22 02:36:22 PM PST 23
Peak memory 225552 kb
Host smart-4a77b01c-de07-4adc-941a-bd65faab0fc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30642189936623712918487373921582834743594039743011648999487840998945969030541 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.30642189936623712918487373921582834743594039743011648999487840998945969030541
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.75563862256786900070952620542663128338813800969624435253183110132729066307593
Short name T1444
Test name
Test status
Simulation time 7918519784 ps
CPU time 219.55 seconds
Started Nov 22 02:36:18 PM PST 23
Finished Nov 22 02:39:58 PM PST 23
Peak memory 1311024 kb
Host smart-11ce8cdf-73b4-43e2-90ac-ce00e50941fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75563862256786900070952620542663128338813800969624435253183110132729066307593 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_host_fifo_watermark.75563862256786900070952620542663128338813800969624435253183110132729066307593
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.675162779163659651797813948318199305466038512840611193512745870603277283436
Short name T633
Test name
Test status
Simulation time 3754070957 ps
CPU time 50.49 seconds
Started Nov 22 02:36:41 PM PST 23
Finished Nov 22 02:37:32 PM PST 23
Peak memory 293756 kb
Host smart-43dadafe-bcf8-490f-a6ae-473994b140b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675162779163659651797813948318199305466038512840611193512745870603277283436 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_host_mode_toggle.675162779163659651797813948318199305466038512840611193512745870603277283436
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.23846936626923970535409054793655529690685121549975862716813293863537276820738
Short name T21
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:36:14 PM PST 23
Finished Nov 22 02:36:15 PM PST 23
Peak memory 202912 kb
Host smart-623c5858-66da-4ab1-ba03-1fe6d510c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23846936626923970535409054793655529690685121549975862716813293863537276820738 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_host_override.23846936626923970535409054793655529690685121549975862716813293863537276820738
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.17699545418819173838968726850861397976960594095014491053860750048992452165560
Short name T507
Test name
Test status
Simulation time 6830796343 ps
CPU time 63.3 seconds
Started Nov 22 02:36:19 PM PST 23
Finished Nov 22 02:37:22 PM PST 23
Peak memory 211400 kb
Host smart-0c5ef3dd-87e1-4ca1-bc30-2faf0498af58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17699545418819173838968726850861397976960594095014491053860750048992452165560 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.i2c_host_perf.17699545418819173838968726850861397976960594095014491053860750048992452165560
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_rx_oversample.98718702189856889751252044870799020431413605432336870576830490826154927727988
Short name T767
Test name
Test status
Simulation time 3939158762 ps
CPU time 111.3 seconds
Started Nov 22 02:36:16 PM PST 23
Finished Nov 22 02:38:08 PM PST 23
Peak memory 345816 kb
Host smart-5e59fe38-5c9c-4438-b520-1802cc20dc4c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98718702189856889751252044870799020431413605432336870576830490826154927727988 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_rx_oversample.98718702189856889751252044870799020431413605432336870576830490826154927727988
Directory /workspace/33.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.57633992253723726172143060643648459015232929210074379822330779492486086065979
Short name T3
Test name
Test status
Simulation time 2343171530 ps
CPU time 36.5 seconds
Started Nov 22 02:36:28 PM PST 23
Finished Nov 22 02:37:06 PM PST 23
Peak memory 299392 kb
Host smart-f4c34da7-e64e-437a-92cc-26e7e672b076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57633992253723726172143060643648459015232929210074379822330779492486086065979 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.i2c_host_smoke.57633992253723726172143060643648459015232929210074379822330779492486086065979
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.48787264030890963113375420659969564455566029758567521011314363360194768104329
Short name T1293
Test name
Test status
Simulation time 32807463528 ps
CPU time 1151.09 seconds
Started Nov 22 02:36:17 PM PST 23
Finished Nov 22 02:55:29 PM PST 23
Peak memory 1957004 kb
Host smart-4615d221-7d78-4a6d-b8f1-88f56c0e4211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48787264030890963113375420659969564455566029758567521011314363360194768104329 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_host_stress_all.48787264030890963113375420659969564455566029758567521011314363360194768104329
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.60077604603937388112578718529221049183284909862254072660813454108508136989164
Short name T1280
Test name
Test status
Simulation time 1466624971 ps
CPU time 12.85 seconds
Started Nov 22 02:36:43 PM PST 23
Finished Nov 22 02:36:56 PM PST 23
Peak memory 214256 kb
Host smart-e19e2b1a-44e6-4ee9-9c5a-9124fa6b75b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60077604603937388112578718529221049183284909862254072660813454108508136989164 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_host_stretch_timeout.60077604603937388112578718529221049183284909862254072660813454108508136989164
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.49202235232903820617344885287465884730936433217947988354799819190837332094587
Short name T282
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.69 seconds
Started Nov 22 02:36:32 PM PST 23
Finished Nov 22 02:36:36 PM PST 23
Peak memory 203040 kb
Host smart-fd98bfa7-e978-4c09-9972-5331d7f9d3f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4920223523290382061734488528746
5884730936433217947988354799819190837332094587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.49202235232903820617344885
287465884730936433217947988354799819190837332094587
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.45997217634860169032121777605440876818925675241391421298666033518482130519774
Short name T1516
Test name
Test status
Simulation time 10166144644 ps
CPU time 30.56 seconds
Started Nov 22 02:36:44 PM PST 23
Finished Nov 22 02:37:15 PM PST 23
Peak memory 382224 kb
Host smart-556a3a04-42e1-4a9b-b2f1-4c80adbd7407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459972176348601690321217776054408768189256752413914
21298666033518482130519774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_acq.4599721763486016903212177760544
0876818925675241391421298666033518482130519774
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.10355151199259358197243586356276628685350724634137321574650236618083477021933
Short name T796
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.87 seconds
Started Nov 22 02:36:41 PM PST 23
Finished Nov 22 02:37:19 PM PST 23
Peak memory 462116 kb
Host smart-562e0a16-c464-4701-b6a7-829e9aa6f194
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103551511992593581972435863562766286853507246341373
21574650236618083477021933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_tx.103551511992593581972435863562766
28685350724634137321574650236618083477021933
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.105417824346748279220246153319522278270746341841130155657245450896870984224525
Short name T539
Test name
Test status
Simulation time 825344371 ps
CPU time 2.46 seconds
Started Nov 22 02:36:43 PM PST 23
Finished Nov 22 02:36:46 PM PST 23
Peak memory 203036 kb
Host smart-a1f057e0-5aa7-465b-9352-18527004e24e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105417824346748279220246153319522278270746341841130
155657245450896870984224525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_hrst.10541782434674827922024615331952227827074634184113
0155657245450896870984224525
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.72087884844994197322347110666613091981501234357684493999997905053764493715831
Short name T588
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.22 seconds
Started Nov 22 02:36:29 PM PST 23
Finished Nov 22 02:36:34 PM PST 23
Peak memory 203640 kb
Host smart-9fce6300-d8b8-405e-b932-7aa84a109ddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72087884844994197322347110666613091981501234357684
493999997905053764493715831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_smoke.7208788484499419732234711066661309198150123
4357684493999997905053764493715831
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.54540520685743453070984416966049924672747378983235467436583398230945782453693
Short name T1277
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.03 seconds
Started Nov 22 02:36:28 PM PST 23
Finished Nov 22 02:36:51 PM PST 23
Peak memory 639152 kb
Host smart-8f937538-6503-4c21-aa55-b3c50f5d5166
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54540520685743453070984416966049924672
747378983235467436583398230945782453693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.54540520685743453070984
416966049924672747378983235467436583398230945782453693
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.91958323794198620360230062785873312562740427327679431917631112731576011563264
Short name T1034
Test name
Test status
Simulation time 834576440 ps
CPU time 2.89 seconds
Started Nov 22 02:36:32 PM PST 23
Finished Nov 22 02:36:36 PM PST 23
Peak memory 203024 kb
Host smart-4a3923bd-a864-4665-9cd6-e0306048300a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919583237941986203602300627858733125627404273276794
31917631112731576011563264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_perf.919583237941986203602300627858733125627404273276794
31917631112731576011563264
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.109610519845401592772631607923093158279221224904117795581447184331495945909192
Short name T610
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.13 seconds
Started Nov 22 02:36:43 PM PST 23
Finished Nov 22 02:36:53 PM PST 23
Peak memory 203084 kb
Host smart-4df49038-2701-47ee-be8b-5a762cc452a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096105198454015927726316079230931582792212249041177955814471843314959
45909192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smoke.109610519845401592772631607923093158279221224904117795581447184331495945909192
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.72616691479008745377404615037200902441643182286231752643271450274839290036411
Short name T1362
Test name
Test status
Simulation time 66540157934 ps
CPU time 1603.51 seconds
Started Nov 22 02:36:32 PM PST 23
Finished Nov 22 03:03:16 PM PST 23
Peak memory 6983384 kb
Host smart-d413cd8f-7475-45c6-9c03-d7d7a2277c88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72616691479008745377404615037200902441643182286231
752643271450274839290036411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_all.72616691479008745377404615037200902441
643182286231752643271450274839290036411
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.29805419069761430477242651753791741520256134096321723156393051469122420225365
Short name T760
Test name
Test status
Simulation time 997771563 ps
CPU time 8.78 seconds
Started Nov 22 02:36:43 PM PST 23
Finished Nov 22 02:36:53 PM PST 23
Peak memory 203012 kb
Host smart-f3275473-a5fc-4035-9205-bed8da9ef650
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980541906976143047724265175379174152025613409632172315639305146912242
0225365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_rd.298054190697614304772426517537917415202561340963217231563930
51469122420225365
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.99902938703237007409591373051236026845049659074907631316806482125987986360937
Short name T759
Test name
Test status
Simulation time 14461449567 ps
CPU time 86.07 seconds
Started Nov 22 02:36:19 PM PST 23
Finished Nov 22 02:37:46 PM PST 23
Peak memory 1542172 kb
Host smart-b24ef2ac-23a1-44de-aa7f-1a40f014e01a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9990293870323700740959137305123602684504965907490763131680648212598798
6360937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_wr.999029387032370074095913730512360268450496590749076313168064
82125987986360937
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.66147937820552682520437075901208110668174031066108287908273611576771231939310
Short name T1447
Test name
Test status
Simulation time 6281818576 ps
CPU time 78.9 seconds
Started Nov 22 02:36:40 PM PST 23
Finished Nov 22 02:37:59 PM PST 23
Peak memory 930636 kb
Host smart-19943a42-1194-429e-88bd-48e6c0dc6a9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6614793782055268252043707590120811066817403106610828790827361157677123
1939310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stretch.6614793782055268252043707590120811066817403106610828790827361157
6771231939310
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.31436311026241580539373426295674485659956631554889209115872154541921569940836
Short name T356
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.37 seconds
Started Nov 22 02:36:31 PM PST 23
Finished Nov 22 02:36:39 PM PST 23
Peak memory 212632 kb
Host smart-f25f54b2-ff11-4dde-8d99-1eb333389154
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314363110262415805393734262956744856599566315548892
09115872154541921569940836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_timeout.314363110262415805393734262956744856599566315
54889209115872154541921569940836
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_ovf.29573737316969858364011825051946573299259864907694773487526462739676514867407
Short name T1543
Test name
Test status
Simulation time 5445414553 ps
CPU time 120.33 seconds
Started Nov 22 02:36:28 PM PST 23
Finished Nov 22 02:38:29 PM PST 23
Peak memory 406736 kb
Host smart-c859b849-9342-4e66-99ad-5a7777478b2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29573737316969858364011825051946573299259864907694
773487526462739676514867407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_tx_ovf.2957373731696985836401182505194657329925986490
7694773487526462739676514867407
Directory /workspace/33.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.57545105201318453403726273047885138071919539980845978348194881592824638920076
Short name T51
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.52 seconds
Started Nov 22 02:36:31 PM PST 23
Finished Nov 22 02:36:37 PM PST 23
Peak memory 205328 kb
Host smart-210d066f-332f-4008-bd71-ef0a07117b09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575451052013184534037262730478851380719195399808459
78348194881592824638920076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_unexp_stop.57545105201318453403726273047885138071919
539980845978348194881592824638920076
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.65817362229027116641500787687682303337609832403469665126796717117728676497217
Short name T416
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:37:44 PM PST 23
Peak memory 202768 kb
Host smart-b2964a9c-f917-47f8-9462-c22e4b4736e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65817362229027116641500787687682303337609832403469665126796717117728676497217 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_alert_test.65817362229027116641500787687682303337609832403469665126796717117728676497217
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.95501966517606633737191738948803324231236965513529464923892590823360130749985
Short name T230
Test name
Test status
Simulation time 74225396 ps
CPU time 1.33 seconds
Started Nov 22 02:36:58 PM PST 23
Finished Nov 22 02:37:01 PM PST 23
Peak memory 211220 kb
Host smart-159f74f2-7fd4-4fb9-9547-6a6b9ae8b354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95501966517606633737191738948803324231236965513529464923892590823360130749985 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_host_error_intr.95501966517606633737191738948803324231236965513529464923892590823360130749985
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.50271152294903797854142915201393458808547567012809260042024863662373314136350
Short name T1126
Test name
Test status
Simulation time 606667565 ps
CPU time 6.82 seconds
Started Nov 22 02:37:08 PM PST 23
Finished Nov 22 02:37:17 PM PST 23
Peak memory 273412 kb
Host smart-85430761-9578-43e7-9bb4-32835b19c4ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50271152294903797854142915201393458808547567012809260042024863662373314136350 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.50271152294903797854142915201393458808547567012809260042024863662373314136350
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.110691958083329808117689125794902427741458488946442236298451978654208087427852
Short name T1100
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.83 seconds
Started Nov 22 02:37:37 PM PST 23
Finished Nov 22 02:38:53 PM PST 23
Peak memory 729380 kb
Host smart-0dad1320-bd52-4479-9893-e73965ed2923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110691958083329808117689125794902427741458488946442236298451978654208087427852 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_host_fifo_full.110691958083329808117689125794902427741458488946442236298451978654208087427852
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.29214244729521749126213043025522351592725647466184314531943275647957757227872
Short name T904
Test name
Test status
Simulation time 7925734012 ps
CPU time 211.52 seconds
Started Nov 22 02:37:36 PM PST 23
Finished Nov 22 02:41:08 PM PST 23
Peak memory 1271616 kb
Host smart-356416a7-c048-4f9a-8796-d915836b0cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29214244729521749126213043025522351592725647466184314531943275647957757227872 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.i2c_host_fifo_overflow.29214244729521749126213043025522351592725647466184314531943275647957757227872
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.44294663238635570081171936762436684416377768074871645474670076763648430120319
Short name T834
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:37:37 PM PST 23
Finished Nov 22 02:37:39 PM PST 23
Peak memory 202836 kb
Host smart-bbeb4fec-b102-46e9-a227-f5ec2d53df5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44294663238635570081171936762436684416377768074871645474670076763648430120319 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.44294663238635570081171936762436684416377768074871645474670076763648430120319
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.46202375065709407027552855489748125422675454452376109903035766233743060944718
Short name T1281
Test name
Test status
Simulation time 236313385 ps
CPU time 3.85 seconds
Started Nov 22 02:37:10 PM PST 23
Finished Nov 22 02:37:17 PM PST 23
Peak memory 225552 kb
Host smart-e6d86d7f-08b9-4545-a45b-0ac122b5b066
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46202375065709407027552855489748125422675454452376109903035766233743060944718 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.46202375065709407027552855489748125422675454452376109903035766233743060944718
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.21220224918965354103091992443999289286572858103882502953507613614589778727356
Short name T537
Test name
Test status
Simulation time 7918519784 ps
CPU time 208.67 seconds
Started Nov 22 02:36:45 PM PST 23
Finished Nov 22 02:40:15 PM PST 23
Peak memory 1311004 kb
Host smart-f9e67e57-3d6b-4674-9efc-1842c0810144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21220224918965354103091992443999289286572858103882502953507613614589778727356 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_host_fifo_watermark.21220224918965354103091992443999289286572858103882502953507613614589778727356
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.64671035758563661886047228498602961856335984622982033842485919847747674778536
Short name T848
Test name
Test status
Simulation time 3754070957 ps
CPU time 55.35 seconds
Started Nov 22 02:37:35 PM PST 23
Finished Nov 22 02:38:31 PM PST 23
Peak memory 293828 kb
Host smart-463199ce-c27c-4720-96cd-37a795de5344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64671035758563661886047228498602961856335984622982033842485919847747674778536 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_host_mode_toggle.64671035758563661886047228498602961856335984622982033842485919847747674778536
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.94581717656887783965392993914639320605502903665058847897688218470220051034382
Short name T1396
Test name
Test status
Simulation time 23672229 ps
CPU time 0.68 seconds
Started Nov 22 02:37:09 PM PST 23
Finished Nov 22 02:37:14 PM PST 23
Peak memory 202900 kb
Host smart-3e4b1365-40db-41cd-88d1-9427b820a955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94581717656887783965392993914639320605502903665058847897688218470220051034382 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_host_override.94581717656887783965392993914639320605502903665058847897688218470220051034382
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.103879053751924530512562350546318365152293947519301237113157898465591163179951
Short name T911
Test name
Test status
Simulation time 6830796343 ps
CPU time 59.58 seconds
Started Nov 22 02:37:01 PM PST 23
Finished Nov 22 02:38:01 PM PST 23
Peak memory 211368 kb
Host smart-0d10508c-3858-4e29-bcaf-0e4597f06e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103879053751924530512562350546318365152293947519301237113157898465591163179951 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.i2c_host_perf.103879053751924530512562350546318365152293947519301237113157898465591163179951
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_rx_oversample.39602904281426258448233135830375785945280753070204383987763645136815796348170
Short name T803
Test name
Test status
Simulation time 3939158762 ps
CPU time 105.49 seconds
Started Nov 22 02:37:50 PM PST 23
Finished Nov 22 02:39:36 PM PST 23
Peak memory 345968 kb
Host smart-ac0edb61-8118-4a3a-92e4-145f8e86a03e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39602904281426258448233135830375785945280753070204383987763645136815796348170 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_rx_oversample.39602904281426258448233135830375785945280753070204383987763645136815796348170
Directory /workspace/34.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.34852224481790106027243344924634897399361795521633905853693755725750198917180
Short name T674
Test name
Test status
Simulation time 2343171530 ps
CPU time 39.32 seconds
Started Nov 22 02:36:42 PM PST 23
Finished Nov 22 02:37:22 PM PST 23
Peak memory 299400 kb
Host smart-e5b6641e-6e3f-4f4e-9f01-3285393bd5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34852224481790106027243344924634897399361795521633905853693755725750198917180 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.i2c_host_smoke.34852224481790106027243344924634897399361795521633905853693755725750198917180
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.87926207732383896113011559191269355399598126380022489248995380938344479298284
Short name T155
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.06 seconds
Started Nov 22 02:37:08 PM PST 23
Finished Nov 22 02:37:23 PM PST 23
Peak memory 214172 kb
Host smart-49169104-0503-411e-9b84-e31885d68dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87926207732383896113011559191269355399598126380022489248995380938344479298284 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_host_stretch_timeout.87926207732383896113011559191269355399598126380022489248995380938344479298284
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.67931917776831492663976757409053910629664081604119094414695885855447815546130
Short name T1308
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.66 seconds
Started Nov 22 02:36:56 PM PST 23
Finished Nov 22 02:37:01 PM PST 23
Peak memory 203092 kb
Host smart-fa288809-286e-4638-a720-d0731ef195e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6793191777683149266397675740905
3910629664081604119094414695885855447815546130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.67931917776831492663976757
409053910629664081604119094414695885855447815546130
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.8129917938956287865265872194696823772983302709272861294474360379626635245524
Short name T1510
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.01 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:38:15 PM PST 23
Peak memory 381996 kb
Host smart-96d95ad2-1a01-451b-88bf-f03dc055d5b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812991793895628786526587219469682377298330270927286
1294474360379626635245524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.81299179389562878652658721946968
23772983302709272861294474360379626635245524
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.58228355273413792269230349493133879730057422940873653397687691146267235469209
Short name T457
Test name
Test status
Simulation time 10065199023 ps
CPU time 37.94 seconds
Started Nov 22 02:37:40 PM PST 23
Finished Nov 22 02:38:18 PM PST 23
Peak memory 462104 kb
Host smart-c8334feb-ad3f-476d-b0dd-1fa7ec115106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582283552734137922692303494931338797300574229408736
53397687691146267235469209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_tx.582283552734137922692303494931338
79730057422940873653397687691146267235469209
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.18645161161798147100474076795258996517945993995709677571566851120884956721934
Short name T106
Test name
Test status
Simulation time 825344371 ps
CPU time 2.42 seconds
Started Nov 22 02:37:39 PM PST 23
Finished Nov 22 02:37:42 PM PST 23
Peak memory 203036 kb
Host smart-ccae3e0c-d6fe-41b8-867c-2653a3e43b14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186451611617981471004740767952589965179459939957096
77571566851120884956721934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_hrst.186451611617981471004740767952589965179459939957096
77571566851120884956721934
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.88950204609490853335950542272054038817092573746883451567661896173720846417557
Short name T264
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.37 seconds
Started Nov 22 02:37:38 PM PST 23
Finished Nov 22 02:37:43 PM PST 23
Peak memory 203716 kb
Host smart-e54775f3-92d1-4a20-aa8e-4c097ea19c0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88950204609490853335950542272054038817092573746883
451567661896173720846417557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.8895020460949085333595054227205403881709257
3746883451567661896173720846417557
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.20085917964740852240509897638288675842675461840187393221748315005920263324330
Short name T630
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.76 seconds
Started Nov 22 02:36:56 PM PST 23
Finished Nov 22 02:37:19 PM PST 23
Peak memory 639272 kb
Host smart-18d1d553-ba59-4b54-8268-1afd7752b93e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20085917964740852240509897638288675842
675461840187393221748315005920263324330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.20085917964740852240509
897638288675842675461840187393221748315005920263324330
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_perf.79366853017547869453942685295267133763340809759888199504766862357347266397185
Short name T477
Test name
Test status
Simulation time 834576440 ps
CPU time 2.98 seconds
Started Nov 22 02:37:39 PM PST 23
Finished Nov 22 02:37:43 PM PST 23
Peak memory 203084 kb
Host smart-84ef81ff-1df6-496e-b19f-c1edd92a47ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793668530175478694539426852952671337633408097598881
99504766862357347266397185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_perf.793668530175478694539426852952671337633408097598881
99504766862357347266397185
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.94642690547677423540338151476220527087744010777247577233394227796936514698402
Short name T1298
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.38 seconds
Started Nov 22 02:37:37 PM PST 23
Finished Nov 22 02:37:48 PM PST 23
Peak memory 202972 kb
Host smart-e787b58a-6cba-4a7d-b19a-5826c4909782
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9464269054767742354033815147622052708774401077724757723339422779693651
4698402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smoke.94642690547677423540338151476220527087744010777247577233394227796936514698402
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.73418813590376502275506582191902717177399920976347130048585662218332519082181
Short name T1178
Test name
Test status
Simulation time 66540157934 ps
CPU time 1556.57 seconds
Started Nov 22 02:36:58 PM PST 23
Finished Nov 22 03:02:57 PM PST 23
Peak memory 6983432 kb
Host smart-4157a9ef-fda4-4d71-a3ad-d0a681cd7273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73418813590376502275506582191902717177399920976347
130048585662218332519082181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_all.73418813590376502275506582191902717177
399920976347130048585662218332519082181
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.35412685369363313307771295501886991263930775773396509589404201092573854836818
Short name T1387
Test name
Test status
Simulation time 997771563 ps
CPU time 8.48 seconds
Started Nov 22 02:37:43 PM PST 23
Finished Nov 22 02:37:52 PM PST 23
Peak memory 203032 kb
Host smart-bd4e380e-b89b-4d9c-862b-600bd5733cd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541268536936331330777129550188699126393077577339650958940420109257385
4836818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_rd.354126853693633133077712955018869912639307757733965095894042
01092573854836818
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.76931446974596756742660433984323164437107990579757743296947162123259549063375
Short name T336
Test name
Test status
Simulation time 14461449567 ps
CPU time 83.06 seconds
Started Nov 22 02:36:58 PM PST 23
Finished Nov 22 02:38:23 PM PST 23
Peak memory 1542164 kb
Host smart-004cf5cc-f56e-4b4c-ade5-49b99c77777f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7693144697459675674266043398432316443710799057975774329694716212325954
9063375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_wr.769314469745967567426604339843231644371079905797577432969471
62123259549063375
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.109193765859992020184284711838966346271960904088133135194813931708149959598249
Short name T677
Test name
Test status
Simulation time 6281818576 ps
CPU time 79.81 seconds
Started Nov 22 02:37:36 PM PST 23
Finished Nov 22 02:38:57 PM PST 23
Peak memory 930604 kb
Host smart-91bdf71c-5bcf-4636-b76f-69dbbeb0ef17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091937658599920201842847118389663462719609040881331351948139317081499
59598249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stretch.109193765859992020184284711838966346271960904088133135194813931
708149959598249
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.41603655480195404310975526532810444101662897823319550628023229266287247521746
Short name T732
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.32 seconds
Started Nov 22 02:37:38 PM PST 23
Finished Nov 22 02:37:46 PM PST 23
Peak memory 212676 kb
Host smart-6c332c6b-bf79-49d9-8fab-9b13560dbc6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416036554801954043109755265328104441016628978233195
50628023229266287247521746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_timeout.416036554801954043109755265328104441016628978
23319550628023229266287247521746
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_ovf.57934931961903271547030153074966419566990373413583272498678618324796936093944
Short name T98
Test name
Test status
Simulation time 5445414553 ps
CPU time 133.59 seconds
Started Nov 22 02:37:39 PM PST 23
Finished Nov 22 02:39:53 PM PST 23
Peak memory 406800 kb
Host smart-76fbb7a9-eec6-4c0b-9943-78fcebe5b5f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57934931961903271547030153074966419566990373413583
272498678618324796936093944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_tx_ovf.5793493196190327154703015307496641956699037341
3583272498678618324796936093944
Directory /workspace/34.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.87528960163055979043255815519415123199232372702915611267814764179337952411758
Short name T188
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.7 seconds
Started Nov 22 02:37:39 PM PST 23
Finished Nov 22 02:37:45 PM PST 23
Peak memory 205336 kb
Host smart-18138839-aa69-4edd-9133-911277ca3d3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875289601630559790432558155194151231992323727029156
11267814764179337952411758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_unexp_stop.87528960163055979043255815519415123199232
372702915611267814764179337952411758
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.65458624995646237169613410169520429934857046246819543125052985093086764500371
Short name T25
Test name
Test status
Simulation time 19975830 ps
CPU time 0.61 seconds
Started Nov 22 02:37:57 PM PST 23
Finished Nov 22 02:37:59 PM PST 23
Peak memory 202708 kb
Host smart-8e48f208-9bcc-4450-9c7f-42f9c282b6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65458624995646237169613410169520429934857046246819543125052985093086764500371 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_alert_test.65458624995646237169613410169520429934857046246819543125052985093086764500371
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1853996197188251521034562776155713381152895572068370195318196454971619199218
Short name T847
Test name
Test status
Simulation time 74225396 ps
CPU time 1.33 seconds
Started Nov 22 02:37:10 PM PST 23
Finished Nov 22 02:37:15 PM PST 23
Peak memory 211340 kb
Host smart-8a6a2735-b9d5-4c28-9abe-2e23b4456193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853996197188251521034562776155713381152895572068370195318196454971619199218 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_host_error_intr.1853996197188251521034562776155713381152895572068370195318196454971619199218
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.102949978038201717270905918180638240280490538699029313645224610165999421775367
Short name T1349
Test name
Test status
Simulation time 606667565 ps
CPU time 6.81 seconds
Started Nov 22 02:37:50 PM PST 23
Finished Nov 22 02:37:58 PM PST 23
Peak memory 273432 kb
Host smart-62fec7bf-0c69-4595-a515-3715e7cb4139
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102949978038201717270905918180638240280490538699029313645224610165999421775367 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.102949978038201717270905918180638240280490538699029313645224610165999421775367
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.80273948595915515856908194272615167259440099527531912251465365343340048018326
Short name T1332
Test name
Test status
Simulation time 3768267272 ps
CPU time 73.85 seconds
Started Nov 22 02:37:49 PM PST 23
Finished Nov 22 02:39:04 PM PST 23
Peak memory 729536 kb
Host smart-df03363e-df85-4bab-a8ec-43318ec4f832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80273948595915515856908194272615167259440099527531912251465365343340048018326 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_host_fifo_full.80273948595915515856908194272615167259440099527531912251465365343340048018326
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.101430763930618242965280655278837484742551138139825652230367512558057151596530
Short name T886
Test name
Test status
Simulation time 7925734012 ps
CPU time 261.22 seconds
Started Nov 22 02:38:06 PM PST 23
Finished Nov 22 02:42:27 PM PST 23
Peak memory 1271540 kb
Host smart-718ca3bf-cf4c-472f-8eda-2f2084719a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101430763930618242965280655278837484742551138139825652230367512558057151596530 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.i2c_host_fifo_overflow.101430763930618242965280655278837484742551138139825652230367512558057151596530
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.88118283082058920807793595931014447043112206127170851986686762108379129606164
Short name T1490
Test name
Test status
Simulation time 209010032 ps
CPU time 0.97 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:37:45 PM PST 23
Peak memory 202932 kb
Host smart-58930b18-81a5-42d2-b22f-27b55edc951f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88118283082058920807793595931014447043112206127170851986686762108379129606164 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.88118283082058920807793595931014447043112206127170851986686762108379129606164
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.99845314888333573312869025460846634217458122346463113264678362728188650951956
Short name T544
Test name
Test status
Simulation time 236313385 ps
CPU time 3.94 seconds
Started Nov 22 02:37:39 PM PST 23
Finished Nov 22 02:37:43 PM PST 23
Peak memory 225532 kb
Host smart-e24fe36d-6927-459a-ad14-6b97dc21b368
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99845314888333573312869025460846634217458122346463113264678362728188650951956 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.99845314888333573312869025460846634217458122346463113264678362728188650951956
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.71037885931069343890921470462799696225714654492789991444152411785300374144054
Short name T753
Test name
Test status
Simulation time 7918519784 ps
CPU time 226.43 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:41:30 PM PST 23
Peak memory 1310944 kb
Host smart-092aedcd-4c73-44da-b4f4-1ddd7218e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71037885931069343890921470462799696225714654492789991444152411785300374144054 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.i2c_host_fifo_watermark.71037885931069343890921470462799696225714654492789991444152411785300374144054
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.19166560943542845098526714479753901374805016452146313684457110836016644990825
Short name T215
Test name
Test status
Simulation time 3754070957 ps
CPU time 52.21 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:39:02 PM PST 23
Peak memory 293720 kb
Host smart-34367f44-a30d-4471-9974-0a43b4e983d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19166560943542845098526714479753901374805016452146313684457110836016644990825 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_host_mode_toggle.19166560943542845098526714479753901374805016452146313684457110836016644990825
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.113735151872811870873299992304607067529564946613774018341184149656077639996836
Short name T1301
Test name
Test status
Simulation time 23672229 ps
CPU time 0.61 seconds
Started Nov 22 02:37:39 PM PST 23
Finished Nov 22 02:37:40 PM PST 23
Peak memory 202868 kb
Host smart-b2556c30-9250-4873-9546-92e8ef510808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113735151872811870873299992304607067529564946613774018341184149656077639996836 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_host_override.113735151872811870873299992304607067529564946613774018341184149656077639996836
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.28381821753463796167892529143387873278499856246957452137686945371935328819759
Short name T303
Test name
Test status
Simulation time 6830796343 ps
CPU time 61.34 seconds
Started Nov 22 02:37:41 PM PST 23
Finished Nov 22 02:38:44 PM PST 23
Peak memory 211380 kb
Host smart-b148b6d0-99f4-4fde-aad4-14a6f7841d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28381821753463796167892529143387873278499856246957452137686945371935328819759 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.i2c_host_perf.28381821753463796167892529143387873278499856246957452137686945371935328819759
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_rx_oversample.80220519785238840658737752054889066454758359301525694662606385431392249766351
Short name T1080
Test name
Test status
Simulation time 3939158762 ps
CPU time 93.74 seconds
Started Nov 22 02:37:50 PM PST 23
Finished Nov 22 02:39:24 PM PST 23
Peak memory 345816 kb
Host smart-b86bbe93-16f6-4b94-85cd-d8070ade2326
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80220519785238840658737752054889066454758359301525694662606385431392249766351 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_rx_oversample.80220519785238840658737752054889066454758359301525694662606385431392249766351
Directory /workspace/35.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.76885636839055706446980491982939699362487995577290246650092360944747944000653
Short name T901
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.2 seconds
Started Nov 22 02:37:39 PM PST 23
Finished Nov 22 02:38:17 PM PST 23
Peak memory 299388 kb
Host smart-a0c9858f-1eb4-41f0-be7b-293d45265f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76885636839055706446980491982939699362487995577290246650092360944747944000653 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.i2c_host_smoke.76885636839055706446980491982939699362487995577290246650092360944747944000653
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.88019809519552811718052346095712671404148732484432276127797134749088449180103
Short name T56
Test name
Test status
Simulation time 32807463528 ps
CPU time 1100.99 seconds
Started Nov 22 02:37:36 PM PST 23
Finished Nov 22 02:55:58 PM PST 23
Peak memory 1956988 kb
Host smart-9428a249-84a5-4233-b23a-94f5f2fca59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88019809519552811718052346095712671404148732484432276127797134749088449180103 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_host_stress_all.88019809519552811718052346095712671404148732484432276127797134749088449180103
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.8166579320463511024019232585675044415847250027335266846223785505614702286655
Short name T373
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.18 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:37:57 PM PST 23
Peak memory 213992 kb
Host smart-d79a49e9-1c8f-4172-8a56-7e8c8efcef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8166579320463511024019232585675044415847250027335266846223785505614702286655 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.i2c_host_stretch_timeout.8166579320463511024019232585675044415847250027335266846223785505614702286655
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.92143968643183802698344854907036670513751120285877168282411644447147127152445
Short name T1144
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.83 seconds
Started Nov 22 02:37:58 PM PST 23
Finished Nov 22 02:38:03 PM PST 23
Peak memory 203020 kb
Host smart-1d6ebe25-7905-40f0-9d9f-6d0b257b3cad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9214396864318380269834485490703
6670513751120285877168282411644447147127152445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.92143968643183802698344854
907036670513751120285877168282411644447147127152445
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.30104797152033520730867004266653441992433245578050176066249451257370971612756
Short name T1374
Test name
Test status
Simulation time 10166144644 ps
CPU time 33.21 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:38:17 PM PST 23
Peak memory 382188 kb
Host smart-d02db55d-dfa9-467e-99db-10d3ebe9e12c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301047971520335207308670042666534419924332455780501
76066249451257370971612756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_acq.3010479715203352073086700426665
3441992433245578050176066249451257370971612756
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.23284279959540325622446525107224583443963627404137055069741969928146020783933
Short name T181
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.75 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:48 PM PST 23
Peak memory 462092 kb
Host smart-9e316c4f-bb90-44d1-9958-1fe170f86ad0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232842799595403256224465251072245834439636274041370
55069741969928146020783933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_tx.232842799595403256224465251072245
83443963627404137055069741969928146020783933
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.44019022842599928929490954562613147073412902987351544972944438806795996194643
Short name T184
Test name
Test status
Simulation time 825344371 ps
CPU time 2.45 seconds
Started Nov 22 02:37:43 PM PST 23
Finished Nov 22 02:37:47 PM PST 23
Peak memory 203068 kb
Host smart-b431aac9-6086-4cd4-8763-913baeaa6aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440190228425999289294909545626131470734129029873515
44972944438806795996194643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_hrst.440190228425999289294909545626131470734129029873515
44972944438806795996194643
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.56655379117835116600789014571509413295699682711897244502342009649813253286334
Short name T1502
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.23 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:38:15 PM PST 23
Peak memory 203624 kb
Host smart-37fe9813-428e-4f2e-adba-aeaa557ebaa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56655379117835116600789014571509413295699682711897
244502342009649813253286334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.5665537911783511660078901457150941329569968
2711897244502342009649813253286334
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.74959362919219018796696489419707016212397423470938478930815968189737992378756
Short name T484
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.05 seconds
Started Nov 22 02:37:43 PM PST 23
Finished Nov 22 02:38:08 PM PST 23
Peak memory 639236 kb
Host smart-4b9eec07-222f-497e-8607-452f521202d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74959362919219018796696489419707016212
397423470938478930815968189737992378756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.74959362919219018796696
489419707016212397423470938478930815968189737992378756
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_perf.26205218217206521697682459436381239315009474817097933243504820197999958019250
Short name T472
Test name
Test status
Simulation time 834576440 ps
CPU time 2.96 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:14 PM PST 23
Peak memory 202976 kb
Host smart-3e104799-f632-413b-96a9-1d582d0eea3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262052182172065216976824594363812393150094748170979
33243504820197999958019250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_perf.262052182172065216976824594363812393150094748170979
33243504820197999958019250
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.30754724861079733655092944761623012684431730670106601550186121455808861720841
Short name T239
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.45 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:20 PM PST 23
Peak memory 202948 kb
Host smart-1fb385b0-6731-4bea-9e4a-ce9878ba897e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075472486107973365509294476162301268443173067010660155018612145580886
1720841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smoke.30754724861079733655092944761623012684431730670106601550186121455808861720841
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.66049702098529010138681013987803095982078352542166520862520445620285083481467
Short name T183
Test name
Test status
Simulation time 66540157934 ps
CPU time 1758.73 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 03:07:30 PM PST 23
Peak memory 6983388 kb
Host smart-41d18be1-3e14-47ba-ade2-871bf198e701
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66049702098529010138681013987803095982078352542166
520862520445620285083481467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_all.66049702098529010138681013987803095982
078352542166520862520445620285083481467
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.86607342539953319230252672307565887108055452832597389657796720206649272646390
Short name T525
Test name
Test status
Simulation time 997771563 ps
CPU time 8.79 seconds
Started Nov 22 02:38:06 PM PST 23
Finished Nov 22 02:38:15 PM PST 23
Peak memory 203012 kb
Host smart-793c2f0d-890b-4403-9388-ad4b2eb04080
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8660734253995331923025267230756588710805545283259738965779672020664927
2646390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_rd.866073425399533192302526723075658871080554528325973896577967
20206649272646390
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.26648194368721497516018242392627352743327467468565031243950590571117656011869
Short name T942
Test name
Test status
Simulation time 14461449567 ps
CPU time 96.41 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:39:48 PM PST 23
Peak memory 1542076 kb
Host smart-2cd46f8d-90f4-48f4-834f-540ab2e90165
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664819436872149751601824239262735274332746746856503124395059057111765
6011869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_wr.266481943687214975160182423926273527433274674685650312439505
90571117656011869
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.99439212962916412089883771248720852826675821347668342588768496566949858232075
Short name T522
Test name
Test status
Simulation time 6281818576 ps
CPU time 80.44 seconds
Started Nov 22 02:38:13 PM PST 23
Finished Nov 22 02:39:35 PM PST 23
Peak memory 930668 kb
Host smart-1855ae52-6515-4a1b-a620-5587aa28ec41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9943921296291641208988377124872085282667582134766834258876849656694985
8232075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stretch.9943921296291641208988377124872085282667582134766834258876849656
6949858232075
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.42300775056133301829667058403780022654799195590153614986071231861920872093887
Short name T169
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.38 seconds
Started Nov 22 02:38:04 PM PST 23
Finished Nov 22 02:38:12 PM PST 23
Peak memory 212652 kb
Host smart-9e5c8051-4052-49b1-a10d-0dceac20e654
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423007750561333018296670584037800226547991955901536
14986071231861920872093887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_timeout.423007750561333018296670584037800226547991955
90153614986071231861920872093887
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_ovf.37716600383406158824949972407682383778581080260809174242345438789290485073204
Short name T1157
Test name
Test status
Simulation time 5445414553 ps
CPU time 121.33 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:39:45 PM PST 23
Peak memory 406860 kb
Host smart-38b3c97a-4a46-4b95-a0f7-683098b2073d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37716600383406158824949972407682383778581080260809
174242345438789290485073204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_tx_ovf.3771660038340615882494997240768238377858108026
0809174242345438789290485073204
Directory /workspace/35.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.29749077287805988232815865681217123137214951994586581122464824816593595890159
Short name T232
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.71 seconds
Started Nov 22 02:37:41 PM PST 23
Finished Nov 22 02:37:48 PM PST 23
Peak memory 205384 kb
Host smart-358e1161-88d3-4333-8790-94826292a21d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297490772878059882328158656812171231372149519945865
81122464824816593595890159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_unexp_stop.29749077287805988232815865681217123137214
951994586581122464824816593595890159
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.11332248569004018761203187964378759815019066558326311129626779104252815960804
Short name T427
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:38:11 PM PST 23
Peak memory 202664 kb
Host smart-e7e5be8f-47af-40c1-a812-63436c4d357f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11332248569004018761203187964378759815019066558326311129626779104252815960804 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_alert_test.11332248569004018761203187964378759815019066558326311129626779104252815960804
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.59628037990434604445544631126960316298534812227114210632398413020018413011275
Short name T308
Test name
Test status
Simulation time 74225396 ps
CPU time 1.39 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:37:45 PM PST 23
Peak memory 211248 kb
Host smart-7a37ecb0-0100-45e5-b358-89436b20041a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59628037990434604445544631126960316298534812227114210632398413020018413011275 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_host_error_intr.59628037990434604445544631126960316298534812227114210632398413020018413011275
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.9529289285586910849164431238008829840852436969290884727164583866642182179820
Short name T485
Test name
Test status
Simulation time 606667565 ps
CPU time 6.84 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:18 PM PST 23
Peak memory 273336 kb
Host smart-a06183a4-dbe6-4187-9966-02eed8b82537
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9529289285586910849164431238008829840852436969290884727164583866642182179820 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.9529289285586910849164431238008829840852436969290884727164583866642182179820
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.1668209490350181437657713959385842951151499395073295715353083955853608383720
Short name T1263
Test name
Test status
Simulation time 3768267272 ps
CPU time 73.11 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:39:24 PM PST 23
Peak memory 729480 kb
Host smart-ddef5ffd-e3cb-4142-b30d-95cfdb39d257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668209490350181437657713959385842951151499395073295715353083955853608383720 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_host_fifo_full.1668209490350181437657713959385842951151499395073295715353083955853608383720
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.28584079463735742439392034515996543978353372330222314097774271478443256367143
Short name T628
Test name
Test status
Simulation time 7925734012 ps
CPU time 227.55 seconds
Started Nov 22 02:37:43 PM PST 23
Finished Nov 22 02:41:32 PM PST 23
Peak memory 1271576 kb
Host smart-5829bf3b-f983-4709-b766-7e8e11e045af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28584079463735742439392034515996543978353372330222314097774271478443256367143 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.i2c_host_fifo_overflow.28584079463735742439392034515996543978353372330222314097774271478443256367143
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3096345131371693148656434685835617868080152780117550715079063189154040510045
Short name T992
Test name
Test status
Simulation time 209010032 ps
CPU time 0.97 seconds
Started Nov 22 02:38:13 PM PST 23
Finished Nov 22 02:38:15 PM PST 23
Peak memory 202980 kb
Host smart-b18bbd51-6c06-4e7a-8ffa-0d42f1c9963a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096345131371693148656434685835617868080152780117550715079063189154040510045 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.3096345131371693148656434685835617868080152780117550715079063189154040510045
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.92258847979263615590818924370873254596135927537170203625567265104383219470255
Short name T277
Test name
Test status
Simulation time 236313385 ps
CPU time 3.91 seconds
Started Nov 22 02:37:41 PM PST 23
Finished Nov 22 02:37:47 PM PST 23
Peak memory 225468 kb
Host smart-0eaacb19-29ed-43ed-974b-e83beb316a03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92258847979263615590818924370873254596135927537170203625567265104383219470255 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.92258847979263615590818924370873254596135927537170203625567265104383219470255
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.13892676898434164695072371140048133756408408881428845921453521588940933057150
Short name T968
Test name
Test status
Simulation time 7918519784 ps
CPU time 198.54 seconds
Started Nov 22 02:37:47 PM PST 23
Finished Nov 22 02:41:07 PM PST 23
Peak memory 1310716 kb
Host smart-f584922e-84b7-4af5-87b1-6bb72c5cd71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13892676898434164695072371140048133756408408881428845921453521588940933057150 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.i2c_host_fifo_watermark.13892676898434164695072371140048133756408408881428845921453521588940933057150
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.59754538178834361391146476841337666630138286569254037036330599749605799977044
Short name T1182
Test name
Test status
Simulation time 3754070957 ps
CPU time 52.17 seconds
Started Nov 22 02:37:43 PM PST 23
Finished Nov 22 02:38:36 PM PST 23
Peak memory 293776 kb
Host smart-43fd597a-0752-44d6-af98-221670e5490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59754538178834361391146476841337666630138286569254037036330599749605799977044 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_host_mode_toggle.59754538178834361391146476841337666630138286569254037036330599749605799977044
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.86836841297394528934716142602377066267057137092757273698908347317300198430477
Short name T1360
Test name
Test status
Simulation time 23672229 ps
CPU time 0.61 seconds
Started Nov 22 02:37:41 PM PST 23
Finished Nov 22 02:37:42 PM PST 23
Peak memory 202820 kb
Host smart-e537a7e9-f59e-4b99-bce6-91789629df1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86836841297394528934716142602377066267057137092757273698908347317300198430477 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_host_override.86836841297394528934716142602377066267057137092757273698908347317300198430477
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.105996608399279231823865646557065019871136606261252039684344885672266473077296
Short name T72
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.1 seconds
Started Nov 22 02:38:05 PM PST 23
Finished Nov 22 02:39:06 PM PST 23
Peak memory 211364 kb
Host smart-695f16cd-6fdc-46b2-9dd4-61cf1f87f6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105996608399279231823865646557065019871136606261252039684344885672266473077296 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.i2c_host_perf.105996608399279231823865646557065019871136606261252039684344885672266473077296
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_rx_oversample.107268583577938073655838833191781114719004714240394946109188551603735732492918
Short name T505
Test name
Test status
Simulation time 3939158762 ps
CPU time 110.61 seconds
Started Nov 22 02:38:12 PM PST 23
Finished Nov 22 02:40:03 PM PST 23
Peak memory 345924 kb
Host smart-8ca3dce8-5d4c-4b68-98b7-4ab179c5aca6
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107268583577938073655838833191781114719004714240394946109188551603735732492918 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_rx_oversample.107268583577938073655838833191781114719004714240394946109188551603735732492918
Directory /workspace/36.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.34872557199092771244905970211227877970556400327420911959694750428456115944004
Short name T821
Test name
Test status
Simulation time 2343171530 ps
CPU time 36.06 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:38:20 PM PST 23
Peak memory 299312 kb
Host smart-ae7258f0-5164-4215-a3fd-f7517b7e9ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34872557199092771244905970211227877970556400327420911959694750428456115944004 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.i2c_host_smoke.34872557199092771244905970211227877970556400327420911959694750428456115944004
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.66283442139926588930146141704271576050487519392540375774172345667144575544234
Short name T205
Test name
Test status
Simulation time 32807463528 ps
CPU time 995.73 seconds
Started Nov 22 02:38:06 PM PST 23
Finished Nov 22 02:54:42 PM PST 23
Peak memory 1957160 kb
Host smart-02c7d9d0-f744-46c6-acca-e692a4e651f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66283442139926588930146141704271576050487519392540375774172345667144575544234 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_host_stress_all.66283442139926588930146141704271576050487519392540375774172345667144575544234
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.63565780000817765580671620719936033032062647731271992342246798156807511805363
Short name T374
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.12 seconds
Started Nov 22 02:38:08 PM PST 23
Finished Nov 22 02:38:22 PM PST 23
Peak memory 214104 kb
Host smart-8e1b1a83-aa27-42d8-ae74-a5d13f41ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63565780000817765580671620719936033032062647731271992342246798156807511805363 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_host_stretch_timeout.63565780000817765580671620719936033032062647731271992342246798156807511805363
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.26793822225576270731716308122334816672256353613722240667934022718075207341422
Short name T1170
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.86 seconds
Started Nov 22 02:37:47 PM PST 23
Finished Nov 22 02:37:52 PM PST 23
Peak memory 202828 kb
Host smart-8c074183-0d6d-4d94-b1eb-f66e67efe21a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679382222557627073171630812233
4816672256353613722240667934022718075207341422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.26793822225576270731716308
122334816672256353613722240667934022718075207341422
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.95837260682882368465745362502790043686842015360087754111466897389468791856300
Short name T1489
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.78 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:44 PM PST 23
Peak memory 382244 kb
Host smart-0e91be8c-0f74-4666-89f9-ce302bd7f18f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958372606828823684657453625027900436868420153600877
54111466897389468791856300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.9583726068288236846574536250279
0043686842015360087754111466897389468791856300
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.75813194480774685405634471057730082212570811466868017019066764698306626050382
Short name T1260
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.36 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:38:18 PM PST 23
Peak memory 462112 kb
Host smart-3ed27537-1839-40ce-819f-c7e99ddb8ef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758131944807746854056344710577300822125708114668680
17019066764698306626050382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_tx.758131944807746854056344710577300
82212570811466868017019066764698306626050382
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.14841501351276301413303801548029676974960144784488237242641206758267262677731
Short name T828
Test name
Test status
Simulation time 825344371 ps
CPU time 2.48 seconds
Started Nov 22 02:37:42 PM PST 23
Finished Nov 22 02:37:46 PM PST 23
Peak memory 202876 kb
Host smart-8e3294f5-0c68-4904-96fc-2c22394fff55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148415013512763014133038015480296769749601447844882
37242641206758267262677731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_hrst.148415013512763014133038015480296769749601447844882
37242641206758267262677731
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.31497880498867943992420202645675692350063632334324332777433321963102382990777
Short name T1518
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.3 seconds
Started Nov 22 02:37:43 PM PST 23
Finished Nov 22 02:37:49 PM PST 23
Peak memory 203720 kb
Host smart-7108ecc2-79e2-438e-8fa4-a0825d56c1cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31497880498867943992420202645675692350063632334324
332777433321963102382990777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_smoke.3149788049886794399242020264567569235006363
2334324332777433321963102382990777
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.62485776318856314955559702707544017566264613478531952048907954016539875713917
Short name T546
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.74 seconds
Started Nov 22 02:37:57 PM PST 23
Finished Nov 22 02:38:22 PM PST 23
Peak memory 639200 kb
Host smart-64818ad4-8b6c-446e-b71b-d67092a9895e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62485776318856314955559702707544017566
264613478531952048907954016539875713917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.62485776318856314955559
702707544017566264613478531952048907954016539875713917
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.65193702244849226310933838219366611626159879257790273328045758677668311269913
Short name T792
Test name
Test status
Simulation time 834576440 ps
CPU time 3 seconds
Started Nov 22 02:37:41 PM PST 23
Finished Nov 22 02:37:45 PM PST 23
Peak memory 203024 kb
Host smart-b9ad31ed-91f3-45b1-ab60-ac74fe0b0334
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651937022448492263109338382193666116261598792577902
73328045758677668311269913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_perf.651937022448492263109338382193666116261598792577902
73328045758677668311269913
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.87354438526123927835889402092909563502705043419919516620699095009942536280047
Short name T947
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.46 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:38:19 PM PST 23
Peak memory 202924 kb
Host smart-8fd80908-1827-4937-8583-0bac0bc9c632
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8735443852612392783588940209290956350270504341991951662069909500994253
6280047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smoke.87354438526123927835889402092909563502705043419919516620699095009942536280047
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.91000150224734382712191834926060654592718277621972533251233242989694785263774
Short name T354
Test name
Test status
Simulation time 66540157934 ps
CPU time 1575.97 seconds
Started Nov 22 02:37:58 PM PST 23
Finished Nov 22 03:04:15 PM PST 23
Peak memory 6983372 kb
Host smart-cffff024-10e3-44ef-94c5-8c8e02ca3d0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91000150224734382712191834926060654592718277621972
533251233242989694785263774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_all.91000150224734382712191834926060654592
718277621972533251233242989694785263774
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.21030075327681292066499977579498027853699098365511016306669745358562968905790
Short name T671
Test name
Test status
Simulation time 997771563 ps
CPU time 8.48 seconds
Started Nov 22 02:37:47 PM PST 23
Finished Nov 22 02:37:56 PM PST 23
Peak memory 203004 kb
Host smart-1eb15299-1727-49a7-a8e1-30cc6424877e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103007532768129206649997757949802785369909836551101630666974535856296
8905790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_rd.210300753276812920664999775794980278536990983655110163066697
45358562968905790
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.80040685415874845850515210186177778554899601193626603919684154301239254721812
Short name T1047
Test name
Test status
Simulation time 14461449567 ps
CPU time 92.56 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:39:42 PM PST 23
Peak memory 1542084 kb
Host smart-3663654a-f7e1-42c3-84b5-f97fa627e2d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8004068541587484585051521018617777855489960119362660391968415430123925
4721812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_wr.800406854158748458505152101861777785548996011936266039196841
54301239254721812
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.76532484120106714389129230354595150806100093301847100126946875754677645684576
Short name T8
Test name
Test status
Simulation time 6281818576 ps
CPU time 74.8 seconds
Started Nov 22 02:38:06 PM PST 23
Finished Nov 22 02:39:21 PM PST 23
Peak memory 930564 kb
Host smart-dde8ea0a-9ef4-4d46-896e-eda94157e40d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7653248412010671438912923035459515080610009330184710012694687575467764
5684576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stretch.7653248412010671438912923035459515080610009330184710012694687575
4677645684576
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.104951285924230537499844033351744430646877671687682622636411904792387774018691
Short name T1461
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.43 seconds
Started Nov 22 02:37:47 PM PST 23
Finished Nov 22 02:37:55 PM PST 23
Peak memory 212616 kb
Host smart-8e268d95-e9b9-41a3-8352-37dcf72986ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104951285924230537499844033351744430646877671687682
622636411904792387774018691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_timeout.10495128592423053749984403335174443064687767
1687682622636411904792387774018691
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_ovf.59524487521729448989267386713939425768998542553106256048772768853288901593006
Short name T225
Test name
Test status
Simulation time 5445414553 ps
CPU time 139.99 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:40:31 PM PST 23
Peak memory 406752 kb
Host smart-e6dd1e72-79f3-4a01-96fd-0807d8e6ac0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59524487521729448989267386713939425768998542553106
256048772768853288901593006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_tx_ovf.5952448752172944898926738671393942576899854255
3106256048772768853288901593006
Directory /workspace/36.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.53926197599005887989599970323219339688221275748593541541074063109364824215905
Short name T1073
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.6 seconds
Started Nov 22 02:37:47 PM PST 23
Finished Nov 22 02:37:54 PM PST 23
Peak memory 205308 kb
Host smart-5c9a5042-f5ce-401b-a353-71ff338b2b99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539261975990058879895999703232193396882212757485935
41541074063109364824215905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_unexp_stop.53926197599005887989599970323219339688221
275748593541541074063109364824215905
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.28470536184295893691952251258359757641905661015947741233868390914289487304327
Short name T1269
Test name
Test status
Simulation time 19975830 ps
CPU time 0.61 seconds
Started Nov 22 02:38:29 PM PST 23
Finished Nov 22 02:38:30 PM PST 23
Peak memory 202708 kb
Host smart-a17679d3-837b-4694-a06d-16f63b644b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28470536184295893691952251258359757641905661015947741233868390914289487304327 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_alert_test.28470536184295893691952251258359757641905661015947741233868390914289487304327
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1777476565302702056334085959323341655117452193893451604952010754275271006998
Short name T1500
Test name
Test status
Simulation time 74225396 ps
CPU time 1.44 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:13 PM PST 23
Peak memory 211344 kb
Host smart-d2c12e4b-abf8-4f30-a7ac-1539898965fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777476565302702056334085959323341655117452193893451604952010754275271006998 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_host_error_intr.1777476565302702056334085959323341655117452193893451604952010754275271006998
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.101863474359926275647486700927972914350423293525970172499658195535932731085424
Short name T891
Test name
Test status
Simulation time 606667565 ps
CPU time 7.03 seconds
Started Nov 22 02:37:41 PM PST 23
Finished Nov 22 02:37:50 PM PST 23
Peak memory 273332 kb
Host smart-3c1e36b9-97fe-4cb1-be17-aa1a445ab347
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101863474359926275647486700927972914350423293525970172499658195535932731085424 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.101863474359926275647486700927972914350423293525970172499658195535932731085424
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.84801587669815490206135460714523199975770997511943611306186670214113229780989
Short name T1531
Test name
Test status
Simulation time 3768267272 ps
CPU time 67.24 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:39:17 PM PST 23
Peak memory 729552 kb
Host smart-eaa5de92-5566-45b9-b02f-2a1389c5f91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84801587669815490206135460714523199975770997511943611306186670214113229780989 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_host_fifo_full.84801587669815490206135460714523199975770997511943611306186670214113229780989
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.113060192601951667318258870800513879770909197941855421507774746134705647958259
Short name T1302
Test name
Test status
Simulation time 7925734012 ps
CPU time 252.71 seconds
Started Nov 22 02:37:43 PM PST 23
Finished Nov 22 02:41:58 PM PST 23
Peak memory 1271564 kb
Host smart-909c86c3-1e45-4aa4-a3db-ba39f394e04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113060192601951667318258870800513879770909197941855421507774746134705647958259 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_host_fifo_overflow.113060192601951667318258870800513879770909197941855421507774746134705647958259
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.18707193661871879220289523384195495794506412966967301322079443998098341663192
Short name T498
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:38:16 PM PST 23
Finished Nov 22 02:38:18 PM PST 23
Peak memory 202952 kb
Host smart-c879dfea-794e-48de-894e-2312e28e7f7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18707193661871879220289523384195495794506412966967301322079443998098341663192 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.18707193661871879220289523384195495794506412966967301322079443998098341663192
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.7507295657557999741769141680756485017357305475820955664934043863983220751718
Short name T609
Test name
Test status
Simulation time 236313385 ps
CPU time 3.82 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:38:14 PM PST 23
Peak memory 225500 kb
Host smart-62d82122-7a0f-4663-a9eb-5ee4ed03e28c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7507295657557999741769141680756485017357305475820955664934043863983220751718 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.7507295657557999741769141680756485017357305475820955664934043863983220751718
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.41603486108089489642471311425913119418713594904328766615909134659644194126052
Short name T946
Test name
Test status
Simulation time 7918519784 ps
CPU time 224.59 seconds
Started Nov 22 02:38:32 PM PST 23
Finished Nov 22 02:42:17 PM PST 23
Peak memory 1310956 kb
Host smart-596309b3-a1c4-4aaf-8cf4-ba466b97de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41603486108089489642471311425913119418713594904328766615909134659644194126052 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_host_fifo_watermark.41603486108089489642471311425913119418713594904328766615909134659644194126052
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.98555521900679076647293930722134146798408477905462923896275993952122142847190
Short name T663
Test name
Test status
Simulation time 3754070957 ps
CPU time 50.71 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:39:02 PM PST 23
Peak memory 293760 kb
Host smart-a38ce9aa-3661-4a39-b651-c0f03ee9eeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98555521900679076647293930722134146798408477905462923896275993952122142847190 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_host_mode_toggle.98555521900679076647293930722134146798408477905462923896275993952122142847190
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.17655498345765596552711497237591970661462736131092147667347962726883515220882
Short name T1165
Test name
Test status
Simulation time 23672229 ps
CPU time 0.67 seconds
Started Nov 22 02:37:44 PM PST 23
Finished Nov 22 02:37:46 PM PST 23
Peak memory 202836 kb
Host smart-0f3b810d-4a1a-48a4-b915-69eb8eecf002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17655498345765596552711497237591970661462736131092147667347962726883515220882 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_host_override.17655498345765596552711497237591970661462736131092147667347962726883515220882
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.91388408506949095705681300245929443613477653239293817524850092098939415303271
Short name T438
Test name
Test status
Simulation time 6830796343 ps
CPU time 62.23 seconds
Started Nov 22 02:38:03 PM PST 23
Finished Nov 22 02:39:06 PM PST 23
Peak memory 211336 kb
Host smart-cb674a59-bbb9-4c5d-ae51-24464b7b7980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91388408506949095705681300245929443613477653239293817524850092098939415303271 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.i2c_host_perf.91388408506949095705681300245929443613477653239293817524850092098939415303271
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_rx_oversample.35392760133168288476200948937844720715273551736471027138347588709383215044761
Short name T1395
Test name
Test status
Simulation time 3939158762 ps
CPU time 107.87 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:39:59 PM PST 23
Peak memory 345920 kb
Host smart-2b55cb24-7dab-4f96-bbef-64c32e6d6f43
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35392760133168288476200948937844720715273551736471027138347588709383215044761 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_rx_oversample.35392760133168288476200948937844720715273551736471027138347588709383215044761
Directory /workspace/37.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.27981282223385089232478767221359089586258724411888952978884173046177734844478
Short name T809
Test name
Test status
Simulation time 2343171530 ps
CPU time 42.9 seconds
Started Nov 22 02:38:13 PM PST 23
Finished Nov 22 02:38:57 PM PST 23
Peak memory 299444 kb
Host smart-dadff50c-9392-4edd-aaa2-001c927c4637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27981282223385089232478767221359089586258724411888952978884173046177734844478 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.i2c_host_smoke.27981282223385089232478767221359089586258724411888952978884173046177734844478
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.16704298753399936743205872184097943452770634447637829787838955749227917126672
Short name T1101
Test name
Test status
Simulation time 32807463528 ps
CPU time 1106.68 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:56:38 PM PST 23
Peak memory 1957164 kb
Host smart-8d074149-3df2-42c8-a1ef-b6223e0bcd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16704298753399936743205872184097943452770634447637829787838955749227917126672 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_host_stress_all.16704298753399936743205872184097943452770634447637829787838955749227917126672
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.83619651613911775242222911013510844300698997280757139415530922877056884108496
Short name T1388
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.36 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:38:24 PM PST 23
Peak memory 214164 kb
Host smart-80103d37-b181-42bf-b9d6-902cffdfbc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83619651613911775242222911013510844300698997280757139415530922877056884108496 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_host_stretch_timeout.83619651613911775242222911013510844300698997280757139415530922877056884108496
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.91542354618319407775010719048968516731982437669165841579491961404887307737500
Short name T1341
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.77 seconds
Started Nov 22 02:38:08 PM PST 23
Finished Nov 22 02:38:13 PM PST 23
Peak memory 203012 kb
Host smart-1eeb5d5e-6b7f-4549-b737-3dd34e78c3cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9154235461831940777501071904896
8516731982437669165841579491961404887307737500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.91542354618319407775010719
048968516731982437669165841579491961404887307737500
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.36167660787504332108588448010669879847318926788730050359336355691057217355330
Short name T1082
Test name
Test status
Simulation time 10166144644 ps
CPU time 29.66 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:38:40 PM PST 23
Peak memory 382256 kb
Host smart-c4e9c3ff-b851-4bd0-bb45-60ff49802440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361676607875043321085884480106698798473189267887300
50359336355691057217355330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.3616766078750433210858844801066
9879847318926788730050359336355691057217355330
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.61463687132363966066280361425179783518364710199918920731044853518607454554726
Short name T1509
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.37 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:47 PM PST 23
Peak memory 462116 kb
Host smart-e4f49bdf-dcd8-46d3-99ba-54a249cc32fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614636871323639660662803614251797835183647101999189
20731044853518607454554726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_tx.614636871323639660662803614251797
83518364710199918920731044853518607454554726
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.23085693904485464675938936136936125676984628666290126246388519040277784977638
Short name T1366
Test name
Test status
Simulation time 825344371 ps
CPU time 2.4 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:13 PM PST 23
Peak memory 203092 kb
Host smart-c4b34061-f909-4138-aaf9-c689c794fb99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230856939044854646759389361369361256769846286662901
26246388519040277784977638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_hrst.230856939044854646759389361369361256769846286662901
26246388519040277784977638
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.31513184187899914603452069609725264688277187565006960956932526545061324719465
Short name T1106
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.12 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:15 PM PST 23
Peak memory 203760 kb
Host smart-df827f90-1408-46b4-b580-4b7f68653078
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31513184187899914603452069609725264688277187565006
960956932526545061324719465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_smoke.3151318418789991460345206960972526468827718
7565006960956932526545061324719465
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.96689182673375653601760130614968021943661079611460050739948882263381346755388
Short name T623
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.09 seconds
Started Nov 22 02:38:04 PM PST 23
Finished Nov 22 02:38:27 PM PST 23
Peak memory 639276 kb
Host smart-07e4cca0-62a1-4c7b-bb54-1d71b28c8450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96689182673375653601760130614968021943
661079611460050739948882263381346755388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.96689182673375653601760
130614968021943661079611460050739948882263381346755388
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.105877824761286802286843285678743127830985892267252406227425797179887564008252
Short name T1172
Test name
Test status
Simulation time 834576440 ps
CPU time 3.35 seconds
Started Nov 22 02:38:05 PM PST 23
Finished Nov 22 02:38:09 PM PST 23
Peak memory 203020 kb
Host smart-3cfee5ba-b85e-49ea-a663-ca8b5d57ff83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105877824761286802286843285678743127830985892267252
406227425797179887564008252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_perf.10587782476128680228684328567874312783098589226725
2406227425797179887564008252
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.43729312759275104518649914384637791531410208720993550611769993262824260624040
Short name T926
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.43 seconds
Started Nov 22 02:38:16 PM PST 23
Finished Nov 22 02:38:26 PM PST 23
Peak memory 202916 kb
Host smart-447f0171-fa60-431b-b197-42881329b725
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4372931275927510451864991438463779153141020872099355061176999326282426
0624040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smoke.43729312759275104518649914384637791531410208720993550611769993262824260624040
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.106494879389324530538595635959006206430674406577505320144647555720600086525900
Short name T791
Test name
Test status
Simulation time 66540157934 ps
CPU time 1473.03 seconds
Started Nov 22 02:38:13 PM PST 23
Finished Nov 22 03:02:47 PM PST 23
Peak memory 6983924 kb
Host smart-ec35f814-1ecd-4d2d-8429-02d4a218b02b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10649487938932453053859563595900620643067440657750
5320144647555720600086525900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_all.1064948793893245305385956359590062064
30674406577505320144647555720600086525900
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1063280593031076754257327902174387448738499548707419101193943274043222410685
Short name T345
Test name
Test status
Simulation time 997771563 ps
CPU time 8.32 seconds
Started Nov 22 02:38:02 PM PST 23
Finished Nov 22 02:38:12 PM PST 23
Peak memory 203004 kb
Host smart-ac468ca9-319a-4118-9727-0cb76627f9bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063280593031076754257327902174387448738499548707419101193943274043222
410685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_rd.1063280593031076754257327902174387448738499548707419101193943
274043222410685
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.112587060459582892552037855029736445301496393370019743193900488511037420894312
Short name T222
Test name
Test status
Simulation time 14461449567 ps
CPU time 94.5 seconds
Started Nov 22 02:38:03 PM PST 23
Finished Nov 22 02:39:38 PM PST 23
Peak memory 1542108 kb
Host smart-d778210c-5c69-467b-b7d0-66a23ae0e791
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125870604595828925520378550297364453014963933700197431939004885110374
20894312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_wr.11258706045958289255203785502973644530149639337001974319390
0488511037420894312
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.96083434627091931566194678103913463925052802083117531527598579107432562949831
Short name T1171
Test name
Test status
Simulation time 6281818576 ps
CPU time 79.77 seconds
Started Nov 22 02:38:16 PM PST 23
Finished Nov 22 02:39:37 PM PST 23
Peak memory 930588 kb
Host smart-ac5c9b5e-6819-4e66-a085-d2719a770b82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9608343462709193156619467810391346392505280208311753152759857910743256
2949831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stretch.9608343462709193156619467810391346392505280208311753152759857910
7432562949831
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.106009353579319217961034164807027658540337804430959424420516950544336196093654
Short name T1575
Test name
Test status
Simulation time 2856220981 ps
CPU time 8.1 seconds
Started Nov 22 02:38:11 PM PST 23
Finished Nov 22 02:38:20 PM PST 23
Peak memory 212676 kb
Host smart-12848049-6ea5-4bfe-93c3-abcef5588168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106009353579319217961034164807027658540337804430959
424420516950544336196093654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_timeout.10600935357931921796103416480702765854033780
4430959424420516950544336196093654
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_ovf.108711906505286049985461741499518542103608215975358878552871071971139591391420
Short name T723
Test name
Test status
Simulation time 5445414553 ps
CPU time 143.97 seconds
Started Nov 22 02:38:14 PM PST 23
Finished Nov 22 02:40:38 PM PST 23
Peak memory 406912 kb
Host smart-8d557034-b843-4b79-91bd-f8c0ef70a716
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10871190650528604998546174149951854210360821597535
8878552871071971139591391420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_tx_ovf.108711906505286049985461741499518542103608215
975358878552871071971139591391420
Directory /workspace/37.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.110537651257651334760607206727186560810843343772177022963014075386471728602693
Short name T1369
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.6 seconds
Started Nov 22 02:38:13 PM PST 23
Finished Nov 22 02:38:19 PM PST 23
Peak memory 205356 kb
Host smart-2b9fd43a-5ca1-41be-a0c4-17750738a561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110537651257651334760607206727186560810843343772177
022963014075386471728602693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_unexp_stop.1105376512576513347606072067271865608108
43343772177022963014075386471728602693
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.10985398927023884773351789039026033858828365793360461890814576878114258815457
Short name T529
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:38:36 PM PST 23
Peak memory 202736 kb
Host smart-bbf795ad-7023-41d0-9157-4d37a43f21d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10985398927023884773351789039026033858828365793360461890814576878114258815457 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_alert_test.10985398927023884773351789039026033858828365793360461890814576878114258815457
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.16702017904929520988142906615680884543944699321348835992375242420594162201578
Short name T145
Test name
Test status
Simulation time 74225396 ps
CPU time 1.39 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:38:37 PM PST 23
Peak memory 211276 kb
Host smart-7419005e-4db2-4f79-8bbf-798abd27220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16702017904929520988142906615680884543944699321348835992375242420594162201578 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_host_error_intr.16702017904929520988142906615680884543944699321348835992375242420594162201578
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3536952097228043479397976388958437328383385775483954729007409032453686252948
Short name T148
Test name
Test status
Simulation time 606667565 ps
CPU time 6.73 seconds
Started Nov 22 02:38:13 PM PST 23
Finished Nov 22 02:38:20 PM PST 23
Peak memory 273504 kb
Host smart-bf4dce34-ef46-4c69-aa1a-eaaa077fbc5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536952097228043479397976388958437328383385775483954729007409032453686252948 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.3536952097228043479397976388958437328383385775483954729007409032453686252948
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.32047960254591915498162680972750621412093166763389347604744129948654106946657
Short name T495
Test name
Test status
Simulation time 3768267272 ps
CPU time 71.47 seconds
Started Nov 22 02:38:31 PM PST 23
Finished Nov 22 02:39:43 PM PST 23
Peak memory 729448 kb
Host smart-54c9eb24-7658-4d7f-9279-bd9a3115eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32047960254591915498162680972750621412093166763389347604744129948654106946657 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_host_fifo_full.32047960254591915498162680972750621412093166763389347604744129948654106946657
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.8770284359073379925923415823109341405513583152436656595946660953972799121079
Short name T1342
Test name
Test status
Simulation time 7925734012 ps
CPU time 253.37 seconds
Started Nov 22 02:38:13 PM PST 23
Finished Nov 22 02:42:27 PM PST 23
Peak memory 1271768 kb
Host smart-9618db7a-16be-4fbd-9365-dc7f1f300b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8770284359073379925923415823109341405513583152436656595946660953972799121079 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_host_fifo_overflow.8770284359073379925923415823109341405513583152436656595946660953972799121079
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.77694437661288635633632380053071817587175929182649691758546961817266671241063
Short name T65
Test name
Test status
Simulation time 209010032 ps
CPU time 0.92 seconds
Started Nov 22 02:38:10 PM PST 23
Finished Nov 22 02:38:12 PM PST 23
Peak memory 202996 kb
Host smart-996e4ff2-9cc4-43db-888b-e5b62b6bbc5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77694437661288635633632380053071817587175929182649691758546961817266671241063 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.77694437661288635633632380053071817587175929182649691758546961817266671241063
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.63622233172596330633338369384738292891603972802408453395874604907097858262833
Short name T1075
Test name
Test status
Simulation time 236313385 ps
CPU time 3.82 seconds
Started Nov 22 02:38:16 PM PST 23
Finished Nov 22 02:38:20 PM PST 23
Peak memory 225396 kb
Host smart-d1e4afc6-6cd5-4d91-800c-08c20dd3859f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63622233172596330633338369384738292891603972802408453395874604907097858262833 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.63622233172596330633338369384738292891603972802408453395874604907097858262833
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.113025789691172439608400879057109838496146691265336403648984365213078530703376
Short name T102
Test name
Test status
Simulation time 7918519784 ps
CPU time 239.95 seconds
Started Nov 22 02:38:13 PM PST 23
Finished Nov 22 02:42:14 PM PST 23
Peak memory 1311044 kb
Host smart-e072ffff-f509-447f-8c3f-3a999858da70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113025789691172439608400879057109838496146691265336403648984365213078530703376 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_host_fifo_watermark.113025789691172439608400879057109838496146691265336403648984365213078530703376
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1219888350966583672644789935083624043146695810626782113542916006319571245806
Short name T1123
Test name
Test status
Simulation time 3754070957 ps
CPU time 52.25 seconds
Started Nov 22 02:38:33 PM PST 23
Finished Nov 22 02:39:26 PM PST 23
Peak memory 293844 kb
Host smart-be19f9ba-8ae5-48d6-aac5-59810edab9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219888350966583672644789935083624043146695810626782113542916006319571245806 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_host_mode_toggle.1219888350966583672644789935083624043146695810626782113542916006319571245806
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.44028903317751554980274041772034062378120370980825992082003488888459860462314
Short name T555
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:38:16 PM PST 23
Finished Nov 22 02:38:17 PM PST 23
Peak memory 202852 kb
Host smart-ddec4ed2-1d79-4117-98da-92bb04b0e48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44028903317751554980274041772034062378120370980825992082003488888459860462314 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_host_override.44028903317751554980274041772034062378120370980825992082003488888459860462314
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.64194813545546853182926593560300899993425136805494040296661376769262355300172
Short name T1156
Test name
Test status
Simulation time 6830796343 ps
CPU time 58.51 seconds
Started Nov 22 02:38:33 PM PST 23
Finished Nov 22 02:39:32 PM PST 23
Peak memory 211304 kb
Host smart-8fd997d6-0f37-45ee-9553-6fb8f474ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64194813545546853182926593560300899993425136805494040296661376769262355300172 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.i2c_host_perf.64194813545546853182926593560300899993425136805494040296661376769262355300172
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_rx_oversample.61299836743096119811461251588149527329468391157565175324958769023072144928544
Short name T1452
Test name
Test status
Simulation time 3939158762 ps
CPU time 116.99 seconds
Started Nov 22 02:38:16 PM PST 23
Finished Nov 22 02:40:14 PM PST 23
Peak memory 345964 kb
Host smart-e5180bf6-25d7-44cb-8926-88801299026e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61299836743096119811461251588149527329468391157565175324958769023072144928544 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_rx_oversample.61299836743096119811461251588149527329468391157565175324958769023072144928544
Directory /workspace/38.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.8644454501057783486727344094441227039084800387390439904597655565812056491981
Short name T392
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.34 seconds
Started Nov 22 02:38:09 PM PST 23
Finished Nov 22 02:38:48 PM PST 23
Peak memory 299384 kb
Host smart-8403df70-1cf5-41a0-ba20-2c8a4d9a0929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8644454501057783486727344094441227039084800387390439904597655565812056491981 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.i2c_host_smoke.8644454501057783486727344094441227039084800387390439904597655565812056491981
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.65462740001948554668320853878247059817022452014094334731710699326297567476142
Short name T422
Test name
Test status
Simulation time 32807463528 ps
CPU time 1180.88 seconds
Started Nov 22 02:38:29 PM PST 23
Finished Nov 22 02:58:11 PM PST 23
Peak memory 1957148 kb
Host smart-09a3ef58-8e6c-479b-90a8-b0510da18a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65462740001948554668320853878247059817022452014094334731710699326297567476142 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_host_stress_all.65462740001948554668320853878247059817022452014094334731710699326297567476142
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.36310356555308350550091261803901346739034543287447698558351179695496897557036
Short name T218
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.27 seconds
Started Nov 22 02:38:28 PM PST 23
Finished Nov 22 02:38:42 PM PST 23
Peak memory 214196 kb
Host smart-392a3207-40d1-473a-908c-e6ee3bb29503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36310356555308350550091261803901346739034543287447698558351179695496897557036 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_host_stretch_timeout.36310356555308350550091261803901346739034543287447698558351179695496897557036
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.91259359820043191914076242120053091747668433263205285590463076720217903416641
Short name T63
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.72 seconds
Started Nov 22 02:38:33 PM PST 23
Finished Nov 22 02:38:37 PM PST 23
Peak memory 203056 kb
Host smart-7c6ffff3-7f3e-46cc-9154-b7823ee382e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9125935982004319191407624212005
3091747668433263205285590463076720217903416641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.91259359820043191914076242
120053091747668433263205285590463076720217903416641
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.47072852012083889834752519701526424172140417974086579034891997718193876329302
Short name T1177
Test name
Test status
Simulation time 10166144644 ps
CPU time 34.23 seconds
Started Nov 22 02:38:30 PM PST 23
Finished Nov 22 02:39:04 PM PST 23
Peak memory 382140 kb
Host smart-e21e1eb3-4b71-49b8-a24c-93bfcca363b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470728520120838898347525197015264241721404179740865
79034891997718193876329302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.4707285201208388983475251970152
6424172140417974086579034891997718193876329302
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.99933766786924930507946555766130865247337737038852971640859316512832257391349
Short name T1275
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.21 seconds
Started Nov 22 02:38:33 PM PST 23
Finished Nov 22 02:39:08 PM PST 23
Peak memory 462096 kb
Host smart-b6b21f9b-f4d7-4161-bd34-d945f3411936
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999337667869249305079465557661308652473377370388529
71640859316512832257391349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_tx.999337667869249305079465557661308
65247337737038852971640859316512832257391349
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.65662699715594648797574318308087905755186853587910455545663830451059160109076
Short name T518
Test name
Test status
Simulation time 825344371 ps
CPU time 2.4 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:38:38 PM PST 23
Peak memory 203052 kb
Host smart-f0c0aab0-b189-44a5-9cb9-c2b40d73c5db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656626997155946487975743183080879057551868535879104
55545663830451059160109076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_hrst.656626997155946487975743183080879057551868535879104
55545663830451059160109076
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.92423553616019064049116009670708441512945262107636901658310536436661623785640
Short name T582
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.13 seconds
Started Nov 22 02:38:21 PM PST 23
Finished Nov 22 02:38:26 PM PST 23
Peak memory 203680 kb
Host smart-5b93fb34-01bc-4025-a15d-2aaea500004f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92423553616019064049116009670708441512945262107636
901658310536436661623785640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.9242355361601906404911600967070844151294526
2107636901658310536436661623785640
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.32301094801339887322484585459295913431293914473985848067179779969269082318577
Short name T1318
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.02 seconds
Started Nov 22 02:38:29 PM PST 23
Finished Nov 22 02:38:53 PM PST 23
Peak memory 639248 kb
Host smart-580a90d6-6ab1-4399-9e84-d4828647e567
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32301094801339887322484585459295913431
293914473985848067179779969269082318577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.32301094801339887322484
585459295913431293914473985848067179779969269082318577
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.48588865907273879380942195259381395833948443912884902382502545060983828501279
Short name T327
Test name
Test status
Simulation time 834576440 ps
CPU time 2.97 seconds
Started Nov 22 02:38:17 PM PST 23
Finished Nov 22 02:38:21 PM PST 23
Peak memory 203064 kb
Host smart-f74ee82c-157d-4d79-bf31-c526068fcc4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485888659072738793809421952593813958339484439128849
02382502545060983828501279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_perf.485888659072738793809421952593813958339484439128849
02382502545060983828501279
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.32578662110191429307293220943793389842857192585081204046566464805744097855662
Short name T1398
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.57 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:38:45 PM PST 23
Peak memory 202984 kb
Host smart-73bf329e-29a0-4862-a5f8-47d1d86ed337
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257866211019142930729322094379338984285719258508120404656646480574409
7855662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smoke.32578662110191429307293220943793389842857192585081204046566464805744097855662
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.68103129945851929874803682669271677111369178982286477516834822570060363034608
Short name T1414
Test name
Test status
Simulation time 66540157934 ps
CPU time 1645.28 seconds
Started Nov 22 02:38:32 PM PST 23
Finished Nov 22 03:05:59 PM PST 23
Peak memory 6983408 kb
Host smart-4040eb3a-83db-48b8-99c4-baae2b305a8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68103129945851929874803682669271677111369178982286
477516834822570060363034608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_all.68103129945851929874803682669271677111
369178982286477516834822570060363034608
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.109970114904118149554702828854405980829948189254621051159247695449089937522313
Short name T447
Test name
Test status
Simulation time 997771563 ps
CPU time 8.43 seconds
Started Nov 22 02:38:32 PM PST 23
Finished Nov 22 02:38:41 PM PST 23
Peak memory 203012 kb
Host smart-d3f32f31-1999-4cfc-8a21-8726712b7529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099701149041181495547028288544059808299481892546210511592476954490899
37522313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_rd.10997011490411814955470282885440598082994818925462105115924
7695449089937522313
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.15018337087771699250509465572461859629986383749246430132399854907858395274959
Short name T1196
Test name
Test status
Simulation time 14461449567 ps
CPU time 88.67 seconds
Started Nov 22 02:38:32 PM PST 23
Finished Nov 22 02:40:01 PM PST 23
Peak memory 1542172 kb
Host smart-03fac68d-7943-4c5e-9519-ff6fe6537bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501833708777169925050946557246185962998638374924643013239985490785839
5274959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_wr.150183370877716992505094655724618596299863837492464301323998
54907858395274959
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.63987152868670316637466731971853633335261483675890040580783815992707333285994
Short name T451
Test name
Test status
Simulation time 6281818576 ps
CPU time 77.49 seconds
Started Nov 22 02:38:34 PM PST 23
Finished Nov 22 02:39:53 PM PST 23
Peak memory 930556 kb
Host smart-8330ee1c-d2aa-47ab-b2fd-0451c826de4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6398715286867031663746673197185363333526148367589004058078381599270733
3285994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stretch.6398715286867031663746673197185363333526148367589004058078381599
2707333285994
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.71353437408984561347507275843289261801875196860399655064112162049366325759475
Short name T383
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.11 seconds
Started Nov 22 02:38:21 PM PST 23
Finished Nov 22 02:38:29 PM PST 23
Peak memory 212692 kb
Host smart-2ee6ba04-8e62-48c5-9848-0b334258b46c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713534374089845613475072758432892618018751968603996
55064112162049366325759475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_timeout.713534374089845613475072758432892618018751968
60399655064112162049366325759475
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_ovf.45807759591821568721517025488036185188707478346098912455131126426297375818855
Short name T755
Test name
Test status
Simulation time 5445414553 ps
CPU time 150.05 seconds
Started Nov 22 02:38:34 PM PST 23
Finished Nov 22 02:41:04 PM PST 23
Peak memory 406848 kb
Host smart-3ba1451c-94c5-4719-b178-011f48cedcc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45807759591821568721517025488036185188707478346098
912455131126426297375818855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_tx_ovf.4580775959182156872151702548803618518870747834
6098912455131126426297375818855
Directory /workspace/38.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.93060267007968252437852486116703409229559054174100546827676539588082530042237
Short name T697
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.39 seconds
Started Nov 22 02:38:37 PM PST 23
Finished Nov 22 02:38:43 PM PST 23
Peak memory 205356 kb
Host smart-54b6c2ed-6085-4b45-9e37-452dade1c260
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930602670079682524378524861167034092295590541741005
46827676539588082530042237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_unexp_stop.93060267007968252437852486116703409229559
054174100546827676539588082530042237
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1215100779595611527801944423194351152156248647953414795903458095856374323301
Short name T160
Test name
Test status
Simulation time 19975830 ps
CPU time 0.59 seconds
Started Nov 22 02:38:33 PM PST 23
Finished Nov 22 02:38:35 PM PST 23
Peak memory 202796 kb
Host smart-7b8789d6-e2ed-4a49-8009-a367c365fd74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215100779595611527801944423194351152156248647953414795903458095856374323301 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_alert_test.1215100779595611527801944423194351152156248647953414795903458095856374323301
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.16753157332280607020829381692151074396259075861097809065394456443949335563809
Short name T1521
Test name
Test status
Simulation time 74225396 ps
CPU time 1.42 seconds
Started Nov 22 02:38:36 PM PST 23
Finished Nov 22 02:38:38 PM PST 23
Peak memory 211276 kb
Host smart-5761d817-0357-48ac-a932-0986bb09326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16753157332280607020829381692151074396259075861097809065394456443949335563809 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_host_error_intr.16753157332280607020829381692151074396259075861097809065394456443949335563809
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.53914926928276684312621361252435196205828999498104866761989221772302730157874
Short name T1554
Test name
Test status
Simulation time 606667565 ps
CPU time 6.83 seconds
Started Nov 22 02:38:36 PM PST 23
Finished Nov 22 02:38:43 PM PST 23
Peak memory 273348 kb
Host smart-409ce9e0-8b61-429d-b02b-fd0585f2d8cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53914926928276684312621361252435196205828999498104866761989221772302730157874 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.53914926928276684312621361252435196205828999498104866761989221772302730157874
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.40307070928690148897070243929901086649658605255301432812710993695216280855839
Short name T214
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.77 seconds
Started Nov 22 02:38:36 PM PST 23
Finished Nov 22 02:39:51 PM PST 23
Peak memory 729404 kb
Host smart-a1dbdd09-2ff8-4857-ba92-76434d57557f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40307070928690148897070243929901086649658605255301432812710993695216280855839 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_host_fifo_full.40307070928690148897070243929901086649658605255301432812710993695216280855839
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.51968610195902528748285891559501139995174673071202821720705202331102899072092
Short name T1292
Test name
Test status
Simulation time 7925734012 ps
CPU time 239.77 seconds
Started Nov 22 02:38:34 PM PST 23
Finished Nov 22 02:42:34 PM PST 23
Peak memory 1271544 kb
Host smart-b6d778e9-2f75-4251-8a21-7b910b0a8335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51968610195902528748285891559501139995174673071202821720705202331102899072092 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.i2c_host_fifo_overflow.51968610195902528748285891559501139995174673071202821720705202331102899072092
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.24369895305187411078388283652145071196288344796190077655786688108081206780831
Short name T371
Test name
Test status
Simulation time 209010032 ps
CPU time 0.92 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:38:37 PM PST 23
Peak memory 202964 kb
Host smart-f0113d0a-c56d-4417-a5cb-7378ce66442a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24369895305187411078388283652145071196288344796190077655786688108081206780831 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.24369895305187411078388283652145071196288344796190077655786688108081206780831
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.582128857161821270600731688074765785348996442735803798794732817257661298763
Short name T1473
Test name
Test status
Simulation time 236313385 ps
CPU time 4.05 seconds
Started Nov 22 02:38:34 PM PST 23
Finished Nov 22 02:38:39 PM PST 23
Peak memory 225568 kb
Host smart-1d46dc88-8bc8-4eec-9f36-8b652156c40c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582128857161821270600731688074765785348996442735803798794732817257661298763 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.582128857161821270600731688074765785348996442735803798794732817257661298763
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.24598208254688689903133565595061132331762915382242605612012600256302485231829
Short name T642
Test name
Test status
Simulation time 7918519784 ps
CPU time 225.26 seconds
Started Nov 22 02:38:36 PM PST 23
Finished Nov 22 02:42:22 PM PST 23
Peak memory 1310928 kb
Host smart-ec404ff6-eb79-403a-8a9b-89279abdc94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24598208254688689903133565595061132331762915382242605612012600256302485231829 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.i2c_host_fifo_watermark.24598208254688689903133565595061132331762915382242605612012600256302485231829
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.28614951139461092804097718509897056902772614704891413023109540618662407220034
Short name T611
Test name
Test status
Simulation time 3754070957 ps
CPU time 57.12 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:39:33 PM PST 23
Peak memory 293756 kb
Host smart-11ef8cef-c11e-4731-9a5e-cc10b43c8440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28614951139461092804097718509897056902772614704891413023109540618662407220034 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_host_mode_toggle.28614951139461092804097718509897056902772614704891413023109540618662407220034
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.110604154388237712125967769866942534888473439234531136306747879523296985996886
Short name T1505
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:38:32 PM PST 23
Finished Nov 22 02:38:33 PM PST 23
Peak memory 202900 kb
Host smart-594cad71-b6b3-4607-b720-8b94d0835c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110604154388237712125967769866942534888473439234531136306747879523296985996886 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_host_override.110604154388237712125967769866942534888473439234531136306747879523296985996886
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.12259470524967735863395795597191962647148802537999542381242623208091802149191
Short name T1295
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.71 seconds
Started Nov 22 02:38:36 PM PST 23
Finished Nov 22 02:39:38 PM PST 23
Peak memory 211268 kb
Host smart-94adcff8-6b9a-4356-881d-40fba4b53b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12259470524967735863395795597191962647148802537999542381242623208091802149191 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.i2c_host_perf.12259470524967735863395795597191962647148802537999542381242623208091802149191
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_rx_oversample.44815425457364169307059797921061579025498286308953482300229841293853439640253
Short name T559
Test name
Test status
Simulation time 3939158762 ps
CPU time 100.16 seconds
Started Nov 22 02:38:32 PM PST 23
Finished Nov 22 02:40:13 PM PST 23
Peak memory 345948 kb
Host smart-75ac2e42-d8e1-46c5-af1a-5554496c72fe
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44815425457364169307059797921061579025498286308953482300229841293853439640253 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_rx_oversample.44815425457364169307059797921061579025498286308953482300229841293853439640253
Directory /workspace/39.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.115691021173367209302109254925596921870032658377913172876010257767295224172562
Short name T1552
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.47 seconds
Started Nov 22 02:38:33 PM PST 23
Finished Nov 22 02:39:11 PM PST 23
Peak memory 299388 kb
Host smart-137e642c-8e29-4fdf-ac69-721a127bfd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115691021173367209302109254925596921870032658377913172876010257767295224172562 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.i2c_host_smoke.115691021173367209302109254925596921870032658377913172876010257767295224172562
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.59233049718170930945513238408248425684206104037840300581116136263031433615149
Short name T1294
Test name
Test status
Simulation time 32807463528 ps
CPU time 1194.13 seconds
Started Nov 22 02:38:36 PM PST 23
Finished Nov 22 02:58:31 PM PST 23
Peak memory 1957096 kb
Host smart-7f86937b-5817-4196-a86c-0bab166c3f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59233049718170930945513238408248425684206104037840300581116136263031433615149 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_host_stress_all.59233049718170930945513238408248425684206104037840300581116136263031433615149
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.73380256172970439093679786266186192062545271329720424806434107929660934805265
Short name T1377
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.88 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:38:50 PM PST 23
Peak memory 214092 kb
Host smart-53cc1103-6199-48a2-b25a-989906bae3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73380256172970439093679786266186192062545271329720424806434107929660934805265 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_host_stretch_timeout.73380256172970439093679786266186192062545271329720424806434107929660934805265
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.54887352479929561879547333200864923899614773273442680724831383299365617499338
Short name T44
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.84 seconds
Started Nov 22 02:38:36 PM PST 23
Finished Nov 22 02:38:41 PM PST 23
Peak memory 202960 kb
Host smart-be1d0087-ea0e-4071-a47e-7847f843531d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5488735247992956187954733320086
4923899614773273442680724831383299365617499338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.54887352479929561879547333
200864923899614773273442680724831383299365617499338
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.6837751027832452904459370465374535194780138747019632365713811684318562609615
Short name T1237
Test name
Test status
Simulation time 10166144644 ps
CPU time 30.3 seconds
Started Nov 22 02:38:34 PM PST 23
Finished Nov 22 02:39:05 PM PST 23
Peak memory 382204 kb
Host smart-17eb2645-489b-4bb9-ae77-f72031b4f863
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683775102783245290445937046537453519478013874701963
2365713811684318562609615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.68377510278324529044593704653745
35194780138747019632365713811684318562609615
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.42137841458461159148068031140700942847259719536663803956842285915890932612109
Short name T1437
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.78 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:39:12 PM PST 23
Peak memory 462068 kb
Host smart-b62abe23-611c-4481-886e-2b7ac4efca2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421378414584611591480680311407009428472597195366638
03956842285915890932612109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_tx.421378414584611591480680311407009
42847259719536663803956842285915890932612109
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.38030159589895831958122472947926577487998557959665154200623975458696781555424
Short name T1402
Test name
Test status
Simulation time 825344371 ps
CPU time 2.38 seconds
Started Nov 22 02:38:32 PM PST 23
Finished Nov 22 02:38:35 PM PST 23
Peak memory 203040 kb
Host smart-048e29fb-d730-4007-98d2-725a0c4d00be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380301595898958319581224729479265774879985579596651
54200623975458696781555424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_hrst.380301595898958319581224729479265774879985579596651
54200623975458696781555424
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.107418099783900480895099612774332882010056683881165978701177636652618744905206
Short name T1198
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.29 seconds
Started Nov 22 02:38:36 PM PST 23
Finished Nov 22 02:38:41 PM PST 23
Peak memory 203624 kb
Host smart-a50bb90d-bd69-4f5b-b795-524300f7bbb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10741809978390048089509961277433288201005668388116
5978701177636652618744905206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_smoke.107418099783900480895099612774332882010056
683881165978701177636652618744905206
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.33751835510675216334108044739267577087749270798606655534161640487061210739993
Short name T1476
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.57 seconds
Started Nov 22 02:38:30 PM PST 23
Finished Nov 22 02:38:53 PM PST 23
Peak memory 639152 kb
Host smart-791e2bb9-4a82-4c65-9a3a-180d087a9c5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33751835510675216334108044739267577087
749270798606655534161640487061210739993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.33751835510675216334108
044739267577087749270798606655534161640487061210739993
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.95165880220973963625943208788379544148824907742084363339593522173724944949550
Short name T1249
Test name
Test status
Simulation time 834576440 ps
CPU time 3.17 seconds
Started Nov 22 02:38:36 PM PST 23
Finished Nov 22 02:38:40 PM PST 23
Peak memory 203084 kb
Host smart-4544576c-d61f-4efc-a5b8-eb4b00058678
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951658802209739636259432087883795441488249077420843
63339593522173724944949550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_perf.951658802209739636259432087883795441488249077420843
63339593522173724944949550
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.27758699042745575787387299329949837863731119450511001094772327659434465790407
Short name T682
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.41 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:38:45 PM PST 23
Peak memory 203028 kb
Host smart-59f2b6ea-c217-48ea-aef5-d7a79f1544fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775869904274557578738729932994983786373111945051100109477232765943446
5790407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smoke.27758699042745575787387299329949837863731119450511001094772327659434465790407
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.79369701099514157653767020900387177009505220990266119248919281898383161837604
Short name T321
Test name
Test status
Simulation time 66540157934 ps
CPU time 1506.07 seconds
Started Nov 22 02:38:32 PM PST 23
Finished Nov 22 03:03:39 PM PST 23
Peak memory 6983444 kb
Host smart-1b26672d-7e92-4227-9682-6fae1c9905ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79369701099514157653767020900387177009505220990266
119248919281898383161837604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_all.79369701099514157653767020900387177009
505220990266119248919281898383161837604
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.113351619079283556411003403393723244975910163174865219426841810199521614974777
Short name T1506
Test name
Test status
Simulation time 997771563 ps
CPU time 9.04 seconds
Started Nov 22 02:38:32 PM PST 23
Finished Nov 22 02:38:42 PM PST 23
Peak memory 203060 kb
Host smart-7367c230-a04f-4e6d-9dcc-1f5132010280
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133516190792835564110034033937232449759101631748652194268418101995216
14974777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_rd.11335161907928355641100340339372324497591016317486521942684
1810199521614974777
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.56736334415373784915711714549667522640566350163613238584820754888708945338969
Short name T1411
Test name
Test status
Simulation time 14461449567 ps
CPU time 94.79 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:40:10 PM PST 23
Peak memory 1542156 kb
Host smart-3e54c3d1-2921-4f4f-b1d4-960e984a1950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5673633441537378491571171454966752264056635016361323858482075488870894
5338969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_wr.567363344153737849157117145496675226405663501636132385848207
54888708945338969
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.82702690078712749897132052897362919991464124301181680900311885734773052344616
Short name T1057
Test name
Test status
Simulation time 6281818576 ps
CPU time 82.18 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:39:58 PM PST 23
Peak memory 930556 kb
Host smart-8abef250-6735-43b9-a0d4-bdb36400a1d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8270269007871274989713205289736291999146412430118168090031188573477305
2344616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stretch.8270269007871274989713205289736291999146412430118168090031188573
4773052344616
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.12472707326971368981718346652802836362529644583707205405391808538244558120617
Short name T563
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.83 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:38:44 PM PST 23
Peak memory 212624 kb
Host smart-734cc0e7-7c9e-424b-bd71-27b46e0406dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124727073269713689817183466528028363625296445837072
05405391808538244558120617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_timeout.124727073269713689817183466528028363625296445
83707205405391808538244558120617
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_ovf.73998951816016817215135355822755008987464006655086677056772034446285746891571
Short name T1478
Test name
Test status
Simulation time 5445414553 ps
CPU time 110.98 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:40:27 PM PST 23
Peak memory 406804 kb
Host smart-21d08019-3f60-4d64-ab7b-065f6ee0328d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73998951816016817215135355822755008987464006655086
677056772034446285746891571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_tx_ovf.7399895181601681721513535582275500898746400665
5086677056772034446285746891571
Directory /workspace/39.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.47080393176402546511383422358957651963516128314510956702496378953335228375887
Short name T1553
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.77 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:38:42 PM PST 23
Peak memory 205368 kb
Host smart-7a83c796-b45f-45b4-879c-9fea8cf13fed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470803931764025465113834223589576519635161283145109
56702496378953335228375887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_unexp_stop.47080393176402546511383422358957651963516
128314510956702496378953335228375887
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.30372610198734242708301998534551678828677946753427696500273352709432544429306
Short name T1262
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:18:44 PM PST 23
Finished Nov 22 02:18:45 PM PST 23
Peak memory 202408 kb
Host smart-74a55a4e-9cc5-42a6-a073-de9fea3c52e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30372610198734242708301998534551678828677946753427696500273352709432544429306 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_alert_test.30372610198734242708301998534551678828677946753427696500273352709432544429306
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.17081050877806084064368992839966654933312773967275849267514657227815235068928
Short name T1288
Test name
Test status
Simulation time 74225396 ps
CPU time 1.38 seconds
Started Nov 22 02:18:33 PM PST 23
Finished Nov 22 02:18:35 PM PST 23
Peak memory 211196 kb
Host smart-1245280e-53ce-4d18-bc58-c8a97e3a05a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17081050877806084064368992839966654933312773967275849267514657227815235068928 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_host_error_intr.17081050877806084064368992839966654933312773967275849267514657227815235068928
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.96812413521613819177645373421305250272696909941923108465120931761666365738424
Short name T1413
Test name
Test status
Simulation time 606667565 ps
CPU time 6.63 seconds
Started Nov 22 02:18:36 PM PST 23
Finished Nov 22 02:18:43 PM PST 23
Peak memory 273312 kb
Host smart-f3e62400-8783-4dcb-92bf-12f32b5ed127
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96812413521613819177645373421305250272696909941923108465120931761666365738424 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.96812413521613819177645373421305250272696909941923108465120931761666365738424
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.45360899541790230009550825589705709486015601485285999453892013758656059746392
Short name T1347
Test name
Test status
Simulation time 3768267272 ps
CPU time 75.21 seconds
Started Nov 22 02:18:18 PM PST 23
Finished Nov 22 02:19:34 PM PST 23
Peak memory 729356 kb
Host smart-894c85d5-a687-4318-ba48-7f54cf48102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45360899541790230009550825589705709486015601485285999453892013758656059746392 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_host_fifo_full.45360899541790230009550825589705709486015601485285999453892013758656059746392
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.37330551207130608805096040258273361189740340074003396273600341321708833912516
Short name T1504
Test name
Test status
Simulation time 7925734012 ps
CPU time 238.54 seconds
Started Nov 22 02:18:47 PM PST 23
Finished Nov 22 02:22:46 PM PST 23
Peak memory 1271384 kb
Host smart-38b5981d-9c1e-46f3-b8d1-36745658c3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37330551207130608805096040258273361189740340074003396273600341321708833912516 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.i2c_host_fifo_overflow.37330551207130608805096040258273361189740340074003396273600341321708833912516
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.43354242195615373280838839916498742634848735892417465302233912751419700744745
Short name T1517
Test name
Test status
Simulation time 209010032 ps
CPU time 0.96 seconds
Started Nov 22 02:18:36 PM PST 23
Finished Nov 22 02:18:37 PM PST 23
Peak memory 202912 kb
Host smart-a8829738-7352-4d90-b028-ba7fe95ca16a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43354242195615373280838839916498742634848735892417465302233912751419700744745 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.43354242195615373280838839916498742634848735892417465302233912751419700744745
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.68031659126922947800503626751955933306060167230696342482626895184925834383794
Short name T550
Test name
Test status
Simulation time 236313385 ps
CPU time 3.83 seconds
Started Nov 22 02:18:34 PM PST 23
Finished Nov 22 02:18:39 PM PST 23
Peak memory 225464 kb
Host smart-59e70bce-c33f-412e-abae-bac5809a31e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68031659126922947800503626751955933306060167230696342482626895184925834383794 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.68031659126922947800503626751955933306060167230696342482626895184925834383794
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.14448280524614953924783811669531877742195834579252282536997721569678212197019
Short name T246
Test name
Test status
Simulation time 7918519784 ps
CPU time 223.91 seconds
Started Nov 22 02:18:50 PM PST 23
Finished Nov 22 02:22:35 PM PST 23
Peak memory 1310884 kb
Host smart-df5c8799-1fad-4239-b45a-7c19a932bee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14448280524614953924783811669531877742195834579252282536997721569678212197019 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.i2c_host_fifo_watermark.14448280524614953924783811669531877742195834579252282536997721569678212197019
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.111252038476327907967896549843791948731554757343589453833383302165970006698984
Short name T771
Test name
Test status
Simulation time 3754070957 ps
CPU time 52.19 seconds
Started Nov 22 02:18:43 PM PST 23
Finished Nov 22 02:19:36 PM PST 23
Peak memory 293736 kb
Host smart-be80826e-40c6-445b-a123-8e1950e0f708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111252038476327907967896549843791948731554757343589453833383302165970006698984 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.i2c_host_mode_toggle.111252038476327907967896549843791948731554757343589453833383302165970006698984
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.67837221739298393233570699624361922129807636630982316212316409397816194038931
Short name T1328
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:18:31 PM PST 23
Finished Nov 22 02:18:32 PM PST 23
Peak memory 202696 kb
Host smart-8cd80a98-8847-4aab-b913-a2554a16a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67837221739298393233570699624361922129807636630982316212316409397816194038931 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_host_override.67837221739298393233570699624361922129807636630982316212316409397816194038931
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.61366614267934287207003565098435343438360669040301972840201407233810450469739
Short name T1480
Test name
Test status
Simulation time 6830796343 ps
CPU time 63.06 seconds
Started Nov 22 02:18:27 PM PST 23
Finished Nov 22 02:19:31 PM PST 23
Peak memory 211404 kb
Host smart-09299613-ee44-4c71-8b8b-2237871c3255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61366614267934287207003565098435343438360669040301972840201407233810450469739 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.i2c_host_perf.61366614267934287207003565098435343438360669040301972840201407233810450469739
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_rx_oversample.115264138347569187284771191193592313415226015995648918054019240041707019721856
Short name T990
Test name
Test status
Simulation time 3939158762 ps
CPU time 100.47 seconds
Started Nov 22 02:18:20 PM PST 23
Finished Nov 22 02:20:02 PM PST 23
Peak memory 345664 kb
Host smart-bac6394e-bb16-48ba-97d2-c54d65da30f4
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115264138347569187284771191193592313415226015995648918054019240041707019721856 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_rx_oversample.115264138347569187284771191193592313415226015995648918054019240041707019721856
Directory /workspace/4.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.72356414570031284420174251589882151201439104013652202212577653605199900781200
Short name T248
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.51 seconds
Started Nov 22 02:18:35 PM PST 23
Finished Nov 22 02:19:14 PM PST 23
Peak memory 299424 kb
Host smart-44f182b9-4b1b-4534-a4ea-b4a9da73c6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72356414570031284420174251589882151201439104013652202212577653605199900781200 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.i2c_host_smoke.72356414570031284420174251589882151201439104013652202212577653605199900781200
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.72123136132928459775444889078515741273982110436389085094756334195930393719796
Short name T1103
Test name
Test status
Simulation time 32807463528 ps
CPU time 958.55 seconds
Started Nov 22 02:18:27 PM PST 23
Finished Nov 22 02:34:26 PM PST 23
Peak memory 1957012 kb
Host smart-1cef3f04-7ce8-4e32-b46e-689453b24bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72123136132928459775444889078515741273982110436389085094756334195930393719796 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_host_stress_all.72123136132928459775444889078515741273982110436389085094756334195930393719796
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.31614476657809877469503546003109366310473213841122452126109647719145612708580
Short name T1472
Test name
Test status
Simulation time 1466624971 ps
CPU time 12.98 seconds
Started Nov 22 02:18:22 PM PST 23
Finished Nov 22 02:18:35 PM PST 23
Peak memory 213912 kb
Host smart-2aa6a5b5-f5e3-4046-9794-695393694f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31614476657809877469503546003109366310473213841122452126109647719145612708580 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_host_stretch_timeout.31614476657809877469503546003109366310473213841122452126109647719145612708580
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.92291548159480126718759630066064127978616489647806989380581790233416296241326
Short name T43
Test name
Test status
Simulation time 62618346 ps
CPU time 0.83 seconds
Started Nov 22 02:18:38 PM PST 23
Finished Nov 22 02:18:40 PM PST 23
Peak memory 220048 kb
Host smart-da5881c8-4386-4e34-8662-991d2460a3ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92291548159480126718759630066064127978616489647806989380581790233416296241326 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_sec_cm.92291548159480126718759630066064127978616489647806989380581790233416296241326
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.89389839956513905467452064698538607570044209995601388393383029395836163021776
Short name T241
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.74 seconds
Started Nov 22 02:19:08 PM PST 23
Finished Nov 22 02:19:12 PM PST 23
Peak memory 203060 kb
Host smart-2af69b15-b279-4ba2-b7d2-aedf2f08a4be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8938983995651390546745206469853
8607570044209995601388393383029395836163021776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.893898399565139054674520646
98538607570044209995601388393383029395836163021776
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.112189888524830150270013776429454810646288859589196787833174902203825097815465
Short name T454
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.86 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:19:43 PM PST 23
Peak memory 382200 kb
Host smart-009a6231-3891-4180-b1fd-7884d0d9c719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112189888524830150270013776429454810646288859589196
787833174902203825097815465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.1121898885248301502700137764294
54810646288859589196787833174902203825097815465
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.18536235398815927446115077492115864299905867970639234631818786757970636086665
Short name T867
Test name
Test status
Simulation time 10065199023 ps
CPU time 38.17 seconds
Started Nov 22 02:18:38 PM PST 23
Finished Nov 22 02:19:17 PM PST 23
Peak memory 463260 kb
Host smart-0c9764c7-8a10-4b8d-9fa5-f0db2d6463b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185362353988159274461150774921158642999058679706392
34631818786757970636086665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_tx.1853623539881592744611507749211586
4299905867970639234631818786757970636086665
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.16115872669594142298240221521697981587475096053764835682587877407664048683413
Short name T530
Test name
Test status
Simulation time 825344371 ps
CPU time 2.52 seconds
Started Nov 22 02:19:08 PM PST 23
Finished Nov 22 02:19:11 PM PST 23
Peak memory 203060 kb
Host smart-3708211c-3549-40fa-bd26-f7f12066b92e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161158726695941422982402215216979815874750960537648
35682587877407664048683413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_hrst.1611587266959414229824022152169798158747509605376483
5682587877407664048683413
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.98338798979571106709066872843955022422323998300497494749798112845120279376423
Short name T483
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.24 seconds
Started Nov 22 02:18:09 PM PST 23
Finished Nov 22 02:18:14 PM PST 23
Peak memory 203428 kb
Host smart-0f20943d-c0f8-4f71-930b-e3c2c1e28ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98338798979571106709066872843955022422323998300497
494749798112845120279376423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_smoke.98338798979571106709066872843955022422323998
300497494749798112845120279376423
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.111494437582913547926780494810690798738497474809953574236999981078815207611114
Short name T1361
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.34 seconds
Started Nov 22 02:18:21 PM PST 23
Finished Nov 22 02:18:44 PM PST 23
Peak memory 638952 kb
Host smart-aa6565c0-4f39-4a7b-91fc-a234935c8436
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11149443758291354792678049481069079873
8497474809953574236999981078815207611114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.11149443758291354792678
0494810690798738497474809953574236999981078815207611114
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.19461736265549395212793430025921029154079684019613708452119324711263001558202
Short name T888
Test name
Test status
Simulation time 834576440 ps
CPU time 2.98 seconds
Started Nov 22 02:18:52 PM PST 23
Finished Nov 22 02:18:56 PM PST 23
Peak memory 203076 kb
Host smart-09dbde36-ebb1-456d-a6cf-c783b84b1e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194617362655493952127934300259210291540796840196137
08452119324711263001558202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_perf.1946173626554939521279343002592102915407968401961370
8452119324711263001558202
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.23367451647307220916507386965661715435092845916149337730676551709386959835553
Short name T1061
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.71 seconds
Started Nov 22 02:18:36 PM PST 23
Finished Nov 22 02:18:47 PM PST 23
Peak memory 203000 kb
Host smart-431c9b4d-94af-404b-bf8a-49ab48c9f984
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336745164730722091650738696566171543509284591614933773067655170938695
9835553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smoke.23367451647307220916507386965661715435092845916149337730676551709386959835553
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.84812874148186963073784124581842816327361361474838772189602780775034578493627
Short name T46
Test name
Test status
Simulation time 66540157934 ps
CPU time 1292.68 seconds
Started Nov 22 02:19:06 PM PST 23
Finished Nov 22 02:40:40 PM PST 23
Peak memory 6983600 kb
Host smart-4e085bbd-459a-4707-94b0-821f22169af0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84812874148186963073784124581842816327361361474838
772189602780775034578493627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_all.848128741481869630737841245818428163273
61361474838772189602780775034578493627
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.75954667069659565402348700282775832168711533053505705114987711785086122824667
Short name T967
Test name
Test status
Simulation time 997771563 ps
CPU time 8.19 seconds
Started Nov 22 02:18:22 PM PST 23
Finished Nov 22 02:18:30 PM PST 23
Peak memory 202768 kb
Host smart-1e4a56af-6fb5-4511-a1a0-e00a13081725
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7595466706965956540234870028277583216871153305350570511498771178508612
2824667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_rd.7595466706965956540234870028277583216871153305350570511498771
1785086122824667
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.8424525522207295670848394021238981932167079895778261854062258579905512902764
Short name T405
Test name
Test status
Simulation time 14461449567 ps
CPU time 79.62 seconds
Started Nov 22 02:18:42 PM PST 23
Finished Nov 22 02:20:03 PM PST 23
Peak memory 1542044 kb
Host smart-4c3e3f4d-67bf-4e0f-9451-31776f7b85ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8424525522207295670848394021238981932167079895778261854062258579905512
902764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_wr.84245255222072956708483940212389819321670798957782618540622585
79905512902764
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.43417139348048682538952160771655898128512025854455933853999613483353844974970
Short name T632
Test name
Test status
Simulation time 6281818576 ps
CPU time 76.61 seconds
Started Nov 22 02:18:35 PM PST 23
Finished Nov 22 02:19:52 PM PST 23
Peak memory 930492 kb
Host smart-7fb5597c-66ab-43c6-bedf-e9520b0056ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4341713934804868253895216077165589812851202585445593385399961348335384
4974970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stretch.43417139348048682538952160771655898128512025854455933853999613483353844974970
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.46982220020005032938036856099939540860236414654592606166356998593370139596822
Short name T429
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.21 seconds
Started Nov 22 02:18:21 PM PST 23
Finished Nov 22 02:18:29 PM PST 23
Peak memory 212364 kb
Host smart-9608d905-0b24-4654-8b7c-f6b6f260be0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469822200200050329380368560999395408602364146545926
06166356998593370139596822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_timeout.4698222002000503293803685609993954086023641465
4592606166356998593370139596822
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_ovf.65057111973550791687783932837041754579876757027814339532142520001773023043860
Short name T719
Test name
Test status
Simulation time 5445414553 ps
CPU time 152.49 seconds
Started Nov 22 02:18:33 PM PST 23
Finished Nov 22 02:21:06 PM PST 23
Peak memory 406836 kb
Host smart-2711ba2e-e5e8-45e5-b7a1-9306b0347a86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65057111973550791687783932837041754579876757027814
339532142520001773023043860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_tx_ovf.65057111973550791687783932837041754579876757027
814339532142520001773023043860
Directory /workspace/4.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.67588302667750204665240234136764360329006552140625534287279141640085316674898
Short name T275
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.76 seconds
Started Nov 22 02:18:18 PM PST 23
Finished Nov 22 02:18:25 PM PST 23
Peak memory 205320 kb
Host smart-16ed424c-269f-41e1-86cb-b80463adf9c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675883026677502046652402341367643603290065521406255
34287279141640085316674898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_unexp_stop.675883026677502046652402341367643603290065
52140625534287279141640085316674898
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.102462044141385141629008566523788622886010869923360906955106617554716497413164
Short name T1093
Test name
Test status
Simulation time 19975830 ps
CPU time 0.62 seconds
Started Nov 22 02:39:00 PM PST 23
Finished Nov 22 02:39:02 PM PST 23
Peak memory 202776 kb
Host smart-520b9c1f-df1e-4987-b262-dd9e273af149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102462044141385141629008566523788622886010869923360906955106617554716497413164 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 40.i2c_alert_test.102462044141385141629008566523788622886010869923360906955106617554716497413164
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.101515088758755859625891496128245791398034340942007309641058388393416218559673
Short name T1258
Test name
Test status
Simulation time 74225396 ps
CPU time 1.37 seconds
Started Nov 22 02:39:23 PM PST 23
Finished Nov 22 02:39:25 PM PST 23
Peak memory 211248 kb
Host smart-595e4c2f-7298-4a54-958d-25ff5af32a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101515088758755859625891496128245791398034340942007309641058388393416218559673 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_host_error_intr.101515088758755859625891496128245791398034340942007309641058388393416218559673
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.4652774575077193347939866907357308402623918564446865145356071703596465438190
Short name T950
Test name
Test status
Simulation time 606667565 ps
CPU time 7.08 seconds
Started Nov 22 02:39:25 PM PST 23
Finished Nov 22 02:39:33 PM PST 23
Peak memory 273376 kb
Host smart-c1f79ec5-bcb7-416a-9c6d-41dd24a9782d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4652774575077193347939866907357308402623918564446865145356071703596465438190 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.4652774575077193347939866907357308402623918564446865145356071703596465438190
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.19863800131768125004056868004530231093567648698339694240334573116211397369910
Short name T203
Test name
Test status
Simulation time 3768267272 ps
CPU time 67.82 seconds
Started Nov 22 02:38:31 PM PST 23
Finished Nov 22 02:39:40 PM PST 23
Peak memory 729460 kb
Host smart-bbaa91b5-98e6-44bc-b070-67e8bf2d93e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19863800131768125004056868004530231093567648698339694240334573116211397369910 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_host_fifo_full.19863800131768125004056868004530231093567648698339694240334573116211397369910
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.74132311868171102040803345409181856415503660960438640471834152614561940182907
Short name T16
Test name
Test status
Simulation time 7925734012 ps
CPU time 215.26 seconds
Started Nov 22 02:39:02 PM PST 23
Finished Nov 22 02:42:38 PM PST 23
Peak memory 1271616 kb
Host smart-c883f5ce-5ad7-4cdc-b26f-866ca234d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74132311868171102040803345409181856415503660960438640471834152614561940182907 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.i2c_host_fifo_overflow.74132311868171102040803345409181856415503660960438640471834152614561940182907
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.106178672858086222560130373787018202711307199038816732347904339164468013226146
Short name T1496
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:39:01 PM PST 23
Finished Nov 22 02:39:02 PM PST 23
Peak memory 202928 kb
Host smart-67f63504-409f-4fdd-a45b-493c92b5e8b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106178672858086222560130373787018202711307199038816732347904339164468013226146 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.106178672858086222560130373787018202711307199038816732347904339164468013226146
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.67594431103644048647049154011543635451336956661841035461350980239741583166747
Short name T455
Test name
Test status
Simulation time 236313385 ps
CPU time 3.6 seconds
Started Nov 22 02:39:10 PM PST 23
Finished Nov 22 02:39:14 PM PST 23
Peak memory 225456 kb
Host smart-3cbb73a6-ffa8-4591-8a44-ef77231fbbca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67594431103644048647049154011543635451336956661841035461350980239741583166747 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.67594431103644048647049154011543635451336956661841035461350980239741583166747
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.113833989919782828938210484715959339593909306887981549435691604817540837455984
Short name T307
Test name
Test status
Simulation time 7918519784 ps
CPU time 214.13 seconds
Started Nov 22 02:38:31 PM PST 23
Finished Nov 22 02:42:06 PM PST 23
Peak memory 1310924 kb
Host smart-b6416e15-6d0a-4732-ba6d-f466e80f211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113833989919782828938210484715959339593909306887981549435691604817540837455984 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_host_fifo_watermark.113833989919782828938210484715959339593909306887981549435691604817540837455984
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.61674926978105534584664833029045958398538321063519083251323448612963653310255
Short name T1142
Test name
Test status
Simulation time 3754070957 ps
CPU time 52.46 seconds
Started Nov 22 02:38:48 PM PST 23
Finished Nov 22 02:39:41 PM PST 23
Peak memory 293684 kb
Host smart-e9fb2d19-480d-46b3-b566-89ec504f0f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61674926978105534584664833029045958398538321063519083251323448612963653310255 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_host_mode_toggle.61674926978105534584664833029045958398538321063519083251323448612963653310255
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.56034892880945049205372051971719061776375470078002061987127077910763687442567
Short name T204
Test name
Test status
Simulation time 23672229 ps
CPU time 0.67 seconds
Started Nov 22 02:38:34 PM PST 23
Finished Nov 22 02:38:35 PM PST 23
Peak memory 202916 kb
Host smart-915fc72f-842b-4832-986a-7e900e0d58ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56034892880945049205372051971719061776375470078002061987127077910763687442567 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_host_override.56034892880945049205372051971719061776375470078002061987127077910763687442567
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.90520222142552638862837783667040434104461613000314054201765344752444262836277
Short name T865
Test name
Test status
Simulation time 6830796343 ps
CPU time 56.95 seconds
Started Nov 22 02:39:02 PM PST 23
Finished Nov 22 02:40:00 PM PST 23
Peak memory 211364 kb
Host smart-4a3e7cfb-c8ea-4419-8248-b2f168b96d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90520222142552638862837783667040434104461613000314054201765344752444262836277 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.i2c_host_perf.90520222142552638862837783667040434104461613000314054201765344752444262836277
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_rx_oversample.3194124689938988621575522900450121402420475770102257046130298472729017018748
Short name T903
Test name
Test status
Simulation time 3939158762 ps
CPU time 98.15 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:41:35 PM PST 23
Peak memory 345892 kb
Host smart-c6326bad-341e-46b6-95c9-850063226a0b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194124689938988621575522900450121402420475770102257046130298472729017018748 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_rx_oversample.3194124689938988621575522900450121402420475770102257046130298472729017018748
Directory /workspace/40.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.44754281135696688338705661326032683833747399370223349214641047350818283409996
Short name T1365
Test name
Test status
Simulation time 2343171530 ps
CPU time 38.56 seconds
Started Nov 22 02:38:35 PM PST 23
Finished Nov 22 02:39:14 PM PST 23
Peak memory 299496 kb
Host smart-681c6344-c482-4a22-a4cb-352374daab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44754281135696688338705661326032683833747399370223349214641047350818283409996 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.i2c_host_smoke.44754281135696688338705661326032683833747399370223349214641047350818283409996
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.34603566386529494293393878341638010974635517011600399220137647618522477331769
Short name T285
Test name
Test status
Simulation time 32807463528 ps
CPU time 1087.77 seconds
Started Nov 22 02:39:37 PM PST 23
Finished Nov 22 02:57:45 PM PST 23
Peak memory 1957080 kb
Host smart-ecd2dce5-3496-4a80-914d-80df95941259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34603566386529494293393878341638010974635517011600399220137647618522477331769 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_host_stress_all.34603566386529494293393878341638010974635517011600399220137647618522477331769
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.66770633150347495479525988961134292834533672105435850459418361242070227172327
Short name T238
Test name
Test status
Simulation time 1466624971 ps
CPU time 12.87 seconds
Started Nov 22 02:38:59 PM PST 23
Finished Nov 22 02:39:13 PM PST 23
Peak memory 214052 kb
Host smart-34452cfd-0703-4a8c-9726-70f0a1fbb1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66770633150347495479525988961134292834533672105435850459418361242070227172327 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_host_stretch_timeout.66770633150347495479525988961134292834533672105435850459418361242070227172327
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.10307521654570231275451297127657561693291715276675323732628729298941021169209
Short name T1405
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.67 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:40:00 PM PST 23
Peak memory 202980 kb
Host smart-c96093a1-24c3-4025-bae6-77643bec7302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030752165457023127545129712765
7561693291715276675323732628729298941021169209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.10307521654570231275451297
127657561693291715276675323732628729298941021169209
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.100521495219333824353563398682556114242660360701712073339147210007412258306931
Short name T395
Test name
Test status
Simulation time 10166144644 ps
CPU time 30.43 seconds
Started Nov 22 02:39:52 PM PST 23
Finished Nov 22 02:40:23 PM PST 23
Peak memory 382220 kb
Host smart-736ef81f-710a-411c-8e2c-7561974e1e92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100521495219333824353563398682556114242660360701712
073339147210007412258306931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.100521495219333824353563398682
556114242660360701712073339147210007412258306931
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.32290139568413924154522219792563591490773728458501572837831155022999672431180
Short name T193
Test name
Test status
Simulation time 10065199023 ps
CPU time 39.82 seconds
Started Nov 22 02:39:36 PM PST 23
Finished Nov 22 02:40:16 PM PST 23
Peak memory 462100 kb
Host smart-5efa5c5d-b6ff-4f01-8a77-b39b36fd5a80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322901395684139241545222197925635914907737284585015
72837831155022999672431180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_tx.322901395684139241545222197925635
91490773728458501572837831155022999672431180
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.8008446320034734076499854698790325615574540890741770553070509585105951456933
Short name T1027
Test name
Test status
Simulation time 825344371 ps
CPU time 2.47 seconds
Started Nov 22 02:39:11 PM PST 23
Finished Nov 22 02:39:14 PM PST 23
Peak memory 203076 kb
Host smart-33723e40-d58b-405d-95c2-54a41e1f6f9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800844632003473407649985469879032561557454089074177
0553070509585105951456933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_hrst.8008446320034734076499854698790325615574540890741770
553070509585105951456933
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.28348180032304333677977690929267210390673145486710908655080693518876031029374
Short name T706
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.44 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:40:01 PM PST 23
Peak memory 203736 kb
Host smart-2e4b3946-123e-40b4-88ff-89323e020f47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28348180032304333677977690929267210390673145486710
908655080693518876031029374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_smoke.2834818003230433367797769092926721039067314
5486710908655080693518876031029374
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.33252799132568398680655491417632262414321817468356903228223115378573682535513
Short name T1368
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.26 seconds
Started Nov 22 02:39:52 PM PST 23
Finished Nov 22 02:40:13 PM PST 23
Peak memory 639248 kb
Host smart-1c077673-62e1-41d1-bfbf-09616a69ee98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33252799132568398680655491417632262414
321817468356903228223115378573682535513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.33252799132568398680655
491417632262414321817468356903228223115378573682535513
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.51868237840618227986519528177750430406723399715035863693685287862753996946281
Short name T1216
Test name
Test status
Simulation time 834576440 ps
CPU time 2.98 seconds
Started Nov 22 02:39:22 PM PST 23
Finished Nov 22 02:39:25 PM PST 23
Peak memory 203084 kb
Host smart-fbc59297-d086-45e9-b010-e7abdf4f0038
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518682378406182279865195281777504304067233997150358
63693685287862753996946281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_perf.518682378406182279865195281777504304067233997150358
63693685287862753996946281
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.18244965032251331186550939085306240049038088229715507362061701387028001738426
Short name T669
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.5 seconds
Started Nov 22 02:39:53 PM PST 23
Finished Nov 22 02:40:03 PM PST 23
Peak memory 202900 kb
Host smart-6775d9df-f2c5-4f4f-9f9d-59dc0b2eca32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824496503225133118655093908530624004903808822971550736206170138702800
1738426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smoke.18244965032251331186550939085306240049038088229715507362061701387028001738426
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.100108586324880826147054860871104350309952688811700366075665780445585108861248
Short name T403
Test name
Test status
Simulation time 66540157934 ps
CPU time 1624.27 seconds
Started Nov 22 02:39:26 PM PST 23
Finished Nov 22 03:06:31 PM PST 23
Peak memory 6983716 kb
Host smart-1cb72254-639a-41cf-af6e-ed066422cf72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10010858632488082614705486087110435030995268881170
0366075665780445585108861248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_all.1001085863248808261470548608711043503
09952688811700366075665780445585108861248
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.44999377403372136800615480457352721461639272959836550026403055462605061768968
Short name T146
Test name
Test status
Simulation time 997771563 ps
CPU time 8.03 seconds
Started Nov 22 02:39:04 PM PST 23
Finished Nov 22 02:39:13 PM PST 23
Peak memory 203088 kb
Host smart-fa2e3bd6-b3f6-42f3-a64f-49b57da2170f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4499937740337213680061548045735272146163927295983655002640305546260506
1768968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_rd.449993774033721368006154804573527214616392729598365500264030
55462605061768968
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.42438459460422627317366474201641636358778634053304553059538648321570960768615
Short name T1025
Test name
Test status
Simulation time 14461449567 ps
CPU time 78.14 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:41:15 PM PST 23
Peak memory 1542052 kb
Host smart-302e8b88-08e3-4c0c-b91f-e78ac3ffd5d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243845946042262731736647420164163635877863405330455305953864832157096
0768615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_wr.424384594604226273173664742016416363587786340533045530595386
48321570960768615
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.60244397595850141055956633807839387954243856690754432397908020758369883323779
Short name T927
Test name
Test status
Simulation time 6281818576 ps
CPU time 75.39 seconds
Started Nov 22 02:39:19 PM PST 23
Finished Nov 22 02:40:35 PM PST 23
Peak memory 930492 kb
Host smart-3a978d2b-27da-4a27-acc0-fc78634da194
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6024439759585014105595663380783938795424385669075443239790802075836988
3323779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stretch.6024439759585014105595663380783938795424385669075443239790802075
8369883323779
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.79996839990058712591822374358284232449801544541310177727056296101901825232515
Short name T394
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.27 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:40:09 PM PST 23
Peak memory 212632 kb
Host smart-726189eb-802c-478b-b86e-7ab724966dab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799968399900587125918223743582842324498015445413101
77727056296101901825232515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_timeout.799968399900587125918223743582842324498015445
41310177727056296101901825232515
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_ovf.53203896475431779437807912472315608074945712234444880519795507394877485020328
Short name T680
Test name
Test status
Simulation time 5445414553 ps
CPU time 121.91 seconds
Started Nov 22 02:38:46 PM PST 23
Finished Nov 22 02:40:48 PM PST 23
Peak memory 406860 kb
Host smart-f6190a01-2904-4f7f-a4d1-76c6b8c827eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53203896475431779437807912472315608074945712234444
880519795507394877485020328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_tx_ovf.5320389647543177943780791247231560807494571223
4444880519795507394877485020328
Directory /workspace/40.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.39861017569043125969970408251064240073428037095580471452857984513627546386046
Short name T293
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.34 seconds
Started Nov 22 02:39:02 PM PST 23
Finished Nov 22 02:39:08 PM PST 23
Peak memory 205432 kb
Host smart-3d52458c-8388-4b5a-bfda-f1e8725709b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398610175690431259699704082510642400734280370955804
71452857984513627546386046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_unexp_stop.39861017569043125969970408251064240073428
037095580471452857984513627546386046
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.101025129351930280152149329918109636486814103983832940654143393663969336195008
Short name T360
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:39:03 PM PST 23
Finished Nov 22 02:39:04 PM PST 23
Peak memory 202688 kb
Host smart-8da53b28-b207-49fe-8145-65dbabb48a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101025129351930280152149329918109636486814103983832940654143393663969336195008 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_alert_test.101025129351930280152149329918109636486814103983832940654143393663969336195008
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.112205064277254806704992163892715122613420695134817789320136124206187187783575
Short name T1124
Test name
Test status
Simulation time 74225396 ps
CPU time 1.36 seconds
Started Nov 22 02:39:50 PM PST 23
Finished Nov 22 02:39:52 PM PST 23
Peak memory 211308 kb
Host smart-3059766e-8966-42b2-a335-f0b8ef0c1576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112205064277254806704992163892715122613420695134817789320136124206187187783575 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_host_error_intr.112205064277254806704992163892715122613420695134817789320136124206187187783575
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.87559299007891092597023665441611092579454523508466272668428276037171813785374
Short name T602
Test name
Test status
Simulation time 606667565 ps
CPU time 6.69 seconds
Started Nov 22 02:39:15 PM PST 23
Finished Nov 22 02:39:22 PM PST 23
Peak memory 273320 kb
Host smart-93f2003f-6d49-4105-b714-5f4b0d7c80d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87559299007891092597023665441611092579454523508466272668428276037171813785374 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.87559299007891092597023665441611092579454523508466272668428276037171813785374
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.69631842293472827003284154185546556467830297443945160946344854395169633478173
Short name T491
Test name
Test status
Simulation time 3768267272 ps
CPU time 69.18 seconds
Started Nov 22 02:39:04 PM PST 23
Finished Nov 22 02:40:14 PM PST 23
Peak memory 729552 kb
Host smart-f8660ffe-4c0c-45c8-b780-f22bbfc7ec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69631842293472827003284154185546556467830297443945160946344854395169633478173 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_host_fifo_full.69631842293472827003284154185546556467830297443945160946344854395169633478173
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.73704385552752024358522824580139123167082537793266231106641366796289731623993
Short name T966
Test name
Test status
Simulation time 7925734012 ps
CPU time 213.16 seconds
Started Nov 22 02:39:02 PM PST 23
Finished Nov 22 02:42:36 PM PST 23
Peak memory 1271580 kb
Host smart-972d57e0-9882-4580-a5e6-89ca8951d4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73704385552752024358522824580139123167082537793266231106641366796289731623993 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.i2c_host_fifo_overflow.73704385552752024358522824580139123167082537793266231106641366796289731623993
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.57693135588403240756483036465038083820987513168677661904779467912683487027428
Short name T1537
Test name
Test status
Simulation time 209010032 ps
CPU time 0.92 seconds
Started Nov 22 02:38:59 PM PST 23
Finished Nov 22 02:39:01 PM PST 23
Peak memory 202992 kb
Host smart-e00ee06a-2ee9-45ed-ae5b-406235d5957b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57693135588403240756483036465038083820987513168677661904779467912683487027428 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.57693135588403240756483036465038083820987513168677661904779467912683487027428
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.104377449694204348056119156896612471906847357151939224277959740692128102710805
Short name T278
Test name
Test status
Simulation time 236313385 ps
CPU time 3.78 seconds
Started Nov 22 02:39:07 PM PST 23
Finished Nov 22 02:39:11 PM PST 23
Peak memory 225456 kb
Host smart-6e25ed30-348a-4f6d-aa81-c502e0924760
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104377449694204348056119156896612471906847357151939224277959740692128102710805 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.104377449694204348056119156896612471906847357151939224277959740692128102710805
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.75484724076261579023187782717182350519902095956928106479872027366701577205295
Short name T452
Test name
Test status
Simulation time 7918519784 ps
CPU time 213.69 seconds
Started Nov 22 02:39:22 PM PST 23
Finished Nov 22 02:42:57 PM PST 23
Peak memory 1310928 kb
Host smart-c30f238b-f36c-445a-8838-ee8660ed75b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75484724076261579023187782717182350519902095956928106479872027366701577205295 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.i2c_host_fifo_watermark.75484724076261579023187782717182350519902095956928106479872027366701577205295
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.102231155798033463873353812705560933405623214279427154771390290711592098103168
Short name T859
Test name
Test status
Simulation time 3754070957 ps
CPU time 53.21 seconds
Started Nov 22 02:39:26 PM PST 23
Finished Nov 22 02:40:19 PM PST 23
Peak memory 293848 kb
Host smart-1a7a2380-e948-47a7-9a73-410791d3cb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102231155798033463873353812705560933405623214279427154771390290711592098103168 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.i2c_host_mode_toggle.102231155798033463873353812705560933405623214279427154771390290711592098103168
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.64232528328357155578094241620282641918434537963439542828663617769703192773273
Short name T578
Test name
Test status
Simulation time 23672229 ps
CPU time 0.67 seconds
Started Nov 22 02:39:20 PM PST 23
Finished Nov 22 02:39:21 PM PST 23
Peak memory 202900 kb
Host smart-552fecab-4a87-4f1a-ac42-ff80b1fed96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64232528328357155578094241620282641918434537963439542828663617769703192773273 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_host_override.64232528328357155578094241620282641918434537963439542828663617769703192773273
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.54966807886580204796266772536576491714455452947884788456572465507896893564548
Short name T1557
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.58 seconds
Started Nov 22 02:39:51 PM PST 23
Finished Nov 22 02:40:52 PM PST 23
Peak memory 211332 kb
Host smart-773724ad-0db1-41e8-b0a8-50a0ba265217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54966807886580204796266772536576491714455452947884788456572465507896893564548 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.i2c_host_perf.54966807886580204796266772536576491714455452947884788456572465507896893564548
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_rx_oversample.105047607465071982936727040181817520802412371537174352270777681625693712253485
Short name T873
Test name
Test status
Simulation time 3939158762 ps
CPU time 108.39 seconds
Started Nov 22 02:39:06 PM PST 23
Finished Nov 22 02:40:55 PM PST 23
Peak memory 346008 kb
Host smart-1fb572ce-e48e-4468-ba22-c792e1491031
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105047607465071982936727040181817520802412371537174352270777681625693712253485 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_rx_oversample.105047607465071982936727040181817520802412371537174352270777681625693712253485
Directory /workspace/41.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.69606564007033843225379810348664758206869650023608214822256907602709577502105
Short name T245
Test name
Test status
Simulation time 2343171530 ps
CPU time 38.51 seconds
Started Nov 22 02:39:50 PM PST 23
Finished Nov 22 02:40:29 PM PST 23
Peak memory 299388 kb
Host smart-e092d02a-aa40-4129-928e-e847c229b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69606564007033843225379810348664758206869650023608214822256907602709577502105 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.i2c_host_smoke.69606564007033843225379810348664758206869650023608214822256907602709577502105
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.77900660121287293637991628398479120310239142283752072039017183555110256144439
Short name T574
Test name
Test status
Simulation time 32807463528 ps
CPU time 1073.69 seconds
Started Nov 22 02:39:52 PM PST 23
Finished Nov 22 02:57:47 PM PST 23
Peak memory 1957128 kb
Host smart-b747e4d6-4bff-48c7-83ac-d110b3d441ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77900660121287293637991628398479120310239142283752072039017183555110256144439 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_host_stress_all.77900660121287293637991628398479120310239142283752072039017183555110256144439
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.64611321657512858846405813222452982940794406859202569268511816960960692887769
Short name T592
Test name
Test status
Simulation time 1466624971 ps
CPU time 13 seconds
Started Nov 22 02:39:08 PM PST 23
Finished Nov 22 02:39:22 PM PST 23
Peak memory 214092 kb
Host smart-061f6862-b79d-4c46-8ccb-1f43c33bf5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64611321657512858846405813222452982940794406859202569268511816960960692887769 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_host_stretch_timeout.64611321657512858846405813222452982940794406859202569268511816960960692887769
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.12229903400482951281210561181346391733744993481136979927880980900553039490098
Short name T1120
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.71 seconds
Started Nov 22 02:39:10 PM PST 23
Finished Nov 22 02:39:14 PM PST 23
Peak memory 203108 kb
Host smart-bb053642-be38-42d0-9b7a-f0eac9b47c2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222990340048295128121056118134
6391733744993481136979927880980900553039490098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.12229903400482951281210561
181346391733744993481136979927880980900553039490098
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.24672392968377620227714511058058734193373821450060368105150056981324639036344
Short name T1162
Test name
Test status
Simulation time 10166144644 ps
CPU time 34.33 seconds
Started Nov 22 02:39:08 PM PST 23
Finished Nov 22 02:39:43 PM PST 23
Peak memory 382116 kb
Host smart-e9bc5b55-3b7c-4392-a280-564b5e394f74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246723929683776202277145110580587341933738214500603
68105150056981324639036344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_acq.2467239296837762022771451105805
8734193373821450060368105150056981324639036344
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.54603489278336202634281137851283065473100601190515807141922786694897259322049
Short name T1370
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.76 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:40:39 PM PST 23
Peak memory 462104 kb
Host smart-c50915c9-7c68-475e-826b-8664923fe5c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546034892783362026342811378512830654731006011905158
07141922786694897259322049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_tx.546034892783362026342811378512830
65473100601190515807141922786694897259322049
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.112842912611263910891259866496570336027169875312976858869480983407705045779439
Short name T269
Test name
Test status
Simulation time 825344371 ps
CPU time 2.41 seconds
Started Nov 22 02:39:49 PM PST 23
Finished Nov 22 02:39:52 PM PST 23
Peak memory 203036 kb
Host smart-861433eb-d1d0-44a1-9b77-c18b038711a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112842912611263910891259866496570336027169875312976
858869480983407705045779439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_hrst.11284291261126391089125986649657033602716987531297
6858869480983407705045779439
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.99290204422264175640845458836575347514464321475816816719762276154735944188610
Short name T488
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.28 seconds
Started Nov 22 02:39:00 PM PST 23
Finished Nov 22 02:39:05 PM PST 23
Peak memory 203664 kb
Host smart-0a90ecfb-e29c-407e-ac29-6fffd3bbb4f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99290204422264175640845458836575347514464321475816
816719762276154735944188610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_smoke.9929020442226417564084545883657534751446432
1475816816719762276154735944188610
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.114520892888370213924580541735075310164028403176739309204246165841408433223746
Short name T431
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.62 seconds
Started Nov 22 02:39:48 PM PST 23
Finished Nov 22 02:40:13 PM PST 23
Peak memory 639220 kb
Host smart-d6eb89d8-561a-4067-b22a-76c4d79d0201
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11452089288837021392458054173507531016
4028403176739309204246165841408433223746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.1145208928883702139245
80541735075310164028403176739309204246165841408433223746
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.92248183513611633019368633987982861538216529807535629104259624021984964770276
Short name T542
Test name
Test status
Simulation time 834576440 ps
CPU time 3.06 seconds
Started Nov 22 02:39:53 PM PST 23
Finished Nov 22 02:39:56 PM PST 23
Peak memory 203084 kb
Host smart-f3dde6c1-858d-488b-9e93-886367ece3b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922481835136116330193686339879828615382165298075356
29104259624021984964770276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_perf.922481835136116330193686339879828615382165298075356
29104259624021984964770276
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.89480762844676044266838187962323239604366019206493598830177717847950541452604
Short name T168
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.52 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:40:11 PM PST 23
Peak memory 202968 kb
Host smart-0ef7efd8-e063-4077-91aa-578350109001
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8948076284467604426683818796232323960436601920649359883017771784795054
1452604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smoke.89480762844676044266838187962323239604366019206493598830177717847950541452604
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.58879832341563720170416658210104149131661291220880275713536633851708355657065
Short name T1180
Test name
Test status
Simulation time 66540157934 ps
CPU time 1643.12 seconds
Started Nov 22 02:39:55 PM PST 23
Finished Nov 22 03:07:19 PM PST 23
Peak memory 6983332 kb
Host smart-608642cd-87d6-4ac0-8759-3caa19dde751
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58879832341563720170416658210104149131661291220880
275713536633851708355657065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_all.58879832341563720170416658210104149131
661291220880275713536633851708355657065
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.64830731413325236072647546093206482497739709893831333161049903740763502918278
Short name T418
Test name
Test status
Simulation time 997771563 ps
CPU time 8.34 seconds
Started Nov 22 02:39:14 PM PST 23
Finished Nov 22 02:39:23 PM PST 23
Peak memory 203104 kb
Host smart-fd847eb1-5e24-43fc-a023-a76aefece467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6483073141332523607264754609320648249773970989383133316104990374076350
2918278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_rd.648307314133252360726475460932064824977397098938313331610499
03740763502918278
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.91560196188916287644033508407176471670094006205860703221417756871907763212540
Short name T1176
Test name
Test status
Simulation time 14461449567 ps
CPU time 97.77 seconds
Started Nov 22 02:39:11 PM PST 23
Finished Nov 22 02:40:49 PM PST 23
Peak memory 1542168 kb
Host smart-39edcdc7-a29c-41a0-a1ae-be2766331ca0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9156019618891628764403350840717647167009400620586070322141775687190776
3212540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_wr.915601961889162876440335084071764716700940062058607032214177
56871907763212540
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.90802998560955434260874815836467221517399505093824668672816944762851059712874
Short name T1152
Test name
Test status
Simulation time 6281818576 ps
CPU time 72.72 seconds
Started Nov 22 02:39:52 PM PST 23
Finished Nov 22 02:41:05 PM PST 23
Peak memory 930584 kb
Host smart-9e9f88af-9844-4848-b494-62a09908c3d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9080299856095543426087481583646722151739950509382466867281694476285105
9712874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stretch.9080299856095543426087481583646722151739950509382466867281694476
2851059712874
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.22599581941241449851073162593668906423616368502466856175535506081888756208230
Short name T489
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.18 seconds
Started Nov 22 02:39:00 PM PST 23
Finished Nov 22 02:39:07 PM PST 23
Peak memory 212612 kb
Host smart-2a8c0e84-ac15-4b7a-9601-9b7ad8560594
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225995819412414498510731625936689064236163685024668
56175535506081888756208230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_timeout.225995819412414498510731625936689064236163685
02466856175535506081888756208230
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_ovf.84375034671929881517540222848540341887652140823532658750064754306822114253630
Short name T1457
Test name
Test status
Simulation time 5445414553 ps
CPU time 130.78 seconds
Started Nov 22 02:39:25 PM PST 23
Finished Nov 22 02:41:36 PM PST 23
Peak memory 406848 kb
Host smart-4d015bdc-e8be-4427-98a8-074afa6f6abc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84375034671929881517540222848540341887652140823532
658750064754306822114253630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_tx_ovf.8437503467192988151754022284854034188765214082
3532658750064754306822114253630
Directory /workspace/41.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.77293444219221785234973144891649336838223690906442703716213222937420006591064
Short name T787
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.63 seconds
Started Nov 22 02:39:53 PM PST 23
Finished Nov 22 02:39:59 PM PST 23
Peak memory 205256 kb
Host smart-92ce134a-7ac2-4823-a47c-69828852a565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772934442192217852349731448916493368382236909064427
03716213222937420006591064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_unexp_stop.77293444219221785234973144891649336838223
690906442703716213222937420006591064
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.61680597658480790934418203977165633375265081913560477589561420818781116357674
Short name T334
Test name
Test status
Simulation time 19975830 ps
CPU time 0.6 seconds
Started Nov 22 02:40:12 PM PST 23
Finished Nov 22 02:40:13 PM PST 23
Peak memory 202724 kb
Host smart-7a051cb7-d760-4444-96e0-eb93f86e6b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61680597658480790934418203977165633375265081913560477589561420818781116357674 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_alert_test.61680597658480790934418203977165633375265081913560477589561420818781116357674
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.14061864404963975359995354021905323427602673677924276144332681231294081710089
Short name T386
Test name
Test status
Simulation time 74225396 ps
CPU time 1.36 seconds
Started Nov 22 02:39:24 PM PST 23
Finished Nov 22 02:39:26 PM PST 23
Peak memory 211356 kb
Host smart-7c1e9834-ff56-4dec-bdef-c708fce08177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14061864404963975359995354021905323427602673677924276144332681231294081710089 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_host_error_intr.14061864404963975359995354021905323427602673677924276144332681231294081710089
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.106546799848597933103425031654824099594955697011313983483645392281868419472592
Short name T933
Test name
Test status
Simulation time 606667565 ps
CPU time 6.67 seconds
Started Nov 22 02:39:49 PM PST 23
Finished Nov 22 02:39:57 PM PST 23
Peak memory 273368 kb
Host smart-5461e39e-f016-40bc-bdc1-cd592390fda7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106546799848597933103425031654824099594955697011313983483645392281868419472592 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.106546799848597933103425031654824099594955697011313983483645392281868419472592
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.95364671005584342765141143930714613534680133368051864682462105622390332232855
Short name T780
Test name
Test status
Simulation time 3768267272 ps
CPU time 72.52 seconds
Started Nov 22 02:39:15 PM PST 23
Finished Nov 22 02:40:28 PM PST 23
Peak memory 729560 kb
Host smart-fdb7054e-3ae0-4d1e-8f0f-0a0623c15974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95364671005584342765141143930714613534680133368051864682462105622390332232855 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_host_fifo_full.95364671005584342765141143930714613534680133368051864682462105622390332232855
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.56161711463987506810144897385401650377814061615813482112279898286161609058219
Short name T315
Test name
Test status
Simulation time 7925734012 ps
CPU time 229.56 seconds
Started Nov 22 02:39:15 PM PST 23
Finished Nov 22 02:43:05 PM PST 23
Peak memory 1271636 kb
Host smart-ac3034e7-0a1a-4c6c-99c1-a93b2de5d2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56161711463987506810144897385401650377814061615813482112279898286161609058219 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.i2c_host_fifo_overflow.56161711463987506810144897385401650377814061615813482112279898286161609058219
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.56721192938364704984934746027356897502298488481845754279970010449576029098785
Short name T1117
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:39:52 PM PST 23
Finished Nov 22 02:39:53 PM PST 23
Peak memory 202900 kb
Host smart-12a84ef8-0519-4345-96f5-461c6db59bf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56721192938364704984934746027356897502298488481845754279970010449576029098785 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.56721192938364704984934746027356897502298488481845754279970010449576029098785
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.22494605580480433771088833138559027140460411871813592525916680514442933669575
Short name T1376
Test name
Test status
Simulation time 236313385 ps
CPU time 3.83 seconds
Started Nov 22 02:39:10 PM PST 23
Finished Nov 22 02:39:14 PM PST 23
Peak memory 225500 kb
Host smart-65e9ee1d-5f28-449d-b2bc-3cdf86baff1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22494605580480433771088833138559027140460411871813592525916680514442933669575 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.22494605580480433771088833138559027140460411871813592525916680514442933669575
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.78749209343188008969664505186618918948258249111764579101956048745089549896975
Short name T101
Test name
Test status
Simulation time 7918519784 ps
CPU time 198.55 seconds
Started Nov 22 02:39:03 PM PST 23
Finished Nov 22 02:42:22 PM PST 23
Peak memory 1310908 kb
Host smart-023b12da-2850-4eea-bf22-8a3f295c1747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78749209343188008969664505186618918948258249111764579101956048745089549896975 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.i2c_host_fifo_watermark.78749209343188008969664505186618918948258249111764579101956048745089549896975
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.66819084126019009105309620687729932533848900283738037336878103208552404257530
Short name T577
Test name
Test status
Simulation time 3754070957 ps
CPU time 50.95 seconds
Started Nov 22 02:40:24 PM PST 23
Finished Nov 22 02:41:16 PM PST 23
Peak memory 293804 kb
Host smart-10f3b91d-36b1-4185-b8db-3be98fa4f2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66819084126019009105309620687729932533848900283738037336878103208552404257530 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_host_mode_toggle.66819084126019009105309620687729932533848900283738037336878103208552404257530
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.11021224685031546524417907200073387018326447262200310007659165987930547465538
Short name T1296
Test name
Test status
Simulation time 23672229 ps
CPU time 0.61 seconds
Started Nov 22 02:39:22 PM PST 23
Finished Nov 22 02:39:23 PM PST 23
Peak memory 202900 kb
Host smart-5c033220-0282-4700-a337-a5eb816c9965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11021224685031546524417907200073387018326447262200310007659165987930547465538 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_host_override.11021224685031546524417907200073387018326447262200310007659165987930547465538
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.62639467542295203058564098540259567444657755497982672312316513155386658682470
Short name T1168
Test name
Test status
Simulation time 6830796343 ps
CPU time 61.85 seconds
Started Nov 22 02:39:10 PM PST 23
Finished Nov 22 02:40:12 PM PST 23
Peak memory 211392 kb
Host smart-076ec567-6484-4055-8e8c-2d6296493e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62639467542295203058564098540259567444657755497982672312316513155386658682470 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.i2c_host_perf.62639467542295203058564098540259567444657755497982672312316513155386658682470
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_rx_oversample.48646936035087618348826798653133460668244781918556245571137687288871306412306
Short name T1236
Test name
Test status
Simulation time 3939158762 ps
CPU time 110.56 seconds
Started Nov 22 02:39:52 PM PST 23
Finished Nov 22 02:41:43 PM PST 23
Peak memory 345912 kb
Host smart-01151fee-b28d-418b-8e4a-27c27916f5be
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48646936035087618348826798653133460668244781918556245571137687288871306412306 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_rx_oversample.48646936035087618348826798653133460668244781918556245571137687288871306412306
Directory /workspace/42.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.98806361858045212853335698906257682808933090498501377300504097751839257192222
Short name T1085
Test name
Test status
Simulation time 2343171530 ps
CPU time 34.88 seconds
Started Nov 22 02:39:02 PM PST 23
Finished Nov 22 02:39:37 PM PST 23
Peak memory 299496 kb
Host smart-bb404aa7-121f-4a57-8872-da863af1d825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98806361858045212853335698906257682808933090498501377300504097751839257192222 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.i2c_host_smoke.98806361858045212853335698906257682808933090498501377300504097751839257192222
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.18862383715243148450809599079205134799048104422667912567943966544859927055871
Short name T1007
Test name
Test status
Simulation time 32807463528 ps
CPU time 1105.22 seconds
Started Nov 22 02:39:25 PM PST 23
Finished Nov 22 02:57:51 PM PST 23
Peak memory 1957164 kb
Host smart-850e66de-9866-4c29-ac68-b5e15b343c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18862383715243148450809599079205134799048104422667912567943966544859927055871 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_host_stress_all.18862383715243148450809599079205134799048104422667912567943966544859927055871
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.90079698677771201192953209983340229592024311074968701078332034595532736506876
Short name T818
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.38 seconds
Started Nov 22 02:39:49 PM PST 23
Finished Nov 22 02:40:03 PM PST 23
Peak memory 214184 kb
Host smart-eec06d7b-4e03-42a4-b0b3-e3ccaeefb4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90079698677771201192953209983340229592024311074968701078332034595532736506876 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_host_stretch_timeout.90079698677771201192953209983340229592024311074968701078332034595532736506876
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.75569065799312652816123956746610156319914916478590507690039903357948110716472
Short name T686
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.7 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:40:00 PM PST 23
Peak memory 202920 kb
Host smart-85c8525d-d562-4545-8e1a-0b73348aa3f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7556906579931265281612395674661
0156319914916478590507690039903357948110716472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.75569065799312652816123956
746610156319914916478590507690039903357948110716472
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.15814126544947836157051345493168654746314038223394132508528155883328700120617
Short name T549
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.89 seconds
Started Nov 22 02:40:26 PM PST 23
Finished Nov 22 02:41:00 PM PST 23
Peak memory 382240 kb
Host smart-6cf554d7-90a6-4806-bf9d-5461ad504b16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158141265449478361570513454931686547463140382233941
32508528155883328700120617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.1581412654494783615705134549316
8654746314038223394132508528155883328700120617
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.87506726010890667574967545669262101556503268827710498949004244787944944552092
Short name T1155
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.62 seconds
Started Nov 22 02:39:24 PM PST 23
Finished Nov 22 02:40:01 PM PST 23
Peak memory 462068 kb
Host smart-133ae6fa-40a5-40d1-b2ca-b86ebb815856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875067260108906675749675456692621015565032688277104
98949004244787944944552092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_tx.875067260108906675749675456692621
01556503268827710498949004244787944944552092
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.32043404421270918978070206563739888572485358492010760777656374484939575894089
Short name T880
Test name
Test status
Simulation time 825344371 ps
CPU time 2.47 seconds
Started Nov 22 02:39:57 PM PST 23
Finished Nov 22 02:40:00 PM PST 23
Peak memory 203084 kb
Host smart-fb94fada-fea0-4704-9e9b-01b2bbc27970
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320434044212709189780702065637398885724853584920107
60777656374484939575894089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_hrst.320434044212709189780702065637398885724853584920107
60777656374484939575894089
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.3594659028606221815320022925217152743618512236552771871106543384882919311436
Short name T603
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.22 seconds
Started Nov 22 02:39:23 PM PST 23
Finished Nov 22 02:39:28 PM PST 23
Peak memory 203704 kb
Host smart-2a772b75-6263-4380-9b1f-897f35c2591d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35946590286062218153200229252171527436185122365527
71871106543384882919311436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_smoke.35946590286062218153200229252171527436185122
36552771871106543384882919311436
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.63759499257467331317781803226291107383771834727783353982407065384826800199096
Short name T1474
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.01 seconds
Started Nov 22 02:39:25 PM PST 23
Finished Nov 22 02:39:48 PM PST 23
Peak memory 639208 kb
Host smart-847cc9b6-64c2-4762-aa9b-add1827c5f3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63759499257467331317781803226291107383
771834727783353982407065384826800199096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.63759499257467331317781
803226291107383771834727783353982407065384826800199096
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.89010840662378446020044366669464473909516832277133803086387308015000492418559
Short name T928
Test name
Test status
Simulation time 834576440 ps
CPU time 2.94 seconds
Started Nov 22 02:39:57 PM PST 23
Finished Nov 22 02:40:00 PM PST 23
Peak memory 202900 kb
Host smart-b9253ae2-afdc-487e-af7a-549c19a79994
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890108406623784460200443666694644739095168322771338
03086387308015000492418559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_perf.890108406623784460200443666694644739095168322771338
03086387308015000492418559
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.58404883008624185903575725800564594494318031427521234872636539420353144847507
Short name T1482
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.61 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:40:11 PM PST 23
Peak memory 202968 kb
Host smart-50f23585-b486-4b14-8a1e-82a30b2c3856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5840488300862418590357572580056459449431803142752123487263653942035314
4847507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smoke.58404883008624185903575725800564594494318031427521234872636539420353144847507
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.43636378931119855486863657483021352622401638435794867912881306976672149621093
Short name T47
Test name
Test status
Simulation time 66540157934 ps
CPU time 1508.75 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 03:05:11 PM PST 23
Peak memory 6983284 kb
Host smart-ff47c334-4674-4d64-ac62-d4733133606a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43636378931119855486863657483021352622401638435794
867912881306976672149621093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_all.43636378931119855486863657483021352622
401638435794867912881306976672149621093
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.102797969344793892775912932182626915039424742781963736243672065997827579438675
Short name T1014
Test name
Test status
Simulation time 997771563 ps
CPU time 8.4 seconds
Started Nov 22 02:39:25 PM PST 23
Finished Nov 22 02:39:34 PM PST 23
Peak memory 202944 kb
Host smart-a96ddbf0-b901-40d1-92e7-4782726cba1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027979693447938927759129321826269150394247427819637362436720659978275
79438675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_rd.10279796934479389277591293218262691503942474278196373624367
2065997827579438675
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.98436103274363353304667800632779038429733787737347082375974249227909333152648
Short name T586
Test name
Test status
Simulation time 14461449567 ps
CPU time 85.45 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:41:22 PM PST 23
Peak memory 1542156 kb
Host smart-b396aea5-e281-4162-86e0-099cef2eb00d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9843610327436335330466780063277903842973378773734708237597424922790933
3152648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_wr.984361032743633533046678006327790384297337877373470823759742
49227909333152648
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.107949728228935687738442821475454781236561013090323837077345757814153832704262
Short name T493
Test name
Test status
Simulation time 6281818576 ps
CPU time 79.86 seconds
Started Nov 22 02:39:51 PM PST 23
Finished Nov 22 02:41:12 PM PST 23
Peak memory 930592 kb
Host smart-1f736741-97bf-4bdf-af70-100de464c81b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079497282289356877384428214754547812365610130903238370773457578141538
32704262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stretch.107949728228935687738442821475454781236561013090323837077345757
814153832704262
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.50357118517073385415868711901967846931644910937086432476457366320821584279764
Short name T573
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.36 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:40:04 PM PST 23
Peak memory 212676 kb
Host smart-939e3e06-c4a0-47b2-a42d-145d29e43842
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503571185170733854158687119019678469316449109370864
32476457366320821584279764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_timeout.503571185170733854158687119019678469316449109
37086432476457366320821584279764
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_ovf.83128057452735312330564807213599029882501102791143023978984328117236524856025
Short name T1305
Test name
Test status
Simulation time 5445414553 ps
CPU time 121.58 seconds
Started Nov 22 02:39:51 PM PST 23
Finished Nov 22 02:41:53 PM PST 23
Peak memory 406820 kb
Host smart-a5b1dc2d-4164-4df1-b432-7f39b671f069
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83128057452735312330564807213599029882501102791143
023978984328117236524856025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_tx_ovf.8312805745273531233056480721359902988250110279
1143023978984328117236524856025
Directory /workspace/42.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.84194010598697123333270517456886377314265684148899276103660373869450038494216
Short name T1130
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.67 seconds
Started Nov 22 02:39:29 PM PST 23
Finished Nov 22 02:39:35 PM PST 23
Peak memory 205380 kb
Host smart-119d35e3-7d9c-429a-b1e5-19a9e233d0a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841940105986971233332705174568863773142656841488992
76103660373869450038494216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_unexp_stop.84194010598697123333270517456886377314265
684148899276103660373869450038494216
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.91783374614912820595230017976200871138855230992271476007814382402941762785041
Short name T1226
Test name
Test status
Simulation time 19975830 ps
CPU time 0.6 seconds
Started Nov 22 02:39:29 PM PST 23
Finished Nov 22 02:39:30 PM PST 23
Peak memory 202800 kb
Host smart-ab6375a7-a7e8-4db0-b099-7af33612a312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91783374614912820595230017976200871138855230992271476007814382402941762785041 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_alert_test.91783374614912820595230017976200871138855230992271476007814382402941762785041
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.90268451312958632272477787637210737978889250058725892774681690551020877596132
Short name T570
Test name
Test status
Simulation time 74225396 ps
CPU time 1.3 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:39:58 PM PST 23
Peak memory 211188 kb
Host smart-05ee1d92-4e13-4343-9abc-7f9a23ef4072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90268451312958632272477787637210737978889250058725892774681690551020877596132 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_host_error_intr.90268451312958632272477787637210737978889250058725892774681690551020877596132
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.41170641417238333721054115375231944036046939792239117414662409628710708700042
Short name T817
Test name
Test status
Simulation time 606667565 ps
CPU time 6.58 seconds
Started Nov 22 02:39:50 PM PST 23
Finished Nov 22 02:39:58 PM PST 23
Peak memory 273384 kb
Host smart-fec5dc3d-4d55-42d3-b90f-85bc227f93e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41170641417238333721054115375231944036046939792239117414662409628710708700042 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.41170641417238333721054115375231944036046939792239117414662409628710708700042
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.102534822568836945010341179161253189108781605490746530766766811979809921503767
Short name T1268
Test name
Test status
Simulation time 3768267272 ps
CPU time 72.92 seconds
Started Nov 22 02:39:11 PM PST 23
Finished Nov 22 02:40:24 PM PST 23
Peak memory 729460 kb
Host smart-b2eaff50-25fd-4372-bd09-8273f8ee279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102534822568836945010341179161253189108781605490746530766766811979809921503767 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_host_fifo_full.102534822568836945010341179161253189108781605490746530766766811979809921503767
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.724241469940991853718934734355862660880592697516681136475732542318557462771
Short name T1580
Test name
Test status
Simulation time 7925734012 ps
CPU time 222.29 seconds
Started Nov 22 02:39:37 PM PST 23
Finished Nov 22 02:43:19 PM PST 23
Peak memory 1271592 kb
Host smart-9636d5d6-6194-40ad-9b57-2b5ba8aebb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724241469940991853718934734355862660880592697516681136475732542318557462771 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_host_fifo_overflow.724241469940991853718934734355862660880592697516681136475732542318557462771
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.25358252291846043485371044868245857006660826471090743047689675409081712996539
Short name T921
Test name
Test status
Simulation time 209010032 ps
CPU time 0.94 seconds
Started Nov 22 02:39:55 PM PST 23
Finished Nov 22 02:39:57 PM PST 23
Peak memory 202964 kb
Host smart-648e80f6-e9b3-4813-9fd9-e12e2b1e8cfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25358252291846043485371044868245857006660826471090743047689675409081712996539 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.25358252291846043485371044868245857006660826471090743047689675409081712996539
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.65407333668141093025543409535684701249103169045793975889527001962175308360785
Short name T885
Test name
Test status
Simulation time 236313385 ps
CPU time 3.74 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:40:01 PM PST 23
Peak memory 225380 kb
Host smart-06ed22aa-6bae-4ae8-874e-f5dd39573205
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65407333668141093025543409535684701249103169045793975889527001962175308360785 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.65407333668141093025543409535684701249103169045793975889527001962175308360785
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.44959148416352575803520745169569214023385762747916246436505289116890194527353
Short name T962
Test name
Test status
Simulation time 7918519784 ps
CPU time 221.7 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:43:39 PM PST 23
Peak memory 1310884 kb
Host smart-93262c4d-9cc9-4241-b374-28de945dea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44959148416352575803520745169569214023385762747916246436505289116890194527353 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_host_fifo_watermark.44959148416352575803520745169569214023385762747916246436505289116890194527353
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.43464247339324558537490082225396735286822349184446717556426669834855802796277
Short name T662
Test name
Test status
Simulation time 3754070957 ps
CPU time 60.53 seconds
Started Nov 22 02:39:35 PM PST 23
Finished Nov 22 02:40:36 PM PST 23
Peak memory 293828 kb
Host smart-7fd9786f-f2a7-4c2e-9c08-09feadb6ae11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43464247339324558537490082225396735286822349184446717556426669834855802796277 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_host_mode_toggle.43464247339324558537490082225396735286822349184446717556426669834855802796277
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.21735998873734157940295921867375782984772147274008360657350894970129437971128
Short name T1450
Test name
Test status
Simulation time 23672229 ps
CPU time 0.65 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:40:32 PM PST 23
Peak memory 202928 kb
Host smart-41e03d41-6798-49e8-b61d-a25b9e7af90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21735998873734157940295921867375782984772147274008360657350894970129437971128 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_host_override.21735998873734157940295921867375782984772147274008360657350894970129437971128
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.103008174212324194504307032723105606796698886282712766918305515569605730428462
Short name T902
Test name
Test status
Simulation time 6830796343 ps
CPU time 59.83 seconds
Started Nov 22 02:39:15 PM PST 23
Finished Nov 22 02:40:15 PM PST 23
Peak memory 211108 kb
Host smart-0bc80bfe-7d80-4e3d-ab3b-e93abba24764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103008174212324194504307032723105606796698886282712766918305515569605730428462 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.i2c_host_perf.103008174212324194504307032723105606796698886282712766918305515569605730428462
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_rx_oversample.66077921167308833242416964656670816362527833291172163450073415783317892969948
Short name T1528
Test name
Test status
Simulation time 3939158762 ps
CPU time 107.35 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:42:24 PM PST 23
Peak memory 345864 kb
Host smart-f4fbac01-0c54-44d4-8d5a-4aa2652627e5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66077921167308833242416964656670816362527833291172163450073415783317892969948 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_rx_oversample.66077921167308833242416964656670816362527833291172163450073415783317892969948
Directory /workspace/43.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.102284743969848841804722558084277233852606958367800276748675620107162450318849
Short name T251
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.48 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:41:09 PM PST 23
Peak memory 299344 kb
Host smart-5758e397-2477-4a86-a471-e90f3272fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102284743969848841804722558084277233852606958367800276748675620107162450318849 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.i2c_host_smoke.102284743969848841804722558084277233852606958367800276748675620107162450318849
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.62492767224555228428355255320121605414669586689535397615435679653783735033451
Short name T1383
Test name
Test status
Simulation time 32807463528 ps
CPU time 1119.85 seconds
Started Nov 22 02:39:57 PM PST 23
Finished Nov 22 02:58:38 PM PST 23
Peak memory 1956944 kb
Host smart-98ca24db-79f5-4bde-8373-9cf623456d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62492767224555228428355255320121605414669586689535397615435679653783735033451 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_host_stress_all.62492767224555228428355255320121605414669586689535397615435679653783735033451
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.22401611738413096261137235846581471418832008239926594924658851242986371717967
Short name T1087
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.31 seconds
Started Nov 22 02:39:15 PM PST 23
Finished Nov 22 02:39:29 PM PST 23
Peak memory 214104 kb
Host smart-b7703d83-ad4f-47c2-a4ee-0c0c073066e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22401611738413096261137235846581471418832008239926594924658851242986371717967 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_host_stretch_timeout.22401611738413096261137235846581471418832008239926594924658851242986371717967
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.45915336005390935170604280346158767940637468598188069996768827014968618593770
Short name T216
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.84 seconds
Started Nov 22 02:39:29 PM PST 23
Finished Nov 22 02:39:33 PM PST 23
Peak memory 203108 kb
Host smart-bb887838-0965-4b33-b3be-149bb4a08016
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4591533600539093517060428034615
8767940637468598188069996768827014968618593770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.45915336005390935170604280
346158767940637468598188069996768827014968618593770
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.8152998872260026295866654190038891114802564548533879409726497022602489461734
Short name T581
Test name
Test status
Simulation time 10166144644 ps
CPU time 34.87 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:40:37 PM PST 23
Peak memory 382228 kb
Host smart-f62986e6-52cd-428d-95b1-da62e0206a99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815299887226002629586665419003889111480256454853387
9409726497022602489461734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_acq.81529988722600262958666541900388
91114802564548533879409726497022602489461734
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.99748341928620894409310822936806193549192877542545603104302485328590425314542
Short name T1160
Test name
Test status
Simulation time 10065199023 ps
CPU time 40.43 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:43 PM PST 23
Peak memory 462032 kb
Host smart-05861443-7558-4035-a05f-0ed00aa645cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997483419286208944093108229368061935491928775425456
03104302485328590425314542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_tx.997483419286208944093108229368061
93549192877542545603104302485328590425314542
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.20054813968784230679058553182053209733016434014670958568836671255645315504965
Short name T349
Test name
Test status
Simulation time 825344371 ps
CPU time 2.38 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:39:59 PM PST 23
Peak memory 203084 kb
Host smart-a9f18516-4fc3-46c7-ae5e-70ddcae105f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200548139687842306790585531820532097330164340146709
58568836671255645315504965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_hrst.200548139687842306790585531820532097330164340146709
58568836671255645315504965
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.30056695130072645970873978941951571588790604271118781613700775714774120793235
Short name T309
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.14 seconds
Started Nov 22 02:39:53 PM PST 23
Finished Nov 22 02:39:58 PM PST 23
Peak memory 203640 kb
Host smart-823c1948-ff94-46f4-a4c8-e7f06aca8c64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30056695130072645970873978941951571588790604271118
781613700775714774120793235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_smoke.3005669513007264597087397894195157158879060
4271118781613700775714774120793235
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.18356888693898086248079847304020141234590030086947286295500468361661430161775
Short name T388
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.21 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:40:19 PM PST 23
Peak memory 639092 kb
Host smart-8343b828-8eb4-44e2-98db-fc310fc84a1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18356888693898086248079847304020141234
590030086947286295500468361661430161775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.18356888693898086248079
847304020141234590030086947286295500468361661430161775
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_perf.86752563018876582932001044825551840426187567077421577057043174353819976900887
Short name T219
Test name
Test status
Simulation time 834576440 ps
CPU time 2.98 seconds
Started Nov 22 02:39:53 PM PST 23
Finished Nov 22 02:39:56 PM PST 23
Peak memory 203076 kb
Host smart-32f94453-fd54-4b67-bbdf-d5193f60ba58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867525630188765829320010448255518404261875670774215
77057043174353819976900887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_perf.867525630188765829320010448255518404261875670774215
77057043174353819976900887
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.115147908991219487110090254163504600790269598202797005459509569285733511135877
Short name T376
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.48 seconds
Started Nov 22 02:39:08 PM PST 23
Finished Nov 22 02:39:18 PM PST 23
Peak memory 203052 kb
Host smart-213e38b4-ec93-4bfc-8386-118aae2fbb4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151479089912194871100902541635046007902695982027970054595095692857335
11135877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smoke.115147908991219487110090254163504600790269598202797005459509569285733511135877
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.57307747905868464941545286915781945361710344290280196319671586406833968429617
Short name T284
Test name
Test status
Simulation time 66540157934 ps
CPU time 1584.67 seconds
Started Nov 22 02:39:14 PM PST 23
Finished Nov 22 03:05:39 PM PST 23
Peak memory 6983448 kb
Host smart-ccf842e2-550b-4ea8-8090-647a204186a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57307747905868464941545286915781945361710344290280
196319671586406833968429617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_all.57307747905868464941545286915781945361
710344290280196319671586406833968429617
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.64871254867561597325451923929835935371160932072426955871147728548862648770891
Short name T804
Test name
Test status
Simulation time 997771563 ps
CPU time 8.79 seconds
Started Nov 22 02:39:47 PM PST 23
Finished Nov 22 02:39:57 PM PST 23
Peak memory 203080 kb
Host smart-2aec4d57-4b03-42b6-b0df-264d3468b162
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6487125486756159732545192392983593537116093207242695587114772854886264
8770891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_rd.648712548675615973254519239298359353711609320724269558711477
28548862648770891
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.32189170901340155378857969733688615045925685889632571986086527495911359101256
Short name T1392
Test name
Test status
Simulation time 14461449567 ps
CPU time 84.87 seconds
Started Nov 22 02:40:31 PM PST 23
Finished Nov 22 02:41:56 PM PST 23
Peak memory 1542044 kb
Host smart-3492b7c9-e559-47cf-a7d8-42042add93df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218917090134015537885796973368861504592568588963257198608652749591135
9101256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_wr.321891709013401553788579697336886150459256858896325719860865
27495911359101256
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.15948077314553421992501524629208531457397483507967248284190958452857753407461
Short name T1309
Test name
Test status
Simulation time 6281818576 ps
CPU time 75.5 seconds
Started Nov 22 02:39:14 PM PST 23
Finished Nov 22 02:40:30 PM PST 23
Peak memory 930668 kb
Host smart-5dbaef58-4c3d-47cf-9b1b-86d5e50bff4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594807731455342199250152462920853145739748350796724828419095845285775
3407461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stretch.1594807731455342199250152462920853145739748350796724828419095845
2857753407461
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.93173906768660491511192302384716374137378423124709987434857187004513736461308
Short name T726
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.29 seconds
Started Nov 22 02:39:48 PM PST 23
Finished Nov 22 02:39:56 PM PST 23
Peak memory 212636 kb
Host smart-5284c7c3-1f78-4a02-9aa8-215059461f4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931739067686604915111923023847163741373784231247099
87434857187004513736461308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_timeout.931739067686604915111923023847163741373784231
24709987434857187004513736461308
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_ovf.42649883746437304015963225382017346923053466533558832396822349479163749647327
Short name T802
Test name
Test status
Simulation time 5445414553 ps
CPU time 124.04 seconds
Started Nov 22 02:40:03 PM PST 23
Finished Nov 22 02:42:08 PM PST 23
Peak memory 406820 kb
Host smart-f7f1279f-6247-4221-a866-3a5a181d1996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42649883746437304015963225382017346923053466533558
832396822349479163749647327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_tx_ovf.4264988374643730401596322538201734692305346653
3558832396822349479163749647327
Directory /workspace/43.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.3371255895468024195750470273798207946785227126048853890574122768392116350192
Short name T864
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.45 seconds
Started Nov 22 02:39:14 PM PST 23
Finished Nov 22 02:39:20 PM PST 23
Peak memory 205384 kb
Host smart-f381b684-0090-4b13-9314-e8c9f5364c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337125589546802419575047027379820794678522712604885
3890574122768392116350192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_unexp_stop.337125589546802419575047027379820794678522
7126048853890574122768392116350192
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.4952513578199182481159023832801114553427624706733485010157644087372620701092
Short name T1548
Test name
Test status
Simulation time 19975830 ps
CPU time 0.56 seconds
Started Nov 22 02:40:34 PM PST 23
Finished Nov 22 02:40:36 PM PST 23
Peak memory 202668 kb
Host smart-87c471ff-8040-4227-8f5d-c32625377656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4952513578199182481159023832801114553427624706733485010157644087372620701092 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_alert_test.4952513578199182481159023832801114553427624706733485010157644087372620701092
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.88431990846280577398958866590821134639228136522603873978070522245734333487264
Short name T348
Test name
Test status
Simulation time 74225396 ps
CPU time 1.39 seconds
Started Nov 22 02:40:15 PM PST 23
Finished Nov 22 02:40:17 PM PST 23
Peak memory 211276 kb
Host smart-3be44bbd-b812-4cee-971b-221983550813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88431990846280577398958866590821134639228136522603873978070522245734333487264 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_host_error_intr.88431990846280577398958866590821134639228136522603873978070522245734333487264
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.104831682699307579459250530776191173380010567734042262782282067935468831675550
Short name T1132
Test name
Test status
Simulation time 606667565 ps
CPU time 6.84 seconds
Started Nov 22 02:40:26 PM PST 23
Finished Nov 22 02:40:33 PM PST 23
Peak memory 273432 kb
Host smart-02192081-ff1e-4080-b93a-52e5d840ed49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104831682699307579459250530776191173380010567734042262782282067935468831675550 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.104831682699307579459250530776191173380010567734042262782282067935468831675550
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.100495347693855282896137974894775444100627753349094891601661557529115038914653
Short name T748
Test name
Test status
Simulation time 3768267272 ps
CPU time 69.46 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:41:41 PM PST 23
Peak memory 729552 kb
Host smart-50efd89e-a8ea-4205-8959-909c75fea3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100495347693855282896137974894775444100627753349094891601661557529115038914653 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_host_fifo_full.100495347693855282896137974894775444100627753349094891601661557529115038914653
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.12525460877108716188855482151791327987266542816381539557693945061660064886018
Short name T226
Test name
Test status
Simulation time 7925734012 ps
CPU time 265.49 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:44:23 PM PST 23
Peak memory 1271420 kb
Host smart-3727d785-761a-4291-a3f3-9442ac88ad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12525460877108716188855482151791327987266542816381539557693945061660064886018 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.i2c_host_fifo_overflow.12525460877108716188855482151791327987266542816381539557693945061660064886018
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.74471881174812269464819206540186443701778447463969270734897046323734118974724
Short name T1449
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:39:26 PM PST 23
Finished Nov 22 02:39:27 PM PST 23
Peak memory 202928 kb
Host smart-26b0a184-89a8-4004-b349-282e01f44a3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74471881174812269464819206540186443701778447463969270734897046323734118974724 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.74471881174812269464819206540186443701778447463969270734897046323734118974724
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.107802682467850814724977681454591177020091336109216667001527081515096949217021
Short name T1415
Test name
Test status
Simulation time 236313385 ps
CPU time 3.9 seconds
Started Nov 22 02:40:03 PM PST 23
Finished Nov 22 02:40:08 PM PST 23
Peak memory 225492 kb
Host smart-3460947f-6b6e-4c74-ac8f-3fe6fe51bb85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107802682467850814724977681454591177020091336109216667001527081515096949217021 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.107802682467850814724977681454591177020091336109216667001527081515096949217021
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.10110922284678625053679290739451496327736945231715705508738873591276861205179
Short name T622
Test name
Test status
Simulation time 7918519784 ps
CPU time 236.86 seconds
Started Nov 22 02:40:00 PM PST 23
Finished Nov 22 02:43:58 PM PST 23
Peak memory 1310944 kb
Host smart-48fab46c-3ba9-4aa4-baa9-a779e25a423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10110922284678625053679290739451496327736945231715705508738873591276861205179 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_host_fifo_watermark.10110922284678625053679290739451496327736945231715705508738873591276861205179
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.36275389520823648233185325972680003289531149755825377948630969629618866385544
Short name T877
Test name
Test status
Simulation time 3754070957 ps
CPU time 62.61 seconds
Started Nov 22 02:39:58 PM PST 23
Finished Nov 22 02:41:01 PM PST 23
Peak memory 293776 kb
Host smart-c25da96a-4ff8-4c01-8ed8-78f1dbe81283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36275389520823648233185325972680003289531149755825377948630969629618866385544 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_host_mode_toggle.36275389520823648233185325972680003289531149755825377948630969629618866385544
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.32807700446487724812155236975702876329275197405510570517412624655820604098359
Short name T470
Test name
Test status
Simulation time 23672229 ps
CPU time 0.61 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:40:31 PM PST 23
Peak memory 202712 kb
Host smart-1c251d85-b7f8-46a0-a04d-92d1ed13099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32807700446487724812155236975702876329275197405510570517412624655820604098359 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_host_override.32807700446487724812155236975702876329275197405510570517412624655820604098359
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.21135351185786903864810096879444957696236057740130813336967260729425808166536
Short name T297
Test name
Test status
Simulation time 6830796343 ps
CPU time 62.18 seconds
Started Nov 22 02:40:05 PM PST 23
Finished Nov 22 02:41:08 PM PST 23
Peak memory 211236 kb
Host smart-e4297fc8-3612-4b7e-a788-24d311b47ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21135351185786903864810096879444957696236057740130813336967260729425808166536 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.i2c_host_perf.21135351185786903864810096879444957696236057740130813336967260729425808166536
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_rx_oversample.48280873902418949711408413256319012142375209930657631524278648676393326971515
Short name T672
Test name
Test status
Simulation time 3939158762 ps
CPU time 116.64 seconds
Started Nov 22 02:39:26 PM PST 23
Finished Nov 22 02:41:23 PM PST 23
Peak memory 345940 kb
Host smart-83c56ed7-ff01-40cc-9aec-ed70b4e55532
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48280873902418949711408413256319012142375209930657631524278648676393326971515 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_rx_oversample.48280873902418949711408413256319012142375209930657631524278648676393326971515
Directory /workspace/44.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.93415030660102553640181713899076465586971668326842831770889566201698920908999
Short name T209
Test name
Test status
Simulation time 2343171530 ps
CPU time 39.69 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:40:36 PM PST 23
Peak memory 299448 kb
Host smart-2bb63b9f-8d4c-484e-a5b6-95e93106a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93415030660102553640181713899076465586971668326842831770889566201698920908999 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.i2c_host_smoke.93415030660102553640181713899076465586971668326842831770889566201698920908999
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.24818271993531134475633027979527860086801378067288816588324333570036237799588
Short name T749
Test name
Test status
Simulation time 32807463528 ps
CPU time 1008.37 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:57:19 PM PST 23
Peak memory 1957040 kb
Host smart-d1012c20-cdd1-4245-b27e-8a1b79834902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24818271993531134475633027979527860086801378067288816588324333570036237799588 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_host_stress_all.24818271993531134475633027979527860086801378067288816588324333570036237799588
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.50929665316624378789900984804789827973934111143006523777460443068382984073571
Short name T644
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.31 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:40:44 PM PST 23
Peak memory 214104 kb
Host smart-f6183291-0d50-4588-97f7-30e8c0fd80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50929665316624378789900984804789827973934111143006523777460443068382984073571 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_host_stretch_timeout.50929665316624378789900984804789827973934111143006523777460443068382984073571
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.85501373480729383538009722117725650140503195908744669856212685296047715690795
Short name T340
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.78 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:06 PM PST 23
Peak memory 202984 kb
Host smart-29c157bb-fc68-40d4-93ec-c972a5fb89c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8550137348072938353800972211772
5650140503195908744669856212685296047715690795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.85501373480729383538009722
117725650140503195908744669856212685296047715690795
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.195141293531301205366176589641521528303024598224430702412195969785697735998
Short name T1049
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.58 seconds
Started Nov 22 02:40:11 PM PST 23
Finished Nov 22 02:40:44 PM PST 23
Peak memory 382260 kb
Host smart-54669684-89c6-403d-81f9-a0e3c18bba7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195141293531301205366176589641521528303024598224430
702412195969785697735998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.195141293531301205366176589641521
528303024598224430702412195969785697735998
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.101053622567064302352211817161178738577123268812467388045296336229527008393043
Short name T1367
Test name
Test status
Simulation time 10065199023 ps
CPU time 39.12 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:40:41 PM PST 23
Peak memory 462092 kb
Host smart-04bc53f6-2d78-4cb0-95a9-a85ceb31db82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101053622567064302352211817161178738577123268812467
388045296336229527008393043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_tx.10105362256706430235221181716117
8738577123268812467388045296336229527008393043
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.112500828578047337018954318857713435550756573632437930442382637810062842576921
Short name T1400
Test name
Test status
Simulation time 825344371 ps
CPU time 2.4 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:06 PM PST 23
Peak memory 203056 kb
Host smart-9c7f3a32-fd49-4d32-bedc-a0ead1878d29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112500828578047337018954318857713435550756573632437
930442382637810062842576921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_hrst.11250082857804733701895431885771343555075657363243
7930442382637810062842576921
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.19281212278937012762149891186868909560999996052231822134674445069670203252360
Short name T646
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.43 seconds
Started Nov 22 02:40:41 PM PST 23
Finished Nov 22 02:40:46 PM PST 23
Peak memory 203636 kb
Host smart-fd14747e-2380-4a17-a4ee-2efc72f1544b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19281212278937012762149891186868909560999996052231
822134674445069670203252360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.1928121227893701276214989118686890956099999
6052231822134674445069670203252360
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.79797964150814646050918804289213574764923423586450751080173514299782926840888
Short name T164
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.61 seconds
Started Nov 22 02:40:03 PM PST 23
Finished Nov 22 02:40:26 PM PST 23
Peak memory 639228 kb
Host smart-c33c7729-df27-402f-9535-5612b5ea6e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79797964150814646050918804289213574764
923423586450751080173514299782926840888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.79797964150814646050918
804289213574764923423586450751080173514299782926840888
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.15520185424294228257394609117843858392896874521094708524145838291580612681715
Short name T147
Test name
Test status
Simulation time 834576440 ps
CPU time 3.04 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:05 PM PST 23
Peak memory 202964 kb
Host smart-8fecb2d2-d6e5-417b-8416-228e1160ca73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155201854242942282573946091178438583928968745210947
08524145838291580612681715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_perf.155201854242942282573946091178438583928968745210947
08524145838291580612681715
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.41554679310072388015287516384243469573290389600932579391205407868260310286086
Short name T194
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.56 seconds
Started Nov 22 02:40:03 PM PST 23
Finished Nov 22 02:40:13 PM PST 23
Peak memory 203016 kb
Host smart-658893c1-941c-4877-bb29-03eebb799bd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155467931007238801528751638424346957329038960093257939120540786826031
0286086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smoke.41554679310072388015287516384243469573290389600932579391205407868260310286086
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.73468702422854745363741700034827397908482103445296233634005893986145339372500
Short name T158
Test name
Test status
Simulation time 66540157934 ps
CPU time 1691.05 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 03:08:15 PM PST 23
Peak memory 6983404 kb
Host smart-4daf6fce-ce83-49c8-bff2-1b66c43d54f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73468702422854745363741700034827397908482103445296
233634005893986145339372500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_all.73468702422854745363741700034827397908
482103445296233634005893986145339372500
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.4705304756412732560806180335423545572907718356283855481869373717737157623081
Short name T1569
Test name
Test status
Simulation time 997771563 ps
CPU time 9.3 seconds
Started Nov 22 02:40:10 PM PST 23
Finished Nov 22 02:40:20 PM PST 23
Peak memory 203080 kb
Host smart-0817fb7b-2d6e-483b-b414-3a19ab1ff841
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4705304756412732560806180335423545572907718356283855481869373717737157
623081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_rd.4705304756412732560806180335423545572907718356283855481869373
717737157623081
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.104469066113480711633170748613329744525715030424064310599676485545850663689274
Short name T567
Test name
Test status
Simulation time 14461449567 ps
CPU time 87.18 seconds
Started Nov 22 02:40:26 PM PST 23
Finished Nov 22 02:41:54 PM PST 23
Peak memory 1542100 kb
Host smart-b61f58a1-e80e-4851-9fe3-8f1d8e965e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044690661134807116331707486133297445257150304240643105996764855458506
63689274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_wr.10446906611348071163317074861332974452571503042406431059967
6485545850663689274
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.95699417915201266690859355686362303150722102411055217504562943395991305977357
Short name T1125
Test name
Test status
Simulation time 6281818576 ps
CPU time 77.14 seconds
Started Nov 22 02:40:15 PM PST 23
Finished Nov 22 02:41:33 PM PST 23
Peak memory 930568 kb
Host smart-63fc4ebc-4f29-4984-98cc-d97752059aeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9569941791520126669085935568636230315072210241105521750456294339599130
5977357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stretch.9569941791520126669085935568636230315072210241105521750456294339
5991305977357
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.57928441147309421352321732102731643841317583973633607940982008185426188750704
Short name T1425
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.87 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:11 PM PST 23
Peak memory 212656 kb
Host smart-aa0ed0f2-3f8c-4644-bd6b-03212f21a1ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579284411473094213523217321027316438413175839736336
07940982008185426188750704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_timeout.579284411473094213523217321027316438413175839
73633607940982008185426188750704
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_ovf.44433216653453407581246922477561403792908112703712090241232098256935702626939
Short name T524
Test name
Test status
Simulation time 5445414553 ps
CPU time 131.68 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:42:09 PM PST 23
Peak memory 406668 kb
Host smart-bc6a9449-8497-4d42-ac35-76061056ef41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44433216653453407581246922477561403792908112703712
090241232098256935702626939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_tx_ovf.4443321665345340758124692247756140379290811270
3712090241232098256935702626939
Directory /workspace/44.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.70522806601678137109253649130428980233752581263488842399550070629555485079871
Short name T584
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.49 seconds
Started Nov 22 02:40:33 PM PST 23
Finished Nov 22 02:40:40 PM PST 23
Peak memory 205316 kb
Host smart-52d72298-fc8e-4e25-97de-41643be82285
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705228066016781371092536491304289802337525812634888
42399550070629555485079871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_unexp_stop.70522806601678137109253649130428980233752
581263488842399550070629555485079871
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.19031461957997782434323886200057767838864098911488602635725465643627181332278
Short name T368
Test name
Test status
Simulation time 19975830 ps
CPU time 0.64 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:39:58 PM PST 23
Peak memory 202784 kb
Host smart-0ffaa41a-3b71-4f06-86ac-ebc8fbe69e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19031461957997782434323886200057767838864098911488602635725465643627181332278 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_alert_test.19031461957997782434323886200057767838864098911488602635725465643627181332278
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.6483656993700022369980310573942527261373336124464436073175580288469608892620
Short name T1285
Test name
Test status
Simulation time 74225396 ps
CPU time 1.34 seconds
Started Nov 22 02:40:36 PM PST 23
Finished Nov 22 02:40:39 PM PST 23
Peak memory 211304 kb
Host smart-17c7971e-1903-4b3c-a12e-ce63df0f6c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6483656993700022369980310573942527261373336124464436073175580288469608892620 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_host_error_intr.6483656993700022369980310573942527261373336124464436073175580288469608892620
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.85603350243136575930761127342481494340016202480769342079782541408021298459137
Short name T381
Test name
Test status
Simulation time 606667565 ps
CPU time 6.68 seconds
Started Nov 22 02:40:36 PM PST 23
Finished Nov 22 02:40:44 PM PST 23
Peak memory 273408 kb
Host smart-68576a2d-3739-41c7-88e0-dfd096d21b01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85603350243136575930761127342481494340016202480769342079782541408021298459137 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.85603350243136575930761127342481494340016202480769342079782541408021298459137
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.73935417692786178693633304022454726807315293021096741370947560227694954077857
Short name T1381
Test name
Test status
Simulation time 3768267272 ps
CPU time 73.16 seconds
Started Nov 22 02:40:12 PM PST 23
Finished Nov 22 02:41:26 PM PST 23
Peak memory 729524 kb
Host smart-200abde2-b3cb-4f38-af2e-b3092a5d3fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73935417692786178693633304022454726807315293021096741370947560227694954077857 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_host_fifo_full.73935417692786178693633304022454726807315293021096741370947560227694954077857
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.48023473779338573402282201091043660951171343083507169589229618357054171339543
Short name T721
Test name
Test status
Simulation time 7925734012 ps
CPU time 228.48 seconds
Started Nov 22 02:40:11 PM PST 23
Finished Nov 22 02:44:00 PM PST 23
Peak memory 1271684 kb
Host smart-5762a1bc-b74c-46e1-83c5-8fc8ada2e7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48023473779338573402282201091043660951171343083507169589229618357054171339543 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.i2c_host_fifo_overflow.48023473779338573402282201091043660951171343083507169589229618357054171339543
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.57347533858231470564465454932230208805435996941718453998339740552440501301106
Short name T729
Test name
Test status
Simulation time 209010032 ps
CPU time 0.96 seconds
Started Nov 22 02:40:07 PM PST 23
Finished Nov 22 02:40:09 PM PST 23
Peak memory 202948 kb
Host smart-d68d54b1-b413-48e4-b24d-f03c54b54b0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57347533858231470564465454932230208805435996941718453998339740552440501301106 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.57347533858231470564465454932230208805435996941718453998339740552440501301106
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.79952534607508154018990935106534099732341737071888265268472234390300512267262
Short name T1210
Test name
Test status
Simulation time 236313385 ps
CPU time 3.67 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:07 PM PST 23
Peak memory 225520 kb
Host smart-13f695c2-d009-4e63-a915-68c2c646ef9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79952534607508154018990935106534099732341737071888265268472234390300512267262 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.79952534607508154018990935106534099732341737071888265268472234390300512267262
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.51895296985306162119235774090214157407219421767102908660023443863150892937318
Short name T878
Test name
Test status
Simulation time 7918519784 ps
CPU time 227.77 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:44:25 PM PST 23
Peak memory 1310880 kb
Host smart-f9f3e793-c2d1-4b31-b118-970bed2a0391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51895296985306162119235774090214157407219421767102908660023443863150892937318 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.i2c_host_fifo_watermark.51895296985306162119235774090214157407219421767102908660023443863150892937318
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.12115512244884388087127977374086630342200269005832573391586859182822336784633
Short name T1357
Test name
Test status
Simulation time 3754070957 ps
CPU time 51.63 seconds
Started Nov 22 02:40:32 PM PST 23
Finished Nov 22 02:41:25 PM PST 23
Peak memory 293780 kb
Host smart-c8f731d7-872c-4648-9c84-5e62972e7c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12115512244884388087127977374086630342200269005832573391586859182822336784633 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_host_mode_toggle.12115512244884388087127977374086630342200269005832573391586859182822336784633
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.5134013903877514387576462407627048917514359361533144687787683618733687110807
Short name T724
Test name
Test status
Simulation time 23672229 ps
CPU time 0.66 seconds
Started Nov 22 02:40:27 PM PST 23
Finished Nov 22 02:40:29 PM PST 23
Peak memory 202980 kb
Host smart-bad99575-73c3-4bc5-ab6a-e47c3d03f510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5134013903877514387576462407627048917514359361533144687787683618733687110807 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_host_override.5134013903877514387576462407627048917514359361533144687787683618733687110807
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.59444038359879143768590053076001537206708453355178377555563801605495005521176
Short name T372
Test name
Test status
Simulation time 6830796343 ps
CPU time 63 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:41:00 PM PST 23
Peak memory 211364 kb
Host smart-25d2cf46-e360-4aeb-9cf7-a4a881928270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59444038359879143768590053076001537206708453355178377555563801605495005521176 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.i2c_host_perf.59444038359879143768590053076001537206708453355178377555563801605495005521176
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_rx_oversample.17294706749894373507821472752808330999128090037335753773606616126935216626530
Short name T104
Test name
Test status
Simulation time 3939158762 ps
CPU time 116.85 seconds
Started Nov 22 02:40:05 PM PST 23
Finished Nov 22 02:42:02 PM PST 23
Peak memory 345844 kb
Host smart-d44d7e38-3ba3-4717-a92e-f46f0e16797a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17294706749894373507821472752808330999128090037335753773606616126935216626530 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_rx_oversample.17294706749894373507821472752808330999128090037335753773606616126935216626530
Directory /workspace/45.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.100766043162020749108654855014500546131442020572270368173698590776647396712225
Short name T220
Test name
Test status
Simulation time 2343171530 ps
CPU time 34.47 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:40:32 PM PST 23
Peak memory 299276 kb
Host smart-43ac1912-b783-4334-8368-49159d05428f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100766043162020749108654855014500546131442020572270368173698590776647396712225 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.i2c_host_smoke.100766043162020749108654855014500546131442020572270368173698590776647396712225
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.67614331234902013532440677898475183360710736070447241370936815092427631697145
Short name T1174
Test name
Test status
Simulation time 32807463528 ps
CPU time 1081.29 seconds
Started Nov 22 02:40:13 PM PST 23
Finished Nov 22 02:58:15 PM PST 23
Peak memory 1957192 kb
Host smart-224c75ca-0573-4300-9b9a-d664ed42efaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67614331234902013532440677898475183360710736070447241370936815092427631697145 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_host_stress_all.67614331234902013532440677898475183360710736070447241370936815092427631697145
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.68091612876869083459183066424500928647965660519867910765322414349666503651822
Short name T450
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.04 seconds
Started Nov 22 02:40:13 PM PST 23
Finished Nov 22 02:40:27 PM PST 23
Peak memory 214156 kb
Host smart-48471032-1dd6-47fd-93eb-5f21d26f1f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68091612876869083459183066424500928647965660519867910765322414349666503651822 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_host_stretch_timeout.68091612876869083459183066424500928647965660519867910765322414349666503651822
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.45444221082419178306760300135016292280081708172210250049118103799229857213434
Short name T420
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.82 seconds
Started Nov 22 02:40:32 PM PST 23
Finished Nov 22 02:40:36 PM PST 23
Peak memory 203108 kb
Host smart-847dddce-c160-4248-b4f1-9f9b02ae6772
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4544422108241917830676030013501
6292280081708172210250049118103799229857213434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.45444221082419178306760300
135016292280081708172210250049118103799229857213434
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.87301263723981408767459206881656030282010100577608500883828761780713907300668
Short name T531
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.46 seconds
Started Nov 22 02:40:28 PM PST 23
Finished Nov 22 02:41:01 PM PST 23
Peak memory 382164 kb
Host smart-38af008b-dbfc-48b9-a91a-f9ae42746f6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873012637239814087674592068816560302820101005776085
00883828761780713907300668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_acq.8730126372398140876745920688165
6030282010100577608500883828761780713907300668
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.100117871963620968111430574058748281386024179208443547763443054266473328576939
Short name T794
Test name
Test status
Simulation time 10065199023 ps
CPU time 38.46 seconds
Started Nov 22 02:40:05 PM PST 23
Finished Nov 22 02:40:44 PM PST 23
Peak memory 462144 kb
Host smart-f30361c3-a4f3-44b3-b69b-5a5af4d3d84f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100117871963620968111430574058748281386024179208443
547763443054266473328576939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_tx.10011787196362096811143057405874
8281386024179208443547763443054266473328576939
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.92127045598369444072034110877540305983007251201729674079653217549388584636274
Short name T105
Test name
Test status
Simulation time 825344371 ps
CPU time 2.53 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:05 PM PST 23
Peak memory 202976 kb
Host smart-0ab0fc54-fb32-44c8-8ae1-d8182f40cf43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921270455983694440720341108775403059830072512017296
74079653217549388584636274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_hrst.921270455983694440720341108775403059830072512017296
74079653217549388584636274
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.12620764337548666928515984257139049904959599201172528662341332063551618415042
Short name T221
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.23 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:40:34 PM PST 23
Peak memory 203652 kb
Host smart-3029962e-f74d-48da-8462-fb438768694f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12620764337548666928515984257139049904959599201172
528662341332063551618415042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.1262076433754866692851598425713904990495959
9201172528662341332063551618415042
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.41688306781250797821884797608231641283632691524116086554589431588742162768725
Short name T1259
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.1 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:40:54 PM PST 23
Peak memory 639168 kb
Host smart-a813f37c-ddbc-4492-a005-a1bd1e7980dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41688306781250797821884797608231641283
632691524116086554589431588742162768725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.41688306781250797821884
797608231641283632691524116086554589431588742162768725
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.44638089647105843268109778578309320258092119210711173202783849579566297081873
Short name T535
Test name
Test status
Simulation time 834576440 ps
CPU time 3.14 seconds
Started Nov 22 02:40:04 PM PST 23
Finished Nov 22 02:40:08 PM PST 23
Peak memory 203044 kb
Host smart-b7f9a495-80df-4275-91d4-5ec14611b89a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446380896471058432681097785783093202580921192107111
73202783849579566297081873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_perf.446380896471058432681097785783093202580921192107111
73202783849579566297081873
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.39531548173840706471729043773534714254144816727742892803554738202381405201073
Short name T1435
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.51 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:40:12 PM PST 23
Peak memory 202964 kb
Host smart-3d560908-9f22-49ac-9a17-4e478d501b4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953154817384070647172904377353471425414481672774289280355473820238140
5201073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smoke.39531548173840706471729043773534714254144816727742892803554738202381405201073
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.76618197323166663710368858657690580467644407797998988424212583845974348769367
Short name T599
Test name
Test status
Simulation time 66540157934 ps
CPU time 1602.76 seconds
Started Nov 22 02:40:15 PM PST 23
Finished Nov 22 03:06:59 PM PST 23
Peak memory 6983384 kb
Host smart-a76f661b-c55e-4a26-8dd7-21a8140facf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76618197323166663710368858657690580467644407797998
988424212583845974348769367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_all.76618197323166663710368858657690580467
644407797998988424212583845974348769367
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.105539452611505504072661421280867703676751459129309145058218165783319658900595
Short name T826
Test name
Test status
Simulation time 997771563 ps
CPU time 8.84 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:11 PM PST 23
Peak memory 202940 kb
Host smart-efcac45d-a1ad-42fe-902f-9f1d7f687ab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055394526115055040726614212808677036767514591293091450582181657833196
58900595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_rd.10553945261150550407266142128086770367675145912930914505821
8165783319658900595
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.47209457543944833048920540940967795624689782125032831653719943277851504796871
Short name T1299
Test name
Test status
Simulation time 14461449567 ps
CPU time 83.44 seconds
Started Nov 22 02:40:05 PM PST 23
Finished Nov 22 02:41:29 PM PST 23
Peak memory 1542028 kb
Host smart-1a1f9ca4-32a0-45aa-9cb0-a6f6169d0c53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4720945754394483304892054094096779562468978212503283165371994327785150
4796871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_wr.472094575439448330489205409409677956246897821250328316537199
43277851504796871
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.23374836289237661820392211470413655014928983466224368740948917097241277151095
Short name T879
Test name
Test status
Simulation time 6281818576 ps
CPU time 81.68 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:41:24 PM PST 23
Peak memory 930516 kb
Host smart-9a93586d-604a-43ad-a97d-9f668ba1a988
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337483628923766182039221147041365501492898346622436874094891709724127
7151095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stretch.2337483628923766182039221147041365501492898346622436874094891709
7241277151095
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.52986581095174891722010207099225177966550991552128625984006836547123687540820
Short name T932
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.53 seconds
Started Nov 22 02:40:31 PM PST 23
Finished Nov 22 02:40:40 PM PST 23
Peak memory 212692 kb
Host smart-75c7df0b-afa5-4a09-8e3e-8015373bdf06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529865810951748917220102070992251779665509915521286
25984006836547123687540820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_timeout.529865810951748917220102070992251779665509915
52128625984006836547123687540820
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_ovf.69501518796715066128564871356293843249424273999665570231682312531239212378529
Short name T1166
Test name
Test status
Simulation time 5445414553 ps
CPU time 140.53 seconds
Started Nov 22 02:40:05 PM PST 23
Finished Nov 22 02:42:26 PM PST 23
Peak memory 406704 kb
Host smart-1ec751fe-4baa-4df1-89f7-7ecfb6c44dc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69501518796715066128564871356293843249424273999665
570231682312531239212378529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_tx_ovf.6950151879671506612856487135629384324942427399
9665570231682312531239212378529
Directory /workspace/45.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.32724863318243781479765781382936177067846250446765280684396129398741829692286
Short name T1440
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.63 seconds
Started Nov 22 02:40:07 PM PST 23
Finished Nov 22 02:40:13 PM PST 23
Peak memory 205368 kb
Host smart-b7826ce9-b61c-4e82-9bbf-837eace0b84e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327248633182437814797657813829361770678462504467652
80684396129398741829692286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_unexp_stop.32724863318243781479765781382936177067846
250446765280684396129398741829692286
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.66737344389180515949027882468016187318017618702841366052851186134955802454258
Short name T971
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:40:31 PM PST 23
Peak memory 202696 kb
Host smart-ca18c9f0-d6ea-4346-aa8d-ba4ad65df287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66737344389180515949027882468016187318017618702841366052851186134955802454258 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_alert_test.66737344389180515949027882468016187318017618702841366052851186134955802454258
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.100728433996161440142150926139452991130304540495359776431509636324157037993346
Short name T1336
Test name
Test status
Simulation time 74225396 ps
CPU time 1.37 seconds
Started Nov 22 02:40:28 PM PST 23
Finished Nov 22 02:40:30 PM PST 23
Peak memory 211344 kb
Host smart-faf23f2b-ab7c-4387-b737-95bc8f5c8669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100728433996161440142150926139452991130304540495359776431509636324157037993346 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_host_error_intr.100728433996161440142150926139452991130304540495359776431509636324157037993346
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.58263347523149085998374010694572302810208576515511983458444784345995086530627
Short name T1012
Test name
Test status
Simulation time 606667565 ps
CPU time 6.63 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:40:44 PM PST 23
Peak memory 273300 kb
Host smart-81f235bf-87e8-40ee-80b2-39982d8c9203
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58263347523149085998374010694572302810208576515511983458444784345995086530627 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.58263347523149085998374010694572302810208576515511983458444784345995086530627
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.30549116137530020404357145647577920638059150258027310240056104371370302038624
Short name T1560
Test name
Test status
Simulation time 3768267272 ps
CPU time 69.78 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:41:07 PM PST 23
Peak memory 729508 kb
Host smart-90591b94-dbf1-4c59-8290-16d84ed4f442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30549116137530020404357145647577920638059150258027310240056104371370302038624 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_host_fifo_full.30549116137530020404357145647577920638059150258027310240056104371370302038624
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.77669770477578030187732964429553034193794037795813416965485825548092133255369
Short name T1574
Test name
Test status
Simulation time 7925734012 ps
CPU time 241.59 seconds
Started Nov 22 02:40:29 PM PST 23
Finished Nov 22 02:44:31 PM PST 23
Peak memory 1271512 kb
Host smart-0e98381a-7ac2-4ca7-b1e1-6afc999ca569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77669770477578030187732964429553034193794037795813416965485825548092133255369 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.i2c_host_fifo_overflow.77669770477578030187732964429553034193794037795813416965485825548092133255369
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.33910447741419800196575436440755051732361594113270103598214515181512821137638
Short name T231
Test name
Test status
Simulation time 209010032 ps
CPU time 0.92 seconds
Started Nov 22 02:40:03 PM PST 23
Finished Nov 22 02:40:05 PM PST 23
Peak memory 202952 kb
Host smart-186917b7-94f5-4314-9d0b-431e5384fe7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33910447741419800196575436440755051732361594113270103598214515181512821137638 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.33910447741419800196575436440755051732361594113270103598214515181512821137638
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.27784968672617091237356797807768876033009590194586385780742250498563139890472
Short name T1556
Test name
Test status
Simulation time 236313385 ps
CPU time 3.93 seconds
Started Nov 22 02:39:58 PM PST 23
Finished Nov 22 02:40:02 PM PST 23
Peak memory 225484 kb
Host smart-f219951e-41c3-4094-a0fa-0a5f923ba403
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27784968672617091237356797807768876033009590194586385780742250498563139890472 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.27784968672617091237356797807768876033009590194586385780742250498563139890472
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.115216393622924619480600986702867378974188663995903676674520133319012255825458
Short name T387
Test name
Test status
Simulation time 7918519784 ps
CPU time 222.23 seconds
Started Nov 22 02:40:03 PM PST 23
Finished Nov 22 02:43:46 PM PST 23
Peak memory 1310964 kb
Host smart-5719e9cd-fbaa-4be2-ac62-f9fef2173f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115216393622924619480600986702867378974188663995903676674520133319012255825458 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_host_fifo_watermark.115216393622924619480600986702867378974188663995903676674520133319012255825458
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.60609143275584406858754769083498296222909244492052117105854348738793069690030
Short name T768
Test name
Test status
Simulation time 3754070957 ps
CPU time 49.33 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:41:21 PM PST 23
Peak memory 293856 kb
Host smart-04c3048b-aa05-4511-867e-96842de01eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60609143275584406858754769083498296222909244492052117105854348738793069690030 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_host_mode_toggle.60609143275584406858754769083498296222909244492052117105854348738793069690030
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.26349759316221276119640296648627141931615681886424867355578458915370136293705
Short name T357
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:40:29 PM PST 23
Finished Nov 22 02:40:30 PM PST 23
Peak memory 202832 kb
Host smart-c9cc185d-cec7-4095-9f3f-8e6578f95d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26349759316221276119640296648627141931615681886424867355578458915370136293705 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_host_override.26349759316221276119640296648627141931615681886424867355578458915370136293705
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.100373936181394402270582640709952187851481086374108707585031224986244780662506
Short name T638
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.35 seconds
Started Nov 22 02:40:25 PM PST 23
Finished Nov 22 02:41:26 PM PST 23
Peak memory 211364 kb
Host smart-4e757d5f-5d04-48da-b47d-35952db60485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100373936181394402270582640709952187851481086374108707585031224986244780662506 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.i2c_host_perf.100373936181394402270582640709952187851481086374108707585031224986244780662506
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_rx_oversample.42949795666157521764960614863606389227473593753702994557668214045124383588378
Short name T1465
Test name
Test status
Simulation time 3939158762 ps
CPU time 115.16 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:41:57 PM PST 23
Peak memory 345884 kb
Host smart-59ef9d7f-30c5-4f61-a34d-54e0b73e684d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42949795666157521764960614863606389227473593753702994557668214045124383588378 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_rx_oversample.42949795666157521764960614863606389227473593753702994557668214045124383588378
Directory /workspace/46.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.30340536502561934061811136971560948434362052866953551904428118244807213496373
Short name T949
Test name
Test status
Simulation time 2343171530 ps
CPU time 35.37 seconds
Started Nov 22 02:40:28 PM PST 23
Finished Nov 22 02:41:04 PM PST 23
Peak memory 299432 kb
Host smart-69fce3cd-9003-4734-9a5c-a90553d91ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30340536502561934061811136971560948434362052866953551904428118244807213496373 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.i2c_host_smoke.30340536502561934061811136971560948434362052866953551904428118244807213496373
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.72087234224468214393393881368351056869669603345062699138422765214597860436812
Short name T55
Test name
Test status
Simulation time 32807463528 ps
CPU time 903.41 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:55:35 PM PST 23
Peak memory 1956988 kb
Host smart-eba4d0e1-e4b9-4513-920d-e2e9d9f59879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72087234224468214393393881368351056869669603345062699138422765214597860436812 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_host_stress_all.72087234224468214393393881368351056869669603345062699138422765214597860436812
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.7658049006810836125837456607059664926568695266370640818882756898031994909954
Short name T1485
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.07 seconds
Started Nov 22 02:40:28 PM PST 23
Finished Nov 22 02:40:42 PM PST 23
Peak memory 214140 kb
Host smart-34055f1f-8cae-403c-90eb-354ef8eb6dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7658049006810836125837456607059664926568695266370640818882756898031994909954 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_host_stretch_timeout.7658049006810836125837456607059664926568695266370640818882756898031994909954
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.45300608589331402901259194798029514755444562420794216115111396017867733773651
Short name T210
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.7 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:40:40 PM PST 23
Peak memory 203052 kb
Host smart-83f5ba3d-e05b-4b54-a65c-37bdd46680e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4530060858933140290125919479802
9514755444562420794216115111396017867733773651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.45300608589331402901259194
798029514755444562420794216115111396017867733773651
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.110415896578599672977057666343247203649425358521658173303861316499184976665034
Short name T22
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.82 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:34 PM PST 23
Peak memory 382172 kb
Host smart-614468b9-10f2-457b-8953-99e55c98fc6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110415896578599672977057666343247203649425358521658
173303861316499184976665034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.110415896578599672977057666343
247203649425358521658173303861316499184976665034
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.109664641118011299390319847896772359325778139154478985004030035845754402305017
Short name T1067
Test name
Test status
Simulation time 10065199023 ps
CPU time 35.74 seconds
Started Nov 22 02:40:33 PM PST 23
Finished Nov 22 02:41:11 PM PST 23
Peak memory 461964 kb
Host smart-3b016693-bd9d-41a7-8fac-440bde83530e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109664641118011299390319847896772359325778139154478
985004030035845754402305017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_tx.10966464111801129939031984789677
2359325778139154478985004030035845754402305017
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.22423083596091566876932000904205846037798678799615831200247523441942631557979
Short name T474
Test name
Test status
Simulation time 825344371 ps
CPU time 2.45 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:40:04 PM PST 23
Peak memory 203048 kb
Host smart-fe6fa0ba-3b9b-432f-968d-f5cf736ce75f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224230835960915668769320009042058460377986787996158
31200247523441942631557979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_hrst.224230835960915668769320009042058460377986787996158
31200247523441942631557979
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.21540270547842011526840348467470722426778831610163262896656841552111290362600
Short name T1573
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.3 seconds
Started Nov 22 02:40:32 PM PST 23
Finished Nov 22 02:40:37 PM PST 23
Peak memory 203760 kb
Host smart-39cf9d26-989c-4c6d-8577-fc88fdb1e8ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21540270547842011526840348467470722426778831610163
262896656841552111290362600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_smoke.2154027054784201152684034846747072242677883
1610163262896656841552111290362600
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.37404260354145223408390707298347011911230394932147268375200697955926333833674
Short name T807
Test name
Test status
Simulation time 5106060125 ps
CPU time 23.31 seconds
Started Nov 22 02:39:58 PM PST 23
Finished Nov 22 02:40:22 PM PST 23
Peak memory 639304 kb
Host smart-1d7aee8b-1c76-40b7-9dc8-011d8e846858
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37404260354145223408390707298347011911
230394932147268375200697955926333833674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.37404260354145223408390
707298347011911230394932147268375200697955926333833674
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_perf.20242246854204013983038212888769470182277541283950511024386655859026932919622
Short name T312
Test name
Test status
Simulation time 834576440 ps
CPU time 2.87 seconds
Started Nov 22 02:40:25 PM PST 23
Finished Nov 22 02:40:29 PM PST 23
Peak memory 203096 kb
Host smart-d1e1f68f-6bcd-4c7f-a1c8-833613c9586b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202422468542040139830382128887694701822775412839505
11024386655859026932919622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_perf.202422468542040139830382128887694701822775412839505
11024386655859026932919622
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.41486433528780050389607169628898587197342374536585929803010461286240619932388
Short name T1300
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.63 seconds
Started Nov 22 02:39:56 PM PST 23
Finished Nov 22 02:40:07 PM PST 23
Peak memory 203012 kb
Host smart-9d8c4e8b-10ba-4f91-bd85-63e578c35de7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148643352878005038960716962889858719734237453658592980301046128624061
9932388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smoke.41486433528780050389607169628898587197342374536585929803010461286240619932388
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.14441839408469503415795654283240398217131704765190602805525236369219863944739
Short name T1550
Test name
Test status
Simulation time 66540157934 ps
CPU time 1465.12 seconds
Started Nov 22 02:40:28 PM PST 23
Finished Nov 22 03:04:54 PM PST 23
Peak memory 6983436 kb
Host smart-409f9d38-dc37-4b1b-988d-bab324bf3d6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14441839408469503415795654283240398217131704765190
602805525236369219863944739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_all.14441839408469503415795654283240398217
131704765190602805525236369219863944739
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.60282236528164578219121578242932581977887530645610932663444330383613928007077
Short name T1109
Test name
Test status
Simulation time 997771563 ps
CPU time 8.81 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:12 PM PST 23
Peak memory 203032 kb
Host smart-86fa190c-9a69-49a8-85a5-ca999a75db64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6028223652816457821912157824293258197788753064561093266344433038361392
8007077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_rd.602822365281645782191215782429325819778875306456109326634443
30383613928007077
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.19952609327382813827180700141918401189705299117243106019619350778647494171724
Short name T734
Test name
Test status
Simulation time 14461449567 ps
CPU time 80.49 seconds
Started Nov 22 02:40:01 PM PST 23
Finished Nov 22 02:41:23 PM PST 23
Peak memory 1542108 kb
Host smart-1053ed02-f5ec-4b31-8174-f7ab123a7358
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995260932738281382718070014191840118970529911724310601961935077864749
4171724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_wr.199526093273828138271807001419184011897052991172431060196193
50778647494171724
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.89286856872660033964540932899493680483063351474235296978964140591504492626402
Short name T370
Test name
Test status
Simulation time 6281818576 ps
CPU time 77.13 seconds
Started Nov 22 02:40:05 PM PST 23
Finished Nov 22 02:41:23 PM PST 23
Peak memory 930472 kb
Host smart-150ac3fe-2d35-4fb8-977c-55defcbfcc04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8928685687266003396454093289949368048306335147423529697896414059150449
2626402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stretch.8928685687266003396454093289949368048306335147423529697896414059
1504492626402
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.106720130875140996653213820891599395069112390977268684962291352011108361292629
Short name T999
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.64 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:11 PM PST 23
Peak memory 212628 kb
Host smart-3c1edba3-27f7-42c1-8981-fd41e96f8a90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106720130875140996653213820891599395069112390977268
684962291352011108361292629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_timeout.10672013087514099665321382089159939506911239
0977268684962291352011108361292629
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_ovf.101527877280511032918108560310689250296142008328271445355099628656386354674008
Short name T761
Test name
Test status
Simulation time 5445414553 ps
CPU time 135.11 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:42:18 PM PST 23
Peak memory 406780 kb
Host smart-7ed23405-d30e-4bbb-a948-975cd2250564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10152787728051103291810856031068925029614200832827
1445355099628656386354674008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_tx_ovf.101527877280511032918108560310689250296142008
328271445355099628656386354674008
Directory /workspace/46.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.111559634688082767961479254821674030344188960173550991544522906534849010069413
Short name T323
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.41 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:08 PM PST 23
Peak memory 205308 kb
Host smart-01363696-a391-40e9-bc20-ce8bcfecbbd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111559634688082767961479254821674030344188960173550
991544522906534849010069413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_unexp_stop.1115596346880827679614792548216740303441
88960173550991544522906534849010069413
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.34106267678439789346252768957234003530343435759735776817634815929721068455587
Short name T24
Test name
Test status
Simulation time 19975830 ps
CPU time 0.62 seconds
Started Nov 22 02:40:53 PM PST 23
Finished Nov 22 02:40:54 PM PST 23
Peak memory 202560 kb
Host smart-d6c760bf-4625-41c4-b706-2c8554c45c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34106267678439789346252768957234003530343435759735776817634815929721068455587 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_alert_test.34106267678439789346252768957234003530343435759735776817634815929721068455587
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.6791901512472259229911184265244143867465547943838575171158896214913491185568
Short name T1421
Test name
Test status
Simulation time 74225396 ps
CPU time 1.38 seconds
Started Nov 22 02:40:28 PM PST 23
Finished Nov 22 02:40:30 PM PST 23
Peak memory 211256 kb
Host smart-593c793f-19c3-43fc-9052-a4bd41d4ae8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6791901512472259229911184265244143867465547943838575171158896214913491185568 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_host_error_intr.6791901512472259229911184265244143867465547943838575171158896214913491185568
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.54973442883458170460005057599597751863280341726041849185559202194556460267899
Short name T337
Test name
Test status
Simulation time 606667565 ps
CPU time 6.63 seconds
Started Nov 22 02:40:33 PM PST 23
Finished Nov 22 02:40:42 PM PST 23
Peak memory 273380 kb
Host smart-4732c2ba-3c7d-4f15-9153-6a141c4fba5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54973442883458170460005057599597751863280341726041849185559202194556460267899 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.54973442883458170460005057599597751863280341726041849185559202194556460267899
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.7824505842061710637757118718277482466260518615752382160993661021657780474166
Short name T504
Test name
Test status
Simulation time 3768267272 ps
CPU time 75.77 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:41:47 PM PST 23
Peak memory 729552 kb
Host smart-7557c376-a4ca-4424-b460-f1cf0b4d79d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7824505842061710637757118718277482466260518615752382160993661021657780474166 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_host_fifo_full.7824505842061710637757118718277482466260518615752382160993661021657780474166
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.72490058674271967497681093218843671027107593220330576362231750454241685093644
Short name T1001
Test name
Test status
Simulation time 7925734012 ps
CPU time 232.72 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:43:55 PM PST 23
Peak memory 1271544 kb
Host smart-ceef2ffa-3e9b-47cf-bd70-15297969d9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72490058674271967497681093218843671027107593220330576362231750454241685093644 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.i2c_host_fifo_overflow.72490058674271967497681093218843671027107593220330576362231750454241685093644
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.15490724477938936621769730715525704731706645817922365544805971350031796963410
Short name T785
Test name
Test status
Simulation time 209010032 ps
CPU time 0.92 seconds
Started Nov 22 02:40:03 PM PST 23
Finished Nov 22 02:40:05 PM PST 23
Peak memory 202928 kb
Host smart-3122dd7a-bb4a-4146-9fcc-3f0414f0fc53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15490724477938936621769730715525704731706645817922365544805971350031796963410 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.15490724477938936621769730715525704731706645817922365544805971350031796963410
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.90730593745463306021657590850709751490266701356244246766180941508098649535721
Short name T456
Test name
Test status
Simulation time 236313385 ps
CPU time 4.04 seconds
Started Nov 22 02:40:08 PM PST 23
Finished Nov 22 02:40:12 PM PST 23
Peak memory 225516 kb
Host smart-3a02e5d1-22ab-4701-b75f-efb6fe184aed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90730593745463306021657590850709751490266701356244246766180941508098649535721 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.90730593745463306021657590850709751490266701356244246766180941508098649535721
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.59317017955715586730802904533383560093526207070328761300447036213028987025772
Short name T1081
Test name
Test status
Simulation time 7918519784 ps
CPU time 208.05 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:44:04 PM PST 23
Peak memory 1310948 kb
Host smart-468c5a3c-0e3f-452e-aeef-db77904ae14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59317017955715586730802904533383560093526207070328761300447036213028987025772 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.i2c_host_fifo_watermark.59317017955715586730802904533383560093526207070328761300447036213028987025772
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.94556250099109881783546096928549166030285849470198538552561920259120628391790
Short name T720
Test name
Test status
Simulation time 3754070957 ps
CPU time 56.07 seconds
Started Nov 22 02:40:36 PM PST 23
Finished Nov 22 02:41:34 PM PST 23
Peak memory 293808 kb
Host smart-51004845-00b4-480d-84ce-b8fd515b992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94556250099109881783546096928549166030285849470198538552561920259120628391790 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_host_mode_toggle.94556250099109881783546096928549166030285849470198538552561920259120628391790
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.71729966380916943906687085983768368965757643118188409259313897453696806139056
Short name T1021
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:40:36 PM PST 23
Finished Nov 22 02:40:38 PM PST 23
Peak memory 202752 kb
Host smart-a322ef2c-a846-431b-a08f-a3c85c50e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71729966380916943906687085983768368965757643118188409259313897453696806139056 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_host_override.71729966380916943906687085983768368965757643118188409259313897453696806139056
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.24365523345890674163386516406918759845222623673664398941276181846874900597413
Short name T288
Test name
Test status
Simulation time 6830796343 ps
CPU time 59.47 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:41:03 PM PST 23
Peak memory 211348 kb
Host smart-82f65afb-d852-41c7-a6d7-f593f96871ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24365523345890674163386516406918759845222623673664398941276181846874900597413 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.i2c_host_perf.24365523345890674163386516406918759845222623673664398941276181846874900597413
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_rx_oversample.61861424341134031134953357545985516039645861588470901494399013935037088939291
Short name T48
Test name
Test status
Simulation time 3939158762 ps
CPU time 101.05 seconds
Started Nov 22 02:40:03 PM PST 23
Finished Nov 22 02:41:45 PM PST 23
Peak memory 345964 kb
Host smart-062c4bd8-7038-476c-a3b3-064ce09246e4
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61861424341134031134953357545985516039645861588470901494399013935037088939291 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_rx_oversample.61861424341134031134953357545985516039645861588470901494399013935037088939291
Directory /workspace/47.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.86667184008591175963353900488635032284011201686958600155602024968149935896802
Short name T471
Test name
Test status
Simulation time 2343171530 ps
CPU time 37.89 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:41 PM PST 23
Peak memory 299384 kb
Host smart-99c5e3ae-7409-4ddc-ac44-07c70937c983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86667184008591175963353900488635032284011201686958600155602024968149935896802 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.i2c_host_smoke.86667184008591175963353900488635032284011201686958600155602024968149935896802
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.42100916789779135670243171953012321898124767313362261999245782991247686599329
Short name T536
Test name
Test status
Simulation time 32807463528 ps
CPU time 1013.03 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:57:23 PM PST 23
Peak memory 1957176 kb
Host smart-648ea65c-5324-4038-b0c4-024e8258b9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42100916789779135670243171953012321898124767313362261999245782991247686599329 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_host_stress_all.42100916789779135670243171953012321898124767313362261999245782991247686599329
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.43451367042039683634753604080631367371504616919496642186169072427030843002956
Short name T1495
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.69 seconds
Started Nov 22 02:40:06 PM PST 23
Finished Nov 22 02:40:21 PM PST 23
Peak memory 214204 kb
Host smart-75145186-76e2-4969-bcf5-8a4f7b1950da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43451367042039683634753604080631367371504616919496642186169072427030843002956 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_host_stretch_timeout.43451367042039683634753604080631367371504616919496642186169072427030843002956
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.53597569232856570269458835386654975997223787474853687299416242793327503125807
Short name T1419
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.79 seconds
Started Nov 22 02:40:31 PM PST 23
Finished Nov 22 02:40:36 PM PST 23
Peak memory 202940 kb
Host smart-773bfb88-1721-4ea9-96ae-a1f2d2aaafdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5359756923285657026945883538665
4975997223787474853687299416242793327503125807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.53597569232856570269458835
386654975997223787474853687299416242793327503125807
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.105881992526312184470779204328592449262159185837987172385004120098318406279639
Short name T1265
Test name
Test status
Simulation time 10166144644 ps
CPU time 33.42 seconds
Started Nov 22 02:40:28 PM PST 23
Finished Nov 22 02:41:02 PM PST 23
Peak memory 382164 kb
Host smart-f232d4c4-5965-4ae8-a2b7-4e186b20043d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105881992526312184470779204328592449262159185837987
172385004120098318406279639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.105881992526312184470779204328
592449262159185837987172385004120098318406279639
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.26637385265189849544198181706973952866185965051074137120671170965350323049263
Short name T814
Test name
Test status
Simulation time 10065199023 ps
CPU time 36.81 seconds
Started Nov 22 02:40:07 PM PST 23
Finished Nov 22 02:40:45 PM PST 23
Peak memory 462144 kb
Host smart-5e944a33-cd59-4e25-925c-ef2fa5b29824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266373852651898495441981817069739528661859650510741
37120671170965350323049263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_tx.266373852651898495441981817069739
52866185965051074137120671170965350323049263
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.61423576718278350253899742619341231806161483891206236678568514616284040106148
Short name T1412
Test name
Test status
Simulation time 825344371 ps
CPU time 2.44 seconds
Started Nov 22 02:40:53 PM PST 23
Finished Nov 22 02:40:56 PM PST 23
Peak memory 202804 kb
Host smart-a2be5ca2-a1fc-4be1-960c-1c3f109591f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614235767182783502538997426193412318061614838912062
36678568514616284040106148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_hrst.614235767182783502538997426193412318061614838912062
36678568514616284040106148
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.50135744408861145147536457355664281119629777725512322387427384617844652639991
Short name T1060
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.25 seconds
Started Nov 22 02:40:34 PM PST 23
Finished Nov 22 02:40:40 PM PST 23
Peak memory 203136 kb
Host smart-ba86f0a4-e75a-42a3-af33-832108014919
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50135744408861145147536457355664281119629777725512
322387427384617844652639991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.5013574440886114514753645735566428111962977
7725512322387427384617844652639991
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.98674442380858883993025779966829515533013333519143007719772131901366003322396
Short name T991
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.22 seconds
Started Nov 22 02:40:06 PM PST 23
Finished Nov 22 02:40:31 PM PST 23
Peak memory 639264 kb
Host smart-1802e16a-c748-4ce4-b7f2-79069901ab12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98674442380858883993025779966829515533
013333519143007719772131901366003322396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.98674442380858883993025
779966829515533013333519143007719772131901366003322396
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.101195369410572009102793202744158526645397764952195682169720024833131677624082
Short name T731
Test name
Test status
Simulation time 834576440 ps
CPU time 3.04 seconds
Started Nov 22 02:40:28 PM PST 23
Finished Nov 22 02:40:32 PM PST 23
Peak memory 202980 kb
Host smart-846b662c-79f9-4c67-9060-712eb11d0386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101195369410572009102793202744158526645397764952195
682169720024833131677624082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_perf.10119536941057200910279320274415852664539776495219
5682169720024833131677624082
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.24225681867289153150504510263730062695225465642253261629279593408734449232309
Short name T789
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.62 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:40:46 PM PST 23
Peak memory 202988 kb
Host smart-5c622812-b8b8-4087-824e-35981d82f9e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422568186728915315050451026373006269522546564225326162927959340873444
9232309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smoke.24225681867289153150504510263730062695225465642253261629279593408734449232309
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.6521122717718153479678421451319270985832988706953317089522971500428402340370
Short name T960
Test name
Test status
Simulation time 66540157934 ps
CPU time 1584.1 seconds
Started Nov 22 02:40:27 PM PST 23
Finished Nov 22 03:06:52 PM PST 23
Peak memory 6983676 kb
Host smart-c93a9591-9621-446f-9691-6e4dddb6f0df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65211227177181534796784214513192709858329887069533
17089522971500428402340370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_all.652112271771815347967842145131927098583
2988706953317089522971500428402340370
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.83270736311804611261901212028289073313144841862170058995289189014326894149780
Short name T1070
Test name
Test status
Simulation time 997771563 ps
CPU time 8.9 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:40:12 PM PST 23
Peak memory 203052 kb
Host smart-70272e8d-403a-46a7-a5a5-9513643b5573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8327073631180461126190121202828907331314484186217005899528918901432689
4149780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_rd.832707363118046112619012120282890733131448418621700589952891
89014326894149780
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.9104881332171157832724578038827739460775210630886516521252923046865447484923
Short name T1582
Test name
Test status
Simulation time 14461449567 ps
CPU time 90.95 seconds
Started Nov 22 02:40:17 PM PST 23
Finished Nov 22 02:41:49 PM PST 23
Peak memory 1542156 kb
Host smart-d2eaab4a-c615-4c57-974e-787c04e30b3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9104881332171157832724578038827739460775210630886516521252923046865447
484923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_wr.9104881332171157832724578038827739460775210630886516521252923
046865447484923
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.60767020385454412857516065186744246844729277001723284143233718585589239689588
Short name T978
Test name
Test status
Simulation time 6281818576 ps
CPU time 72.39 seconds
Started Nov 22 02:40:02 PM PST 23
Finished Nov 22 02:41:15 PM PST 23
Peak memory 930552 kb
Host smart-20419bd8-1ce3-4e16-9083-b1598be73012
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6076702038545441285751606518674424684472927700172328414323371858558923
9689588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stretch.6076702038545441285751606518674424684472927700172328414323371858
5589239689588
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.103279036787421518014868181233871211491756311623608119293256448066261582257851
Short name T318
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.39 seconds
Started Nov 22 02:40:33 PM PST 23
Finished Nov 22 02:40:41 PM PST 23
Peak memory 212624 kb
Host smart-4b43d19c-683b-4529-b48f-68484a5b5153
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103279036787421518014868181233871211491756311623608
119293256448066261582257851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_timeout.10327903678742151801486818123387121149175631
1623608119293256448066261582257851
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_ovf.44126558847942243642473524666192710860263279065604703699894108458080821224656
Short name T798
Test name
Test status
Simulation time 5445414553 ps
CPU time 120.4 seconds
Started Nov 22 02:40:34 PM PST 23
Finished Nov 22 02:42:35 PM PST 23
Peak memory 406792 kb
Host smart-80876438-3959-41d1-8d5b-f369018be4a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44126558847942243642473524666192710860263279065604
703699894108458080821224656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_tx_ovf.4412655884794224364247352466619271086026327906
5604703699894108458080821224656
Directory /workspace/47.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.1452205004875877656208261537542313955021820423006736635143673639661813654867
Short name T1409
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.45 seconds
Started Nov 22 02:40:33 PM PST 23
Finished Nov 22 02:40:40 PM PST 23
Peak memory 205320 kb
Host smart-257f2b40-3d6f-4980-8e21-15bd2a02db1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145220500487587765620826153754231395502182042300673
6635143673639661813654867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_unexp_stop.145220500487587765620826153754231395502182
0423006736635143673639661813654867
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.31264386409698238594121126076125165860376017887874931562555002761969015059999
Short name T1247
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:40:46 PM PST 23
Finished Nov 22 02:40:48 PM PST 23
Peak memory 202768 kb
Host smart-8ffbca73-e77a-4f4b-bc81-ed2ea2f02948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31264386409698238594121126076125165860376017887874931562555002761969015059999 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_alert_test.31264386409698238594121126076125165860376017887874931562555002761969015059999
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.34467372601579083238411366970946171113695856187004486914187025568791875903280
Short name T501
Test name
Test status
Simulation time 74225396 ps
CPU time 1.29 seconds
Started Nov 22 02:40:48 PM PST 23
Finished Nov 22 02:40:50 PM PST 23
Peak memory 211248 kb
Host smart-c421aae0-e320-4628-be83-5201914bb651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34467372601579083238411366970946171113695856187004486914187025568791875903280 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_host_error_intr.34467372601579083238411366970946171113695856187004486914187025568791875903280
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.47920561804339887757689876001114793141690526654471752160009307663919894389067
Short name T440
Test name
Test status
Simulation time 606667565 ps
CPU time 6.71 seconds
Started Nov 22 02:40:50 PM PST 23
Finished Nov 22 02:40:57 PM PST 23
Peak memory 273404 kb
Host smart-b4beb796-fcb7-456c-93e8-c80dfeac627e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47920561804339887757689876001114793141690526654471752160009307663919894389067 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.47920561804339887757689876001114793141690526654471752160009307663919894389067
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.111896095284195637046155567655112068406184810066021723508575292563345805780924
Short name T1524
Test name
Test status
Simulation time 3768267272 ps
CPU time 77.29 seconds
Started Nov 22 02:40:30 PM PST 23
Finished Nov 22 02:41:48 PM PST 23
Peak memory 729472 kb
Host smart-d71a8341-7390-4885-b9fa-1bedb9a859b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111896095284195637046155567655112068406184810066021723508575292563345805780924 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_host_fifo_full.111896095284195637046155567655112068406184810066021723508575292563345805780924
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.33962536255495950055780983026848039947867157046385174795361122034643291729714
Short name T263
Test name
Test status
Simulation time 7925734012 ps
CPU time 249.21 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:44:47 PM PST 23
Peak memory 1271584 kb
Host smart-d89b123c-5f83-41d3-961b-320370905445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33962536255495950055780983026848039947867157046385174795361122034643291729714 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.i2c_host_fifo_overflow.33962536255495950055780983026848039947867157046385174795361122034643291729714
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.53241438299296728459655856404403332169572720667434309023250936725250246990522
Short name T948
Test name
Test status
Simulation time 209010032 ps
CPU time 0.97 seconds
Started Nov 22 02:40:42 PM PST 23
Finished Nov 22 02:40:44 PM PST 23
Peak memory 202924 kb
Host smart-c6260fe9-e22c-494a-9805-7bd13ac88bd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53241438299296728459655856404403332169572720667434309023250936725250246990522 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.53241438299296728459655856404403332169572720667434309023250936725250246990522
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.98897896628868651398543968875156910921309461309850217021447726429325679827016
Short name T1468
Test name
Test status
Simulation time 236313385 ps
CPU time 3.83 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:40:41 PM PST 23
Peak memory 225520 kb
Host smart-95747e9f-5065-4323-b21b-93b146c6644d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98897896628868651398543968875156910921309461309850217021447726429325679827016 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.98897896628868651398543968875156910921309461309850217021447726429325679827016
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.52577542676902357522096018725043119170197587275028423435078615895777974714293
Short name T271
Test name
Test status
Simulation time 7918519784 ps
CPU time 229.6 seconds
Started Nov 22 02:40:55 PM PST 23
Finished Nov 22 02:44:46 PM PST 23
Peak memory 1310956 kb
Host smart-4ce263b9-fc05-45af-8c15-6b258a8c8660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52577542676902357522096018725043119170197587275028423435078615895777974714293 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_host_fifo_watermark.52577542676902357522096018725043119170197587275028423435078615895777974714293
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.44098534476956730536280923500811857380777584209504476706646231316231318018301
Short name T192
Test name
Test status
Simulation time 3754070957 ps
CPU time 57.96 seconds
Started Nov 22 02:40:36 PM PST 23
Finished Nov 22 02:41:36 PM PST 23
Peak memory 293716 kb
Host smart-d507b5b7-7d7d-4613-bd48-483bf8c0af83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44098534476956730536280923500811857380777584209504476706646231316231318018301 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_host_mode_toggle.44098534476956730536280923500811857380777584209504476706646231316231318018301
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.95705227913736608810112678347703076460510776891252167376072912307269932066261
Short name T752
Test name
Test status
Simulation time 23672229 ps
CPU time 0.61 seconds
Started Nov 22 02:40:41 PM PST 23
Finished Nov 22 02:40:42 PM PST 23
Peak memory 202880 kb
Host smart-2c192504-26ff-4d4b-b452-f5c65b02d6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95705227913736608810112678347703076460510776891252167376072912307269932066261 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_host_override.95705227913736608810112678347703076460510776891252167376072912307269932066261
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.110395570463477452228119717044284828129189076298601545700097264065128815813666
Short name T800
Test name
Test status
Simulation time 6830796343 ps
CPU time 59.12 seconds
Started Nov 22 02:40:44 PM PST 23
Finished Nov 22 02:41:44 PM PST 23
Peak memory 211280 kb
Host smart-cf169337-bebf-4075-9a18-95f5003d3878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110395570463477452228119717044284828129189076298601545700097264065128815813666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.i2c_host_perf.110395570463477452228119717044284828129189076298601545700097264065128815813666
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_rx_oversample.47215798429607502962441934338557581462765156975397781940475818770023003974764
Short name T1184
Test name
Test status
Simulation time 3939158762 ps
CPU time 97.26 seconds
Started Nov 22 02:40:36 PM PST 23
Finished Nov 22 02:42:15 PM PST 23
Peak memory 345972 kb
Host smart-27fbfbfa-afb8-458f-8802-87bc56c4bfb1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47215798429607502962441934338557581462765156975397781940475818770023003974764 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_rx_oversample.47215798429607502962441934338557581462765156975397781940475818770023003974764
Directory /workspace/48.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.111265970238854396848885836368243108235951129857133237048304703511599605793650
Short name T446
Test name
Test status
Simulation time 2343171530 ps
CPU time 33.93 seconds
Started Nov 22 02:40:47 PM PST 23
Finished Nov 22 02:41:21 PM PST 23
Peak memory 299404 kb
Host smart-9c842d62-5479-4347-9c17-46667b94b427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111265970238854396848885836368243108235951129857133237048304703511599605793650 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.i2c_host_smoke.111265970238854396848885836368243108235951129857133237048304703511599605793650
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.84538774780890564088571270619097677376079345972337257665557114525768276210737
Short name T810
Test name
Test status
Simulation time 32807463528 ps
CPU time 1017.55 seconds
Started Nov 22 02:40:43 PM PST 23
Finished Nov 22 02:57:41 PM PST 23
Peak memory 1957068 kb
Host smart-727cf7a7-b15b-4645-b23a-c8faf6eb2bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84538774780890564088571270619097677376079345972337257665557114525768276210737 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_host_stress_all.84538774780890564088571270619097677376079345972337257665557114525768276210737
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.84956895866443708614909865982574972026983598302202533118977188697285516999564
Short name T811
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.23 seconds
Started Nov 22 02:40:42 PM PST 23
Finished Nov 22 02:40:56 PM PST 23
Peak memory 214172 kb
Host smart-b31533ac-3ab0-4c8b-a8b3-db6e14eb6c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84956895866443708614909865982574972026983598302202533118977188697285516999564 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_host_stretch_timeout.84956895866443708614909865982574972026983598302202533118977188697285516999564
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.109676435299471345969156335157812275720184751267835925962055930011872968002881
Short name T614
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.85 seconds
Started Nov 22 02:40:49 PM PST 23
Finished Nov 22 02:40:54 PM PST 23
Peak memory 203116 kb
Host smart-19f71add-b05c-4c83-a434-688457fa40b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096764352994713459691563351578
12275720184751267835925962055930011872968002881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1096764352994713459691563
35157812275720184751267835925962055930011872968002881
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.104255708054165673098154174430164009518128323800501068567736119541179382917991
Short name T1453
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.73 seconds
Started Nov 22 02:40:36 PM PST 23
Finished Nov 22 02:41:09 PM PST 23
Peak memory 382192 kb
Host smart-0c1eb0bd-f75c-4e7c-b8f5-159754fd49fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104255708054165673098154174430164009518128323800501
068567736119541179382917991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_acq.104255708054165673098154174430
164009518128323800501068567736119541179382917991
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.25348057462385255695759325805783026723191315726911231453587406636094959741140
Short name T874
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.4 seconds
Started Nov 22 02:40:34 PM PST 23
Finished Nov 22 02:41:10 PM PST 23
Peak memory 462116 kb
Host smart-df958878-bd44-4bdb-991d-9e1fd93400a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253480574623852556957593258057830267231913157269112
31453587406636094959741140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_tx.253480574623852556957593258057830
26723191315726911231453587406636094959741140
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.8827251128969633368837044778545485793637721390752081620926498657864892755994
Short name T1464
Test name
Test status
Simulation time 825344371 ps
CPU time 2.5 seconds
Started Nov 22 02:40:48 PM PST 23
Finished Nov 22 02:40:52 PM PST 23
Peak memory 202976 kb
Host smart-83fa4641-4810-49c4-924f-401012aff3fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882725112896963336883704477854548579363772139075208
1620926498657864892755994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_hrst.8827251128969633368837044778545485793637721390752081
620926498657864892755994
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.96400637231352688894292726658454450028559822540970326898342417594029227588823
Short name T876
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.22 seconds
Started Nov 22 02:40:36 PM PST 23
Finished Nov 22 02:40:42 PM PST 23
Peak memory 203632 kb
Host smart-b890071d-c5bb-4576-b7a7-a295ea8e4ae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96400637231352688894292726658454450028559822540970
326898342417594029227588823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_smoke.9640063723135268889429272665845445002855982
2540970326898342417594029227588823
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.33831081372200480423478297272344048858513061055295933351911226759083875210097
Short name T1469
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.13 seconds
Started Nov 22 02:40:46 PM PST 23
Finished Nov 22 02:41:11 PM PST 23
Peak memory 639192 kb
Host smart-e0b733b4-2b5c-4a01-9973-4a26f553004a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33831081372200480423478297272344048858
513061055295933351911226759083875210097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.33831081372200480423478
297272344048858513061055295933351911226759083875210097
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.39949413519753844033837623055209179333454856024230950771544065924786553290662
Short name T852
Test name
Test status
Simulation time 834576440 ps
CPU time 3.06 seconds
Started Nov 22 02:40:47 PM PST 23
Finished Nov 22 02:40:50 PM PST 23
Peak memory 203084 kb
Host smart-e2e94aca-8154-418a-a2d3-238b089055a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399494135197538440338376230552091793334548560242309
50771544065924786553290662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_perf.399494135197538440338376230552091793334548560242309
50771544065924786553290662
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.100028086787384436581663685255936421324248889026312602349785709603246008168
Short name T476
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.82 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:40:46 PM PST 23
Peak memory 203040 kb
Host smart-15303adc-3567-427c-9e24-4faa518d0095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000280867873844365816636852559364213242488890263126023497857096032460
08168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smoke.100028086787384436581663685255936421324248889026312602349785709603246008168
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.22304134974067956050016542510995950178478680633539638261141020304928972541860
Short name T1276
Test name
Test status
Simulation time 66540157934 ps
CPU time 1582.41 seconds
Started Nov 22 02:40:40 PM PST 23
Finished Nov 22 03:07:03 PM PST 23
Peak memory 6983432 kb
Host smart-efcdd0b5-0555-4429-b323-bd8add3f90d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22304134974067956050016542510995950178478680633539
638261141020304928972541860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_all.22304134974067956050016542510995950178
478680633539638261141020304928972541860
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.74924781676802852013625339905941136558929097392518633376205025219933206677478
Short name T68
Test name
Test status
Simulation time 997771563 ps
CPU time 8.62 seconds
Started Nov 22 02:40:43 PM PST 23
Finished Nov 22 02:40:53 PM PST 23
Peak memory 202992 kb
Host smart-eb6880dd-944c-4d6d-844b-94e83c3386a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7492478167680285201362533990594113655892909739251863337620502521993320
6677478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_rd.749247816768028520136253399059411365589290973925186333762050
25219933206677478
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.72554299466161330704312777414571627712885825645470959319539522604777124001647
Short name T1038
Test name
Test status
Simulation time 14461449567 ps
CPU time 89.26 seconds
Started Nov 22 02:40:38 PM PST 23
Finished Nov 22 02:42:08 PM PST 23
Peak memory 1542144 kb
Host smart-8b0fae00-74e4-4843-bdc0-18002ba46845
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7255429946616133070431277741457162771288582564547095931953952260477712
4001647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_wr.725542994661613307043127774145716277128858256454709593195395
22604777124001647
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.111712177736904867576753688019796297171232235577519330148680768282183515516006
Short name T844
Test name
Test status
Simulation time 6281818576 ps
CPU time 80.14 seconds
Started Nov 22 02:40:43 PM PST 23
Finished Nov 22 02:42:04 PM PST 23
Peak memory 930624 kb
Host smart-00a1239b-9014-4c02-82bb-c9a468c565e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117121777369048675767536880197962971712322355775193301486807682821835
15516006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stretch.111712177736904867576753688019796297171232235577519330148680768
282183515516006
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.90763769586031126982789919162197653785629224511571170023511128077886308224593
Short name T986
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.68 seconds
Started Nov 22 02:40:37 PM PST 23
Finished Nov 22 02:40:46 PM PST 23
Peak memory 212564 kb
Host smart-0b207ea0-54c0-4535-82a0-c894712a35f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907637695860311269827899191621976537856292245115711
70023511128077886308224593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_timeout.907637695860311269827899191621976537856292245
11571170023511128077886308224593
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_ovf.20648743772743854981677407521509466251850004799176304254559329355809192447654
Short name T1245
Test name
Test status
Simulation time 5445414553 ps
CPU time 135.62 seconds
Started Nov 22 02:40:49 PM PST 23
Finished Nov 22 02:43:06 PM PST 23
Peak memory 406876 kb
Host smart-c6cc5a85-bff1-4d84-8a10-f4b350970c16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648743772743854981677407521509466251850004799176
304254559329355809192447654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_tx_ovf.2064874377274385498167740752150946625185000479
9176304254559329355809192447654
Directory /workspace/48.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.55240610337285706215284118733582412905329123968682333026003018815009639835201
Short name T820
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.45 seconds
Started Nov 22 02:40:55 PM PST 23
Finished Nov 22 02:41:02 PM PST 23
Peak memory 205336 kb
Host smart-5de68ca0-ed52-4ea2-b095-0585b1c57110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552406103372857062152841187335824129053291239686823
33026003018815009639835201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_unexp_stop.55240610337285706215284118733582412905329
123968682333026003018815009639835201
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.98705868285613226429902492821889517065702090587444506262358510424771510103434
Short name T547
Test name
Test status
Simulation time 19975830 ps
CPU time 0.58 seconds
Started Nov 22 02:40:54 PM PST 23
Finished Nov 22 02:40:56 PM PST 23
Peak memory 202776 kb
Host smart-61f3edbc-c755-4154-8b78-4f8b45cb9027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98705868285613226429902492821889517065702090587444506262358510424771510103434 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_alert_test.98705868285613226429902492821889517065702090587444506262358510424771510103434
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.34185346863293326178087506548013388108315719213157561143346180263884998936872
Short name T987
Test name
Test status
Simulation time 74225396 ps
CPU time 1.36 seconds
Started Nov 22 02:40:53 PM PST 23
Finished Nov 22 02:40:56 PM PST 23
Peak memory 211280 kb
Host smart-a2857dab-7cfa-477c-9c5c-37f229d5e2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34185346863293326178087506548013388108315719213157561143346180263884998936872 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_host_error_intr.34185346863293326178087506548013388108315719213157561143346180263884998936872
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.9975848803180196454207773377634922695468646733220034185679050989645876791834
Short name T156
Test name
Test status
Simulation time 606667565 ps
CPU time 6.7 seconds
Started Nov 22 02:40:49 PM PST 23
Finished Nov 22 02:40:57 PM PST 23
Peak memory 273284 kb
Host smart-ef8de1a9-349b-4ddd-8904-2630e07c1d4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9975848803180196454207773377634922695468646733220034185679050989645876791834 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.9975848803180196454207773377634922695468646733220034185679050989645876791834
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.65216357830326827883016145262665666586270998273029679051254729499559752265019
Short name T1327
Test name
Test status
Simulation time 3768267272 ps
CPU time 69.18 seconds
Started Nov 22 02:40:49 PM PST 23
Finished Nov 22 02:41:59 PM PST 23
Peak memory 729508 kb
Host smart-d09668dd-2bba-42f4-bd5f-0f4d6cf04862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65216357830326827883016145262665666586270998273029679051254729499559752265019 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_host_fifo_full.65216357830326827883016145262665666586270998273029679051254729499559752265019
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.103967761175099208291040859840509489014849478527892049272197322410387410023907
Short name T350
Test name
Test status
Simulation time 7925734012 ps
CPU time 262.75 seconds
Started Nov 22 02:40:53 PM PST 23
Finished Nov 22 02:45:16 PM PST 23
Peak memory 1271316 kb
Host smart-baff1447-0c14-470d-9cd9-6038bcc04384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103967761175099208291040859840509489014849478527892049272197322410387410023907 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_host_fifo_overflow.103967761175099208291040859840509489014849478527892049272197322410387410023907
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.71582536043455325783151562218227130656652553020786408220527203701520776634605
Short name T1127
Test name
Test status
Simulation time 209010032 ps
CPU time 0.97 seconds
Started Nov 22 02:40:49 PM PST 23
Finished Nov 22 02:40:50 PM PST 23
Peak memory 202836 kb
Host smart-a3196b63-b678-4d22-9970-a09e5ecd0525
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71582536043455325783151562218227130656652553020786408220527203701520776634605 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.71582536043455325783151562218227130656652553020786408220527203701520776634605
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.92108814429630026503967598234561194594962020638770942887817987315464074474272
Short name T1446
Test name
Test status
Simulation time 236313385 ps
CPU time 3.64 seconds
Started Nov 22 02:40:55 PM PST 23
Finished Nov 22 02:41:00 PM PST 23
Peak memory 225500 kb
Host smart-dac81474-674c-4155-aefb-d3fb86dd1396
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92108814429630026503967598234561194594962020638770942887817987315464074474272 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.92108814429630026503967598234561194594962020638770942887817987315464074474272
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.57533031579306801003578012976831232580768625875217166765646045568131938472730
Short name T994
Test name
Test status
Simulation time 7918519784 ps
CPU time 212.75 seconds
Started Nov 22 02:40:49 PM PST 23
Finished Nov 22 02:44:22 PM PST 23
Peak memory 1310880 kb
Host smart-6f20e72e-458d-4599-a1f9-57b14b0ef026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57533031579306801003578012976831232580768625875217166765646045568131938472730 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_host_fifo_watermark.57533031579306801003578012976831232580768625875217166765646045568131938472730
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.5473389017987090681323989463127104717032157209086771777313990166472815706130
Short name T486
Test name
Test status
Simulation time 3754070957 ps
CPU time 48.17 seconds
Started Nov 22 02:40:43 PM PST 23
Finished Nov 22 02:41:32 PM PST 23
Peak memory 293688 kb
Host smart-1fa14086-c5b3-49d7-8941-9f3a0ac1757e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5473389017987090681323989463127104717032157209086771777313990166472815706130 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_host_mode_toggle.5473389017987090681323989463127104717032157209086771777313990166472815706130
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.115193716316238912596496131444738172317385055499805115619728931685768107831375
Short name T676
Test name
Test status
Simulation time 23672229 ps
CPU time 0.64 seconds
Started Nov 22 02:40:43 PM PST 23
Finished Nov 22 02:40:44 PM PST 23
Peak memory 202696 kb
Host smart-8ff07f4a-ba75-49eb-a2ac-0131e8cffd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115193716316238912596496131444738172317385055499805115619728931685768107831375 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_host_override.115193716316238912596496131444738172317385055499805115619728931685768107831375
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.79518546619907708139840685814042916724067625865050512237941052047270128647402
Short name T1532
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.1 seconds
Started Nov 22 02:40:47 PM PST 23
Finished Nov 22 02:41:48 PM PST 23
Peak memory 211380 kb
Host smart-2f1c3ea4-341b-4b1d-9ae6-f700a409fb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79518546619907708139840685814042916724067625865050512237941052047270128647402 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.i2c_host_perf.79518546619907708139840685814042916724067625865050512237941052047270128647402
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_rx_oversample.4567568692526367577582616119098240306101592961528992463871699713808096319961
Short name T1279
Test name
Test status
Simulation time 3939158762 ps
CPU time 107.22 seconds
Started Nov 22 02:40:40 PM PST 23
Finished Nov 22 02:42:28 PM PST 23
Peak memory 345984 kb
Host smart-a8a44c52-73af-4838-946f-42409d80d27e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4567568692526367577582616119098240306101592961528992463871699713808096319961 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_rx_oversample.4567568692526367577582616119098240306101592961528992463871699713808096319961
Directory /workspace/49.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.43115617536454012401757978503979431541766048017186757006713364838178065441390
Short name T583
Test name
Test status
Simulation time 2343171530 ps
CPU time 38.21 seconds
Started Nov 22 02:40:50 PM PST 23
Finished Nov 22 02:41:29 PM PST 23
Peak memory 299468 kb
Host smart-f0380776-1fe8-45d6-835a-28b75e140c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43115617536454012401757978503979431541766048017186757006713364838178065441390 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.i2c_host_smoke.43115617536454012401757978503979431541766048017186757006713364838178065441390
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.45157254474135589956604781645646564399189122891879183842475086606877884077177
Short name T1197
Test name
Test status
Simulation time 32807463528 ps
CPU time 998.51 seconds
Started Nov 22 02:40:41 PM PST 23
Finished Nov 22 02:57:20 PM PST 23
Peak memory 1956988 kb
Host smart-9f282150-8139-4350-965e-575498ebb96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45157254474135589956604781645646564399189122891879183842475086606877884077177 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_host_stress_all.45157254474135589956604781645646564399189122891879183842475086606877884077177
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.46200118893936626479869011834078151995428239158497047813325375044748988083322
Short name T435
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.81 seconds
Started Nov 22 02:40:36 PM PST 23
Finished Nov 22 02:40:51 PM PST 23
Peak memory 214100 kb
Host smart-8059544f-0fcb-4b34-a7a9-6fe33e733490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46200118893936626479869011834078151995428239158497047813325375044748988083322 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_host_stretch_timeout.46200118893936626479869011834078151995428239158497047813325375044748988083322
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.76122508618190620235295744881390735063793230769651802565118486875861321562335
Short name T1289
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.92 seconds
Started Nov 22 02:40:46 PM PST 23
Finished Nov 22 02:40:50 PM PST 23
Peak memory 203084 kb
Host smart-dfc2dfdc-a157-4ba9-90f7-0f0287347900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7612250861819062023529574488139
0735063793230769651802565118486875861321562335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.76122508618190620235295744
881390735063793230769651802565118486875861321562335
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.22257539488336529292242374653750684622698071877815724165947868834174255634076
Short name T310
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.76 seconds
Started Nov 22 02:40:51 PM PST 23
Finished Nov 22 02:41:23 PM PST 23
Peak memory 382224 kb
Host smart-ceaabe45-d2a4-4f22-8ccb-511f5965fac2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222575394883365292922423746537506846226980718778157
24165947868834174255634076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.2225753948833652929224237465375
0684622698071877815724165947868834174255634076
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.61103609788828542496214563642326705791438204261812261940365756330539968544990
Short name T938
Test name
Test status
Simulation time 10065199023 ps
CPU time 33.95 seconds
Started Nov 22 02:40:52 PM PST 23
Finished Nov 22 02:41:27 PM PST 23
Peak memory 462104 kb
Host smart-57cc0762-c896-4f5f-9076-b6947f9e0c14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611036097888285424962145636423267057914382042618122
61940365756330539968544990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_tx.611036097888285424962145636423267
05791438204261812261940365756330539968544990
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.63005595635195552397192436811538308866637103223366003841753689900798559579683
Short name T1053
Test name
Test status
Simulation time 825344371 ps
CPU time 2.35 seconds
Started Nov 22 02:40:51 PM PST 23
Finished Nov 22 02:40:54 PM PST 23
Peak memory 202856 kb
Host smart-980b5dc9-e681-41dd-a9d9-5141fc049a5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630055956351955523971924368115383088666371032233660
03841753689900798559579683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_hrst.630055956351955523971924368115383088666371032233660
03841753689900798559579683
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.72217592760492581926860253443590704290484157965261675456948152046597537791064
Short name T566
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.13 seconds
Started Nov 22 02:40:37 PM PST 23
Finished Nov 22 02:40:42 PM PST 23
Peak memory 203632 kb
Host smart-d4b36e41-9401-46ca-96d2-6847e115a9fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72217592760492581926860253443590704290484157965261
675456948152046597537791064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_smoke.7221759276049258192686025344359070429048415
7965261675456948152046597537791064
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.101708107091078433684117554769534549625207914814801417869247260341888300666874
Short name T854
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.11 seconds
Started Nov 22 02:40:48 PM PST 23
Finished Nov 22 02:41:10 PM PST 23
Peak memory 639252 kb
Host smart-ffa788ad-1173-4696-b818-38eaab05ca01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10170810709107843368411755476953454962
5207914814801417869247260341888300666874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1017081070910784336841
17554769534549625207914814801417869247260341888300666874
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_perf.83380149777525798837901204175876073588862652100733324521836382533777026154835
Short name T6
Test name
Test status
Simulation time 834576440 ps
CPU time 2.91 seconds
Started Nov 22 02:40:50 PM PST 23
Finished Nov 22 02:40:54 PM PST 23
Peak memory 203044 kb
Host smart-b9543510-4af7-4a01-8370-e356c9c93f93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833801497775257988379012041758760735888626521007333
24521836382533777026154835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_perf.833801497775257988379012041758760735888626521007333
24521836382533777026154835
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.106540444146364594506438638577060190200196505580348459540865727093194268312082
Short name T1089
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.32 seconds
Started Nov 22 02:40:50 PM PST 23
Finished Nov 22 02:41:00 PM PST 23
Peak memory 203020 kb
Host smart-f0506c7c-c85f-49db-bcfd-36317537731e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065404441463645945064386385770601902001965055803484595408657270931942
68312082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smoke.106540444146364594506438638577060190200196505580348459540865727093194268312082
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.91492027880500699194040388689984037329696135965148658197780953300330377669515
Short name T657
Test name
Test status
Simulation time 66540157934 ps
CPU time 1793.03 seconds
Started Nov 22 02:40:49 PM PST 23
Finished Nov 22 03:10:43 PM PST 23
Peak memory 6983392 kb
Host smart-09f958f7-2d3c-48dd-b256-0703a209b313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91492027880500699194040388689984037329696135965148
658197780953300330377669515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_all.91492027880500699194040388689984037329
696135965148658197780953300330377669515
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.73177840359335949434434234567105505363165840141195845379199448109781213848048
Short name T171
Test name
Test status
Simulation time 997771563 ps
CPU time 8.58 seconds
Started Nov 22 02:40:43 PM PST 23
Finished Nov 22 02:40:53 PM PST 23
Peak memory 203064 kb
Host smart-10b14728-d0fb-4dd6-b753-cc95da128c28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7317784035933594943443423456710550536316584014119584537919944810978121
3848048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_rd.731778403593359494344342345671055053631658401411958453791994
48109781213848048
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.88918440752397687049084259640223803453754388617819473485656855706235501126051
Short name T404
Test name
Test status
Simulation time 14461449567 ps
CPU time 80.15 seconds
Started Nov 22 02:40:41 PM PST 23
Finished Nov 22 02:42:02 PM PST 23
Peak memory 1542104 kb
Host smart-fbda2a4b-3ed5-4fe2-ad3a-fe8ef887c22c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8891844075239768704908425964022380345375438861781947348565685570623550
1126051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_wr.889184407523976870490842596402238034537543886178194734856568
55706235501126051
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.59108512541296052499933041103283129579321057821756409382391358958344477823998
Short name T1463
Test name
Test status
Simulation time 6281818576 ps
CPU time 77.83 seconds
Started Nov 22 02:40:42 PM PST 23
Finished Nov 22 02:42:01 PM PST 23
Peak memory 930556 kb
Host smart-74a07fbc-2d6d-497b-babf-c7bbfa29383c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5910851254129605249993304110328312957932105782175640938239135895834447
7823998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stretch.5910851254129605249993304110328312957932105782175640938239135895
8344477823998
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.78313214706079575594786315676400730930489889820183679690096512493677162801699
Short name T561
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.4 seconds
Started Nov 22 02:40:49 PM PST 23
Finished Nov 22 02:40:57 PM PST 23
Peak memory 212632 kb
Host smart-0575b68e-0a73-4723-a364-96ab3b3fa6b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783132147060795755947863156764007309304898898201836
79690096512493677162801699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_timeout.783132147060795755947863156764007309304898898
20183679690096512493677162801699
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_ovf.54760343471194713560509629298012382813429753064592258712855283467387853541057
Short name T1527
Test name
Test status
Simulation time 5445414553 ps
CPU time 128.48 seconds
Started Nov 22 02:40:35 PM PST 23
Finished Nov 22 02:42:46 PM PST 23
Peak memory 406712 kb
Host smart-83e84db6-6c4d-4b78-bce3-eb0eb9095dcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54760343471194713560509629298012382813429753064592
258712855283467387853541057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_tx_ovf.5476034347119471356050962929801238281342975306
4592258712855283467387853541057
Directory /workspace/49.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.38227064165303238710416852772591882942585618761938929209974784520689687165419
Short name T704
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.53 seconds
Started Nov 22 02:40:54 PM PST 23
Finished Nov 22 02:41:00 PM PST 23
Peak memory 205088 kb
Host smart-7a5c799a-0377-4bfa-a327-1e51899f992f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382270641653032387104168527725918829425856187619389
29209974784520689687165419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_unexp_stop.38227064165303238710416852772591882942585
618761938929209974784520689687165419
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.49700630852636710997948445707128237927502421936622442613532022568866289265467
Short name T1153
Test name
Test status
Simulation time 19975830 ps
CPU time 0.59 seconds
Started Nov 22 02:19:15 PM PST 23
Finished Nov 22 02:19:17 PM PST 23
Peak memory 202860 kb
Host smart-3087edcf-025c-4157-9f66-ebad7dac9856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49700630852636710997948445707128237927502421936622442613532022568866289265467 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_alert_test.49700630852636710997948445707128237927502421936622442613532022568866289265467
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.94688011188609187143573371405277856358294099023385991586322863270975424877160
Short name T1378
Test name
Test status
Simulation time 74225396 ps
CPU time 1.35 seconds
Started Nov 22 02:18:36 PM PST 23
Finished Nov 22 02:18:38 PM PST 23
Peak memory 211308 kb
Host smart-d7cb8035-8fa0-4257-917c-25cb58795aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94688011188609187143573371405277856358294099023385991586322863270975424877160 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_host_error_intr.94688011188609187143573371405277856358294099023385991586322863270975424877160
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.5849758091570729808018180168128650027873209145394444321423090843381578396261
Short name T240
Test name
Test status
Simulation time 606667565 ps
CPU time 6.73 seconds
Started Nov 22 02:18:42 PM PST 23
Finished Nov 22 02:18:49 PM PST 23
Peak memory 273300 kb
Host smart-471bd5f5-a404-4d3b-bedb-208124842578
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5849758091570729808018180168128650027873209145394444321423090843381578396261 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.5849758091570729808018180168128650027873209145394444321423090843381578396261
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.78168291896848342233339899930397826440730032591058972785839655519368771474666
Short name T974
Test name
Test status
Simulation time 3768267272 ps
CPU time 73.33 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:20:25 PM PST 23
Peak memory 729452 kb
Host smart-04bd94e4-56d6-48a7-87ac-1ae62eeb37d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78168291896848342233339899930397826440730032591058972785839655519368771474666 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_host_fifo_full.78168291896848342233339899930397826440730032591058972785839655519368771474666
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.8767748544834048679494783074706195958439538296072250375060438996271964641542
Short name T702
Test name
Test status
Simulation time 7925734012 ps
CPU time 245.23 seconds
Started Nov 22 02:18:51 PM PST 23
Finished Nov 22 02:22:57 PM PST 23
Peak memory 1271644 kb
Host smart-6a2e9b16-256c-4a0f-8655-9b0776863150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8767748544834048679494783074706195958439538296072250375060438996271964641542 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_host_fifo_overflow.8767748544834048679494783074706195958439538296072250375060438996271964641542
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.21568037640432533599114012970906069960684597799434348769230493995087050092396
Short name T1255
Test name
Test status
Simulation time 209010032 ps
CPU time 0.97 seconds
Started Nov 22 02:18:54 PM PST 23
Finished Nov 22 02:18:56 PM PST 23
Peak memory 202856 kb
Host smart-75fb0aef-6c8e-4bff-bf73-01c54f8cd9e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21568037640432533599114012970906069960684597799434348769230493995087050092396 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.21568037640432533599114012970906069960684597799434348769230493995087050092396
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.77939744571858771617523808610850757484949112920556408653886589694903515230128
Short name T636
Test name
Test status
Simulation time 236313385 ps
CPU time 3.97 seconds
Started Nov 22 02:18:37 PM PST 23
Finished Nov 22 02:18:42 PM PST 23
Peak memory 225512 kb
Host smart-6c298598-1f07-4583-a94c-d42c95fb5e59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77939744571858771617523808610850757484949112920556408653886589694903515230128 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.77939744571858771617523808610850757484949112920556408653886589694903515230128
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.75812598121744789068253873892119551896724824925945115345463522863001457020707
Short name T857
Test name
Test status
Simulation time 7918519784 ps
CPU time 205.63 seconds
Started Nov 22 02:18:38 PM PST 23
Finished Nov 22 02:22:05 PM PST 23
Peak memory 1311008 kb
Host smart-0a4a03c8-5e63-4001-a92a-8c01861639de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75812598121744789068253873892119551896724824925945115345463522863001457020707 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.i2c_host_fifo_watermark.75812598121744789068253873892119551896724824925945115345463522863001457020707
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.105991879840941777221106571756174978924494947447458218215739150751721862307290
Short name T408
Test name
Test status
Simulation time 3754070957 ps
CPU time 48.03 seconds
Started Nov 22 02:18:55 PM PST 23
Finished Nov 22 02:19:43 PM PST 23
Peak memory 293708 kb
Host smart-a333ac53-651f-4335-be70-f72d6501dcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105991879840941777221106571756174978924494947447458218215739150751721862307290 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_host_mode_toggle.105991879840941777221106571756174978924494947447458218215739150751721862307290
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.86443914032708684226130340164333778714820654095648333552968909652981004774984
Short name T897
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:18:39 PM PST 23
Finished Nov 22 02:18:40 PM PST 23
Peak memory 202792 kb
Host smart-6aa259ed-c032-4062-838f-f224d8b193c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86443914032708684226130340164333778714820654095648333552968909652981004774984 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_host_override.86443914032708684226130340164333778714820654095648333552968909652981004774984
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.104619951231079209108617140407892066911159197817673661834825806868704165770238
Short name T1359
Test name
Test status
Simulation time 6830796343 ps
CPU time 61.36 seconds
Started Nov 22 02:18:39 PM PST 23
Finished Nov 22 02:19:41 PM PST 23
Peak memory 211308 kb
Host smart-bd9aef9c-888d-4f0a-a2f7-dbe20bee8bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104619951231079209108617140407892066911159197817673661834825806868704165770238 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.i2c_host_perf.104619951231079209108617140407892066911159197817673661834825806868704165770238
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_rx_oversample.41563906063678509898895476508327282205606111825797836119524668983348387348770
Short name T1406
Test name
Test status
Simulation time 3939158762 ps
CPU time 106.63 seconds
Started Nov 22 02:18:21 PM PST 23
Finished Nov 22 02:20:08 PM PST 23
Peak memory 345864 kb
Host smart-b638288c-9cd5-4258-8d57-a393ac90c034
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41563906063678509898895476508327282205606111825797836119524668983348387348770 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_rx_oversample.41563906063678509898895476508327282205606111825797836119524668983348387348770
Directory /workspace/5.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.72627961900717624287020575878262724881315756624972473472473953052769292166809
Short name T770
Test name
Test status
Simulation time 2343171530 ps
CPU time 34.05 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:19:45 PM PST 23
Peak memory 299252 kb
Host smart-291a0a4e-0c1a-472a-8cef-9a24cdb276a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72627961900717624287020575878262724881315756624972473472473953052769292166809 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.i2c_host_smoke.72627961900717624287020575878262724881315756624972473472473953052769292166809
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.31326622473385873304774479958078428400895089599584276811689228392234672068761
Short name T1326
Test name
Test status
Simulation time 32807463528 ps
CPU time 1142.34 seconds
Started Nov 22 02:18:50 PM PST 23
Finished Nov 22 02:37:53 PM PST 23
Peak memory 1957028 kb
Host smart-d985ac8a-2718-4c94-be00-5b5c9723b210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31326622473385873304774479958078428400895089599584276811689228392234672068761 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_host_stress_all.31326622473385873304774479958078428400895089599584276811689228392234672068761
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.22393042026167510668862021965930485081947196975325377727656836386801558543450
Short name T1577
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.76 seconds
Started Nov 22 02:18:52 PM PST 23
Finished Nov 22 02:19:06 PM PST 23
Peak memory 214124 kb
Host smart-3f7fe293-fffd-44bc-8411-cfcfb5d1d788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22393042026167510668862021965930485081947196975325377727656836386801558543450 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_host_stretch_timeout.22393042026167510668862021965930485081947196975325377727656836386801558543450
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.53922138014887710917463576789446420232441644851175722538540102457056805517561
Short name T1484
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.64 seconds
Started Nov 22 02:18:47 PM PST 23
Finished Nov 22 02:18:51 PM PST 23
Peak memory 202872 kb
Host smart-7f96f8fe-1019-4d8a-a7c2-5e6823502e3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5392213801488771091746357678944
6420232441644851175722538540102457056805517561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.539221380148877109174635767
89446420232441644851175722538540102457056805517561
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.77805183277826461373172889018100547699971246872854638892944111081831397701762
Short name T709
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.34 seconds
Started Nov 22 02:18:23 PM PST 23
Finished Nov 22 02:18:56 PM PST 23
Peak memory 382228 kb
Host smart-821f99a4-652d-4458-9a5a-7595b1178138
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778051832778264613731728890181005476999712468728546
38892944111081831397701762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_acq.77805183277826461373172889018100
547699971246872854638892944111081831397701762
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.88619273677017751535045003819127046017830544904393287414225897031206684264373
Short name T1234
Test name
Test status
Simulation time 10065199023 ps
CPU time 35.11 seconds
Started Nov 22 02:19:09 PM PST 23
Finished Nov 22 02:19:45 PM PST 23
Peak memory 463076 kb
Host smart-a68079fb-bcd1-4724-83e9-420aeb89b454
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886192736770177515350450038191270460178305449043932
87414225897031206684264373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_tx.8861927367701775153504500381912704
6017830544904393287414225897031206684264373
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.69065795634556039805229777015382449334409024181695008605208551993331194946218
Short name T1471
Test name
Test status
Simulation time 825344371 ps
CPU time 2.52 seconds
Started Nov 22 02:18:35 PM PST 23
Finished Nov 22 02:18:38 PM PST 23
Peak memory 202992 kb
Host smart-2cca5da9-e726-4583-b96b-838089fafbc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690657956345560398052297770153824493344090241816950
08605208551993331194946218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_hrst.6906579563455603980522977701538244933440902418169500
8605208551993331194946218
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.64478944872698217118255709668337167929638902589651290880336403434643614028566
Short name T1511
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.38 seconds
Started Nov 22 02:18:49 PM PST 23
Finished Nov 22 02:18:54 PM PST 23
Peak memory 203660 kb
Host smart-44f97195-b7bf-4f13-b45b-91cb45395a1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64478944872698217118255709668337167929638902589651
290880336403434643614028566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_smoke.64478944872698217118255709668337167929638902
589651290880336403434643614028566
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.44434541303578671059554523654850934970235502776801155156550033777704912874875
Short name T270
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.79 seconds
Started Nov 22 02:18:54 PM PST 23
Finished Nov 22 02:19:17 PM PST 23
Peak memory 639176 kb
Host smart-27954c94-0605-407e-ad0d-200792657d90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44434541303578671059554523654850934970
235502776801155156550033777704912874875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.444345413035786710595545
23654850934970235502776801155156550033777704912874875
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.98832483236141719131956279285206235475789353703802052511827809825444545423614
Short name T1242
Test name
Test status
Simulation time 834576440 ps
CPU time 2.91 seconds
Started Nov 22 02:18:39 PM PST 23
Finished Nov 22 02:18:43 PM PST 23
Peak memory 202964 kb
Host smart-14a02615-23d4-4244-a203-215fe413358e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988324832361417191319562792852062354757893537038020
52511827809825444545423614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_perf.9883248323614171913195627928520623547578935370380205
2511827809825444545423614
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.70153526990254673055188507321152447190722016140403712199586795924430536552253
Short name T1545
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.83 seconds
Started Nov 22 02:18:34 PM PST 23
Finished Nov 22 02:18:45 PM PST 23
Peak memory 203048 kb
Host smart-0ed3dd90-85c6-4159-aef5-73b3d7012dd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7015352699025467305518850732115244719072201614040371219958679592443053
6552253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smoke.70153526990254673055188507321152447190722016140403712199586795924430536552253
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.86720847148071395799997890656793009027799929566540944285871048909814951761646
Short name T1314
Test name
Test status
Simulation time 66540157934 ps
CPU time 1233.24 seconds
Started Nov 22 02:18:43 PM PST 23
Finished Nov 22 02:39:17 PM PST 23
Peak memory 6983528 kb
Host smart-9263091f-0119-47a0-bf73-2bf717328212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86720847148071395799997890656793009027799929566540
944285871048909814951761646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_all.867208471480713957999978906567930090277
99929566540944285871048909814951761646
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.50916551735228394091046149775482021005713639735357188986329431734505979190468
Short name T273
Test name
Test status
Simulation time 997771563 ps
CPU time 8.71 seconds
Started Nov 22 02:19:08 PM PST 23
Finished Nov 22 02:19:17 PM PST 23
Peak memory 203152 kb
Host smart-063424ca-ca81-41e9-97ab-9e872d1932ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5091655173522839409104614977548202100571363973535718898632943173450597
9190468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_rd.5091655173522839409104614977548202100571363973535718898632943
1734505979190468
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.98743247938839657289085710285916768349915422270161835966016059074946578904167
Short name T1536
Test name
Test status
Simulation time 14461449567 ps
CPU time 78.28 seconds
Started Nov 22 02:18:48 PM PST 23
Finished Nov 22 02:20:07 PM PST 23
Peak memory 1541728 kb
Host smart-d7ac455c-6ecd-4684-bf22-0458ababf3b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9874324793883965728908571028591676834991542227016183596601605907494657
8904167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_wr.9874324793883965728908571028591676834991542227016183596601605
9074946578904167
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.36819912340009840145985267512630263731586604422386412244654014639177674655280
Short name T667
Test name
Test status
Simulation time 6281818576 ps
CPU time 68.77 seconds
Started Nov 22 02:18:49 PM PST 23
Finished Nov 22 02:19:58 PM PST 23
Peak memory 930428 kb
Host smart-6f7752df-7c7f-463c-a6cf-395c2cd90ffb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681991234000984014598526751263026373158660442238641224465401463917767
4655280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stretch.36819912340009840145985267512630263731586604422386412244654014639177674655280
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.96232940922564763205585094857104828171812086340530005843967795523717940064014
Short name T1544
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.24 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:19:18 PM PST 23
Peak memory 212520 kb
Host smart-2e98f634-5b28-49e2-b7d0-13875e9fe486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962329409225647632055850948571048281718120863405300
05843967795523717940064014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_timeout.9623294092256476320558509485710482817181208634
0530005843967795523717940064014
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_ovf.94869738935207514977870250893172094284416934333201302709098204092542325899647
Short name T1566
Test name
Test status
Simulation time 5445414553 ps
CPU time 130.89 seconds
Started Nov 22 02:18:36 PM PST 23
Finished Nov 22 02:20:47 PM PST 23
Peak memory 406800 kb
Host smart-073e4e57-6ef7-4e0d-a003-ddd8b945f90b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94869738935207514977870250893172094284416934333201
302709098204092542325899647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_tx_ovf.94869738935207514977870250893172094284416934333
201302709098204092542325899647
Directory /workspace/5.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.71683926354217904698999254880171596008535785016670700161536941294905751152961
Short name T629
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.32 seconds
Started Nov 22 02:19:05 PM PST 23
Finished Nov 22 02:19:11 PM PST 23
Peak memory 205384 kb
Host smart-84c2e78c-5c45-45d8-a353-cb894d0bafd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716839263542179046989992548801715960085357850166707
00161536941294905751152961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_unexp_stop.716839263542179046989992548801715960085357
85016670700161536941294905751152961
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.39725065019337538081042538727600043961135042989535694097709202101255531350054
Short name T1173
Test name
Test status
Simulation time 19975830 ps
CPU time 0.64 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:19:12 PM PST 23
Peak memory 202788 kb
Host smart-d67f036e-6228-499a-bed9-a11d6ffec4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725065019337538081042538727600043961135042989535694097709202101255531350054 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_alert_test.39725065019337538081042538727600043961135042989535694097709202101255531350054
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.40634871893636358886612346935327377335877307563683106441955177500968601657241
Short name T1266
Test name
Test status
Simulation time 74225396 ps
CPU time 1.3 seconds
Started Nov 22 02:18:54 PM PST 23
Finished Nov 22 02:18:56 PM PST 23
Peak memory 211208 kb
Host smart-40a6b1d0-abf2-4334-a6a3-8f44b4d00014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40634871893636358886612346935327377335877307563683106441955177500968601657241 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_host_error_intr.40634871893636358886612346935327377335877307563683106441955177500968601657241
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.64007574640356631113549832695829625162588468870470482828659701202332551328111
Short name T1379
Test name
Test status
Simulation time 606667565 ps
CPU time 6.71 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:19:18 PM PST 23
Peak memory 273440 kb
Host smart-c9e99743-c7c3-4542-91cc-a53351ed1186
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64007574640356631113549832695829625162588468870470482828659701202332551328111 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.64007574640356631113549832695829625162588468870470482828659701202332551328111
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.113465999992773535931592093338441800308793043144138019464546349386426392895410
Short name T698
Test name
Test status
Simulation time 3768267272 ps
CPU time 70.52 seconds
Started Nov 22 02:18:47 PM PST 23
Finished Nov 22 02:19:58 PM PST 23
Peak memory 729280 kb
Host smart-d4de6d61-4c7f-48b2-af82-99628ab9f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113465999992773535931592093338441800308793043144138019464546349386426392895410 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_host_fifo_full.113465999992773535931592093338441800308793043144138019464546349386426392895410
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.105348857117958870117022513669350185807448408234597301769873575209492311253611
Short name T827
Test name
Test status
Simulation time 7925734012 ps
CPU time 218.64 seconds
Started Nov 22 02:18:46 PM PST 23
Finished Nov 22 02:22:26 PM PST 23
Peak memory 1271380 kb
Host smart-690abb7f-0dfc-413e-965e-8c1ff37d7c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105348857117958870117022513669350185807448408234597301769873575209492311253611 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_host_fifo_overflow.105348857117958870117022513669350185807448408234597301769873575209492311253611
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.88409213255064211352493834207376369121272178162492297282723696348142945542126
Short name T975
Test name
Test status
Simulation time 209010032 ps
CPU time 0.95 seconds
Started Nov 22 02:18:48 PM PST 23
Finished Nov 22 02:18:50 PM PST 23
Peak memory 202960 kb
Host smart-4dcf6407-8e47-4bbd-9b76-146d71d4a1f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88409213255064211352493834207376369121272178162492297282723696348142945542126 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.88409213255064211352493834207376369121272178162492297282723696348142945542126
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.15165716745364113861588254061794880083970890130983424681394472012316910245430
Short name T858
Test name
Test status
Simulation time 236313385 ps
CPU time 3.61 seconds
Started Nov 22 02:18:42 PM PST 23
Finished Nov 22 02:18:47 PM PST 23
Peak memory 225416 kb
Host smart-64749f4e-76b5-4f36-8a9a-03e1917af9d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15165716745364113861588254061794880083970890130983424681394472012316910245430 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.15165716745364113861588254061794880083970890130983424681394472012316910245430
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.25984060676703743186107595682640689077503254636490870980917048307587939363539
Short name T1422
Test name
Test status
Simulation time 7918519784 ps
CPU time 214.92 seconds
Started Nov 22 02:18:44 PM PST 23
Finished Nov 22 02:22:19 PM PST 23
Peak memory 1310932 kb
Host smart-18b29722-437a-4491-bd2e-78c7a4b8a3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25984060676703743186107595682640689077503254636490870980917048307587939363539 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_host_fifo_watermark.25984060676703743186107595682640689077503254636490870980917048307587939363539
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.74263123575162835139985404328706977717902054673071352892837170547969710920968
Short name T59
Test name
Test status
Simulation time 3754070957 ps
CPU time 54.11 seconds
Started Nov 22 02:18:44 PM PST 23
Finished Nov 22 02:19:39 PM PST 23
Peak memory 293624 kb
Host smart-e9279c11-f482-4716-9e45-22403c3eee1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74263123575162835139985404328706977717902054673071352892837170547969710920968 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_host_mode_toggle.74263123575162835139985404328706977717902054673071352892837170547969710920968
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.87043752366557198696132368307610183253220171552917301651596096875444762352256
Short name T1433
Test name
Test status
Simulation time 23672229 ps
CPU time 0.64 seconds
Started Nov 22 02:18:37 PM PST 23
Finished Nov 22 02:18:38 PM PST 23
Peak memory 202812 kb
Host smart-f453a321-8e67-4e19-a76b-c29fa015e117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87043752366557198696132368307610183253220171552917301651596096875444762352256 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_host_override.87043752366557198696132368307610183253220171552917301651596096875444762352256
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.43123657379551283015591049042220119425922019436821300054927901885536750433737
Short name T1195
Test name
Test status
Simulation time 6830796343 ps
CPU time 61.45 seconds
Started Nov 22 02:18:49 PM PST 23
Finished Nov 22 02:19:51 PM PST 23
Peak memory 211364 kb
Host smart-9d6ca27e-00eb-4a13-a5ba-37eaeb288a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43123657379551283015591049042220119425922019436821300054927901885536750433737 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.i2c_host_perf.43123657379551283015591049042220119425922019436821300054927901885536750433737
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_rx_oversample.72909150373886254186485579272590684689972348236914442844178765082864599568463
Short name T1364
Test name
Test status
Simulation time 3939158762 ps
CPU time 89.01 seconds
Started Nov 22 02:18:47 PM PST 23
Finished Nov 22 02:20:17 PM PST 23
Peak memory 345752 kb
Host smart-96dd2afc-7c7c-433e-8396-0e8294a47c7e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72909150373886254186485579272590684689972348236914442844178765082864599568463 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_rx_oversample.72909150373886254186485579272590684689972348236914442844178765082864599568463
Directory /workspace/6.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.53669081221773378277892032312093853652025427155041368579075442712628105993057
Short name T202
Test name
Test status
Simulation time 2343171530 ps
CPU time 35.87 seconds
Started Nov 22 02:18:39 PM PST 23
Finished Nov 22 02:19:15 PM PST 23
Peak memory 299308 kb
Host smart-dde0f55b-751e-4bce-a52d-c7696c2931b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53669081221773378277892032312093853652025427155041368579075442712628105993057 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.i2c_host_smoke.53669081221773378277892032312093853652025427155041368579075442712628105993057
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.24427687672945491827801660092747882323671385781678567547030775443275749406975
Short name T500
Test name
Test status
Simulation time 32807463528 ps
CPU time 941.74 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:34:52 PM PST 23
Peak memory 1956664 kb
Host smart-f1cc0472-47e4-4675-8438-bdf6fbe0ee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24427687672945491827801660092747882323671385781678567547030775443275749406975 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_host_stress_all.24427687672945491827801660092747882323671385781678567547030775443275749406975
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.52871684846625216823072314281418438805870560875319433756066546571856460049749
Short name T162
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.46 seconds
Started Nov 22 02:18:44 PM PST 23
Finished Nov 22 02:18:58 PM PST 23
Peak memory 214040 kb
Host smart-2d632bd1-a8f6-43e8-97d0-6ac1b762b38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52871684846625216823072314281418438805870560875319433756066546571856460049749 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_host_stretch_timeout.52871684846625216823072314281418438805870560875319433756066546571856460049749
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.50838511145929412628336615768516867633104336620630052930511228656070303875873
Short name T714
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.73 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:19:14 PM PST 23
Peak memory 202724 kb
Host smart-8af064e0-8723-47f8-9196-3d46f89647d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5083851114592941262833661576851
6867633104336620630052930511228656070303875873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.508385111459294126283366157
68516867633104336620630052930511228656070303875873
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.18465811167150158057547040954710632079940816969080552516364399105295570048604
Short name T953
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.32 seconds
Started Nov 22 02:18:38 PM PST 23
Finished Nov 22 02:19:10 PM PST 23
Peak memory 382148 kb
Host smart-73b43663-7a9d-4bc4-a405-d95aa271770a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184658111671501580575470409547106320799408169690805
52516364399105295570048604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.18465811167150158057547040954710
632079940816969080552516364399105295570048604
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.9682334086190432829015801619299770347588145036224114814744290115875854077280
Short name T280
Test name
Test status
Simulation time 10065199023 ps
CPU time 39.06 seconds
Started Nov 22 02:18:50 PM PST 23
Finished Nov 22 02:19:30 PM PST 23
Peak memory 463196 kb
Host smart-2eca0c3a-9bd1-471a-a0cc-3c8fed828368
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968233408619043282901580161929977034758814503622411
4814744290115875854077280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_tx.96823340861904328290158016192997703
47588145036224114814744290115875854077280
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.900757303451104539038941723532453704030787959381471942102055941361928617771
Short name T1128
Test name
Test status
Simulation time 825344371 ps
CPU time 2.49 seconds
Started Nov 22 02:19:08 PM PST 23
Finished Nov 22 02:19:11 PM PST 23
Peak memory 203040 kb
Host smart-1811f500-4ddb-45d6-8b35-a85767f1bcc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900757303451104539038941723532453704030787959381471
942102055941361928617771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_hrst.900757303451104539038941723532453704030787959381471942
102055941361928617771
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.51959287003235359921500271750177022006623928990813196703695277023318239904295
Short name T367
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.31 seconds
Started Nov 22 02:18:49 PM PST 23
Finished Nov 22 02:18:54 PM PST 23
Peak memory 203624 kb
Host smart-96b0650b-c1db-4af8-9c7b-0e509bee7db3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51959287003235359921500271750177022006623928990813
196703695277023318239904295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_smoke.51959287003235359921500271750177022006623928
990813196703695277023318239904295
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.112551053738186988541172686522564934583876698426146493779476338910438530230456
Short name T883
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.71 seconds
Started Nov 22 02:18:47 PM PST 23
Finished Nov 22 02:19:11 PM PST 23
Peak memory 639052 kb
Host smart-a720b0be-cc93-47c8-8f00-e891b18a96cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11255105373818698854117268652256493458
3876698426146493779476338910438530230456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.11255105373818698854117
2686522564934583876698426146493779476338910438530230456
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.42877834055798672187106757195916243001227135593909351583125203320770494051401
Short name T217
Test name
Test status
Simulation time 834576440 ps
CPU time 2.89 seconds
Started Nov 22 02:19:08 PM PST 23
Finished Nov 22 02:19:12 PM PST 23
Peak memory 202996 kb
Host smart-b4504b08-a11f-44de-8d3e-6e66579699e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428778340557986721871067571959162430012271355939093
51583125203320770494051401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_perf.4287783405579867218710675719591624300122713559390935
1583125203320770494051401
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.37199455053518164958206863574392014079193926755942963758911862282336980083501
Short name T247
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.58 seconds
Started Nov 22 02:18:43 PM PST 23
Finished Nov 22 02:18:53 PM PST 23
Peak memory 202988 kb
Host smart-fcbb9212-a2a8-4d16-b53a-5f9fd99ae52b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719945505351816495820686357439201407919392675594296375891186228233698
0083501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smoke.37199455053518164958206863574392014079193926755942963758911862282336980083501
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.94267494741514341686115848437204610513418584240658352860797882386986698867395
Short name T1330
Test name
Test status
Simulation time 66540157934 ps
CPU time 1530.2 seconds
Started Nov 22 02:18:54 PM PST 23
Finished Nov 22 02:44:25 PM PST 23
Peak memory 6983536 kb
Host smart-32a852ac-9e50-44d9-93ea-c7470934209b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94267494741514341686115848437204610513418584240658
352860797882386986698867395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_all.942674947415143416861158484372046105134
18584240658352860797882386986698867395
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.46582260953415392837525207830251384861290170070588078292110436197460901566326
Short name T1317
Test name
Test status
Simulation time 997771563 ps
CPU time 8.91 seconds
Started Nov 22 02:18:38 PM PST 23
Finished Nov 22 02:18:48 PM PST 23
Peak memory 202992 kb
Host smart-20d025d2-2de9-4732-bbce-20a365d19f9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4658226095341539283752520783025138486129017007058807829211043619746090
1566326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_rd.4658226095341539283752520783025138486129017007058807829211043
6197460901566326
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.65444877403032986274273197644712993137209297614019107600377784967064603343218
Short name T1430
Test name
Test status
Simulation time 14461449567 ps
CPU time 81.04 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:20:31 PM PST 23
Peak memory 1542100 kb
Host smart-d5a2c8bb-fc56-431d-a24e-4616721c9080
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6544487740303298627427319764471299313720929761401910760037778496706460
3343218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_wr.6544487740303298627427319764471299313720929761401910760037778
4967064603343218
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.107406670346328012346317618736046400502134758910843774988358723419274536893983
Short name T1486
Test name
Test status
Simulation time 6281818576 ps
CPU time 74.64 seconds
Started Nov 22 02:18:34 PM PST 23
Finished Nov 22 02:19:49 PM PST 23
Peak memory 930548 kb
Host smart-230b1315-e800-4914-b82c-a531879d32f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074066703463280123463176187360464005021347589108437749883587234192745
36893983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stretch.1074066703463280123463176187360464005021347589108437749883587234
19274536893983
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.21871169207856789501403814355003034279157934069989436640738825007472786993850
Short name T1535
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.3 seconds
Started Nov 22 02:18:49 PM PST 23
Finished Nov 22 02:18:57 PM PST 23
Peak memory 212628 kb
Host smart-f6cded9f-3035-43da-acb9-e5fdd622bb1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218711692078567895014038143550030342791579340699894
36640738825007472786993850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_timeout.2187116920785678950140381435500303427915793406
9989436640738825007472786993850
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_ovf.58999495402597323599018964400795067880255099539406614019976742997852680706422
Short name T708
Test name
Test status
Simulation time 5445414553 ps
CPU time 129.5 seconds
Started Nov 22 02:18:49 PM PST 23
Finished Nov 22 02:20:59 PM PST 23
Peak memory 406776 kb
Host smart-941a0625-d015-40ec-89c5-e914710f1e1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58999495402597323599018964400795067880255099539406
614019976742997852680706422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_tx_ovf.58999495402597323599018964400795067880255099539
406614019976742997852680706422
Directory /workspace/6.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.57521074746336845676397703258729958181993409138721154654639002885753371552567
Short name T290
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.8 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:19:17 PM PST 23
Peak memory 205344 kb
Host smart-7cd6538b-3f4b-42df-b49b-778ab9051ec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575210747463368456763977032587299581819934091387211
54654639002885753371552567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_unexp_stop.575210747463368456763977032587299581819934
09138721154654639002885753371552567
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.34887947680225899331558725163884900882942665085190024379153592941976550222589
Short name T618
Test name
Test status
Simulation time 19975830 ps
CPU time 0.59 seconds
Started Nov 22 02:19:15 PM PST 23
Finished Nov 22 02:19:17 PM PST 23
Peak memory 202860 kb
Host smart-a50db770-a7c9-4aa4-93d8-b1f5878c8f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34887947680225899331558725163884900882942665085190024379153592941976550222589 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_alert_test.34887947680225899331558725163884900882942665085190024379153592941976550222589
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.111564617354775262948012980310204902084333820135352209190148562751374985021106
Short name T930
Test name
Test status
Simulation time 74225396 ps
CPU time 1.31 seconds
Started Nov 22 02:18:54 PM PST 23
Finished Nov 22 02:18:56 PM PST 23
Peak memory 211208 kb
Host smart-c06e4fbf-a61a-458f-8ee7-196fac42608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111564617354775262948012980310204902084333820135352209190148562751374985021106 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_host_error_intr.111564617354775262948012980310204902084333820135352209190148562751374985021106
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.15090704713118215848157944548305756738539963818356981279819987601832288590815
Short name T1072
Test name
Test status
Simulation time 606667565 ps
CPU time 6.82 seconds
Started Nov 22 02:19:06 PM PST 23
Finished Nov 22 02:19:14 PM PST 23
Peak memory 273420 kb
Host smart-d37eee66-6341-42f7-8993-c204f401a7f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15090704713118215848157944548305756738539963818356981279819987601832288590815 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.15090704713118215848157944548305756738539963818356981279819987601832288590815
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.16250682124143551910926748703922172892769710091465246518418138824772998409537
Short name T478
Test name
Test status
Simulation time 3768267272 ps
CPU time 72.59 seconds
Started Nov 22 02:19:09 PM PST 23
Finished Nov 22 02:20:22 PM PST 23
Peak memory 729404 kb
Host smart-dee42f7f-496d-40de-a857-0dbbae8f0399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16250682124143551910926748703922172892769710091465246518418138824772998409537 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_host_fifo_full.16250682124143551910926748703922172892769710091465246518418138824772998409537
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.56606587667769565502619999708821014396144425922944213668934218156769301012211
Short name T1086
Test name
Test status
Simulation time 7925734012 ps
CPU time 235.63 seconds
Started Nov 22 02:18:44 PM PST 23
Finished Nov 22 02:22:40 PM PST 23
Peak memory 1271376 kb
Host smart-8e3cf857-007b-4a98-a26b-7451c3dae9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56606587667769565502619999708821014396144425922944213668934218156769301012211 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.i2c_host_fifo_overflow.56606587667769565502619999708821014396144425922944213668934218156769301012211
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.24227339635099937828824047590872791122631881692903465110742333701974890804307
Short name T1375
Test name
Test status
Simulation time 209010032 ps
CPU time 0.92 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:19:13 PM PST 23
Peak memory 202960 kb
Host smart-89091562-652d-41b2-bff7-2a6927bd8386
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24227339635099937828824047590872791122631881692903465110742333701974890804307 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.24227339635099937828824047590872791122631881692903465110742333701974890804307
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.60761257773507444456532162079119808129114895598922010764373553371437996802592
Short name T695
Test name
Test status
Simulation time 236313385 ps
CPU time 3.82 seconds
Started Nov 22 02:18:54 PM PST 23
Finished Nov 22 02:18:59 PM PST 23
Peak memory 225424 kb
Host smart-4214b63d-127b-45e1-9631-aeb8dc2ef146
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60761257773507444456532162079119808129114895598922010764373553371437996802592 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.60761257773507444456532162079119808129114895598922010764373553371437996802592
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.61760305040116632724931390601127455062451211422573418266461838268778618667578
Short name T585
Test name
Test status
Simulation time 7918519784 ps
CPU time 201.65 seconds
Started Nov 22 02:19:12 PM PST 23
Finished Nov 22 02:22:34 PM PST 23
Peak memory 1311032 kb
Host smart-86c55fb2-3e50-456e-ac7f-c2bcb3fed896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61760305040116632724931390601127455062451211422573418266461838268778618667578 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.i2c_host_fifo_watermark.61760305040116632724931390601127455062451211422573418266461838268778618667578
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.26317140821370113800756228834347535000021810205570926196206520945077456986265
Short name T1095
Test name
Test status
Simulation time 3754070957 ps
CPU time 54.81 seconds
Started Nov 22 02:19:09 PM PST 23
Finished Nov 22 02:20:04 PM PST 23
Peak memory 293852 kb
Host smart-5432e323-7b52-4d3f-b8c0-69715fb1e1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26317140821370113800756228834347535000021810205570926196206520945077456986265 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_host_mode_toggle.26317140821370113800756228834347535000021810205570926196206520945077456986265
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.99839821256617673100497515227047547271284003437472664047772095305978964040850
Short name T10
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:19:05 PM PST 23
Finished Nov 22 02:19:07 PM PST 23
Peak memory 202820 kb
Host smart-8d74dd93-7933-4e17-bf64-eb82457bd48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99839821256617673100497515227047547271284003437472664047772095305978964040850 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_host_override.99839821256617673100497515227047547271284003437472664047772095305978964040850
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.22687336295264716076805359459588384198719234252545994755563871407436103895392
Short name T1201
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.58 seconds
Started Nov 22 02:19:08 PM PST 23
Finished Nov 22 02:20:09 PM PST 23
Peak memory 211176 kb
Host smart-1675b9ea-d95f-4ac4-a000-dd41f611c844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22687336295264716076805359459588384198719234252545994755563871407436103895392 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.i2c_host_perf.22687336295264716076805359459588384198719234252545994755563871407436103895392
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_rx_oversample.31243937170568768233271441265393137721590500018083727288379305242836343242713
Short name T1519
Test name
Test status
Simulation time 3939158762 ps
CPU time 118.21 seconds
Started Nov 22 02:19:06 PM PST 23
Finished Nov 22 02:21:05 PM PST 23
Peak memory 345980 kb
Host smart-c1f75e65-e400-4382-9190-0a1197caec7e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31243937170568768233271441265393137721590500018083727288379305242836343242713 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_rx_oversample.31243937170568768233271441265393137721590500018083727288379305242836343242713
Directory /workspace/7.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.36073239463925276043222725786681959901864133461162245024460100869474948949690
Short name T443
Test name
Test status
Simulation time 2343171530 ps
CPU time 38.71 seconds
Started Nov 22 02:19:13 PM PST 23
Finished Nov 22 02:19:52 PM PST 23
Peak memory 299124 kb
Host smart-96df0b1b-a81d-44ac-aa99-5a58431a89d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36073239463925276043222725786681959901864133461162245024460100869474948949690 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.i2c_host_smoke.36073239463925276043222725786681959901864133461162245024460100869474948949690
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.41339112825830704562797779933134799683876270218515768138798469905701374835962
Short name T1581
Test name
Test status
Simulation time 32807463528 ps
CPU time 991.79 seconds
Started Nov 22 02:18:44 PM PST 23
Finished Nov 22 02:35:17 PM PST 23
Peak memory 1956952 kb
Host smart-74652843-b1d8-4bb0-88dc-deba9a5b931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41339112825830704562797779933134799683876270218515768138798469905701374835962 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_host_stress_all.41339112825830704562797779933134799683876270218515768138798469905701374835962
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2437175466692754079796785658472088351999525925531934046562891152054646349175
Short name T153
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.34 seconds
Started Nov 22 02:19:09 PM PST 23
Finished Nov 22 02:19:24 PM PST 23
Peak memory 214040 kb
Host smart-7d6f28d5-0113-4615-8fb2-e92cda171e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437175466692754079796785658472088351999525925531934046562891152054646349175 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.i2c_host_stretch_timeout.2437175466692754079796785658472088351999525925531934046562891152054646349175
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.13818517868830233751649338016855160169586995423072503587908920385404643969962
Short name T409
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.74 seconds
Started Nov 22 02:18:49 PM PST 23
Finished Nov 22 02:18:54 PM PST 23
Peak memory 203068 kb
Host smart-026fd284-800d-4d4f-a750-f56f64e739f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381851786883023375164933801685
5160169586995423072503587908920385404643969962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.138185178688302337516493380
16855160169586995423072503587908920385404643969962
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.24110635699186862686574801868395923886513080265717593226998325795123085978737
Short name T580
Test name
Test status
Simulation time 10166144644 ps
CPU time 31.13 seconds
Started Nov 22 02:18:50 PM PST 23
Finished Nov 22 02:19:22 PM PST 23
Peak memory 382084 kb
Host smart-fe9a26d1-734d-47e4-9126-4e598c05ebd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241106356991868626865748018683959238865130802657175
93226998325795123085978737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.24110635699186862686574801868395
923886513080265717593226998325795123085978737
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.43213183929603298752921355791371069333994714017998248136168522387520930102208
Short name T480
Test name
Test status
Simulation time 10065199023 ps
CPU time 38.48 seconds
Started Nov 22 02:19:36 PM PST 23
Finished Nov 22 02:20:16 PM PST 23
Peak memory 463148 kb
Host smart-ce9ebf3e-d5ad-427b-badd-801bd446816c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432131839296032987529213557913710693339947140179982
48136168522387520930102208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_tx.4321318392960329875292135579137106
9333994714017998248136168522387520930102208
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.184690207068693999060682697221170090188910487178618062598601283031441146632
Short name T1037
Test name
Test status
Simulation time 825344371 ps
CPU time 2.46 seconds
Started Nov 22 02:19:09 PM PST 23
Finished Nov 22 02:19:12 PM PST 23
Peak memory 203008 kb
Host smart-062ce0ea-a2be-4eab-af3e-f6201b79cf77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184690207068693999060682697221170090188910487178618
062598601283031441146632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_hrst.184690207068693999060682697221170090188910487178618062
598601283031441146632
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.100767737727507985603842319008630784125562850142356936997621887354167590341479
Short name T591
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.14 seconds
Started Nov 22 02:18:53 PM PST 23
Finished Nov 22 02:18:58 PM PST 23
Peak memory 203664 kb
Host smart-5b70c5f0-a9ac-44f7-92cc-11614315f11f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10076773772750798560384231900863078412556285014235
6936997621887354167590341479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_smoke.1007677377275079856038423190086307841255628
50142356936997621887354167590341479
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.46178509050396065215014572015933914001505312346025178695045241769494415402246
Short name T1487
Test name
Test status
Simulation time 5106060125 ps
CPU time 21.5 seconds
Started Nov 22 02:19:12 PM PST 23
Finished Nov 22 02:19:35 PM PST 23
Peak memory 639264 kb
Host smart-ab2652d6-e5e7-4e12-bdb9-85799c65907a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46178509050396065215014572015933914001
505312346025178695045241769494415402246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.461785090503960652150145
72015933914001505312346025178695045241769494415402246
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.82303548038917110535867081173685558151111985588700118150433684152024434085906
Short name T937
Test name
Test status
Simulation time 834576440 ps
CPU time 3.06 seconds
Started Nov 22 02:18:49 PM PST 23
Finished Nov 22 02:18:53 PM PST 23
Peak memory 203040 kb
Host smart-09a1b6e8-a11f-4fcf-bdfa-d4a766939a28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823035480389171105358670811736855581511119855887001
18150433684152024434085906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_perf.8230354803891711053586708117368555815111198558870011
8150433684152024434085906
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.63187357941575846375458022192830311639524554079015755610901088889803195245019
Short name T909
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.61 seconds
Started Nov 22 02:19:08 PM PST 23
Finished Nov 22 02:19:19 PM PST 23
Peak memory 202948 kb
Host smart-1fd5949f-cdbd-4fa4-b958-80d262fda899
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6318735794157584637545802219283031163952455407901575561090108888980319
5245019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smoke.63187357941575846375458022192830311639524554079015755610901088889803195245019
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.101053314976945589815783658689568095240023731982706525866621159940428243351308
Short name T887
Test name
Test status
Simulation time 66540157934 ps
CPU time 1660.12 seconds
Started Nov 22 02:19:34 PM PST 23
Finished Nov 22 02:47:15 PM PST 23
Peak memory 6983752 kb
Host smart-537f5b41-bca5-42fb-8264-8a0c4b7c2084
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10105331497694558981578365868956809524002373198270
6525866621159940428243351308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_all.10105331497694558981578365868956809524
0023731982706525866621159940428243351308
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.98045477836874684655456976277517999650688382777364907107618162455855248744794
Short name T515
Test name
Test status
Simulation time 997771563 ps
CPU time 8.37 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:19:19 PM PST 23
Peak memory 202888 kb
Host smart-a7c84cfd-f382-48a1-8c55-4ba36c080694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9804547783687468465545697627751799965068838277736490710761816245585524
8744794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_rd.9804547783687468465545697627751799965068838277736490710761816
2455855248744794
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.96540177809808579339994117499589666322591984265014457107049150129401374115958
Short name T1443
Test name
Test status
Simulation time 14461449567 ps
CPU time 91.92 seconds
Started Nov 22 02:18:54 PM PST 23
Finished Nov 22 02:20:27 PM PST 23
Peak memory 1542052 kb
Host smart-869e3be7-be38-47c7-af56-901c02b86612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9654017780980857933999411749958966632259198426501445710704915012940137
4115958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_wr.9654017780980857933999411749958966632259198426501445710704915
0129401374115958
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.104783849548351309342553012972692148982579623653555042450657234339159750628191
Short name T552
Test name
Test status
Simulation time 6281818576 ps
CPU time 77.49 seconds
Started Nov 22 02:18:54 PM PST 23
Finished Nov 22 02:20:12 PM PST 23
Peak memory 930536 kb
Host smart-0c669517-c56d-45f7-85dc-b3104964d30d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047838495483513093425530129726921489825796236535550424506572343391597
50628191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stretch.1047838495483513093425530129726921489825796236535550424506572343
39159750628191
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.61591433035140458501063807861064821363696603430475510251523018485803163655105
Short name T1311
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.5 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:19:19 PM PST 23
Peak memory 212656 kb
Host smart-40a374a5-ab18-4332-a065-3b4afcbf19d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615914330351404585010638078610648213636966034304755
10251523018485803163655105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_timeout.6159143303514045850106380786106482136369660343
0475510251523018485803163655105
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_ovf.101877739832727310652686479368619435157316721903582786969571901577753636844249
Short name T1020
Test name
Test status
Simulation time 5445414553 ps
CPU time 129.1 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:21:21 PM PST 23
Peak memory 406852 kb
Host smart-0d3d40ff-74ce-473e-8cdd-a147ea1b948f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187773983272731065268647936861943515731672190358
2786969571901577753636844249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_tx_ovf.1018777398327273106526864793686194351573167219
03582786969571901577753636844249
Directory /workspace/7.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.80063783969866502983095889869905641181249261297719543446620825154830754487081
Short name T150
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.47 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:19:17 PM PST 23
Peak memory 205280 kb
Host smart-c1400df7-cdec-4a9b-b3fb-91f8cbdc0e83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800637839698665029830958898699056411812492612977195
43446620825154830754487081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_unexp_stop.800637839698665029830958898699056411812492
61297719543446620825154830754487081
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.11307227440145226529514629279174842007297713524055217850917816723746956049448
Short name T161
Test name
Test status
Simulation time 19975830 ps
CPU time 0.6 seconds
Started Nov 22 02:19:13 PM PST 23
Finished Nov 22 02:19:15 PM PST 23
Peak memory 202508 kb
Host smart-6495a61a-24c4-42fb-82d1-adaacc00b60d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307227440145226529514629279174842007297713524055217850917816723746956049448 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_alert_test.11307227440145226529514629279174842007297713524055217850917816723746956049448
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.102812283635664601577676251001171938781509932537539972766464564023530597384405
Short name T1104
Test name
Test status
Simulation time 74225396 ps
CPU time 1.32 seconds
Started Nov 22 02:19:19 PM PST 23
Finished Nov 22 02:19:22 PM PST 23
Peak memory 211356 kb
Host smart-713ddcf4-466f-422f-aa33-7f7eb7dfeca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102812283635664601577676251001171938781509932537539972766464564023530597384405 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_host_error_intr.102812283635664601577676251001171938781509932537539972766464564023530597384405
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.78589145480017854278901538807494611729683790437859155667433095836635669035236
Short name T605
Test name
Test status
Simulation time 606667565 ps
CPU time 6.88 seconds
Started Nov 22 02:18:51 PM PST 23
Finished Nov 22 02:18:58 PM PST 23
Peak memory 273312 kb
Host smart-7958be95-ab00-4ab9-91f2-957dfe38a1c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78589145480017854278901538807494611729683790437859155667433095836635669035236 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.78589145480017854278901538807494611729683790437859155667433095836635669035236
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.114585995410692753373309588578553391810443319945230291044212867885736895227263
Short name T1491
Test name
Test status
Simulation time 3768267272 ps
CPU time 70.14 seconds
Started Nov 22 02:19:30 PM PST 23
Finished Nov 22 02:20:42 PM PST 23
Peak memory 729280 kb
Host smart-30300640-1588-4ffa-84f4-b7f504bce958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114585995410692753373309588578553391810443319945230291044212867885736895227263 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_host_fifo_full.114585995410692753373309588578553391810443319945230291044212867885736895227263
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.111803227748488465943250396154709435547757606753648815145215026989908107471694
Short name T17
Test name
Test status
Simulation time 7925734012 ps
CPU time 217.19 seconds
Started Nov 22 02:19:16 PM PST 23
Finished Nov 22 02:22:54 PM PST 23
Peak memory 1271592 kb
Host smart-328dbde4-dce0-497d-bfa5-6c315ae23435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111803227748488465943250396154709435547757606753648815145215026989908107471694 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.i2c_host_fifo_overflow.111803227748488465943250396154709435547757606753648815145215026989908107471694
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.18587663040864316627357999774542906880168616694748309749194311311645450731388
Short name T1439
Test name
Test status
Simulation time 209010032 ps
CPU time 0.94 seconds
Started Nov 22 02:19:33 PM PST 23
Finished Nov 22 02:19:34 PM PST 23
Peak memory 203040 kb
Host smart-6743dbda-053e-4518-ac4e-ae4e65edc9b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18587663040864316627357999774542906880168616694748309749194311311645450731388 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.18587663040864316627357999774542906880168616694748309749194311311645450731388
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.111370186451008267858239965734312125063967653285287002059923853844101175960460
Short name T1146
Test name
Test status
Simulation time 236313385 ps
CPU time 3.81 seconds
Started Nov 22 02:19:19 PM PST 23
Finished Nov 22 02:19:25 PM PST 23
Peak memory 225468 kb
Host smart-e090de56-e4bc-445e-ad94-855c4b0eff06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111370186451008267858239965734312125063967653285287002059923853844101175960460 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.111370186451008267858239965734312125063967653285287002059923853844101175960460
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.44172135312283687695707056701078242093848344249815261556871153015503949042354
Short name T910
Test name
Test status
Simulation time 7918519784 ps
CPU time 201.2 seconds
Started Nov 22 02:19:15 PM PST 23
Finished Nov 22 02:22:37 PM PST 23
Peak memory 1310708 kb
Host smart-cb5f1844-6b39-4d0a-8242-10ba77678d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44172135312283687695707056701078242093848344249815261556871153015503949042354 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.i2c_host_fifo_watermark.44172135312283687695707056701078242093848344249815261556871153015503949042354
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.48128977634226223671930816841623444417244769648673369229420989429866262294134
Short name T916
Test name
Test status
Simulation time 3754070957 ps
CPU time 58.89 seconds
Started Nov 22 02:19:15 PM PST 23
Finished Nov 22 02:20:15 PM PST 23
Peak memory 293900 kb
Host smart-a1d4b74a-119f-4dba-bce3-119a3254f931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48128977634226223671930816841623444417244769648673369229420989429866262294134 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_host_mode_toggle.48128977634226223671930816841623444417244769648673369229420989429866262294134
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.82437420282989004534537840613388441941040291279609521239425478353342073683515
Short name T1051
Test name
Test status
Simulation time 23672229 ps
CPU time 0.62 seconds
Started Nov 22 02:18:52 PM PST 23
Finished Nov 22 02:18:53 PM PST 23
Peak memory 202812 kb
Host smart-57186e4c-a8aa-4334-8826-1cc63dff2ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82437420282989004534537840613388441941040291279609521239425478353342073683515 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_host_override.82437420282989004534537840613388441941040291279609521239425478353342073683515
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.10660675004127193310468333807678151800610678923512282929728896964048633760758
Short name T397
Test name
Test status
Simulation time 6830796343 ps
CPU time 61.17 seconds
Started Nov 22 02:19:16 PM PST 23
Finished Nov 22 02:20:18 PM PST 23
Peak memory 211368 kb
Host smart-c270115a-5c0e-40d0-92a4-4dc9da481544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10660675004127193310468333807678151800610678923512282929728896964048633760758 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.i2c_host_perf.10660675004127193310468333807678151800610678923512282929728896964048633760758
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_rx_oversample.61559975762208312364571734331232709611680745419739235423283397156250056657665
Short name T718
Test name
Test status
Simulation time 3939158762 ps
CPU time 100.29 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:20:52 PM PST 23
Peak memory 345912 kb
Host smart-16051c77-a94d-485a-8787-cf053bb9f300
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61559975762208312364571734331232709611680745419739235423283397156250056657665 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_rx_oversample.61559975762208312364571734331232709611680745419739235423283397156250056657665
Directory /workspace/8.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.74193934629314109744534026998610892970487671269501797006690280539803549048978
Short name T437
Test name
Test status
Simulation time 2343171530 ps
CPU time 39.4 seconds
Started Nov 22 02:18:49 PM PST 23
Finished Nov 22 02:19:29 PM PST 23
Peak memory 299380 kb
Host smart-26225ce8-cbbf-4fe0-8b48-77c0c1805d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74193934629314109744534026998610892970487671269501797006690280539803549048978 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.i2c_host_smoke.74193934629314109744534026998610892970487671269501797006690280539803549048978
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.38837951612503703055980589510584960762158226609891751134238791500437047610455
Short name T1097
Test name
Test status
Simulation time 32807463528 ps
CPU time 983.21 seconds
Started Nov 22 02:19:28 PM PST 23
Finished Nov 22 02:35:54 PM PST 23
Peak memory 1957128 kb
Host smart-fff177dc-f04e-4c34-ba55-98f46e2cfdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38837951612503703055980589510584960762158226609891751134238791500437047610455 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_host_stress_all.38837951612503703055980589510584960762158226609891751134238791500437047610455
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.31587804281590431781328140412642965725163186642113584728978727940780747595199
Short name T742
Test name
Test status
Simulation time 1466624971 ps
CPU time 13.14 seconds
Started Nov 22 02:19:41 PM PST 23
Finished Nov 22 02:19:54 PM PST 23
Peak memory 214240 kb
Host smart-d4be5e1b-4c38-400d-83af-d728edf35ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31587804281590431781328140412642965725163186642113584728978727940780747595199 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_host_stretch_timeout.31587804281590431781328140412642965725163186642113584728978727940780747595199
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.15622202565691873644611653737713818363963896547378832598952863893177969548112
Short name T1078
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.9 seconds
Started Nov 22 02:19:33 PM PST 23
Finished Nov 22 02:19:38 PM PST 23
Peak memory 203064 kb
Host smart-44f3c83d-9990-470e-a37e-2bd11b42439f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562220256569187364461165373771
3818363963896547378832598952863893177969548112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.156222025656918736446116537
37713818363963896547378832598952863893177969548112
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.115346187955595705041907538664442084304294030046916759897786194273708319104920
Short name T173
Test name
Test status
Simulation time 10166144644 ps
CPU time 32.91 seconds
Started Nov 22 02:19:31 PM PST 23
Finished Nov 22 02:20:05 PM PST 23
Peak memory 382152 kb
Host smart-894bb1ca-84aa-42be-99f0-c553f7e2d3b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115346187955595705041907538664442084304294030046916
759897786194273708319104920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.1153461879555957050419075386644
42084304294030046916759897786194273708319104920
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.98301731279419595789225530912558723184123095961493915765439484330404182551949
Short name T428
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.14 seconds
Started Nov 22 02:19:13 PM PST 23
Finished Nov 22 02:19:48 PM PST 23
Peak memory 463064 kb
Host smart-6072b380-53a0-433d-a448-3aebae832f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983017312794195957892255309125587231841230959614939
15765439484330404182551949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_tx.9830173127941959578922553091255872
3184123095961493915765439484330404182551949
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.32981296052109803811806613589429554650973064797833737961727054533646943318221
Short name T1428
Test name
Test status
Simulation time 825344371 ps
CPU time 2.52 seconds
Started Nov 22 02:19:35 PM PST 23
Finished Nov 22 02:19:39 PM PST 23
Peak memory 203088 kb
Host smart-ccc7d65f-eb86-4fff-bcd0-95dbb7bf938d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329812960521098038118066135894295546509730647978337
37961727054533646943318221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_hrst.3298129605210980381180661358942955465097306479783373
7961727054533646943318221
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.9292402227916073856417726015087609155088733195663512108754423519846484309328
Short name T619
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.31 seconds
Started Nov 22 02:19:12 PM PST 23
Finished Nov 22 02:19:17 PM PST 23
Peak memory 203624 kb
Host smart-798bf961-6dc7-440a-837c-a96783ae052d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92924022279160738564177260150876091550887331956635
12108754423519846484309328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_smoke.929240222791607385641772601508760915508873319
5663512108754423519846484309328
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.45034320802854447127270856826413229845376143701069601789102173939235406556298
Short name T434
Test name
Test status
Simulation time 5106060125 ps
CPU time 24.49 seconds
Started Nov 22 02:19:12 PM PST 23
Finished Nov 22 02:19:37 PM PST 23
Peak memory 638952 kb
Host smart-cc8d3c28-b532-48f8-a65d-d7b9b230cc88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45034320802854447127270856826413229845
376143701069601789102173939235406556298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.450343208028544471272708
56826413229845376143701069601789102173939235406556298
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.33149858467507595345533067871526859475677230274836018657743156890489166456854
Short name T369
Test name
Test status
Simulation time 834576440 ps
CPU time 2.96 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:19:15 PM PST 23
Peak memory 203044 kb
Host smart-7d9fa5a6-f731-49a4-8891-e0bcfa608b54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331498584675075953455330678715268594756772302748360
18657743156890489166456854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_perf.3314985846750759534553306787152685947567723027483601
8657743156890489166456854
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.24651341463817066103923869688578903463574905138315416229686430054455414974139
Short name T972
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.33 seconds
Started Nov 22 02:19:12 PM PST 23
Finished Nov 22 02:19:22 PM PST 23
Peak memory 202868 kb
Host smart-601be1b3-9536-4c13-b128-e73bd91a9b07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465134146381706610392386968857890346357490513831541622968643005445541
4974139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smoke.24651341463817066103923869688578903463574905138315416229686430054455414974139
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.85831193666983971147676887636098740352838496828560824218382732615615842570053
Short name T182
Test name
Test status
Simulation time 66540157934 ps
CPU time 1685.49 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:47:16 PM PST 23
Peak memory 6983568 kb
Host smart-4c3191b5-f785-4f58-b45d-5728914f07c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85831193666983971147676887636098740352838496828560
824218382732615615842570053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_all.858311936669839711476768876360987403528
38496828560824218382732615615842570053
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.13183987849568660618669598016943199828942037954050728717769591992370353158408
Short name T1022
Test name
Test status
Simulation time 997771563 ps
CPU time 8.71 seconds
Started Nov 22 02:19:35 PM PST 23
Finished Nov 22 02:19:44 PM PST 23
Peak memory 203032 kb
Host smart-51aa219a-03e3-4bed-b473-73701d5917a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318398784956866061866959801694319982894203795405072871776959199237035
3158408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_rd.1318398784956866061866959801694319982894203795405072871776959
1992370353158408
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.88500878490839330760728442384437304861192310871997883822031710505132373055403
Short name T1134
Test name
Test status
Simulation time 14461449567 ps
CPU time 84.84 seconds
Started Nov 22 02:19:37 PM PST 23
Finished Nov 22 02:21:02 PM PST 23
Peak memory 1541860 kb
Host smart-d411524e-245a-4041-abe9-9c2a7a22ca7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8850087849083933076072844238443730486119231087199788382203171050513237
3055403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_wr.8850087849083933076072844238443730486119231087199788382203171
0505132373055403
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.56918261300069159541675847156642282159243988619714478959773448453124674586239
Short name T912
Test name
Test status
Simulation time 6281818576 ps
CPU time 74.17 seconds
Started Nov 22 02:19:34 PM PST 23
Finished Nov 22 02:20:49 PM PST 23
Peak memory 930588 kb
Host smart-31595b97-972f-4196-b55c-0fbf203f3322
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5691826130006915954167584715664228215924398861971447895977344845312467
4586239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stretch.56918261300069159541675847156642282159243988619714478959773448453124674586239
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.73022771112441421344850949956301140307152846907635703423544290873506083418397
Short name T1385
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.54 seconds
Started Nov 22 02:19:27 PM PST 23
Finished Nov 22 02:19:36 PM PST 23
Peak memory 212564 kb
Host smart-b81f170c-0836-4373-9b90-b10ce27bcfa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730227711124414213448509499563011403071528469076357
03423544290873506083418397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_timeout.7302277111244142134485094995630114030715284690
7635703423544290873506083418397
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_ovf.106841963087995735254741214223995517350385873666952487755447564757278174047555
Short name T1483
Test name
Test status
Simulation time 5445414553 ps
CPU time 134.95 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:21:27 PM PST 23
Peak memory 406764 kb
Host smart-cad42436-56ff-4d28-89df-286f67e3f38b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10684196308799573525474121422399551735038587366695
2487755447564757278174047555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_tx_ovf.1068419630879957352547412142239955173503858736
66952487755447564757278174047555
Directory /workspace/8.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.42386978470922123306287187530199574647358280599866480481491898221344418006208
Short name T283
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.77 seconds
Started Nov 22 02:19:36 PM PST 23
Finished Nov 22 02:19:43 PM PST 23
Peak memory 205288 kb
Host smart-11c84c07-fa4b-4ab4-9347-b7a2644c2cf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423869784709221233062871875301995746473582805998664
80481491898221344418006208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_unexp_stop.423869784709221233062871875301995746473582
80599866480481491898221344418006208
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.109308776671630559333344660384653593245305298013738363011921077655712573478945
Short name T634
Test name
Test status
Simulation time 19975830 ps
CPU time 0.57 seconds
Started Nov 22 02:19:20 PM PST 23
Finished Nov 22 02:19:22 PM PST 23
Peak memory 202484 kb
Host smart-fc2e5bc5-08a4-421e-a6d6-eac807e1cadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109308776671630559333344660384653593245305298013738363011921077655712573478945 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_alert_test.109308776671630559333344660384653593245305298013738363011921077655712573478945
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.24310692710099248183778366501011152852617939180695211927997582030555077804830
Short name T722
Test name
Test status
Simulation time 74225396 ps
CPU time 1.36 seconds
Started Nov 22 02:19:32 PM PST 23
Finished Nov 22 02:19:34 PM PST 23
Peak memory 211196 kb
Host smart-d193786d-39c5-4de3-bef8-d7c0f42e31b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24310692710099248183778366501011152852617939180695211927997582030555077804830 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_host_error_intr.24310692710099248183778366501011152852617939180695211927997582030555077804830
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.56065365981644681253669345906714333786402799212386888658401522072645495110774
Short name T943
Test name
Test status
Simulation time 606667565 ps
CPU time 6.72 seconds
Started Nov 22 02:19:30 PM PST 23
Finished Nov 22 02:19:38 PM PST 23
Peak memory 273244 kb
Host smart-0d788c99-878c-4423-b78f-fa96c43c9a21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56065365981644681253669345906714333786402799212386888658401522072645495110774 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.56065365981644681253669345906714333786402799212386888658401522072645495110774
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.80250718181620117142125786602538226685710555649858034346179967151531959734930
Short name T1003
Test name
Test status
Simulation time 3768267272 ps
CPU time 74.62 seconds
Started Nov 22 02:19:21 PM PST 23
Finished Nov 22 02:20:41 PM PST 23
Peak memory 729224 kb
Host smart-773ac2fb-591b-4557-9d58-17a5c3c64879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80250718181620117142125786602538226685710555649858034346179967151531959734930 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_host_fifo_full.80250718181620117142125786602538226685710555649858034346179967151531959734930
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.22405772730088734945657948517666312593249175802137565778926107326570727607495
Short name T1114
Test name
Test status
Simulation time 7925734012 ps
CPU time 264.38 seconds
Started Nov 22 02:19:21 PM PST 23
Finished Nov 22 02:23:51 PM PST 23
Peak memory 1271608 kb
Host smart-4bf377e5-981a-4e3e-86ec-74998a9c9b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22405772730088734945657948517666312593249175802137565778926107326570727607495 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.i2c_host_fifo_overflow.22405772730088734945657948517666312593249175802137565778926107326570727607495
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.45109268753692620436509180831986552696305244315607607780702846376437615729237
Short name T9
Test name
Test status
Simulation time 209010032 ps
CPU time 0.94 seconds
Started Nov 22 02:19:19 PM PST 23
Finished Nov 22 02:19:22 PM PST 23
Peak memory 202884 kb
Host smart-4032cbba-6c3e-46c7-99b9-52156b4163b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45109268753692620436509180831986552696305244315607607780702846376437615729237 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.45109268753692620436509180831986552696305244315607607780702846376437615729237
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2757934237861715630422784987782080034083237494778100297799911687700682874177
Short name T1099
Test name
Test status
Simulation time 236313385 ps
CPU time 3.96 seconds
Started Nov 22 02:19:33 PM PST 23
Finished Nov 22 02:19:38 PM PST 23
Peak memory 225400 kb
Host smart-2ca02bee-291b-4ba3-973f-7035d5ec19b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757934237861715630422784987782080034083237494778100297799911687700682874177 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.2757934237861715630422784987782080034083237494778100297799911687700682874177
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.53826787577979748577187247422596671503315765267182745923892953311993247405713
Short name T1353
Test name
Test status
Simulation time 7918519784 ps
CPU time 202.74 seconds
Started Nov 22 02:19:37 PM PST 23
Finished Nov 22 02:23:00 PM PST 23
Peak memory 1310708 kb
Host smart-dc4c787a-baad-42d5-bfe1-c31f03591df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53826787577979748577187247422596671503315765267182745923892953311993247405713 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.i2c_host_fifo_watermark.53826787577979748577187247422596671503315765267182745923892953311993247405713
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.15666428527156279400529982535829407072969029854304758582298646254549657385400
Short name T1010
Test name
Test status
Simulation time 3754070957 ps
CPU time 48.59 seconds
Started Nov 22 02:19:34 PM PST 23
Finished Nov 22 02:20:23 PM PST 23
Peak memory 293688 kb
Host smart-5f1fe214-e44f-471b-ba27-3d4b78503d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15666428527156279400529982535829407072969029854304758582298646254549657385400 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_host_mode_toggle.15666428527156279400529982535829407072969029854304758582298646254549657385400
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.23177505116201530222619919597054233958780854446260864244694043090862512765622
Short name T934
Test name
Test status
Simulation time 23672229 ps
CPU time 0.63 seconds
Started Nov 22 02:19:28 PM PST 23
Finished Nov 22 02:19:32 PM PST 23
Peak memory 202880 kb
Host smart-e1f56755-c59e-4938-bb19-889c0c3f0ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23177505116201530222619919597054233958780854446260864244694043090862512765622 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_host_override.23177505116201530222619919597054233958780854446260864244694043090862512765622
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.92573867634184849957558117619077494685109315173061740592972718770613551830853
Short name T475
Test name
Test status
Simulation time 6830796343 ps
CPU time 60.04 seconds
Started Nov 22 02:19:35 PM PST 23
Finished Nov 22 02:20:35 PM PST 23
Peak memory 211364 kb
Host smart-a7c85ae0-3c36-40ed-8b09-32dac2f47177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92573867634184849957558117619077494685109315173061740592972718770613551830853 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.i2c_host_perf.92573867634184849957558117619077494685109315173061740592972718770613551830853
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_rx_oversample.75487161573357826346130368317186552994104146426878007606824939713965929648358
Short name T894
Test name
Test status
Simulation time 3939158762 ps
CPU time 111.84 seconds
Started Nov 22 02:19:15 PM PST 23
Finished Nov 22 02:21:07 PM PST 23
Peak memory 345936 kb
Host smart-6874ab33-d427-445b-b440-04a2b0224d01
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75487161573357826346130368317186552994104146426878007606824939713965929648358 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_rx_oversample.75487161573357826346130368317186552994104146426878007606824939713965929648358
Directory /workspace/9.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.102717385147309222144584352866666941858187823942773869454774123443736926873112
Short name T842
Test name
Test status
Simulation time 2343171530 ps
CPU time 34.28 seconds
Started Nov 22 02:19:12 PM PST 23
Finished Nov 22 02:19:47 PM PST 23
Peak memory 299464 kb
Host smart-dacf5296-f3be-404b-84cc-764fb05f1942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102717385147309222144584352866666941858187823942773869454774123443736926873112 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.i2c_host_smoke.102717385147309222144584352866666941858187823942773869454774123443736926873112
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.17628917290810611639029928419340217463769733367697613160068466611242241535346
Short name T1352
Test name
Test status
Simulation time 32807463528 ps
CPU time 1033.24 seconds
Started Nov 22 02:19:31 PM PST 23
Finished Nov 22 02:36:45 PM PST 23
Peak memory 1957076 kb
Host smart-f6b65702-4559-4657-b022-2bf50656a8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17628917290810611639029928419340217463769733367697613160068466611242241535346 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_host_stress_all.17628917290810611639029928419340217463769733367697613160068466611242241535346
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.104741579852287683791648414981442642467979185963375073202873221811879697757543
Short name T262
Test name
Test status
Simulation time 1466624971 ps
CPU time 14.28 seconds
Started Nov 22 02:19:22 PM PST 23
Finished Nov 22 02:19:42 PM PST 23
Peak memory 214092 kb
Host smart-d47a879e-4cab-4003-a343-41afa7e5dab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104741579852287683791648414981442642467979185963375073202873221811879697757543 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_host_stretch_timeout.104741579852287683791648414981442642467979185963375073202873221811879697757543
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.86546193604981823702640150692767611382744088965365553908479337208506666412054
Short name T61
Test name
Test status
Simulation time 1519570960 ps
CPU time 3.72 seconds
Started Nov 22 02:19:34 PM PST 23
Finished Nov 22 02:19:38 PM PST 23
Peak memory 203068 kb
Host smart-e621ac84-7689-4a3b-855e-e5b58f0d8d1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8654619360498182370264015069276
7611382744088965365553908479337208506666412054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.865461936049818237026401506
92767611382744088965365553908479337208506666412054
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.99374453381773896954847005774959259590040812507132092541778700733374905667592
Short name T1416
Test name
Test status
Simulation time 10166144644 ps
CPU time 30.79 seconds
Started Nov 22 02:19:30 PM PST 23
Finished Nov 22 02:20:02 PM PST 23
Peak memory 382084 kb
Host smart-6466ef7b-11b5-41ae-a344-19a5d4c7385b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993744533817738969548470057749592595900408125071320
92541778700733374905667592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.99374453381773896954847005774959
259590040812507132092541778700733374905667592
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.20815625004414829692637711668607204412782433618708981923654075141557426403370
Short name T917
Test name
Test status
Simulation time 10065199023 ps
CPU time 34.48 seconds
Started Nov 22 02:19:33 PM PST 23
Finished Nov 22 02:20:08 PM PST 23
Peak memory 463228 kb
Host smart-49f5e120-c557-4767-9e38-feaa48ee842b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208156250044148296926377116686072044127824336187089
81923654075141557426403370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_tx.2081562500441482969263771166860720
4412782433618708981923654075141557426403370
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.27534199397269590870323514766885710540078849096456724368890378698632011247684
Short name T782
Test name
Test status
Simulation time 825344371 ps
CPU time 2.51 seconds
Started Nov 22 02:19:20 PM PST 23
Finished Nov 22 02:19:24 PM PST 23
Peak memory 203048 kb
Host smart-8b8a609d-90bb-4ad0-97eb-4bff1af1da0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275341993972695908703235147668857105400788490964567
24368890378698632011247684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_hrst.2753419939726959087032351476688571054007884909645672
4368890378698632011247684
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.81675371751665755944157202909370908584381872660857406122047191327168224850091
Short name T892
Test name
Test status
Simulation time 1588231125 ps
CPU time 4.22 seconds
Started Nov 22 02:19:32 PM PST 23
Finished Nov 22 02:19:37 PM PST 23
Peak memory 203736 kb
Host smart-7db5afb2-a142-4cbb-a79c-6b795f3a2a3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81675371751665755944157202909370908584381872660857
406122047191327168224850091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_smoke.81675371751665755944157202909370908584381872
660857406122047191327168224850091
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.46235642735572587336319670998039519840855385752070732785017242349843153637847
Short name T890
Test name
Test status
Simulation time 5106060125 ps
CPU time 22.37 seconds
Started Nov 22 02:19:11 PM PST 23
Finished Nov 22 02:19:34 PM PST 23
Peak memory 639164 kb
Host smart-84c9fc46-bdc9-4b46-b84f-ee0594dd2dc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46235642735572587336319670998039519840
855385752070732785017242349843153637847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.462356427355725873363196
70998039519840855385752070732785017242349843153637847
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.75590205937680740220788284864304569136923611702347174766382833308127525718743
Short name T979
Test name
Test status
Simulation time 834576440 ps
CPU time 3.07 seconds
Started Nov 22 02:19:31 PM PST 23
Finished Nov 22 02:19:35 PM PST 23
Peak memory 202992 kb
Host smart-934edfff-f195-45b6-b63b-231928d1895f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755902059376807402207882848643045691369236117023471
74766382833308127525718743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_perf.7559020593768074022078828486430456913692361170234717
4766382833308127525718743
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.78019900027450885134986161615503726130298744489112103942536622011779558697043
Short name T941
Test name
Test status
Simulation time 1504713936 ps
CPU time 9.64 seconds
Started Nov 22 02:19:32 PM PST 23
Finished Nov 22 02:19:42 PM PST 23
Peak memory 202996 kb
Host smart-87a92bb1-b9e1-455a-8b3a-927b4c0e67a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7801990002745088513498616161550372613029874448911210394253662201177955
8697043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smoke.78019900027450885134986161615503726130298744489112103942536622011779558697043
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.40684837553142315456624469982609563584650283725242988762081955392722733153652
Short name T497
Test name
Test status
Simulation time 66540157934 ps
CPU time 1424.57 seconds
Started Nov 22 02:19:20 PM PST 23
Finished Nov 22 02:43:06 PM PST 23
Peak memory 6983308 kb
Host smart-6f1d2c4a-da4c-48ea-b5fa-f0a2e7538f94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40684837553142315456624469982609563584650283725242
988762081955392722733153652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_all.406848375531423154566244699826095635846
50283725242988762081955392722733153652
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.50500692178663981657285683022941989396709228341641656561299438800756550337261
Short name T1404
Test name
Test status
Simulation time 997771563 ps
CPU time 8.54 seconds
Started Nov 22 02:19:10 PM PST 23
Finished Nov 22 02:19:19 PM PST 23
Peak memory 202964 kb
Host smart-00f8064a-5cfb-4512-aa82-79543625492b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5050069217866398165728568302294198939670922834164165656129943880075655
0337261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_rd.5050069217866398165728568302294198939670922834164165656129943
8800756550337261
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.75717335906107998977647549086107275532255252315443626672429129976488056428315
Short name T1310
Test name
Test status
Simulation time 14461449567 ps
CPU time 90.38 seconds
Started Nov 22 02:19:19 PM PST 23
Finished Nov 22 02:20:51 PM PST 23
Peak memory 1542176 kb
Host smart-a286eac3-1faf-492f-88a5-1145126974d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7571733590610799897764754908610727553225525231544362667242912997648805
6428315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_wr.7571733590610799897764754908610727553225525231544362667242912
9976488056428315
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.73379434726256346409426390637384059437234642688344358469895064136081074017032
Short name T788
Test name
Test status
Simulation time 6281818576 ps
CPU time 71.83 seconds
Started Nov 22 02:19:33 PM PST 23
Finished Nov 22 02:20:46 PM PST 23
Peak memory 930580 kb
Host smart-6689d7a6-57da-42d3-a4fd-b41f3d458db6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7337943472625634640942639063738405943723464268834435846989506413608107
4017032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stretch.73379434726256346409426390637384059437234642688344358469895064136081074017032
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.77362803941409236459849132957536357347568961803602023516286689425232245841997
Short name T627
Test name
Test status
Simulation time 2856220981 ps
CPU time 7.48 seconds
Started Nov 22 02:19:37 PM PST 23
Finished Nov 22 02:19:45 PM PST 23
Peak memory 212364 kb
Host smart-9ba62204-a57a-48e9-a406-edab71b1ff4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773628039414092364598491329575363573475689618036020
23516286689425232245841997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_timeout.7736280394140923645984913295753635734756896180
3602023516286689425232245841997
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_ovf.111081188445991994310741277537346445198265043337981854773898944862288789633083
Short name T313
Test name
Test status
Simulation time 5445414553 ps
CPU time 132.7 seconds
Started Nov 22 02:19:13 PM PST 23
Finished Nov 22 02:21:27 PM PST 23
Peak memory 406668 kb
Host smart-fc01280b-585e-46d1-9544-6d1c3baf2921
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11108118844599199431074127753734644519826504333798
1854773898944862288789633083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_tx_ovf.1110811884459919943107412775373464451982650433
37981854773898944862288789633083
Directory /workspace/9.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.79405981721702534013121719073788628933629137452988431824923380077414704936151
Short name T579
Test name
Test status
Simulation time 1922317738 ps
CPU time 5.71 seconds
Started Nov 22 02:19:33 PM PST 23
Finished Nov 22 02:19:39 PM PST 23
Peak memory 205336 kb
Host smart-3c1719ae-3120-4af1-a973-22d8705b51c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794059817217025340131217190737886289336291374529884
31824923380077414704936151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_unexp_stop.794059817217025340131217190737886289336291
37452988431824923380077414704936151
Directory /workspace/9.i2c_target_unexp_stop/latest
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