671f2b57e2| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.689m | 11.461ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 42.880s | 8.090ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.720s | 41.509us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.750s | 28.400us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.930s | 341.504us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.330s | 329.958us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.400s | 104.691us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.750s | 28.400us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.330s | 329.958us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.900s | 151.197us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 55.415m | 171.030ms | 37 | 50 | 74.00 |
| V2 | host_perf | i2c_host_perf | 32.273m | 26.371ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.690s | 50.115us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 14.033m | 13.272ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 17.197m | 19.965ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.290s | 217.945us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 36.660s | 1.952ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.320s | 1.422ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.757m | 17.515ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 59.530s | 1.459ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 6.691m | 3.297ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 3.498m | 24.501ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 9.300s | 4.471ms | 50 | 50 | 100.00 |
| V2 | target_glitch | i2c_target_glitch | 4.610s | 1.118ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 48.495m | 44.323ms | 44 | 50 | 88.00 |
| V2 | target_perf | i2c_target_perf | 6.260s | 17.262ms | 50 | 50 | 100.00 |
| V2 | target_fifo_overflow | i2c_target_tx_ovf | 5.311m | 4.270ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.743m | 14.531ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.070s | 5.856ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.335m | 10.093ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.451m | 10.164ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 45.512m | 44.420ms | 46 | 50 | 92.00 |
| i2c_target_stress_rd | 1.743m | 14.531ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 11.068m | 19.599ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.370s | 8.774ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 35.355m | 29.021ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.490s | 6.531ms | 48 | 50 | 96.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.690s | 1.422ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.650s | 18.430us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 57.269us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.900s | 525.457us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.900s | 525.457us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.720s | 41.509us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.750s | 28.400us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.330s | 329.958us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.970s | 91.608us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.720s | 41.509us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.750s | 28.400us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.330s | 329.958us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.970s | 91.608us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1460 | 1492 | 97.86 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.400s | 1.974ms | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.910s | 125.090us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.400s | 1.974ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 14.844m | 15.900ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 1640 | 1772 | 92.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 32 | 32 | 26 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.25 | 99.07 | 96.59 | 100.00 | 93.91 | 98.13 | 100.00 | 93.07 |
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 81 failures:
0.i2c_host_stress_all.59424085998389112386949709860302992972127208960098736854234614597926842487636
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:1864e5ac-2e08-4230-a4bd-b0a9c308728f
2.i2c_host_stress_all.39241143704141171035024897137973930812446712716556855778740594367051864247084
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:a837a6f4-5363-4bd3-80fa-dafa14df6970
... and 11 more failures.
0.i2c_host_stress_all_with_rand_reset.4905466179711136778572932836819063386434135712881547450786593828608634652113
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:64e46edc-5da8-48ac-8e2c-aca7e41982be
1.i2c_host_stress_all_with_rand_reset.34962723013539730211372458618714416537465788272736525510037416935773664925820
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:46794b2e-b263-48e1-99aa-8aed52e09451
... and 48 more failures.
1.i2c_target_stretch.99487676952268435193455648676603520784089442261209356702338784968229391175323
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
Job ID: smart:f2ffae53-629c-4455-a3d1-2487fdf3f944
2.i2c_target_stretch.42104103828007351515228952514136643867130429047655917149005737482798541668422
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
Job ID: smart:6b8d2220-bc11-4268-b470-087f92b8615b
... and 4 more failures.
3.i2c_target_stress_wr.74718360722840000858440321651257078289900320394128905699644975618808131802536
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_wr/latest/run.log
Job ID: smart:78932d6c-28ac-454e-9644-e468466428cb
10.i2c_target_stress_wr.33270205165134524354838410087008718962885762164754530003599027902919736579541
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_wr/latest/run.log
Job ID: smart:2a27e8f0-01da-42b6-a3e7-3bcc055d7365
... and 2 more failures.
6.i2c_target_stress_all.113676195756533141396107864511366900940153184735678189763728815865616938361198
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
Job ID: smart:8740f98e-d3a2-4f97-b744-eb962663e0fa
15.i2c_target_stress_all.26006843074783119012555184601066749185468069444635800773882298100628869405846
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
Job ID: smart:07b709a2-3214-4732-958b-30f1bd23e6d1
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:787) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 16 failures:
2.i2c_target_stress_all_with_rand_reset.115678712953689458091329146374391246965239267926044058073657849823637861241315
Line 323, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4525844165 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (10 [0xa] vs 8 [0x8])
UVM_INFO @ 4525844165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.59098706596983343798419059646728951738046792775573980780088151237271818063526
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6108292080 ps: (i2c_scoreboard.sv:787) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 4 [0x4])
UVM_INFO @ 6108292080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 10 failures:
0.i2c_target_stress_all_with_rand_reset.70383135556916147341397803199725841190291868639184440698906348819316072145856
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 21190092133 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xb0236494) == 0x0
UVM_INFO @ 21190092133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.64364951436960675968698590586652986563819903959103420519188962087675513850158
Line 316, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4123817872 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x9dd44614) == 0x0
UVM_INFO @ 4123817872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 7 failures:
3.i2c_target_stress_all_with_rand_reset.68112675605079587842346479227500919786791221841882595225290370341844056508656
Line 316, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4881988821 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 4881988821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_stress_all_with_rand_reset.3392632654117985984270274697698159386214199554766818508080109877317154839065
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5440420942 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 5440420942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_monitor.sv:448) monitor [monitor] ack_stop detected has 5 failures:
7.i2c_target_stress_all_with_rand_reset.58931145719028653151240396497849606531884449098708990551942071767556926488419
Line 386, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15900452842 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 15900452842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.66674337441198576865030709882331675975502653189294275287397187154379228557397
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8776742 ps: (i2c_monitor.sv:448) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 8776742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:779) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 5 failures:
24.i2c_target_stress_all_with_rand_reset.46542496579369309857007644958714548688489679977211005770348025507678425365540
Line 357, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10026537065 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (104 [0x68] vs 9 [0x9])
UVM_INFO @ 10026537065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_stress_all_with_rand_reset.100322530117497850274473962055255268217681040057070755888999515791484208065922
Line 300, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18909224865 ps: (i2c_scoreboard.sv:779) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (221 [0xdd] vs 242 [0xf2])
UVM_INFO @ 18909224865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending 'scl_i' has 4 failures:
1.i2c_target_stress_all_with_rand_reset.41909102871409082606694673447507156338698695481065042644032615335193518588248
Line 318, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 23505492540 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 23505492540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_stress_all_with_rand_reset.108556889368601070616707331062480622430938774965509109707655081932739364348056
Line 274, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending 'scl_i'
UVM_ERROR @ 1512253044 ps: (i2c_fsm.sv:1354) [ASSERT FAILED] SclInputGlitch_A
UVM_INFO @ 1512253044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
7.i2c_target_bad_addr.28856119365076333338436871489607490175536523350045110691610891664285132561331
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_bad_addr.21598243288543122998843727536053425725598599997441826761721936023855881997184
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:483) [i2c_common_vseq] Check failed data == * (* [*] vs * [*]) has 1 failures:
0.i2c_same_csr_outstanding.3457960255601893087920321176022634672232897202240838565397929526690253152529
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 13604120 ps: (cip_base_vseq.sv:483) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 13604120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:791) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
47.i2c_target_stress_all_with_rand_reset.32612735859157016094051071615748121766177205686604106322104364227587599462173
Line 381, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9589213043 ps: (i2c_scoreboard.sv:791) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (0 [0x0] vs 152 [0x98])
UVM_INFO @ 9589213043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---