Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

217248

1

T1

1152

T3

811

T11

866

ack

18260

1

T1

36

T3

62

T9

48

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	894	1			T1	6		T3	2		T11	1
high	48086	1			T1	238		T3	187		T9	3
med	87953	1			T1	474		T3	329		T9	10
sml	97694	1			T1	467		T3	350		T9	35
all_zero	881	1			T1	3		T3	5		T11	4

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117885

1

T1

617

T3

420

T9

28

auto[1]

117623

1

T1

571

T3

453

T9

20

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161351

1

T1

799

T3

598

T9

38

auto[1]

74157

1

T1

389

T3

275

T9

10

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

224870

1

T1

1171

T3

841

T9

19

auto[1]

10638

1

T1

17

T3

32

T9

29

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

222232

1

T1

1153

T3

839

T9

29

auto[1]

13276

1

T1

35

T3

34

T9

19

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223981

1

T1

1154

T3

841

T9

29

auto[1]

11527

1

T1

34

T3

32

T9

19

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117885

1

T1

617

T3

420

T9

28

auto[1]

117623

1

T1

571

T3

453

T9

20

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161351

1

T1

799

T3

598

T9

38

auto[1]

74157

1

T1

389

T3

275

T9

10

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

224870

1

T1

1171

T3

841

T9

19

auto[1]

10638

1

T1

17

T3

32

T9

29

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

222232

1

T1

1153

T3

839

T9

29

auto[1]

13276

1

T1

35

T3

34

T9

19

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223981

1

T1

1154

T3

841

T9

29

auto[1]

11527

1

T1

34

T3

32

T9

19

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

12

1

T169

1

T170

1

T171

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T172

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T44

1

T173

1

T174

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

578

1

T1

4

T3

4

T11

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

301

1

T1

3

T3

1

T65

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

283

1

T1

1

T3

1

T40

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1047

1

T1

4

T3

4

T11

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

500

1

T1

2

T11

2

T65

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

564

1

T1

2

T3

1

T11

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1023

1

T1

2

T3

4

T65

4

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

532

1

T1

1

T3

2

T11

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

522

1

T1

2

T3

1

T65

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

22

1

T35

1

T175

1

T176

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

11

1

T96

1

T177

1

T178

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

13

1

T179

1

T180

1

T124

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	69166	1			T1	394		T3	256		T11	285
write_address_byte	13276	1			T1	35		T3	34		T9	19
read_with_ack	3784	1			T3	9		T9	10		T35	30
read_with_nack	6854	1			T1	17		T3	23		T9	19
stop_byte	11527	1			T1	34		T3	32		T9	19
write_address_byte_nak	8550	1			T1	32		T3	18		T11	18
data_byte_nack	217248	1			T1	1152		T3	811		T11	866
stop_byte_nack	8200	1			T1	31		T3	18		T11	18
nakok_byte_nack	108495	1			T1	551		T3	418		T11	433
nakok_addr_byte_nack	4285	1			T1	15		T3	8		T11	12