Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
91.30 91.30 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_protocol_cov_cg 91.30 1 100 1 64 64



Group Instance : i2c_protocol_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.30 1 100 1 64 64



Summary for Group Instance i2c_protocol_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 47 3 44 93.62
Crosses 68 7 61 89.71


Variables for Group Instance i2c_protocol_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
RStart_before_read_data_ACK_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_Ack_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_transmission_cp 1 0 1 100.00 100 1 1 0
RStart_during_read_data_cp 1 0 1 100.00 100 1 1 0
RStart_during_rw_bit_cp 1 1 0 0.00 100 1 1 0
RStart_during_write_data_cp 1 0 1 100.00 100 1 1 0
Read_data_ack_before_stop_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Ack_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Nack_cp 1 0 1 100.00 100 1 1 0
Start_followed_by_Rstart_cp 1 0 1 100.00 100 1 1 2
Stop_after_read_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_read_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_write_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_addr_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_data_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_read_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_write_cp 1 0 1 100.00 100 1 1 0
bus_state_cp 17 1 16 94.12 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0
num_rd_bytes_cp 5 0 5 100.00 100 1 1 0
num_wr_bytes_cp 5 0 5 100.00 100 1 1 0


Crosses for Group Instance i2c_protocol_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
bus_state_x_ip_mode_cp 34 3 31 91.18 100 1 1 0
num_rd_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
num_wr_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
Stop_after_write_data_ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Stop_after_read_data_ack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_write_data_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Stop_after_read_data_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Nack_x_ip_mode_cp 2 1 1 50.00 100 1 1 0
Start_followed_by_Rstart_cp_x_ip_mode_cp 2 1 1 50.00 100 1 1 0


Summary for Variable RStart_before_read_data_ACK_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_before_read_data_ACK_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_before_read_data_ACK_Nack 27078 1 T2 8 T7 7 T13 27


Summary for Variable RStart_during_address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_address_Acknowledge 4 1 T49 2 T50 2


Summary for Variable RStart_during_address_transmission_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_transmission_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_address_transmission 8 1 T7 1 T150 1 T151 1


Summary for Variable RStart_during_read_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_read_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_read_data 822 1 T14 6 T15 11 T39 13


Summary for Variable RStart_during_rw_bit_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_rw_bit 0 1 1


Summary for Variable RStart_during_write_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_write_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_write_data 23988 1 T2 10 T7 6 T8 82


Summary for Variable Read_data_ack_before_stop_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Read_data_ack_before_stop_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Read_data_ack_before_stop 424 1 T14 8 T15 15 T39 5


Summary for Variable Rstart_after_Address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack 12 1 T40 1 T49 5 T50 5


Summary for Variable Rstart_after_Address_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack 4 1 T49 2 T50 2


Summary for Variable Start_followed_by_Rstart_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for Start_followed_by_Rstart_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[1] 6 1 T152 4 T153 2


Summary for Variable Stop_after_read_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack 19438 1 T1 17 T2 2 T3 50


Summary for Variable Stop_after_read_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_ack 424 1 T14 8 T15 15 T39 5


Summary for Variable Stop_after_write_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack 4 1 T154 1 T155 1 T138 1


Summary for Variable Stop_after_write_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack 12925 1 T1 18 T2 1 T3 12


Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_addr_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_addr 11 1 T156 1 T157 1 T158 1


Summary for Variable Stop_without_ACK_after_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_data 8038 1 T2 1 T7 1 T8 4


Summary for Variable Stop_without_ACK_after_read_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_read 0 1 1


Summary for Variable Stop_without_ACK_after_write_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_write_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Stop_without_ACK_after_write 8 1 T49 4 T50 4


Summary for Variable bus_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 17 1 16 94.12


User Defined Bins for bus_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_addr_nack 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle 211660 1 T21 14 T23 7 T26 2
stop 33388 1 T105 1 T1 35 T2 3
write_data_nack 13321 1 T49 2 T154 6244 T50 2
write_data_ack 1690959 1 T1 4044 T2 207 T3 2852
read_data_nack 209528 1 T1 72 T2 32 T3 200
read_data_ack 1832809 1 T1 3273 T2 252 T3 5003
write_data 11339636 1 T1 24106 T2 1478 T3 17036
read_data 15251031 1 T1 28203 T2 2327 T3 44256
write_addr_nack 4 1 T49 2 T50 2 - -
write_addr_ack 134134 1 T1 62 T2 43 T3 40
read_addr_ack 169736 1 T1 66 T2 33 T3 175
write 156057 1 T1 72 T2 48 T3 55
read 146188 1 T1 54 T2 30 T3 150
addr 1802728 1 T1 619 T2 452 T3 1161
rstart 136426 1 T2 36 T7 36 T8 164
start 87896 1 T1 95 T2 8 T3 172


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 17640293 1 T21 4 T23 2 T26 1
host 15575208 1 T21 10 T23 5 T26 1


Summary for Variable num_rd_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_rd_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 45744 1 T1 72 T3 382 T10 4
high 1720785 1 T1 9784 T3 8105 T13 102
mid 3029739 1 T1 10864 T2 213 T3 14158
low 9189663 1 T1 9884 T2 1995 T3 18257
one 1103511 1 T1 496 T2 190 T3 1286


Summary for Variable num_wr_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_wr_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 36875 1 T1 90 T3 302 T14 60
high 1291036 1 T1 8794 T3 5868 T8 492
mid 2000343 1 T1 9628 T3 6462 T8 1300
low 7281510 1 T1 8814 T2 1177 T3 5888
one 944307 1 T1 444 T2 229 T3 294


Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 34 3 31 91.18 3


Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Element holes
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[read_addr_nack] * -- -- 2


Uncovered bins
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[write_addr_nack] [host] 0 1 1


Covered bins
bus_state_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle device 209206 1 T21 4 T23 2 T26 1
idle host 2454 1 T21 10 T23 5 T26 1
stop device 16925 1 T2 3 T7 3 T8 4
stop host 16463 1 T105 1 T1 35 T3 65
write_data_nack device 4 1 T49 2 T50 2 - -
write_data_nack host 13317 1 T154 6244 T159 125 T155 154
write_data_ack device 930790 1 T2 207 T7 153 T8 2625
write_data_ack host 760169 1 T1 4044 T3 2852 T11 3067
read_data_nack device 116622 1 T2 32 T7 29 T13 85
read_data_nack host 92906 1 T1 72 T3 200 T10 4
read_data_ack device 864340 1 T2 252 T7 310 T13 833
read_data_ack host 968469 1 T1 3273 T3 5003 T10 159
write_data device 6781386 1 T2 1478 T7 1100 T8 18725
write_data host 4558250 1 T1 24106 T3 17036 T11 18195
read_data device 6587865 1 T2 2327 T7 1963 T13 5577
read_data host 8663166 1 T1 28203 T3 44256 T10 1539
write_addr_nack device 4 1 T49 2 T50 2 - -
write_addr_ack device 109953 1 T2 43 T7 29 T8 303
write_addr_ack host 24181 1 T1 62 T3 40 T11 45
read_addr_ack device 130032 1 T2 33 T7 32 T13 96
read_addr_ack host 39704 1 T1 66 T3 175 T10 3
write device 127754 1 T2 48 T7 32 T8 348
write host 28303 1 T1 72 T3 55 T11 52
read device 111732 1 T2 30 T7 27 T13 84
read host 34456 1 T1 54 T3 150 T10 3
addr device 1476902 1 T2 452 T7 317 T8 1932
addr host 325826 1 T1 619 T3 1161 T10 15
rstart device 132676 1 T2 36 T7 36 T8 164
rstart host 3750 1 T40 2 T35 59 T30 20
start device 44102 1 T2 8 T7 12 T8 10
start host 43794 1 T1 95 T3 172 T10 2


Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_rd_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 1455 1 T14 96 T15 96 T160 168
device high 69698 1 T13 102 T14 3419 T15 4066
device mid 474294 1 T2 213 T7 244 T13 680
device low 5343229 1 T2 1995 T7 1698 T13 4525
device one 797463 1 T2 190 T7 176 T13 603
host sixtyfour 44289 1 T1 72 T3 382 T10 4
host high 1651087 1 T1 9784 T3 8105 T10 531
host mid 2555445 1 T1 10864 T3 14158 T10 600
host low 3846434 1 T1 9884 T3 18257 T10 526
host one 306048 1 T1 496 T3 1286 T10 22


Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_wr_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 2016 1 T14 60 T15 274 T55 30
device high 86258 1 T8 492 T52 90 T13 145
device mid 502582 1 T8 1300 T52 2280 T13 1099
device low 5404031 1 T2 1177 T7 885 T8 15176
device one 796984 1 T2 229 T7 173 T8 2239
host sixtyfour 34859 1 T1 90 T3 302 T11 318
host high 1204778 1 T1 8794 T3 5868 T11 6386
host mid 1497761 1 T1 9628 T3 6462 T11 7016
host low 1877479 1 T1 8814 T3 5888 T11 6366
host one 147323 1 T1 444 T3 294 T11 316


Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins
Stop_after_write_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack device 7588 1 T2 1 T7 1 T8 4
Stop_after_write_data_ack host 5337 1 T1 18 T3 12 T11 13


Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Element holes
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [host] 0 1 1


Covered bins
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_ack device 424 1 T14 8 T15 15 T39 5


Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Element holes
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Covered bins
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_Nack host 4 1 T154 1 T155 1 T138 1


Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins
Stop_after_read_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack device 8499 1 T2 2 T7 2 T13 1
Stop_after_read_data_Nack host 10939 1 T1 17 T3 50 T9 47


Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Bins
Rstart_after_Address_Ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack device 10 1 T49 5 T50 5
Rstart_after_Address_Ack host 2 1 T40 1 T44 1


Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Element holes
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [host] 0 1 1


Covered bins
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack device 4 1 T49 2 T50 2


Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Element holes
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Excluded/Illegal bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTSTATUS
[auto[0]] [device , host] -- Excluded (2 bins)


Covered bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[1] host 6 1 T152 4 T153 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%