Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47755941	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16350898

1

T19

20

T20

8

T21

376

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56420100	1			T19	20		T20	11		T21	639
values[0x0]	3841069	1			T19	8		T20	3		T21	195
values[0x1]	3845670	1			T19	12		T20	8		T21	204

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35138926	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28967913

1

T19

26

T20

12

T21

593

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	215991	1			T21	3		T23	1		T73	2
valid_sources[0x01]	475769	1			T23	2		T25	5		T73	1
valid_sources[0x02]	222055	1			T22	1		T23	2		T73	1
valid_sources[0x03]	958425	1			T21	2		T23	1		T28	1
valid_sources[0x04]	252124	1			T22	10		T23	3		T24	1
valid_sources[0x05]	253650	1			T21	1		T23	3		T25	3
valid_sources[0x06]	228575	1			T19	1		T25	1		T26	1
valid_sources[0x07]	233305	1			T21	5		T23	1		T24	1
valid_sources[0x08]	395589	1			T21	1		T23	1		T103	4
valid_sources[0x09]	264295	1			T21	2		T22	2		T23	4
valid_sources[0x0a]	249859	1			T21	12		T23	3		T25	2
valid_sources[0x0b]	226618	1			T23	3		T26	1		T73	2
valid_sources[0x0c]	290317	1			T21	8		T23	1		T26	1
valid_sources[0x0d]	206027	1			T22	5		T23	1		T25	1
valid_sources[0x0e]	209618	1			T21	1		T23	4		T28	2
valid_sources[0x0f]	214207	1			T21	3		T23	1		T73	4
valid_sources[0x10]	220405	1			T20	2		T21	8		T22	2
valid_sources[0x11]	558361	1			T23	4		T73	6		T81	4
valid_sources[0x12]	207885	1			T19	1		T21	16		T25	3
valid_sources[0x13]	214468	1			T21	10		T22	13		T73	2
valid_sources[0x14]	295386	1			T23	4		T26	2		T28	4
valid_sources[0x15]	258149	1			T21	1		T61	1		T73	4
valid_sources[0x16]	275108	1			T21	3		T22	8		T23	2
valid_sources[0x17]	217900	1			T21	2		T23	3		T25	2
valid_sources[0x18]	343650	1			T21	3		T23	1		T73	1
valid_sources[0x19]	238030	1			T23	4		T73	7		T103	4
valid_sources[0x1a]	229946	1			T21	4		T25	1		T73	1
valid_sources[0x1b]	410772	1			T21	4		T23	2		T28	1
valid_sources[0x1c]	222364	1			T19	1		T23	1		T73	5
valid_sources[0x1d]	209874	1			T73	1		T103	4		T1	6
valid_sources[0x1e]	229124	1			T22	1		T23	3		T25	6
valid_sources[0x1f]	207757	1			T22	15		T25	6		T26	2
valid_sources[0x20]	244595	1			T19	1		T21	2		T23	2
valid_sources[0x21]	199780	1			T23	5		T25	1		T26	2
valid_sources[0x22]	362472	1			T23	3		T25	2		T26	1
valid_sources[0x23]	236927	1			T19	1		T21	8		T23	3
valid_sources[0x24]	274662	1			T21	4		T23	2		T73	2
valid_sources[0x25]	210968	1			T21	7		T23	5		T73	4
valid_sources[0x26]	227298	1			T21	15		T23	5		T27	1
valid_sources[0x27]	206077	1			T22	9		T23	2		T73	1
valid_sources[0x28]	204079	1			T21	3		T23	2		T25	4
valid_sources[0x29]	247453	1			T73	3		T103	3		T81	5
valid_sources[0x2a]	225776	1			T21	2		T23	3		T73	3
valid_sources[0x2b]	206913	1			T19	1		T21	6		T23	2
valid_sources[0x2c]	221791	1			T23	4		T25	5		T73	2
valid_sources[0x2d]	225524	1			T21	7		T25	1		T73	2
valid_sources[0x2e]	199358	1			T21	1		T22	1		T73	4
valid_sources[0x2f]	201621	1			T22	2		T23	1		T24	1
valid_sources[0x30]	208184	1			T21	1		T22	10		T23	2
valid_sources[0x31]	223623	1			T21	5		T23	2		T25	3
valid_sources[0x32]	392972	1			T21	16		T22	6		T23	1
valid_sources[0x33]	222971	1			T23	2		T73	2		T103	3
valid_sources[0x34]	205925	1			T21	7		T22	3		T24	1
valid_sources[0x35]	215209	1			T21	8		T23	2		T26	1
valid_sources[0x36]	214708	1			T21	6		T22	23		T103	1
valid_sources[0x37]	238406	1			T21	10		T23	3		T25	1
valid_sources[0x38]	277897	1			T21	12		T22	7		T26	2
valid_sources[0x39]	210656	1			T21	4		T23	2		T25	4
valid_sources[0x3a]	206363	1			T21	6		T23	2		T25	8
valid_sources[0x3b]	508158	1			T19	1		T21	5		T23	2
valid_sources[0x3c]	201535	1			T19	1		T21	12		T23	1
valid_sources[0x3d]	235752	1			T21	2		T23	1		T27	1
valid_sources[0x3e]	212821	1			T22	5		T23	3		T73	4
valid_sources[0x3f]	224006	1			T19	1		T21	3		T23	1
valid_sources[0x40]	234122	1			T21	2		T26	1		T28	1
valid_sources[0x41]	201529	1			T21	1		T23	1		T28	1
valid_sources[0x42]	232674	1			T23	3		T26	1		T73	1
valid_sources[0x43]	213511	1			T23	2		T26	2		T61	1
valid_sources[0x44]	220671	1			T23	1		T28	2		T103	4
valid_sources[0x45]	238959	1			T28	1		T61	1		T73	1
valid_sources[0x46]	379964	1			T21	3		T22	2		T23	2
valid_sources[0x47]	271266	1			T21	5		T23	3		T24	1
valid_sources[0x48]	361146	1			T20	9		T21	1		T23	3
valid_sources[0x49]	231536	1			T21	15		T23	2		T24	1
valid_sources[0x4a]	207490	1			T21	2		T23	4		T25	2
valid_sources[0x4b]	287772	1			T23	5		T27	3		T73	5
valid_sources[0x4c]	407502	1			T21	5		T103	2		T81	1
valid_sources[0x4d]	234983	1			T21	1		T23	3		T73	4
valid_sources[0x4e]	208286	1			T21	3		T22	6		T23	1
valid_sources[0x4f]	236647	1			T21	4		T22	1		T23	2
valid_sources[0x50]	221498	1			T23	2		T25	2		T26	1
valid_sources[0x51]	288443	1			T21	17		T23	3		T25	2
valid_sources[0x52]	227772	1			T21	6		T23	2		T73	2
valid_sources[0x53]	238819	1			T21	9		T73	2		T103	4
valid_sources[0x54]	211958	1			T21	4		T22	11		T23	4
valid_sources[0x55]	350044	1			T19	1		T21	21		T23	1
valid_sources[0x56]	219753	1			T21	4		T23	2		T26	1
valid_sources[0x57]	263450	1			T23	4		T73	5		T103	1
valid_sources[0x58]	207557	1			T19	1		T21	18		T23	2
valid_sources[0x59]	224041	1			T21	5		T22	19		T23	1
valid_sources[0x5a]	211935	1			T21	7		T28	1		T103	1
valid_sources[0x5b]	246069	1			T21	3		T22	2		T23	4
valid_sources[0x5c]	223195	1			T21	11		T23	3		T73	1
valid_sources[0x5d]	206259	1			T23	2		T28	2		T73	2
valid_sources[0x5e]	226949	1			T23	1		T73	4		T103	3
valid_sources[0x5f]	227607	1			T19	1		T23	4		T25	2
valid_sources[0x60]	216490	1			T21	13		T23	2		T103	3
valid_sources[0x61]	213428	1			T21	6		T23	1		T28	1
valid_sources[0x62]	218830	1			T21	4		T23	2		T25	9
valid_sources[0x63]	367154	1			T21	17		T23	2		T25	2
valid_sources[0x64]	233112	1			T21	9		T28	2		T73	2
valid_sources[0x65]	381770	1			T23	2		T25	2		T73	1
valid_sources[0x66]	232420	1			T21	3		T23	1		T73	2
valid_sources[0x67]	213584	1			T19	2		T21	1		T26	1
valid_sources[0x68]	196794	1			T23	3		T27	1		T103	2
valid_sources[0x69]	240324	1			T21	6		T23	2		T26	1
valid_sources[0x6a]	498417	1			T19	1		T21	2		T27	2
valid_sources[0x6b]	227304	1			T19	1		T23	2		T28	2
valid_sources[0x6c]	203804	1			T21	11		T23	2		T25	1
valid_sources[0x6d]	233988	1			T21	1		T22	2		T23	1
valid_sources[0x6e]	211412	1			T21	2		T23	4		T25	3
valid_sources[0x6f]	223313	1			T19	1		T21	4		T73	6
valid_sources[0x70]	214456	1			T21	6		T23	1		T28	1
valid_sources[0x71]	246773	1			T19	1		T21	6		T23	2
valid_sources[0x72]	206532	1			T21	1		T23	2		T27	1
valid_sources[0x73]	220197	1			T19	3		T21	4		T23	2
valid_sources[0x74]	206984	1			T19	1		T21	5		T22	25
valid_sources[0x75]	206478	1			T21	10		T23	5		T26	1
valid_sources[0x76]	991767	1			T19	1		T22	5		T23	3
valid_sources[0x77]	218662	1			T22	2		T23	3		T24	1
valid_sources[0x78]	206502	1			T23	1		T25	3		T61	1
valid_sources[0x79]	245006	1			T23	2		T73	3		T103	2
valid_sources[0x7a]	216901	1			T22	3		T28	2		T73	2
valid_sources[0x7b]	223808	1			T21	11		T23	5		T73	1
valid_sources[0x7c]	883068	1			T23	1		T61	1		T73	6
valid_sources[0x7d]	213332	1			T21	3		T22	1		T23	2
valid_sources[0x7e]	206371	1			T21	4		T23	2		T28	4
valid_sources[0x7f]	231408	1			T22	2		T25	10		T73	2
valid_sources[0x80]	197268	1			T19	1		T23	2		T25	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13422514

1

T19

12

T20

4

T21

86

values[0x0]

all_enables

biggest_size

1886087

1

T19

5

T20

2

T21

145

values[0x1]

all_enables

biggest_size

1042297

1

T19

3

T20

2

T21

145