Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_intr_state_tx_stretch 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_acq_full 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_fmt_threshold 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_threshold 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_fmt_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_nak 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_tx_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_nak 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_full 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_fbyte 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_start 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_stop 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_readb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_rcont 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_nakok 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxilvl 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtilvl 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_sclval 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing0_thigh 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing0_tlow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing1_t_r 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing1_t_f 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing4_t_buf 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_address0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_mask0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_address1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_mask1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_txdata 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=2,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_fbyte

SCORECOND
100.00 100.00
tb.dut.u_reg.u_txdata

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT19,T20,T21
1CoveredT21,T23,T25
Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_fmt_threshold

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_threshold

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_fmt_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_nak

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_tx_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_tx_stretch

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_acq_full

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_nak

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_full

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_start

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_stop

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_readb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_rcont

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_nakok

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_sclval

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT19,T20,T21
1CoveredT19,T20,T21
Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing0_thigh

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing0_tlow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing1_t_r

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing1_t_f

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing4_t_buf

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT19,T20,T21
1CoveredT21,T23,T25
Cond Coverage for Module : prim_subreg ( parameter DW=31,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT19,T20,T21
1CoveredT21,T23,T25
Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT19,T20,T21
1CoveredT21,T23,T25
Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtilvl

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT19,T20,T21
1CoveredT21,T23,T25
Cond Coverage for Module : prim_subreg ( parameter DW=3,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxilvl

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT19,T20,T21
1CoveredT21,T23,T25
Cond Coverage for Module : prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_address0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_mask0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_address1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_mask1

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT19,T20,T21
1CoveredT21,T23,T25
Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:
-1-StatusTests
1 Covered T19,T20,T21
0 Covered T19,T20,T21 



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T19,T20,T21
0 1 Covered T19,T20,T21
0 0 Covered T19,T20,T21

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%