Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.79	100.00	87.18			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_rxfifo	96.15	100.00	84.62			100.00	100.00
tb.dut.i2c_core.u_i2c_txfifo	96.15	100.00	84.62			100.00	100.00
tb.dut.i2c_core.u_i2c_fmtfifo	97.12	100.00	88.46			100.00	100.00
tb.dut.i2c_core.u_i2c_acqfifo	97.12	100.00	88.46			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.44	97.00	77.22			94.12		i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_txfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.44	97.00	77.22			94.12		i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_fmtfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.44	97.00	77.22			94.12		i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_acqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.44	97.00	77.22			94.12		i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
97.12	88.46

tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T40

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T56,T57
1	0	1	Covered	T1,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T40

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=10,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
97.12	88.46

tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T51,T52

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T49,T50
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T62,T63,T64
1	0	1	Covered	T2,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T51,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T51,T52

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=0,Depth=64,OutputZeroIfEmpty=1,Secure=0,DepthW=7,gen_normal_fifo.PTRV_W=6,gen_normal_fifo.PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_rxfifo

SCORE	COND
96.15	84.62

tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T10

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T14,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T10

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T10
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1980837404	605980698	0	0
DepthKnown_A	1980837404	1980085308	0	0
RvalidKnown_A	1980837404	1980085308	0	0
WreadyKnown_A	1980837404	1980085308	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1980837404	605980698	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1980837404	605980698	0	0
T1	1184792	850088	0	0
T2	219960	20422	0	0
T3	492788	356850	0	0
T7	134284	10766	0	0
T8	2461340	612910	0	0
T9	0	317540	0	0
T10	34694	31756	0	0
T11	0	629084	0	0
T12	0	677368	0	0
T13	2647272	643821	0	0
T14	0	160636	0	0
T17	0	102165	0	0
T29	714208	95051	0	0
T40	0	1290248	0	0
T46	0	11295	0	0
T51	993432	247189	0	0
T52	957316	238253	0	0
T58	197556	24547	0	0
T65	0	88257	0	0
T66	0	607	0	0
T67	0	9352	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1980837404	1980085308	0	0
T1	2369584	2369200	0	0
T2	219960	219564	0	0
T3	492788	492384	0	0
T7	134284	133952	0	0
T8	2461340	2460996	0	0
T13	2647272	2646924	0	0
T29	714208	713824	0	0
T51	993432	993068	0	0
T52	957316	956972	0	0
T58	197556	197320	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1980837404	1980085308	0	0
T1	2369584	2369200	0	0
T2	219960	219564	0	0
T3	492788	492384	0	0
T7	134284	133952	0	0
T8	2461340	2460996	0	0
T13	2647272	2646924	0	0
T29	714208	713824	0	0
T51	993432	993068	0	0
T52	957316	956972	0	0
T58	197556	197320	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1980837404	1980085308	0	0
T1	2369584	2369200	0	0
T2	219960	219564	0	0
T3	492788	492384	0	0
T7	134284	133952	0	0
T8	2461340	2460996	0	0
T13	2647272	2646924	0	0
T29	714208	713824	0	0
T51	993432	993068	0	0
T52	957316	956972	0	0
T58	197556	197320	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1980837404	605980698	0	0
T1	1184792	850088	0	0
T2	219960	20422	0	0
T3	492788	356850	0	0
T7	134284	10766	0	0
T8	2461340	612910	0	0
T9	0	317540	0	0
T10	34694	31756	0	0
T11	0	629084	0	0
T12	0	677368	0	0
T13	2647272	643821	0	0
T14	0	160636	0	0
T17	0	102165	0	0
T29	714208	95051	0	0
T40	0	1290248	0	0
T46	0	11295	0	0
T51	993432	247189	0	0
T52	957316	238253	0	0
T58	197556	24547	0	0
T65	0	88257	0	0
T66	0	607	0	0
T67	0	9352	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T10

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T9,T11
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T10

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T10
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495209351	40372114	0	0
DepthKnown_A	495209351	495021327	0	0
RvalidKnown_A	495209351	495021327	0	0
WreadyKnown_A	495209351	495021327	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	495209351	40372114	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	40372114	0	0
T1	592396	287520	0	0
T2	54990	0	0	0
T3	123197	237035	0	0
T7	33571	0	0	0
T8	615335	0	0	0
T9	0	39910	0	0
T10	0	15607	0	0
T11	0	208945	0	0
T12	0	213073	0	0
T13	661818	0	0	0
T29	178552	0	0	0
T40	0	417121	0	0
T51	248358	0	0	0
T52	239329	0	0	0
T58	49389	0	0	0
T65	0	7453	0	0
T67	0	9352	0	0
T68	0	2918	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	40372114	0	0
T1	592396	287520	0	0
T2	54990	0	0	0
T3	123197	237035	0	0
T7	33571	0	0	0
T8	615335	0	0	0
T9	0	39910	0	0
T10	0	15607	0	0
T11	0	208945	0	0
T12	0	213073	0	0
T13	661818	0	0	0
T29	178552	0	0	0
T40	0	417121	0	0
T51	248358	0	0	0
T52	239329	0	0	0
T58	49389	0	0	0
T65	0	7453	0	0
T67	0	9352	0	0
T68	0	2918	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T14,T18

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T7,T13
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T7,T13
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T14,T15,T16
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T13

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T7,T13
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T13

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T14,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T13

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T14,T18

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T13
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T14,T18
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T7,T13

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T13

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_txfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495209351	151921604	0	0
DepthKnown_A	495209351	495021327	0	0
RvalidKnown_A	495209351	495021327	0	0
WreadyKnown_A	495209351	495021327	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	495209351	151921604	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	151921604	0	0
T2	54990	30038	0	0
T3	123197	0	0	0
T7	33571	18505	0	0
T8	615335	0	0	0
T10	17347	0	0	0
T13	661818	552954	0	0
T14	0	487582	0	0
T17	0	222605	0	0
T18	0	503109	0	0
T29	178552	77245	0	0
T51	248358	0	0	0
T52	239329	0	0	0
T58	49389	22280	0	0
T59	0	52620	0	0
T60	0	35154	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	151921604	0	0
T2	54990	30038	0	0
T3	123197	0	0	0
T7	33571	18505	0	0
T8	615335	0	0	0
T10	17347	0	0	0
T13	661818	552954	0	0
T14	0	487582	0	0
T17	0	222605	0	0
T18	0	503109	0	0
T29	178552	77245	0	0
T51	248358	0	0	0
T52	239329	0	0	0
T58	49389	22280	0	0
T59	0	52620	0	0
T60	0	35154	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T40

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T56,T57
1	0	1	Covered	T1,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T40

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T40
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_fmtfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495209351	180050753	0	0
DepthKnown_A	495209351	495021327	0	0
RvalidKnown_A	495209351	495021327	0	0
WreadyKnown_A	495209351	495021327	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	495209351	180050753	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	180050753	0	0
T1	592396	562568	0	0
T2	54990	0	0	0
T3	123197	119815	0	0
T7	33571	0	0	0
T8	615335	0	0	0
T9	0	277630	0	0
T10	0	16149	0	0
T11	0	420139	0	0
T12	0	464295	0	0
T13	661818	0	0	0
T29	178552	0	0	0
T40	0	873127	0	0
T46	0	11295	0	0
T51	248358	0	0	0
T52	239329	0	0	0
T58	49389	0	0	0
T65	0	80804	0	0
T66	0	607	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	180050753	0	0
T1	592396	562568	0	0
T2	54990	0	0	0
T3	123197	119815	0	0
T7	33571	0	0	0
T8	615335	0	0	0
T9	0	277630	0	0
T10	0	16149	0	0
T11	0	420139	0	0
T12	0	464295	0	0
T13	661818	0	0	0
T29	178552	0	0	0
T40	0	873127	0	0
T46	0	11295	0	0
T51	248358	0	0	0
T52	239329	0	0	0
T58	49389	0	0	0
T65	0	80804	0	0
T66	0	607	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Covered	Percent
Conditions	26	23	88.46
Logical	26	23	88.46
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (7'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T51,T52

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((7'(gen_normal_fifo.wptr_value) - 7'(gen_normal_fifo.rptr_value))) : (((7'(Depth) - 7'(gen_normal_fifo.rptr_value)) + 7'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T49,T50
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T62,T63,T64
1	0	1	Covered	T2,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T51,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T51,T52

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T51,T52
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T7,T8

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_i2c_acqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495209351	233636227	0	0
DepthKnown_A	495209351	495021327	0	0
RvalidKnown_A	495209351	495021327	0	0
WreadyKnown_A	495209351	495021327	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	495209351	233636227	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	233636227	0	0
T2	54990	20422	0	0
T3	123197	0	0	0
T7	33571	10766	0	0
T8	615335	612910	0	0
T10	17347	0	0	0
T13	661818	643821	0	0
T14	0	160636	0	0
T17	0	102165	0	0
T29	178552	95051	0	0
T51	248358	247189	0	0
T52	239329	238253	0	0
T58	49389	24547	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	495021327	0	0
T1	592396	592300	0	0
T2	54990	54891	0	0
T3	123197	123096	0	0
T7	33571	33488	0	0
T8	615335	615249	0	0
T13	661818	661731	0	0
T29	178552	178456	0	0
T51	248358	248267	0	0
T52	239329	239243	0	0
T58	49389	49330	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	495209351	233636227	0	0
T2	54990	20422	0	0
T3	123197	0	0	0
T7	33571	10766	0	0
T8	615335	612910	0	0
T10	17347	0	0	0
T13	661818	643821	0	0
T14	0	160636	0	0
T17	0	102165	0	0
T29	178552	95051	0	0
T51	248358	247189	0	0
T52	239329	238253	0	0
T58	49389	24547	0	0