Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

235905

1

T1

1216

T10

960

T11

694

ack

19657

1

T1

38

T10

30

T11

111

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	915	1			T1	3		T10	5		T64	1
high	52326	1			T1	255		T10	214		T11	144
med	94911	1			T1	464		T10	400		T11	301
sml	106427	1			T1	524		T10	365		T11	358
all_zero	983	1			T1	8		T10	6		T11	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127323

1

T1

638

T10

494

T11

397

auto[1]

128239

1

T1

616

T10

496

T11

408

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174866

1

T1

857

T10

676

T11

580

auto[1]

80696

1

T1

397

T10

314

T11

225

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244191

1

T1

1236

T10

976

T11

758

auto[1]

11371

1

T1

18

T10

14

T11

47

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241151

1

T1

1217

T10

961

T11

702

auto[1]

14411

1

T1

37

T10

29

T11

103

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242954

1

T1

1218

T10

962

T11

711

auto[1]

12608

1

T1

36

T10

28

T11

94

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127323

1

T1

638

T10

494

T11

397

auto[1]

128239

1

T1

616

T10

496

T11

408

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174866

1

T1

857

T10

676

T11

580

auto[1]

80696

1

T1

397

T10

314

T11

225

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244191

1

T1

1236

T10

976

T11

758

auto[1]

11371

1

T1

18

T10

14

T11

47

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241151

1

T1

1217

T10

961

T11

702

auto[1]

14411

1

T1

37

T10

29

T11

103

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242954

1

T1

1218

T10

962

T11

711

auto[1]

12608

1

T1

36

T10

28

T11

94

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

15

1

T180

1

T181

1

T182

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

5

1

T183

1

T184

2

T185

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T186

1

T187

1

T188

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

579

1

T11

4

T64

2

T12

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

292

1

T1

1

T10

1

T64

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

324

1

T1

1

T11

3

T64

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1080

1

T1

4

T10

1

T11

6

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

565

1

T1

1

T10

5

T11

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

593

1

T1

4

T10

1

T11

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1121

1

T1

6

T10

2

T11

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

573

1

T1

3

T10

1

T11

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

604

1

T1

2

T10

2

T11

5

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

18

1

T37

1

T133

1

T189

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

12

1

T11

1

T190

1

T191

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

9

1

T11

1

T135

1

T152

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	74488	1			T1	403		T10	303		T11	202
write_address_byte	14411	1			T1	37		T10	29		T11	103
read_with_ack	3942	1			T61	12		T62	12		T37	40
read_with_nack	7429	1			T1	18		T10	14		T11	47
stop_byte	12608	1			T1	36		T10	28		T11	94
write_address_byte_nak	9296	1			T1	34		T10	26		T11	76
data_byte_nack	235905	1			T1	1216		T10	960		T11	694
stop_byte_nack	8967	1			T1	33		T10	25		T11	71
nakok_byte_nack	118465	1			T1	595		T10	485		T11	355
nakok_addr_byte_nack	4779	1			T1	18		T10	11		T11	40