Group : i2c_env_pkg::i2c_timing_param_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : i2c_env_pkg::i2c_timing_param_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
75.00 52.50 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

10 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.t_f_cg 50.00 1 100 1 64 64
i2c_env_pkg.t_r_cg 50.00 1 100 1 64 64
i2c_env_pkg.thd_dat_cg 50.00 1 100 1 64 64
i2c_env_pkg.thd_sta_cg 50.00 1 100 1 64 64
i2c_env_pkg.thigh_cg 50.00 1 100 1 64 64
i2c_env_pkg.tlow_cg 50.00 1 100 1 64 64
i2c_env_pkg.tsu_dat_cg 50.00 1 100 1 64 64
i2c_env_pkg.tsu_sta_cg 50.00 1 100 1 64 64
i2c_env_pkg.tsu_sto_cg 50.00 1 100 1 64 64
i2c_env_pkg.t_buf_cg 75.00 1 100 1 64 64




Group Instance : i2c_env_pkg.t_f_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.t_f_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.t_f_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.t_r_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.t_r_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.t_r_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.thd_dat_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.thd_dat_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.thd_dat_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.thd_sta_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.thd_sta_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.thd_sta_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.thigh_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.thigh_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.thigh_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.tlow_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.tlow_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.tlow_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.tsu_dat_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.tsu_dat_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.tsu_dat_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.tsu_sta_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.tsu_sta_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.tsu_sta_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.tsu_sto_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.tsu_sto_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 2 2 50.00


Variables for Group Instance i2c_env_pkg.tsu_sto_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 2 2 50.00 100 1 1 0



Group Instance : i2c_env_pkg.t_buf_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
75.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.t_buf_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 1 3 75.00


Variables for Group Instance i2c_env_pkg.t_buf_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_timing_param 4 1 3 75.00 100 1 1 0


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
med 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
low 14294 1 T1 32 T10 26 T7 1
zero 23 1 T11 1 T151 1 T152 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
med 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
low 14309 1 T1 32 T10 26 T7 1
zero 8 1 T153 1 T135 1 T154 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 26 1 T155 1 T130 1 T153 1
low 15146 1 T1 38 T10 29 T7 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 15 1 T155 1 T153 1 T81 1
low 15385 1 T1 26 T10 21 T7 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 27 1 T155 1 T130 1 T153 1
low 18264 1 T1 34 T10 28 T7 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 27 1 T155 1 T130 1 T153 1
low 18264 1 T1 34 T10 28 T7 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
med 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
low 15166 1 T1 38 T10 29 T7 1
zero 6 1 T11 1 T32 1 T151 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 26 1 T155 1 T130 1 T153 1
low 15374 1 T1 26 T10 21 T7 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1
zero 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 15 1 T155 1 T153 1 T81 1
low 18669 1 T1 38 T10 28 T7 1


Summary for Variable cp_timing_param

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for cp_timing_param

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
high 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
med 26 1 T155 1 T130 1 T153 1
low 17801 1 T1 33 T10 25 T7 1
zero 857 1 T1 5 T10 3 T11 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%