Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49339637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17880524

1

T20

191

T21

24

T22

817

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	59222211	1			T20	349		T21	20		T22	208
values[0x0]	3998043	1			T20	101		T21	14		T22	296
values[0x1]	3999907	1			T20	98		T21	6		T22	351

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36331391	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30888770

1

T20

302

T21

26

T22

836

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	232566	1			T20	2		T25	6		T29	5
valid_sources[0x01]	552166	1			T20	1		T22	10		T25	7
valid_sources[0x02]	221712	1			T20	6		T22	12		T25	7
valid_sources[0x03]	240588	1			T20	1		T25	10		T29	10
valid_sources[0x04]	398345	1			T20	4		T25	7		T29	9
valid_sources[0x05]	248267	1			T20	2		T24	1		T25	5
valid_sources[0x06]	242507	1			T25	8		T29	6		T73	1
valid_sources[0x07]	224826	1			T20	3		T22	7		T25	9
valid_sources[0x08]	250369	1			T22	1		T25	2		T29	1
valid_sources[0x09]	219077	1			T20	3		T22	10		T25	2
valid_sources[0x0a]	244708	1			T20	3		T23	2		T25	9
valid_sources[0x0b]	229831	1			T20	2		T24	1		T25	3
valid_sources[0x0c]	239901	1			T20	2		T22	5		T25	12
valid_sources[0x0d]	255463	1			T20	3		T22	8		T25	12
valid_sources[0x0e]	282452	1			T20	3		T22	1		T25	3
valid_sources[0x0f]	412465	1			T20	2		T24	1		T25	8
valid_sources[0x10]	285183	1			T20	4		T25	7		T27	2
valid_sources[0x11]	269885	1			T20	3		T22	1		T25	6
valid_sources[0x12]	231003	1			T20	1		T22	4		T25	7
valid_sources[0x13]	201058	1			T22	3		T25	5		T95	1
valid_sources[0x14]	312794	1			T22	7		T25	9		T29	6
valid_sources[0x15]	239476	1			T20	4		T22	4		T25	6
valid_sources[0x16]	269762	1			T20	2		T22	1		T25	8
valid_sources[0x17]	249080	1			T20	3		T25	7		T28	1
valid_sources[0x18]	211587	1			T20	1		T22	5		T24	1
valid_sources[0x19]	206216	1			T20	1		T25	10		T29	6
valid_sources[0x1a]	546236	1			T20	1		T22	1		T25	13
valid_sources[0x1b]	248688	1			T20	2		T22	6		T25	6
valid_sources[0x1c]	255535	1			T25	6		T29	3		T74	2
valid_sources[0x1d]	228586	1			T22	8		T24	1		T25	6
valid_sources[0x1e]	326644	1			T25	4		T29	7		T73	1
valid_sources[0x1f]	357660	1			T20	1		T25	8		T29	3
valid_sources[0x20]	241341	1			T24	1		T25	6		T29	6
valid_sources[0x21]	230021	1			T20	2		T22	3		T25	10
valid_sources[0x22]	241004	1			T20	4		T25	5		T29	7
valid_sources[0x23]	297109	1			T20	3		T22	4		T25	4
valid_sources[0x24]	236313	1			T22	4		T25	11		T29	4
valid_sources[0x25]	218437	1			T20	2		T25	7		T29	2
valid_sources[0x26]	219271	1			T25	10		T29	3		T73	1
valid_sources[0x27]	216540	1			T20	1		T22	3		T25	4
valid_sources[0x28]	208712	1			T20	3		T25	9		T108	2
valid_sources[0x29]	229387	1			T22	9		T25	5		T29	1
valid_sources[0x2a]	210977	1			T20	3		T25	10		T29	4
valid_sources[0x2b]	220150	1			T20	6		T22	5		T25	8
valid_sources[0x2c]	515602	1			T20	5		T22	9		T25	3
valid_sources[0x2d]	242263	1			T20	5		T25	6		T29	1
valid_sources[0x2e]	234958	1			T20	1		T22	1		T25	11
valid_sources[0x2f]	235479	1			T20	3		T24	1		T25	3
valid_sources[0x30]	250195	1			T20	3		T25	9		T29	6
valid_sources[0x31]	276055	1			T20	4		T25	7		T29	2
valid_sources[0x32]	248684	1			T20	3		T22	1		T25	5
valid_sources[0x33]	214437	1			T20	1		T25	10		T79	7
valid_sources[0x34]	228227	1			T20	2		T25	4		T27	3
valid_sources[0x35]	207197	1			T20	5		T25	10		T27	1
valid_sources[0x36]	306525	1			T20	1		T25	5		T29	10
valid_sources[0x37]	207523	1			T25	6		T29	20		T73	2
valid_sources[0x38]	205204	1			T20	2		T22	11		T24	1
valid_sources[0x39]	234540	1			T20	1		T25	4		T73	1
valid_sources[0x3a]	320414	1			T20	1		T22	9		T25	15
valid_sources[0x3b]	240242	1			T20	2		T22	2		T25	10
valid_sources[0x3c]	221284	1			T22	7		T25	11		T29	4
valid_sources[0x3d]	219546	1			T22	13		T25	10		T73	3
valid_sources[0x3e]	219483	1			T20	3		T22	1		T25	7
valid_sources[0x3f]	229305	1			T25	8		T73	2		T74	3
valid_sources[0x40]	223379	1			T20	5		T22	2		T25	6
valid_sources[0x41]	204021	1			T20	2		T24	1		T25	9
valid_sources[0x42]	222874	1			T22	8		T25	4		T28	7
valid_sources[0x43]	204699	1			T20	4		T25	3		T29	4
valid_sources[0x44]	246835	1			T20	6		T25	8		T29	2
valid_sources[0x45]	209747	1			T20	1		T23	3		T24	1
valid_sources[0x46]	220867	1			T20	3		T22	1		T25	10
valid_sources[0x47]	224842	1			T20	3		T22	2		T25	11
valid_sources[0x48]	227580	1			T25	12		T28	2		T29	2
valid_sources[0x49]	212448	1			T22	9		T25	10		T28	3
valid_sources[0x4a]	230583	1			T20	5		T22	8		T25	10
valid_sources[0x4b]	225202	1			T22	12		T24	1		T25	15
valid_sources[0x4c]	231724	1			T20	1		T25	11		T29	8
valid_sources[0x4d]	245541	1			T20	1		T22	2		T25	12
valid_sources[0x4e]	300548	1			T22	3		T25	7		T29	3
valid_sources[0x4f]	271786	1			T20	1		T22	12		T25	3
valid_sources[0x50]	400644	1			T20	3		T22	1		T25	14
valid_sources[0x51]	221800	1			T20	2		T25	12		T29	10
valid_sources[0x52]	228038	1			T20	2		T22	6		T24	1
valid_sources[0x53]	227230	1			T22	6		T24	1		T25	7
valid_sources[0x54]	290306	1			T22	10		T25	5		T27	2
valid_sources[0x55]	225532	1			T20	3		T22	1		T25	8
valid_sources[0x56]	442933	1			T20	6		T22	7		T25	4
valid_sources[0x57]	321856	1			T20	3		T22	16		T25	11
valid_sources[0x58]	231588	1			T20	3		T24	1		T25	4
valid_sources[0x59]	244163	1			T20	2		T22	2		T25	11
valid_sources[0x5a]	230922	1			T20	4		T24	1		T25	12
valid_sources[0x5b]	241394	1			T22	12		T25	8		T29	8
valid_sources[0x5c]	227573	1			T20	5		T22	1		T25	7
valid_sources[0x5d]	223284	1			T20	1		T25	6		T26	18
valid_sources[0x5e]	1198197	1			T20	3		T22	18		T25	3
valid_sources[0x5f]	243619	1			T20	1		T25	10		T29	1
valid_sources[0x60]	217115	1			T20	1		T25	10		T29	3
valid_sources[0x61]	226818	1			T25	3		T29	12		T73	3
valid_sources[0x62]	241369	1			T20	2		T22	3		T25	7
valid_sources[0x63]	230226	1			T20	1		T22	4		T25	9
valid_sources[0x64]	231404	1			T25	7		T29	1		T73	3
valid_sources[0x65]	241928	1			T20	4		T22	5		T25	11
valid_sources[0x66]	220815	1			T25	5		T29	1		T108	1
valid_sources[0x67]	234245	1			T20	2		T22	5		T25	2
valid_sources[0x68]	294019	1			T20	2		T22	4		T23	2
valid_sources[0x69]	275817	1			T20	1		T25	5		T27	2
valid_sources[0x6a]	217442	1			T25	7		T29	7		T95	1
valid_sources[0x6b]	238441	1			T20	1		T22	2		T24	1
valid_sources[0x6c]	246681	1			T20	2		T22	8		T25	1
valid_sources[0x6d]	217381	1			T20	1		T25	6		T29	8
valid_sources[0x6e]	219033	1			T20	4		T22	1		T25	10
valid_sources[0x6f]	243885	1			T20	1		T22	11		T25	6
valid_sources[0x70]	225940	1			T20	1		T22	16		T25	8
valid_sources[0x71]	208239	1			T20	6		T22	12		T24	1
valid_sources[0x72]	236714	1			T20	3		T22	1		T24	1
valid_sources[0x73]	272669	1			T20	1		T25	13		T29	1
valid_sources[0x74]	241115	1			T22	2		T25	9		T29	10
valid_sources[0x75]	385699	1			T20	2		T22	4		T25	5
valid_sources[0x76]	307148	1			T22	6		T25	11		T29	10
valid_sources[0x77]	248268	1			T20	4		T22	12		T25	5
valid_sources[0x78]	220569	1			T20	1		T22	6		T25	5
valid_sources[0x79]	252722	1			T20	3		T25	6		T29	2
valid_sources[0x7a]	240641	1			T20	9		T25	5		T29	10
valid_sources[0x7b]	548784	1			T20	2		T22	4		T24	1
valid_sources[0x7c]	257805	1			T22	4		T25	6		T29	3
valid_sources[0x7d]	214165	1			T20	1		T25	4		T29	3
valid_sources[0x7e]	240599	1			T20	2		T22	2		T25	6
valid_sources[0x7f]	208185	1			T22	7		T25	15		T29	7
valid_sources[0x80]	226286	1			T20	1		T22	3		T25	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14816019

1

T20

56

T21

14

T22

204

values[0x0]

all_enables

biggest_size

1971571

1

T20

73

T21

9

T22

292

values[0x1]

all_enables

biggest_size

1092934

1

T20

62

T21

1

T22

321