Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fifo_level_cg

Group : i2c_env_pkg::i2c_fifo_level_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	91.18	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.rx_fifo_level_cg	82.35	1	100	1	64	64
i2c_env_pkg.fmt_fifo_level_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
82.35	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	3	5	62.50

Variables for Group Instance i2c_env_pkg.rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	0	5	100.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	3	5	62.50	100	1	1	0

---

Group Instance : i2c_env_pkg.fmt_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.fmt_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	0	5	100.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	0	8	100.00	100	1	1	0

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fifolvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	33143	1			T1	30		T10	26		T7	19
lvl[1]	153	1			T1	1		T10	3		T64	1
lvl[4]	263	1			T1	2		T10	1		T64	1
lvl[8]	157	1			T1	1		T10	1		T64	1
lvl[16]	172	1			T1	3		T64	1		T51	3

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29783

1

T1

37

T10

31

T7

19

auto[1]

4105

1

T11

60

T12

26

T13

18

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31220

1

T1

36

T10

30

T7

18

auto[1]

2668

1

T1

1

T10

1

T7

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	3	5	62.50	3
Automatically Generated Cross Bins	8	3	5	62.50	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Uncovered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	NUMBER	STATUS
[lvl[1]]	[auto[1]]	0	1	1
[lvl[8] , lvl[16]]	[auto[1]]	--	--	2

Covered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lvl[1]	auto[0]	153	1			T1	1		T10	3		T64	1
lvl[4]	auto[0]	181	1			T1	2		T10	1		T64	1
lvl[4]	auto[1]	82	1			T130	24		T81	28		T200	30
lvl[8]	auto[0]	157	1			T1	1		T10	1		T64	1
lvl[16]	auto[0]	172	1			T1	3		T64	1		T51	3

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fifolvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	31344	1			T1	1		T10	2		T7	19
lvl[1]	1438	1			T1	17		T10	18		T64	10
lvl[4]	388	1			T1	7		T10	4		T64	2
lvl[8]	371	1			T1	6		T10	5		T64	8
lvl[16]	347	1			T1	6		T10	2		T64	1

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27639

1

T1

37

T10

31

T7

19

auto[1]

6249

1

T11

93

T12

27

T13

19

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30857

1

T1

36

T10

30

T7

18

auto[1]

3031

1

T1

1

T10

1

T7

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lvl[1]	auto[0]	1213	1			T1	17		T10	18		T64	10
lvl[1]	auto[1]	225	1			T52	2		T53	2		T130	33
lvl[4]	auto[0]	325	1			T1	7		T10	4		T64	2
lvl[4]	auto[1]	63	1			T52	2		T53	2		T54	2
lvl[8]	auto[0]	332	1			T1	6		T10	5		T64	8
lvl[8]	auto[1]	39	1			T52	4		T54	1		T201	2
lvl[16]	auto[0]	321	1			T1	6		T10	2		T64	1
lvl[16]	auto[1]	26	1			T202	2		T203	24		-	-

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded