Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	531367416	99183	0	0
ctrl_rd_A	531367416	2500	0	0
fifo_ctrl_rd_A	531367416	6085	0	0
host_timeout_ctrl_rd_A	531367416	2151	0	0
intr_enable_rd_A	531367416	4683	0	0
ovrd_rd_A	531367416	3214	0	0
target_id_rd_A	531367416	2431	0	0
timeout_ctrl_rd_A	531367416	2223	0	0
timing0_rd_A	531367416	2237	0	0
timing1_rd_A	531367416	2250	0	0
timing2_rd_A	531367416	2182	0	0
timing3_rd_A	531367416	2283	0	0
timing4_rd_A	531367416	2358	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	99183	0	0
T20	6340	1	0	0
T21	2149	0	0	0
T22	4966	743	0	0
T23	1908	0	0	0
T24	893	0	0	0
T25	14451	0	0	0
T26	1248	0	0	0
T27	1480	0	0	0
T28	1521	0	0	0
T29	10241	7	0	0
T73	0	257	0	0
T74	0	1045	0	0
T78	0	3	0	0
T80	0	280	0	0
T83	0	33	0	0
T85	0	461	0	0
T92	0	4	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	2500	0	0
T78	6221	89	0	0
T80	8119	21	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	55	0	0
T93	0	73	0	0
T107	0	260	0	0
T113	935	0	0	0
T114	0	151	0	0
T127	2066	0	0	0
T129	0	472	0	0
T136	0	8	0	0
T137	0	122	0	0
T138	0	47	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	6085	0	0
T10	0	112	0	0
T51	0	106	0	0
T78	6221	113	0	0
T80	8119	20	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	50	0	0
T113	935	0	0	0
T114	0	145	0	0
T127	2066	0	0	0
T129	0	428	0	0
T133	0	122	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0
T142	0	58	0	0
T143	0	107	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	2151	0	0
T78	6221	39	0	0
T80	8119	4	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	34	0	0
T93	0	28	0	0
T107	0	187	0	0
T113	935	0	0	0
T114	0	142	0	0
T127	2066	0	0	0
T129	0	452	0	0
T136	0	9	0	0
T137	0	50	0	0
T138	0	33	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	4683	0	0
T21	2149	19	0	0
T22	4966	0	0	0
T23	1908	14	0	0
T24	893	0	0	0
T25	14451	0	0	0
T26	1248	0	0	0
T27	1480	26	0	0
T28	1521	0	0	0
T29	10241	0	0	0
T78	0	389	0	0
T80	0	25	0	0
T92	0	113	0	0
T95	904	0	0	0
T114	0	145	0	0
T140	0	17	0	0
T141	0	9	0	0
T144	0	30	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	3214	0	0
T4	0	42	0	0
T5	0	27	0	0
T6	0	89	0	0
T78	6221	101	0	0
T80	8119	17	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	42	0	0
T113	935	0	0	0
T114	0	138	0	0
T127	2066	0	0	0
T129	0	420	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0
T145	0	25	0	0
T146	0	38	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	2431	0	0
T78	6221	92	0	0
T80	8119	10	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	47	0	0
T93	0	99	0	0
T107	0	253	0	0
T113	935	0	0	0
T114	0	176	0	0
T127	2066	0	0	0
T129	0	378	0	0
T136	0	27	0	0
T137	0	112	0	0
T138	0	9	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	2223	0	0
T78	6221	60	0	0
T80	8119	16	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	21	0	0
T93	0	42	0	0
T107	0	229	0	0
T113	935	0	0	0
T114	0	127	0	0
T127	2066	0	0	0
T129	0	419	0	0
T136	0	9	0	0
T137	0	54	0	0
T138	0	32	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	2237	0	0
T78	6221	61	0	0
T80	8119	34	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	52	0	0
T93	0	34	0	0
T107	0	253	0	0
T113	935	0	0	0
T114	0	126	0	0
T127	2066	0	0	0
T129	0	409	0	0
T136	0	11	0	0
T137	0	85	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0
T147	0	3	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	2250	0	0
T78	6221	64	0	0
T80	8119	13	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	39	0	0
T93	0	59	0	0
T107	0	252	0	0
T113	935	0	0	0
T114	0	138	0	0
T127	2066	0	0	0
T129	0	479	0	0
T136	0	13	0	0
T137	0	73	0	0
T138	0	15	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	2182	0	0
T78	6221	75	0	0
T83	1513	0	0	0
T91	2723	0	0	0
T92	5692	27	0	0
T93	0	58	0	0
T107	908601	234	0	0
T114	6519	138	0	0
T129	40752	457	0	0
T136	0	15	0	0
T137	0	71	0	0
T138	0	13	0	0
T141	1545	0	0	0
T148	0	6	0	0
T149	1396	0	0	0
T150	1076	0	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	2283	0	0
T78	6221	65	0	0
T80	8119	11	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	57	0	0
T93	0	55	0	0
T107	0	291	0	0
T113	935	0	0	0
T114	0	154	0	0
T127	2066	0	0	0
T129	0	452	0	0
T136	0	21	0	0
T137	0	60	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0
T147	0	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531367416	2358	0	0
T78	6221	61	0	0
T80	8119	28	0	0
T82	1868	0	0	0
T83	1513	0	0	0
T85	2758	0	0	0
T92	0	16	0	0
T93	0	57	0	0
T107	0	354	0	0
T113	935	0	0	0
T114	0	163	0	0
T127	2066	0	0	0
T129	0	430	0	0
T136	0	9	0	0
T137	0	60	0	0
T139	1207	0	0	0
T140	1253	0	0	0
T141	1545	0	0	0
T147	0	5	0	0