Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

231888

1

T3

85

T9

1088

T10

333

ack

18955

1

T2

40

T3

1

T9

34

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	948	1			T2	1		T9	4		T10	1
high	51416	1			T2	3		T3	20		T9	227
med	93786	1			T2	4		T3	36		T9	429
sml	103773	1			T2	32		T3	29		T9	455
all_zero	920	1			T3	1		T9	7		T11	14

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125254

1

T2

22

T3

49

T9

557

auto[1]

125589

1

T2

18

T3

37

T9

565

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171495

1

T2

25

T3

54

T9

782

auto[1]

79348

1

T2

15

T3

32

T9

340

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240023

1

T2

13

T3

86

T9

1106

auto[1]

10820

1

T2

27

T9

16

T10

75

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236927

1

T2

27

T3

85

T9

1089

auto[1]

13916

1

T2

13

T3

1

T9

33

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238580

1

T2

28

T3

85

T9

1090

auto[1]

12263

1

T2

12

T3

1

T9

32

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125254

1

T2

22

T3

49

T9

557

auto[1]

125589

1

T2

18

T3

37

T9

565

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171495

1

T2

25

T3

54

T9

782

auto[1]

79348

1

T2

15

T3

32

T9

340

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240023

1

T2

13

T3

86

T9

1106

auto[1]

10820

1

T2

27

T9

16

T10

75

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236927

1

T2

27

T3

85

T9

1089

auto[1]

13916

1

T2

13

T3

1

T9

33

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238580

1

T2

28

T3

85

T9

1090

auto[1]

12263

1

T2

12

T3

1

T9

32

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

14

1

T102

1

T152

1

T153

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T154

1

T155

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T156

1

T157

1

T158

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

609

1

T9

1

T10

4

T32

5

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

311

1

T10

1

T11

5

T12

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

338

1

T32

5

T11

6

T12

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1150

1

T9

5

T10

5

T32

9

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

560

1

T10

3

T32

3

T60

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

556

1

T9

1

T10

2

T32

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1162

1

T9

4

T10

6

T32

15

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

521

1

T9

2

T10

2

T32

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

582

1

T9

3

T10

5

T32

5

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

15

1

T126

1

T127

1

T159

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

17

1

T13

1

T160

1

T161

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

9

1

T67

1

T162

1

T163

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	73251	1			T3	32		T9	357		T10	81
write_address_byte	13916	1			T2	13		T3	1		T9	33
read_with_ack	3717	1			T2	15		T10	40		T32	29
read_with_nack	7103	1			T2	12		T9	16		T10	35
stop_byte	12263	1			T2	12		T3	1		T9	32
write_address_byte_nak	9107	1			T9	30		T10	53		T32	84
data_byte_nack	231888	1			T3	85		T9	1088		T10	333
stop_byte_nack	8941	1			T3	1		T9	29		T10	41
nakok_byte_nack	116096	1			T3	37		T9	546		T10	178
nakok_addr_byte_nack	4524	1			T9	17		T10	25		T32	38