Unified Coverage Report :: Group :: i2c_env_pkg::i2c_interrupts_cg

Group : i2c_env_pkg::i2c_interrupts_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.interrupts_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.interrupts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.interrupts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	0	45	100.00

Variables for Group Instance i2c_env_pkg.interrupts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_full	2	0	2	100.00	100	1	1	2
cp_acq_full_test	1	0	1	100.00	100	1	1	2
cp_cmd_complete	2	0	2	100.00	100	1	1	2
cp_cmd_complete_test	1	0	1	100.00	100	1	1	2
cp_fmt_overflow	2	0	2	100.00	100	1	1	2
cp_fmt_overflow_test	1	0	1	100.00	100	1	1	2
cp_fmt_threshold	2	0	2	100.00	100	1	1	2
cp_fmt_threshold_test	1	0	1	100.00	100	1	1	2
cp_host_timeout	2	0	2	100.00	100	1	1	2
cp_host_timeout_test	1	0	1	100.00	100	1	1	2
cp_nak	2	0	2	100.00	100	1	1	2
cp_nak_test	1	0	1	100.00	100	1	1	2
cp_rx_overflow	2	0	2	100.00	100	1	1	2
cp_rx_overflow_test	1	0	1	100.00	100	1	1	2
cp_rx_threshold	2	0	2	100.00	100	1	1	2
cp_rx_threshold_test	1	0	1	100.00	100	1	1	2
cp_scl_interference	2	0	2	100.00	100	1	1	2
cp_scl_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_interference	2	0	2	100.00	100	1	1	2
cp_sda_interference_test	1	0	1	100.00	100	1	1	2
cp_sda_unstable	2	0	2	100.00	100	1	1	2
cp_sda_unstable_test	1	0	1	100.00	100	1	1	2
cp_stretch_timeout	2	0	2	100.00	100	1	1	2
cp_stretch_timeout_test	1	0	1	100.00	100	1	1	2
cp_tx_overflow	2	0	2	100.00	100	1	1	2
cp_tx_overflow_test	1	0	1	100.00	100	1	1	2
cp_tx_stretch	2	0	2	100.00	100	1	1	2
cp_tx_stretch_test	1	0	1	100.00	100	1	1	2
cp_unexp_stop	2	0	2	100.00	100	1	1	2
cp_unexp_stop_test	1	0	1	100.00	100	1	1	2

Summary for Variable cp_acq_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3880233

1

T22

10

T25

6

T61

10

auto[1]

3878752

1

T22

10

T25

3

T61

6

---

Summary for Variable cp_acq_full_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_acq_full_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

325

1

T22

6

T25

3

T61

6

---

Summary for Variable cp_cmd_complete

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cmd_complete

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3880214

1

T22

7

T25

15

T61

8

auto[1]

3878714

1

T22

6

T25

2

T61

6

---

Summary for Variable cp_cmd_complete_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_cmd_complete_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

311

1

T22

6

T25

3

T61

3

---

Summary for Variable cp_fmt_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmt_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3879988

1

T22

10

T25

5

T61

6

auto[1]

3878972

1

T22

12

T25

5

T61

8

---

Summary for Variable cp_fmt_overflow_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_fmt_overflow_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

297

1

T22

5

T25

5

T61

5

---

Summary for Variable cp_fmt_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmt_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3881197

1

T22

14

T25

8

T61

4

auto[1]

3877658

1

T22

15

T25

7

T61

11

---

Summary for Variable cp_fmt_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_fmt_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

294

1

T22

3

T25

4

T61

4

---

Summary for Variable cp_host_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_host_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3878374

1

T22

9

T25

2

T61

11

auto[1]

3880592

1

T22

6

T25

2

T61

7

---

Summary for Variable cp_host_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_host_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

274

1

T22

5

T25

4

T61

2

---

Summary for Variable cp_nak

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nak

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3883520

1

T22

4

T25

13

T61

9

auto[1]

3875449

1

T22

17

T25

7

T61

15

---

Summary for Variable cp_nak_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_nak_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

284

1

T22

7

T25

3

T61

8

---

Summary for Variable cp_rx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3882028

1

T22

9

T25

2

T61

4

auto[1]

3876871

1

T22

1

T25

3

T61

10

---

Summary for Variable cp_rx_overflow_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_overflow_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

263

1

T22

2

T25

3

T61

8

---

Summary for Variable cp_rx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3881117

1

T22

4

T25

18

T61

10

auto[1]

3877765

1

T22

10

T25

4

T61

5

---

Summary for Variable cp_rx_threshold_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_rx_threshold_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

292

1

T22

6

T25

2

T61

3

---

Summary for Variable cp_scl_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_scl_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3882637

1

T22

15

T25

9

T61

13

auto[1]

3876286

1

T22

6

T25

9

T61

10

---

Summary for Variable cp_scl_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_scl_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

278

1

T22

2

T25

3

T61

2

---

Summary for Variable cp_sda_interference

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_interference

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3880423

1

T22

8

T25

11

T61

17

auto[1]

3878598

1

T22

2

T25

10

T61

8

---

Summary for Variable cp_sda_interference_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_interference_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

289

1

T22

5

T25

5

T61

3

---

Summary for Variable cp_sda_unstable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sda_unstable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3883312

1

T22

9

T25

7

T61

9

auto[1]

3875673

1

T22

9

T25

1

T61

2

---

Summary for Variable cp_sda_unstable_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_sda_unstable_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

275

1

T22

3

T25

5

T61

5

---

Summary for Variable cp_stretch_timeout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stretch_timeout

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3877790

1

T22

9

T25

19

T61

7

auto[1]

3881167

1

T22

9

T25

4

T61

10

---

Summary for Variable cp_stretch_timeout_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_stretch_timeout_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

270

1

T22

5

T25

3

T61

4

---

Summary for Variable cp_tx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3880932

1

T22

7

T25

10

T61

8

auto[1]

3877964

1

T22

3

T25

1

T61

14

---

Summary for Variable cp_tx_overflow_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_overflow_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

261

1

T22

4

T25

2

T61

3

---

Summary for Variable cp_tx_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_stretch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3879874

1

T22

8

T25

6

T61

9

auto[1]

3879006

1

T22

8

T25

4

T61

5

---

Summary for Variable cp_tx_stretch_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_tx_stretch_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

300

1

T22

3

T25

6

T61

5

---

Summary for Variable cp_unexp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unexp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3881313

1

T22

6

T25

2

T61

15

auto[1]

3877615

1

T22

10

T25

9

T61

4

---

Summary for Variable cp_unexp_stop_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	0	1	100.00

Automatically Generated Bins for cp_unexp_stop_test

Excluded/Illegal bins

NAME	COUNT	STATUS
dis	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

245

1

T22

6

T25

5

T61

3