Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49496358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16579780

1

T17

151

T18

356

T19

1148

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57879543	1			T17	70		T18	160		T19	959
values[0x0]	4099400	1			T17	64		T18	103		T19	462
values[0x1]	4097195	1			T17	77		T18	94		T19	494

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36381276	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29694862

1

T17

180

T18

356

T19

1260

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	220744	1			T17	21		T19	7		T20	3
valid_sources[0x01]	364752	1			T19	8		T20	7		T26	3
valid_sources[0x02]	235906	1			T19	2		T20	2		T21	1
valid_sources[0x03]	212009	1			T19	14		T20	1		T26	3
valid_sources[0x04]	224934	1			T18	3		T19	5		T20	8
valid_sources[0x05]	197933	1			T18	2		T19	6		T20	4
valid_sources[0x06]	250647	1			T18	1		T19	3		T20	3
valid_sources[0x07]	217426	1			T18	3		T19	5		T20	9
valid_sources[0x08]	220592	1			T19	6		T20	5		T24	1
valid_sources[0x09]	227595	1			T19	9		T20	1		T24	3
valid_sources[0x0a]	208145	1			T18	3		T19	8		T20	2
valid_sources[0x0b]	203804	1			T18	17		T19	7		T20	2
valid_sources[0x0c]	214722	1			T17	15		T19	3		T20	9
valid_sources[0x0d]	225288	1			T19	8		T20	6		T26	2
valid_sources[0x0e]	203674	1			T17	4		T19	12		T20	6
valid_sources[0x0f]	330136	1			T19	6		T20	4		T26	18
valid_sources[0x10]	319532	1			T19	10		T20	2		T26	3
valid_sources[0x11]	231592	1			T18	1		T19	5		T20	10
valid_sources[0x12]	207045	1			T19	7		T20	5		T26	2
valid_sources[0x13]	228544	1			T19	6		T20	7		T21	3
valid_sources[0x14]	223276	1			T19	10		T20	5		T21	1
valid_sources[0x15]	220739	1			T19	6		T20	3		T26	3
valid_sources[0x16]	268384	1			T18	2		T19	10		T20	2
valid_sources[0x17]	231990	1			T17	3		T19	11		T20	3
valid_sources[0x18]	227722	1			T18	5		T19	8		T20	3
valid_sources[0x19]	247973	1			T17	2		T18	3		T19	9
valid_sources[0x1a]	224083	1			T18	2		T19	10		T21	7
valid_sources[0x1b]	217761	1			T19	13		T20	5		T21	1
valid_sources[0x1c]	220061	1			T19	7		T20	2		T21	4
valid_sources[0x1d]	237508	1			T18	3		T19	7		T20	4
valid_sources[0x1e]	219540	1			T18	3		T19	11		T20	5
valid_sources[0x1f]	207854	1			T18	1		T19	1		T20	4
valid_sources[0x20]	221944	1			T18	4		T19	7		T20	4
valid_sources[0x21]	224835	1			T19	8		T20	2		T26	10
valid_sources[0x22]	199768	1			T19	12		T20	4		T26	8
valid_sources[0x23]	201296	1			T17	3		T19	10		T20	1
valid_sources[0x24]	224461	1			T19	8		T20	7		T26	2
valid_sources[0x25]	229461	1			T19	8		T20	2		T21	1
valid_sources[0x26]	206391	1			T19	5		T20	2		T26	4
valid_sources[0x27]	212192	1			T19	7		T20	2		T26	1
valid_sources[0x28]	206155	1			T19	12		T20	4		T68	2
valid_sources[0x29]	210758	1			T19	13		T20	3		T26	3
valid_sources[0x2a]	226938	1			T17	1		T19	7		T20	5
valid_sources[0x2b]	201352	1			T19	8		T20	1		T26	9
valid_sources[0x2c]	206439	1			T17	11		T19	9		T20	2
valid_sources[0x2d]	232383	1			T19	5		T20	5		T21	3
valid_sources[0x2e]	196357	1			T19	4		T20	6		T68	5
valid_sources[0x2f]	213659	1			T19	8		T20	4		T68	1
valid_sources[0x30]	220166	1			T17	1		T18	6		T19	9
valid_sources[0x31]	230387	1			T18	3		T19	6		T20	6
valid_sources[0x32]	874757	1			T19	4		T20	2		T26	2
valid_sources[0x33]	226794	1			T19	7		T20	2		T26	2
valid_sources[0x34]	217379	1			T18	3		T19	4		T20	5
valid_sources[0x35]	439450	1			T19	8		T20	4		T26	10
valid_sources[0x36]	225811	1			T18	14		T19	5		T20	6
valid_sources[0x37]	236979	1			T19	9		T20	5		T26	9
valid_sources[0x38]	250874	1			T18	8		T19	9		T20	10
valid_sources[0x39]	215568	1			T19	9		T20	8		T23	13
valid_sources[0x3a]	292608	1			T19	11		T20	5		T26	4
valid_sources[0x3b]	340847	1			T17	3		T18	2		T19	5
valid_sources[0x3c]	217691	1			T19	4		T20	3		T26	1
valid_sources[0x3d]	249361	1			T19	14		T20	4		T26	8
valid_sources[0x3e]	216566	1			T19	4		T20	3		T26	6
valid_sources[0x3f]	359104	1			T19	9		T20	7		T26	4
valid_sources[0x40]	227784	1			T18	1		T19	8		T20	3
valid_sources[0x41]	217245	1			T18	12		T19	7		T20	2
valid_sources[0x42]	203632	1			T18	1		T19	9		T20	4
valid_sources[0x43]	225572	1			T19	9		T20	8		T26	3
valid_sources[0x44]	203304	1			T19	9		T20	4		T21	2
valid_sources[0x45]	205947	1			T18	11		T19	12		T20	3
valid_sources[0x46]	205043	1			T18	3		T19	7		T20	5
valid_sources[0x47]	213255	1			T18	11		T19	7		T20	5
valid_sources[0x48]	297414	1			T18	2		T19	6		T20	2
valid_sources[0x49]	222817	1			T17	1		T18	2		T19	6
valid_sources[0x4a]	201902	1			T19	4		T20	3		T26	7
valid_sources[0x4b]	207085	1			T17	11		T18	6		T19	10
valid_sources[0x4c]	198739	1			T18	3		T19	8		T20	5
valid_sources[0x4d]	222342	1			T18	14		T19	10		T20	2
valid_sources[0x4e]	405815	1			T19	6		T20	7		T26	7
valid_sources[0x4f]	218537	1			T19	4		T20	7		T26	5
valid_sources[0x50]	653710	1			T19	5		T20	3		T26	3
valid_sources[0x51]	230471	1			T19	10		T20	3		T26	2
valid_sources[0x52]	237034	1			T19	5		T20	6		T26	5
valid_sources[0x53]	211354	1			T19	9		T20	4		T26	1
valid_sources[0x54]	206278	1			T19	9		T20	6		T22	40
valid_sources[0x55]	211408	1			T19	13		T20	2		T26	2
valid_sources[0x56]	206124	1			T17	1		T19	10		T20	2
valid_sources[0x57]	236408	1			T19	7		T20	4		T26	3
valid_sources[0x58]	227363	1			T19	11		T20	4		T26	7
valid_sources[0x59]	219432	1			T19	10		T20	1		T24	5
valid_sources[0x5a]	312578	1			T17	22		T19	10		T20	6
valid_sources[0x5b]	247268	1			T19	7		T20	5		T26	5
valid_sources[0x5c]	233045	1			T17	7		T19	5		T20	8
valid_sources[0x5d]	211618	1			T17	7		T19	8		T20	5
valid_sources[0x5e]	205872	1			T19	17		T20	7		T26	3
valid_sources[0x5f]	220997	1			T17	3		T19	12		T20	3
valid_sources[0x60]	204573	1			T19	8		T20	6		T26	5
valid_sources[0x61]	205273	1			T19	4		T20	4		T26	5
valid_sources[0x62]	223433	1			T19	5		T20	6		T68	1
valid_sources[0x63]	218594	1			T17	2		T19	5		T20	4
valid_sources[0x64]	210569	1			T18	1		T19	4		T20	4
valid_sources[0x65]	216258	1			T19	6		T20	2		T26	3
valid_sources[0x66]	202814	1			T17	1		T19	9		T20	1
valid_sources[0x67]	272257	1			T18	1		T19	10		T20	4
valid_sources[0x68]	227433	1			T19	10		T20	2		T21	3
valid_sources[0x69]	214248	1			T19	12		T20	6		T24	2
valid_sources[0x6a]	223287	1			T17	1		T19	10		T20	1
valid_sources[0x6b]	212138	1			T17	1		T19	4		T20	7
valid_sources[0x6c]	205369	1			T19	6		T20	6		T26	6
valid_sources[0x6d]	1480079	1			T17	3		T19	6		T20	3
valid_sources[0x6e]	220750	1			T18	4		T19	5		T20	4
valid_sources[0x6f]	213863	1			T19	6		T20	1		T26	1
valid_sources[0x70]	277054	1			T19	8		T20	5		T26	7
valid_sources[0x71]	213283	1			T19	8		T20	7		T26	3
valid_sources[0x72]	233604	1			T19	10		T20	2		T24	1
valid_sources[0x73]	209341	1			T19	5		T20	3		T68	1
valid_sources[0x74]	219174	1			T17	10		T19	2		T26	11
valid_sources[0x75]	234894	1			T18	2		T19	6		T20	6
valid_sources[0x76]	218115	1			T19	13		T20	3		T26	1
valid_sources[0x77]	212599	1			T18	5		T19	6		T20	5
valid_sources[0x78]	207004	1			T19	7		T20	2		T26	1
valid_sources[0x79]	217286	1			T17	5		T19	2		T20	5
valid_sources[0x7a]	218281	1			T18	9		T19	9		T20	5
valid_sources[0x7b]	216206	1			T19	5		T26	3		T128	1
valid_sources[0x7c]	217908	1			T19	7		T20	4		T21	1
valid_sources[0x7d]	225427	1			T19	8		T20	3		T68	1
valid_sources[0x7e]	254369	1			T19	12		T26	5		T68	1
valid_sources[0x7f]	220105	1			T19	9		T20	7		T21	3
valid_sources[0x80]	227543	1			T18	19		T19	8		T20	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13478751

1

T17

41

T18

160

T19

501

values[0x0]

all_enables

biggest_size

2000932

1

T17

59

T18

103

T19

317

values[0x1]

all_enables

biggest_size

1100097

1

T17

51

T18

93

T19

330