Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	541518786	30315	0	0
ctrl_rd_A	541518786	1999	0	0
fifo_ctrl_rd_A	541518786	4802	0	0
host_timeout_ctrl_rd_A	541518786	1401	0	0
intr_enable_rd_A	541518786	3378	0	0
ovrd_rd_A	541518786	2445	0	0
target_id_rd_A	541518786	2076	0	0
timeout_ctrl_rd_A	541518786	1628	0	0
timing0_rd_A	541518786	1739	0	0
timing1_rd_A	541518786	1831	0	0
timing2_rd_A	541518786	1699	0	0
timing3_rd_A	541518786	1680	0	0
timing4_rd_A	541518786	1846	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	30315	0	0
T17	2610	140	0	0
T18	3513	0	0	0
T19	18399	0	0	0
T20	9346	8	0	0
T21	1485	3	0	0
T22	1173	0	0	0
T23	2288	13	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	4	0	0
T68	0	459	0	0
T69	0	2	0	0
T73	0	403	0	0
T103	0	20	0	0
T128	0	11	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	1999	0	0
T19	18399	105	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	23	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T75	0	504	0	0
T83	0	285	0	0
T84	0	105	0	0
T103	2122	0	0	0
T105	0	17	0	0
T107	0	5	0	0
T109	0	9	0	0
T111	0	20	0	0
T115	0	55	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	4802	0	0
T19	18399	147	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	22	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T84	0	65	0	0
T92	0	2	0	0
T103	2122	0	0	0
T105	0	45	0	0
T107	0	45	0	0
T109	0	3	0	0
T111	0	17	0	0
T115	0	32	0	0
T129	0	56	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	1401	0	0
T19	18399	107	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	11	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T75	0	325	0	0
T84	0	31	0	0
T92	0	3	0	0
T103	2122	0	0	0
T105	0	22	0	0
T107	0	11	0	0
T109	0	2	0	0
T111	0	23	0	0
T115	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	3378	0	0
T19	18399	76	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	16	0	0
T23	2288	79	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T84	0	287	0	0
T90	0	16	0	0
T103	2122	0	0	0
T105	0	20	0	0
T107	0	39	0	0
T109	0	3	0	0
T111	0	14	0	0
T115	0	57	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	2445	0	0
T19	18399	114	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	16	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T84	0	84	0	0
T92	0	7	0	0
T103	2122	0	0	0
T105	0	22	0	0
T107	0	2	0	0
T109	0	4	0	0
T111	0	10	0	0
T115	0	32	0	0
T130	0	50	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	2076	0	0
T19	18399	128	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	5	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T75	0	477	0	0
T84	0	154	0	0
T92	0	4	0	0
T103	2122	0	0	0
T105	0	23	0	0
T107	0	17	0	0
T109	0	17	0	0
T111	0	51	0	0
T115	0	27	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	1628	0	0
T19	18399	117	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	16	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T75	0	429	0	0
T84	0	34	0	0
T92	0	1	0	0
T103	2122	0	0	0
T105	0	30	0	0
T107	0	10	0	0
T109	0	1	0	0
T111	0	38	0	0
T115	0	27	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	1739	0	0
T19	18399	165	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	16	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T75	0	516	0	0
T84	0	26	0	0
T92	0	9	0	0
T103	2122	0	0	0
T105	0	30	0	0
T107	0	13	0	0
T109	0	11	0	0
T111	0	26	0	0
T115	0	11	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	1831	0	0
T19	18399	150	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	23	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T75	0	442	0	0
T84	0	59	0	0
T92	0	3	0	0
T103	2122	0	0	0
T105	0	45	0	0
T107	0	7	0	0
T109	0	13	0	0
T111	0	24	0	0
T115	0	66	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	1699	0	0
T19	18399	107	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	20	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T75	0	556	0	0
T83	0	172	0	0
T84	0	63	0	0
T92	0	3	0	0
T103	2122	0	0	0
T105	0	31	0	0
T107	0	6	0	0
T111	0	7	0	0
T115	0	46	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	1680	0	0
T19	18399	161	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	4	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T75	0	447	0	0
T84	0	28	0	0
T92	0	9	0	0
T103	2122	0	0	0
T105	0	24	0	0
T107	0	15	0	0
T109	0	13	0	0
T111	0	20	0	0
T115	0	10	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541518786	1846	0	0
T19	18399	128	0	0
T20	9346	0	0	0
T21	1485	0	0	0
T22	1173	0	0	0
T23	2288	24	0	0
T24	843	0	0	0
T25	1600	0	0	0
T26	7658	0	0	0
T68	3671	0	0	0
T75	0	557	0	0
T84	0	52	0	0
T92	0	2	0	0
T103	2122	0	0	0
T105	0	3	0	0
T107	0	5	0	0
T109	0	3	0	0
T111	0	31	0	0
T115	0	35	0	0