Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
33.33	0.00	0.00	100.00				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	588337	10389	0	0
ctrl_rd_A	588337	2193	0	0
fifo_ctrl_rd_A	588337	2740	0	0
host_timeout_ctrl_rd_A	588337	1447	0	0
intr_enable_rd_A	588337	4747	0	0
ovrd_rd_A	588337	2102	0	0
target_id_rd_A	588337	2296	0	0
timeout_ctrl_rd_A	588337	1830	0	0
timing0_rd_A	588337	1917	0	0
timing1_rd_A	588337	1789	0	0
timing2_rd_A	588337	1950	0	0
timing3_rd_A	588337	1747	0	0
timing4_rd_A	588337	1875	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	10389	0	0
T4	4224	3	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T8	2470	458	0	0
T9	2950	37	0	0
T10	1003	0	0	0
T11	1859	0	0	0
T13	0	299	0	0
T14	0	350	0	0
T15	0	4	0	0
T16	0	438	0	0
T20	1874	0	0	0
T21	905	0	0	0
T22	845	0	0	0
T25	0	14	0	0
T59	0	45	0	0
T60	0	42	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	2193	0	0
T4	4224	0	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T7	1672	5	0	0
T8	2470	0	0	0
T9	2950	0	0	0
T10	1003	0	0	0
T11	1859	0	0	0
T13	0	26	0	0
T15	0	137	0	0
T18	0	62	0	0
T20	1874	0	0	0
T21	905	0	0	0
T26	0	91	0	0
T30	0	24	0	0
T34	0	2	0	0
T51	0	141	0	0
T61	0	27	0	0
T62	0	20	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	2740	0	0
T4	4224	0	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T7	1672	3	0	0
T8	2470	0	0	0
T9	2950	0	0	0
T10	1003	0	0	0
T11	1859	0	0	0
T13	0	9	0	0
T15	0	290	0	0
T18	0	127	0	0
T20	1874	0	0	0
T21	905	0	0	0
T26	0	121	0	0
T30	0	18	0	0
T34	0	22	0	0
T51	0	238	0	0
T61	0	26	0	0
T62	0	5	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	1447	0	0
T13	8690	19	0	0
T14	2418	0	0	0
T15	11400	60	0	0
T18	0	49	0	0
T26	0	30	0	0
T28	1636	0	0	0
T29	1687	0	0	0
T30	1805	1	0	0
T34	0	27	0	0
T51	0	71	0	0
T59	2229	0	0	0
T60	1372	0	0	0
T61	0	9	0	0
T62	0	4	0	0
T63	0	42	0	0
T64	940	0	0	0
T65	1472	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	4747	0	0
T4	4224	0	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T7	1672	34	0	0
T8	2470	0	0	0
T9	2950	0	0	0
T10	1003	0	0	0
T11	1859	19	0	0
T12	0	10	0	0
T13	0	8	0	0
T15	0	672	0	0
T18	0	108	0	0
T20	1874	0	0	0
T21	905	0	0	0
T26	0	374	0	0
T30	0	69	0	0
T51	0	505	0	0
T66	0	6	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	2102	0	0
T4	4224	0	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T7	1672	3	0	0
T8	2470	0	0	0
T9	2950	0	0	0
T10	1003	0	0	0
T11	1859	0	0	0
T13	0	10	0	0
T15	0	178	0	0
T18	0	71	0	0
T20	1874	0	0	0
T21	905	0	0	0
T26	0	66	0	0
T30	0	2	0	0
T34	0	7	0	0
T35	0	3	0	0
T51	0	198	0	0
T61	0	20	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	2296	0	0
T4	4224	0	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T7	1672	4	0	0
T8	2470	0	0	0
T9	2950	0	0	0
T10	1003	0	0	0
T11	1859	0	0	0
T13	0	11	0	0
T15	0	170	0	0
T18	0	81	0	0
T20	1874	0	0	0
T21	905	0	0	0
T26	0	68	0	0
T30	0	17	0	0
T34	0	18	0	0
T35	0	7	0	0
T51	0	154	0	0
T61	0	44	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	1830	0	0
T13	8690	9	0	0
T14	2418	0	0	0
T15	11400	109	0	0
T18	0	52	0	0
T26	0	37	0	0
T28	1636	0	0	0
T29	1687	0	0	0
T30	1805	3	0	0
T34	0	18	0	0
T35	0	2	0	0
T51	0	102	0	0
T59	2229	0	0	0
T60	1372	0	0	0
T61	0	1	0	0
T63	0	58	0	0
T64	940	0	0	0
T65	1472	0	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	1917	0	0
T4	4224	0	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T7	1672	4	0	0
T8	2470	0	0	0
T9	2950	0	0	0
T10	1003	0	0	0
T11	1859	0	0	0
T13	0	4	0	0
T15	0	123	0	0
T18	0	55	0	0
T20	1874	0	0	0
T21	905	0	0	0
T26	0	62	0	0
T34	0	6	0	0
T35	0	1	0	0
T51	0	104	0	0
T61	0	27	0	0
T62	0	25	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	1789	0	0
T4	4224	0	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T7	1672	7	0	0
T8	2470	0	0	0
T9	2950	0	0	0
T10	1003	0	0	0
T11	1859	0	0	0
T13	0	11	0	0
T15	0	106	0	0
T18	0	64	0	0
T20	1874	0	0	0
T21	905	0	0	0
T26	0	80	0	0
T30	0	7	0	0
T34	0	39	0	0
T51	0	127	0	0
T62	0	7	0	0
T63	0	38	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	1950	0	0
T13	8690	21	0	0
T14	2418	0	0	0
T15	11400	157	0	0
T18	0	39	0	0
T26	0	57	0	0
T28	1636	0	0	0
T29	1687	0	0	0
T30	1805	8	0	0
T34	0	46	0	0
T51	0	152	0	0
T59	2229	0	0	0
T60	1372	0	0	0
T61	0	46	0	0
T62	0	8	0	0
T63	0	47	0	0
T64	940	0	0	0
T65	1472	0	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	1747	0	0
T4	4224	0	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T7	1672	11	0	0
T8	2470	0	0	0
T9	2950	0	0	0
T10	1003	0	0	0
T11	1859	0	0	0
T13	0	9	0	0
T15	0	104	0	0
T18	0	55	0	0
T20	1874	0	0	0
T21	905	0	0	0
T26	0	62	0	0
T30	0	8	0	0
T34	0	21	0	0
T51	0	98	0	0
T61	0	46	0	0
T62	0	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588337	1875	0	0
T4	4224	0	0	0
T5	4152	0	0	0
T6	3670	0	0	0
T7	1672	2	0	0
T8	2470	0	0	0
T9	2950	0	0	0
T10	1003	0	0	0
T11	1859	0	0	0
T13	0	29	0	0
T15	0	113	0	0
T18	0	60	0	0
T20	1874	0	0	0
T21	905	0	0	0
T26	0	52	0	0
T34	0	42	0	0
T51	0	109	0	0
T61	0	26	0	0
T62	0	3	0	0
T63	0	47	0	0