Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	21909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32351

1

T1

314

T2

31

T3

180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28088	1			T1	147		T2	64		T3	341
values[0x0]	12641	1			T1	113		T2	21		T3	88
values[0x1]	13531	1			T1	122		T2	14		T3	118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15773	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38487

1

T1

338

T2

59

T3

304

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	146	1			T1	8		T4	6		T5	1
valid_sources[0x01]	150	1			T1	4		T5	1		T13	1
valid_sources[0x02]	166	1			T1	5		T4	3		T5	1
valid_sources[0x03]	164	1			T1	3		T4	4		T5	2
valid_sources[0x04]	513	1			T1	1		T4	6		T15	1
valid_sources[0x05]	199	1			T2	9		T4	2		T5	2
valid_sources[0x06]	197	1			T1	4		T4	10		T15	3
valid_sources[0x07]	234	1			T4	6		T6	1		T15	2
valid_sources[0x08]	159	1			T4	3		T5	1		T13	2
valid_sources[0x09]	185	1			T4	1		T13	1		T6	1
valid_sources[0x0a]	153	1			T2	1		T4	2		T15	3
valid_sources[0x0b]	309	1			T1	2		T4	4		T13	3
valid_sources[0x0c]	293	1			T1	3		T4	4		T13	2
valid_sources[0x0d]	178	1			T4	4		T5	1		T13	1
valid_sources[0x0e]	180	1			T4	3		T5	1		T13	2
valid_sources[0x0f]	182	1			T1	4		T4	4		T5	1
valid_sources[0x10]	284	1			T1	4		T4	2		T5	1
valid_sources[0x11]	257	1			T4	4		T5	1		T13	1
valid_sources[0x12]	351	1			T1	5		T2	7		T3	3
valid_sources[0x13]	135	1			T4	4		T5	2		T13	1
valid_sources[0x14]	260	1			T4	3		T6	3		T15	6
valid_sources[0x15]	181	1			T1	2		T4	6		T5	1
valid_sources[0x16]	149	1			T1	4		T4	7		T13	3
valid_sources[0x17]	149	1			T1	1		T4	3		T5	1
valid_sources[0x18]	179	1			T4	7		T5	1		T15	3
valid_sources[0x19]	308	1			T4	8		T5	1		T6	2
valid_sources[0x1a]	176	1			T4	1		T5	1		T13	1
valid_sources[0x1b]	156	1			T4	3		T15	1		T16	4
valid_sources[0x1c]	244	1			T1	1		T4	4		T5	2
valid_sources[0x1d]	164	1			T1	7		T4	3		T13	3
valid_sources[0x1e]	182	1			T1	2		T4	6		T5	1
valid_sources[0x1f]	179	1			T4	1		T13	1		T14	1
valid_sources[0x20]	324	1			T4	4		T13	2		T15	5
valid_sources[0x21]	183	1			T4	4		T5	2		T13	1
valid_sources[0x22]	373	1			T4	2		T16	2		T22	5
valid_sources[0x23]	151	1			T1	5		T4	5		T5	2
valid_sources[0x24]	177	1			T1	1		T4	4		T13	3
valid_sources[0x25]	323	1			T1	9		T3	22		T4	1
valid_sources[0x26]	285	1			T1	10		T4	4		T5	1
valid_sources[0x27]	209	1			T3	24		T4	3		T6	1
valid_sources[0x28]	173	1			T4	1		T5	1		T13	1
valid_sources[0x29]	216	1			T4	4		T5	1		T13	1
valid_sources[0x2a]	269	1			T1	1		T4	5		T5	1
valid_sources[0x2b]	203	1			T4	3		T13	1		T6	1
valid_sources[0x2c]	140	1			T1	1		T4	2		T5	1
valid_sources[0x2d]	178	1			T1	5		T4	11		T15	2
valid_sources[0x2e]	314	1			T4	6		T5	1		T13	2
valid_sources[0x2f]	147	1			T4	2		T13	1		T14	3
valid_sources[0x30]	333	1			T1	3		T4	4		T5	2
valid_sources[0x31]	223	1			T1	1		T4	8		T5	1
valid_sources[0x32]	164	1			T1	1		T4	6		T13	2
valid_sources[0x33]	187	1			T4	2		T13	1		T6	1
valid_sources[0x34]	123	1			T1	3		T4	7		T13	1
valid_sources[0x35]	192	1			T4	5		T15	1		T16	2
valid_sources[0x36]	174	1			T1	1		T4	3		T5	1
valid_sources[0x37]	347	1			T4	10		T13	1		T14	1
valid_sources[0x38]	216	1			T1	2		T4	3		T5	1
valid_sources[0x39]	226	1			T1	2		T4	8		T5	2
valid_sources[0x3a]	228	1			T1	2		T2	10		T4	2
valid_sources[0x3b]	189	1			T1	2		T4	1		T13	1
valid_sources[0x3c]	137	1			T4	5		T15	3		T16	3
valid_sources[0x3d]	194	1			T4	2		T13	3		T14	2
valid_sources[0x3e]	157	1			T1	1		T4	3		T5	1
valid_sources[0x3f]	186	1			T4	2		T6	1		T15	2
valid_sources[0x40]	179	1			T1	1		T4	2		T5	1
valid_sources[0x41]	171	1			T1	1		T4	1		T5	1
valid_sources[0x42]	210	1			T4	4		T13	1		T14	1
valid_sources[0x43]	276	1			T1	2		T4	16		T13	1
valid_sources[0x44]	233	1			T1	4		T4	5		T13	2
valid_sources[0x45]	253	1			T4	3		T6	1		T15	2
valid_sources[0x46]	262	1			T1	6		T4	3		T14	2
valid_sources[0x47]	235	1			T4	4		T5	2		T14	1
valid_sources[0x48]	180	1			T1	1		T4	3		T13	2
valid_sources[0x49]	288	1			T1	2		T4	8		T5	1
valid_sources[0x4a]	200	1			T1	2		T4	7		T13	1
valid_sources[0x4b]	206	1			T5	1		T13	1		T15	8
valid_sources[0x4c]	226	1			T4	3		T5	1		T6	1
valid_sources[0x4d]	672	1			T1	6		T4	3		T13	2
valid_sources[0x4e]	165	1			T4	8		T5	1		T13	1
valid_sources[0x4f]	196	1			T1	4		T4	4		T6	2
valid_sources[0x50]	315	1			T13	1		T15	4		T16	5
valid_sources[0x51]	140	1			T4	5		T5	2		T14	1
valid_sources[0x52]	355	1			T1	1		T3	87		T4	7
valid_sources[0x53]	148	1			T4	5		T5	1		T16	2
valid_sources[0x54]	194	1			T4	6		T13	1		T15	3
valid_sources[0x55]	130	1			T4	4		T13	4		T15	2
valid_sources[0x56]	352	1			T4	3		T15	4		T16	4
valid_sources[0x57]	246	1			T1	1		T4	5		T5	1
valid_sources[0x58]	150	1			T1	9		T4	2		T5	2
valid_sources[0x59]	257	1			T1	3		T4	12		T5	1
valid_sources[0x5a]	191	1			T1	2		T4	2		T14	1
valid_sources[0x5b]	202	1			T1	2		T3	23		T4	2
valid_sources[0x5c]	149	1			T4	5		T16	4		T22	2
valid_sources[0x5d]	203	1			T4	1		T13	2		T14	1
valid_sources[0x5e]	157	1			T4	7		T13	1		T14	1
valid_sources[0x5f]	315	1			T4	6		T5	2		T6	1
valid_sources[0x60]	120	1			T4	3		T5	1		T6	1
valid_sources[0x61]	140	1			T4	6		T13	2		T6	3
valid_sources[0x62]	184	1			T4	12		T5	1		T13	2
valid_sources[0x63]	176	1			T1	2		T4	4		T13	2
valid_sources[0x64]	146	1			T5	2		T13	1		T15	2
valid_sources[0x65]	319	1			T1	2		T4	3		T5	2
valid_sources[0x66]	402	1			T1	13		T3	55		T4	10
valid_sources[0x67]	210	1			T1	5		T4	5		T13	3
valid_sources[0x68]	361	1			T1	3		T3	110		T4	4
valid_sources[0x69]	165	1			T4	2		T5	3		T6	1
valid_sources[0x6a]	151	1			T4	8		T5	2		T13	2
valid_sources[0x6b]	182	1			T4	8		T13	2		T6	1
valid_sources[0x6c]	128	1			T1	1		T4	1		T13	1
valid_sources[0x6d]	195	1			T4	7		T5	1		T15	3
valid_sources[0x6e]	234	1			T1	2		T4	3		T5	1
valid_sources[0x6f]	152	1			T4	5		T13	2		T14	1
valid_sources[0x70]	132	1			T1	2		T4	6		T13	1
valid_sources[0x71]	291	1			T4	3		T13	2		T6	2
valid_sources[0x72]	158	1			T2	1		T4	6		T6	1
valid_sources[0x73]	161	1			T1	1		T4	7		T14	1
valid_sources[0x74]	134	1			T1	2		T4	1		T14	3
valid_sources[0x75]	231	1			T1	8		T4	2		T5	1
valid_sources[0x76]	168	1			T4	4		T5	1		T13	1
valid_sources[0x77]	174	1			T4	8		T6	3		T15	2
valid_sources[0x78]	176	1			T4	1		T13	1		T6	3
valid_sources[0x79]	220	1			T1	3		T4	9		T13	2
valid_sources[0x7a]	149	1			T2	4		T4	13		T5	1
valid_sources[0x7b]	174	1			T1	1		T4	1		T14	1
valid_sources[0x7c]	280	1			T1	2		T4	4		T15	4
valid_sources[0x7d]	149	1			T4	5		T13	1		T6	2
valid_sources[0x7e]	159	1			T1	4		T5	1		T14	1
valid_sources[0x7f]	222	1			T2	6		T4	1		T13	2
valid_sources[0x80]	186	1			T1	1		T4	6		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12062

1

T1

93

T2

4

T3

43

values[0x0]

all_enables

biggest_size

10305

1

T1

107

T2

15

T3

56

values[0x1]

all_enables

biggest_size

9984

1

T1

114

T2

12

T3

81