Unified Coverage Report :: Module :: i2c_reg_top

Module : i2c_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	97.96			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.49	100.00	97.96			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	97.96			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	98.99	98.99	90.32		99.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
33.33	0.00	0.00	100.00				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acqdata_abyte	66.67	66.67
u_acqdata_signal	66.67	66.67
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_enablehost	100.00	100.00	100.00			100.00
u_ctrl_enabletarget	100.00	100.00	100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_fdata0_qe	100.00	100.00				100.00
u_fdata_fbyte	100.00	100.00	100.00			100.00
u_fdata_nakok	100.00	100.00	100.00			100.00
u_fdata_rcont	100.00	100.00	100.00			100.00
u_fdata_readb	100.00	100.00	100.00			100.00
u_fdata_start	100.00	100.00	100.00			100.00
u_fdata_stop	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_acqrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtilvl	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxilvl	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_fifo_status_acqlvl	100.00	100.00
u_fifo_status_fmtlvl	100.00	100.00
u_fifo_status_rxlvl	100.00	100.00
u_fifo_status_txlvl	100.00	100.00
u_host_timeout_ctrl	100.00	100.00	100.00			100.00
u_intr_enable_acq_full	100.00	100.00	100.00			100.00
u_intr_enable_cmd_complete	100.00	100.00	100.00			100.00
u_intr_enable_fmt_overflow	100.00	100.00	100.00			100.00
u_intr_enable_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_enable_host_timeout	100.00	100.00	100.00			100.00
u_intr_enable_nak	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_scl_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_unstable	100.00	100.00	100.00			100.00
u_intr_enable_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_enable_tx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_tx_stretch	100.00	100.00	100.00			100.00
u_intr_enable_unexp_stop	100.00	100.00	100.00			100.00
u_intr_state_acq_full	62.59	77.78	50.00			60.00
u_intr_state_cmd_complete	100.00	100.00	100.00			100.00
u_intr_state_fmt_overflow	100.00	100.00	100.00			100.00
u_intr_state_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_state_host_timeout	100.00	100.00	100.00			100.00
u_intr_state_nak	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_threshold	100.00	100.00	100.00			100.00
u_intr_state_scl_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_unstable	100.00	100.00	100.00			100.00
u_intr_state_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_state_tx_overflow	100.00	100.00	100.00			100.00
u_intr_state_tx_stretch	62.59	77.78	50.00			60.00
u_intr_state_unexp_stop	100.00	100.00	100.00			100.00
u_intr_test_acq_full	100.00	100.00
u_intr_test_cmd_complete	100.00	100.00
u_intr_test_fmt_overflow	100.00	100.00
u_intr_test_fmt_threshold	100.00	100.00
u_intr_test_host_timeout	100.00	100.00
u_intr_test_nak	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_threshold	100.00	100.00
u_intr_test_scl_interference	100.00	100.00
u_intr_test_sda_interference	100.00	100.00
u_intr_test_sda_unstable	100.00	100.00
u_intr_test_stretch_timeout	100.00	100.00
u_intr_test_tx_overflow	100.00	100.00
u_intr_test_tx_stretch	100.00	100.00
u_intr_test_unexp_stop	100.00	100.00
u_ovrd_sclval	100.00	100.00	100.00			100.00
u_ovrd_sdaval	100.00	100.00	100.00			100.00
u_ovrd_txovrden	100.00	100.00	100.00			100.00
u_prim_reg_we_check	50.00	100.00		0.00
u_rdata	66.67	66.67
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_acqempty	100.00	100.00
u_status_acqfull	100.00	100.00
u_status_fmtempty	100.00	100.00
u_status_fmtfull	100.00	100.00
u_status_hostidle	100.00	100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_targetidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_target_id_address0	100.00	100.00	100.00			100.00
u_target_id_address1	100.00	100.00	100.00			100.00
u_target_id_mask0	100.00	100.00	100.00			100.00
u_target_id_mask1	100.00	100.00	100.00			100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timing0_thigh	100.00	100.00	100.00			100.00
u_timing0_tlow	100.00	100.00	100.00			100.00
u_timing1_t_f	100.00	100.00	100.00			100.00
u_timing1_t_r	100.00	100.00	100.00			100.00
u_timing2_thd_sta	100.00	100.00	100.00			100.00
u_timing2_tsu_sta	100.00	100.00	100.00			100.00
u_timing3_thd_dat	100.00	100.00	100.00			100.00
u_timing3_tsu_dat	100.00	100.00	100.00			100.00
u_timing4_t_buf	100.00	100.00	100.00			100.00
u_timing4_tsu_sto	100.00	100.00	100.00			100.00
u_txdata	100.00	100.00	100.00			100.00
u_txdata0_qe	100.00	100.00				100.00
u_val_scl_rx	66.67	66.67
u_val_sda_rx	66.67	66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
TOTAL		295	295	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	1122	1	1	100.00
CONT_ASSIGN	1137	1	1	100.00
CONT_ASSIGN	1153	1	1	100.00
CONT_ASSIGN	1169	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1201	1	1	100.00
CONT_ASSIGN	1217	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1361	1	1	100.00
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1381	1	1	100.00
CONT_ASSIGN	1673	1	1	100.00
CONT_ASSIGN	1701	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1757	1	1	100.00
CONT_ASSIGN	1785	1	1	100.00
CONT_ASSIGN	1813	1	1	100.00
CONT_ASSIGN	1854	1	1	100.00
CONT_ASSIGN	1882	1	1	100.00
CONT_ASSIGN	1910	1	1	100.00
CONT_ASSIGN	1938	1	1	100.00
CONT_ASSIGN	1966	1	1	100.00
CONT_ASSIGN	1994	1	1	100.00
CONT_ASSIGN	2689	1	1	100.00
ALWAYS	2723	23	23	100.00
CONT_ASSIGN	2748	1	1	100.00
ALWAYS	2752	1	1	100.00
CONT_ASSIGN	2778	1	1	100.00
CONT_ASSIGN	2780	1	1	100.00
CONT_ASSIGN	2782	1	1	100.00
CONT_ASSIGN	2784	1	1	100.00
CONT_ASSIGN	2786	1	1	100.00
CONT_ASSIGN	2788	1	1	100.00
CONT_ASSIGN	2790	1	1	100.00
CONT_ASSIGN	2792	1	1	100.00
CONT_ASSIGN	2794	1	1	100.00
CONT_ASSIGN	2796	1	1	100.00
CONT_ASSIGN	2798	1	1	100.00
CONT_ASSIGN	2800	1	1	100.00
CONT_ASSIGN	2802	1	1	100.00
CONT_ASSIGN	2804	1	1	100.00
CONT_ASSIGN	2805	1	1	100.00
CONT_ASSIGN	2807	1	1	100.00
CONT_ASSIGN	2809	1	1	100.00
CONT_ASSIGN	2811	1	1	100.00
CONT_ASSIGN	2813	1	1	100.00
CONT_ASSIGN	2815	1	1	100.00
CONT_ASSIGN	2817	1	1	100.00
CONT_ASSIGN	2819	1	1	100.00
CONT_ASSIGN	2821	1	1	100.00
CONT_ASSIGN	2823	1	1	100.00
CONT_ASSIGN	2825	1	1	100.00
CONT_ASSIGN	2827	1	1	100.00
CONT_ASSIGN	2829	1	1	100.00
CONT_ASSIGN	2831	1	1	100.00
CONT_ASSIGN	2833	1	1	100.00
CONT_ASSIGN	2835	1	1	100.00
CONT_ASSIGN	2836	1	1	100.00
CONT_ASSIGN	2838	1	1	100.00
CONT_ASSIGN	2840	1	1	100.00
CONT_ASSIGN	2842	1	1	100.00
CONT_ASSIGN	2844	1	1	100.00
CONT_ASSIGN	2846	1	1	100.00
CONT_ASSIGN	2848	1	1	100.00
CONT_ASSIGN	2850	1	1	100.00
CONT_ASSIGN	2852	1	1	100.00
CONT_ASSIGN	2854	1	1	100.00
CONT_ASSIGN	2856	1	1	100.00
CONT_ASSIGN	2858	1	1	100.00
CONT_ASSIGN	2860	1	1	100.00
CONT_ASSIGN	2862	1	1	100.00
CONT_ASSIGN	2864	1	1	100.00
CONT_ASSIGN	2866	1	1	100.00
CONT_ASSIGN	2867	1	1	100.00
CONT_ASSIGN	2869	1	1	100.00
CONT_ASSIGN	2870	1	1	100.00
CONT_ASSIGN	2872	1	1	100.00
CONT_ASSIGN	2874	1	1	100.00
CONT_ASSIGN	2876	1	1	100.00
CONT_ASSIGN	2877	1	1	100.00
CONT_ASSIGN	2878	1	1	100.00
CONT_ASSIGN	2879	1	1	100.00
CONT_ASSIGN	2881	1	1	100.00
CONT_ASSIGN	2883	1	1	100.00
CONT_ASSIGN	2885	1	1	100.00
CONT_ASSIGN	2887	1	1	100.00
CONT_ASSIGN	2889	1	1	100.00
CONT_ASSIGN	2891	1	1	100.00
CONT_ASSIGN	2892	1	1	100.00
CONT_ASSIGN	2894	1	1	100.00
CONT_ASSIGN	2896	1	1	100.00
CONT_ASSIGN	2898	1	1	100.00
CONT_ASSIGN	2900	1	1	100.00
CONT_ASSIGN	2902	1	1	100.00
CONT_ASSIGN	2904	1	1	100.00
CONT_ASSIGN	2905	1	1	100.00
CONT_ASSIGN	2906	1	1	100.00
CONT_ASSIGN	2908	1	1	100.00
CONT_ASSIGN	2910	1	1	100.00
CONT_ASSIGN	2912	1	1	100.00
CONT_ASSIGN	2913	1	1	100.00
CONT_ASSIGN	2914	1	1	100.00
CONT_ASSIGN	2916	1	1	100.00
CONT_ASSIGN	2918	1	1	100.00
CONT_ASSIGN	2919	1	1	100.00
CONT_ASSIGN	2921	1	1	100.00
CONT_ASSIGN	2923	1	1	100.00
CONT_ASSIGN	2924	1	1	100.00
CONT_ASSIGN	2926	1	1	100.00
CONT_ASSIGN	2928	1	1	100.00
CONT_ASSIGN	2929	1	1	100.00
CONT_ASSIGN	2931	1	1	100.00
CONT_ASSIGN	2933	1	1	100.00
CONT_ASSIGN	2934	1	1	100.00
CONT_ASSIGN	2936	1	1	100.00
CONT_ASSIGN	2938	1	1	100.00
CONT_ASSIGN	2939	1	1	100.00
CONT_ASSIGN	2941	1	1	100.00
CONT_ASSIGN	2943	1	1	100.00
CONT_ASSIGN	2944	1	1	100.00
CONT_ASSIGN	2946	1	1	100.00
CONT_ASSIGN	2948	1	1	100.00
CONT_ASSIGN	2950	1	1	100.00
CONT_ASSIGN	2952	1	1	100.00
CONT_ASSIGN	2953	1	1	100.00
CONT_ASSIGN	2954	1	1	100.00
CONT_ASSIGN	2956	1	1	100.00
CONT_ASSIGN	2957	1	1	100.00
CONT_ASSIGN	2959	1	1	100.00
ALWAYS	2963	23	23	100.00
ALWAYS	2990	103	103	100.00
CONT_ASSIGN	3170	0	0
CONT_ASSIGN	3178	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
1122	1	1
1137	1	1
1153	1	1
1169	1	1
1185	1	1
1201	1	1
1217	1	1
1233	1	1
1249	1	1
1265	1	1
1281	1	1
1297	1	1
1313	1	1
1329	1	1
1345	1	1
1361	1	1
1367	1	1
1381	1	1
1673	1	1
1701	1	1
1729	1	1
1757	1	1
1785	1	1
1813	1	1
1854	1	1
1882	1	1
1910	1	1
1938	1	1
1966	1	1
1994	1	1
2689	1	1
2723	1	1
2724	1	1
2725	1	1
2726	1	1
2727	1	1
2728	1	1
2729	1	1
2730	1	1
2731	1	1
2732	1	1
2733	1	1
2734	1	1
2735	1	1
2736	1	1
2737	1	1
2738	1	1
2739	1	1
2740	1	1
2741	1	1
2742	1	1
2743	1	1
2744	1	1
2745	1	1
2748	1	1
2752	1	1
2778	1	1
2780	1	1
2782	1	1
2784	1	1
2786	1	1
2788	1	1
2790	1	1
2792	1	1
2794	1	1
2796	1	1
2798	1	1
2800	1	1
2802	1	1
2804	1	1
2805	1	1
2807	1	1
2809	1	1
2811	1	1
2813	1	1
2815	1	1
2817	1	1
2819	1	1
2821	1	1
2823	1	1
2825	1	1
2827	1	1
2829	1	1
2831	1	1
2833	1	1
2835	1	1
2836	1	1
2838	1	1
2840	1	1
2842	1	1
2844	1	1
2846	1	1
2848	1	1
2850	1	1
2852	1	1
2854	1	1
2856	1	1
2858	1	1
2860	1	1
2862	1	1
2864	1	1
2866	1	1
2867	1	1
2869	1	1
2870	1	1
2872	1	1
2874	1	1
2876	1	1
2877	1	1
2878	1	1
2879	1	1
2881	1	1
2883	1	1
2885	1	1
2887	1	1
2889	1	1
2891	1	1
2892	1	1
2894	1	1
2896	1	1
2898	1	1
2900	1	1
2902	1	1
2904	1	1
2905	1	1
2906	1	1
2908	1	1
2910	1	1
2912	1	1
2913	1	1
2914	1	1
2916	1	1
2918	1	1
2919	1	1
2921	1	1
2923	1	1
2924	1	1
2926	1	1
2928	1	1
2929	1	1
2931	1	1
2933	1	1
2934	1	1
2936	1	1
2938	1	1
2939	1	1
2941	1	1
2943	1	1
2944	1	1
2946	1	1
2948	1	1
2950	1	1
2952	1	1
2953	1	1
2954	1	1
2956	1	1
2957	1	1
2959	1	1
2963	1	1
2964	1	1
2965	1	1
2966	1	1
2967	1	1
2968	1	1
2969	1	1
2970	1	1
2971	1	1
2972	1	1
2973	1	1
2974	1	1
2975	1	1
2976	1	1
2977	1	1
2978	1	1
2979	1	1
2980	1	1
2981	1	1
2982	1	1
2983	1	1
2984	1	1
2985	1	1
2990	1	1
2991	1	1
2993	1	1
2994	1	1
2995	1	1
2996	1	1
2997	1	1
2998	1	1
2999	1	1
3000	1	1
3001	1	1
3002	1	1
3003	1	1
3004	1	1
3005	1	1
3006	1	1
3007	1	1
3011	1	1
3012	1	1
3013	1	1
3014	1	1
3015	1	1
3016	1	1
3017	1	1
3018	1	1
3019	1	1
3020	1	1
3021	1	1
3022	1	1
3023	1	1
3024	1	1
3025	1	1
3029	1	1
3030	1	1
3031	1	1
3032	1	1
3033	1	1
3034	1	1
3035	1	1
3036	1	1
3037	1	1
3038	1	1
3039	1	1
3040	1	1
3041	1	1
3042	1	1
3043	1	1
3047	1	1
3051	1	1
3052	1	1
3053	1	1
3057	1	1
3058	1	1
3059	1	1
3060	1	1
3061	1	1
3062	1	1
3063	1	1
3064	1	1
3065	1	1
3066	1	1
3070	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3078	1	1
3079	1	1
3083	1	1
3084	1	1
3085	1	1
3086	1	1
3087	1	1
3088	1	1
3092	1	1
3093	1	1
3094	1	1
3095	1	1
3099	1	1
3100	1	1
3101	1	1
3105	1	1
3106	1	1
3110	1	1
3111	1	1
3115	1	1
3116	1	1
3120	1	1
3121	1	1
3125	1	1
3126	1	1
3130	1	1
3131	1	1
3135	1	1
3136	1	1
3140	1	1
3141	1	1
3142	1	1
3143	1	1
3147	1	1
3148	1	1
3152	1	1
3156	1	1
3170		unreachable
3178	1	1
3179	1	1

---

Cond Coverage for Module : i2c_reg_top

	Total	Covered	Percent
Conditions	245	240	97.96
Logical	245	240	97.96
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T13
1	1	Covered	T1,T2,T3

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T23

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T3,T4,T23
1	0	0	Covered	T3,T4,T23

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T23
0	1	0	Covered	T13,T15,T16
1	0	0	Covered	T13,T15,T16

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T13

 LINE       2724
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2725
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2726
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       2727
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2728
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2729
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2730
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2731
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2732
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2733
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_STATUS_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2734
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2735
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2736
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2737
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2738
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2739
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2740
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2741
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2742
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2743
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2744
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2745
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2748
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2748
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       2752
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T13

 LINE       2752
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
22 (addr_hit[21] & ((|(4'...	Covered	T3,T4,T5
21 (addr_hit[20] & ((|(4'...	Covered	T1,T3,T4
20 (addr_hit[19] & ((|(4'...	Covered	T4,T13,T15
19 (addr_hit[18] & ((|(4'...	Covered	T1,T2,T3
18 (addr_hit[17] & ((|(4'...	Covered	T1,T2,T3
17 (addr_hit[16] & ((|(4'...	Covered	T1,T2,T3
16 (addr_hit[15] & ((|(4'...	Covered	T1,T2,T3
15 (addr_hit[14] & ((|(4'...	Covered	T1,T2,T3
14 (addr_hit[13] & ((|(4'...	Covered	T1,T2,T3
13 (addr_hit[12] & ((|(4'...	Covered	T1,T2,T3
12 (addr_hit[11] & ((|(4'...	Covered	T3,T4,T13
11 (addr_hit[10] & ((|(4'...	Covered	T1,T3,T4
10 (addr_hit[9] & ((|(4'b...	Covered	T1,T4,T5
9 (addr_hit[8] & ((|(4'b...	Covered	T1,T2,T3
8 (addr_hit[7] & ((|(4'b...	Covered	T1,T2,T3
7 (addr_hit[6] & ((|(4'b...	Covered	T4,T13,T15
6 (addr_hit[5] & ((|(4'b...	Covered	T1,T4,T5
5 (addr_hit[4] & ((|(4'b...	Covered	T2,T3,T4
4 (addr_hit[3] & ((|(4'b...	Covered	T1,T3,T4
3 (addr_hit[2] & ((|(4'b...	Covered	T4,T5,T13
2 (addr_hit[1] & ((|(4'b...	Covered	T1,T2,T3
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T4

 LINE       2752
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T4

 LINE       2752
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T5,T13

 LINE       2752
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       2752
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       2752
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       2752
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T13,T15

 LINE       2752
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       2752
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       2752
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T13

 LINE       2752
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2752
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T13,T15

 LINE       2752
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       2752
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       2778
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T13,T15
1	1	1	Covered	T6,T7,T8

 LINE       2805
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T4,T13
1	1	1	Covered	T1,T2,T3

 LINE       2836
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T13,T15,T18
1	1	1	Covered	T7,T8,T11

 LINE       2867
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T15,T16
1	1	1	Covered	T1,T2,T3

 LINE       2870
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T15,T16,T18
1	1	1	Covered	T1,T2,T3

 LINE       2877
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T57,T58,T59
1	1	1	Covered	T1,T5,T14

 LINE       2878
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T60,T61,T59
1	1	1	Not Covered

 LINE       2879
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T1,T2,T3

 LINE       2892
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T1,T2,T3

 LINE       2905
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T60,T62,T63
1	1	1	Covered	T1,T5,T14

 LINE       2906
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T15,T17
1	1	1	Covered	T1,T2,T3

 LINE       2913
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T23,T64
1	1	1	Not Covered

 LINE       2914
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T1,T2,T3

 LINE       2919
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T1,T2,T3

 LINE       2924
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T15,T17
1	1	1	Covered	T1,T2,T3

 LINE       2929
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T13,T15
1	1	1	Covered	T1,T2,T3

 LINE       2934
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T15,T16
1	1	1	Covered	T1,T2,T3

 LINE       2939
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T15,T18
1	1	1	Covered	T1,T2,T3

 LINE       2944
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T17,T19
1	1	1	Covered	T1,T2,T3

 LINE       2953
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T65,T57,T63
1	1	1	Not Covered

 LINE       2954
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T13,T15
1	1	1	Covered	T1,T2,T3

 LINE       2957
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T15,T17
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
Branches		28	28	100.00
TERNARY	2748	2	2	100.00
IF	71	3	3	100.00
CASE	2991	23	23	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2748	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T23
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	2991	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	563253	45916	0	0
reAfterRv	563253	45914	0	0
rePulse	563253	26060	0	0
wePulse	563253	19854	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	45916	0	0
T1	2465	125	0	0
T2	1786	99	0	0
T3	5420	546	0	0
T4	11173	1065	0	0
T5	1407	65	0	0
T6	2093	184	0	0
T7	1302	40	0	0
T8	1122	22	0	0
T13	6492	41	0	0
T14	1705	80	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	45914	0	0
T1	2465	125	0	0
T2	1786	99	0	0
T3	5420	546	0	0
T4	11173	1065	0	0
T5	1407	65	0	0
T6	2093	184	0	0
T7	1302	40	0	0
T8	1122	22	0	0
T13	6492	41	0	0
T14	1705	80	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	26060	0	0
T1	2465	86	0	0
T2	1786	64	0	0
T3	5420	340	0	0
T4	11173	667	0	0
T5	1407	45	0	0
T6	2093	80	0	0
T7	1302	20	0	0
T8	1122	11	0	0
T13	6492	5	0	0
T14	1705	55	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	19854	0	0
T1	2465	39	0	0
T2	1786	35	0	0
T3	5420	206	0	0
T4	11173	398	0	0
T5	1407	20	0	0
T6	2093	104	0	0
T7	1302	20	0	0
T8	1122	11	0	0
T13	6492	36	0	0
T14	1705	25	0	0