Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
33.33	0.00	0.00	100.00				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	563253	10907	0	0
ctrl_rd_A	563253	1604	0	0
fifo_ctrl_rd_A	563253	2142	0	0
host_timeout_ctrl_rd_A	563253	1198	0	0
intr_enable_rd_A	563253	4383	0	0
ovrd_rd_A	563253	1578	0	0
target_id_rd_A	563253	1851	0	0
timeout_ctrl_rd_A	563253	1262	0	0
timing0_rd_A	563253	1481	0	0
timing1_rd_A	563253	1397	0	0
timing2_rd_A	563253	1383	0	0
timing3_rd_A	563253	1401	0	0
timing4_rd_A	563253	1407	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	10907	0	0
T1	2465	77	0	0
T2	1786	0	0	0
T3	5420	4	0	0
T4	11173	6	0	0
T5	1407	39	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	489	0	0
T14	1705	15	0	0
T15	0	924	0	0
T16	0	552	0	0
T17	0	117	0	0
T18	0	840	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1604	0	0
T2	1786	11	0	0
T3	5420	0	0	0
T4	11173	54	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	18	0	0
T23	0	78	0	0
T24	0	447	0	0
T26	0	17	0	0
T27	0	58	0	0
T29	0	79	0	0
T66	0	13	0	0
T67	0	12	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	2142	0	0
T4	11173	198	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T16	8437	0	0	0
T17	2651	0	0	0
T18	0	6	0	0
T23	0	105	0	0
T24	0	459	0	0
T27	0	30	0	0
T29	0	71	0	0
T30	0	4	0	0
T32	0	5	0	0
T66	0	5	0	0
T67	0	25	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1198	0	0
T4	11173	29	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T16	8437	0	0	0
T17	2651	0	0	0
T18	0	2	0	0
T23	0	54	0	0
T24	0	430	0	0
T27	0	46	0	0
T29	0	90	0	0
T30	0	3	0	0
T32	0	17	0	0
T66	0	8	0	0
T67	0	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	4383	0	0
T2	1786	55	0	0
T3	5420	0	0	0
T4	11173	323	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	3	0	0
T23	0	264	0	0
T24	0	454	0	0
T26	0	63	0	0
T27	0	50	0	0
T66	0	9	0	0
T67	0	14	0	0
T68	0	18	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1578	0	0
T2	1786	16	0	0
T3	5420	0	0	0
T4	11173	87	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	11	0	0
T23	0	75	0	0
T24	0	439	0	0
T26	0	9	0	0
T27	0	30	0	0
T29	0	67	0	0
T66	0	7	0	0
T67	0	21	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1851	0	0
T2	1786	34	0	0
T3	5420	0	0	0
T4	11173	78	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	10	0	0
T23	0	107	0	0
T24	0	416	0	0
T26	0	14	0	0
T27	0	43	0	0
T29	0	95	0	0
T66	0	6	0	0
T67	0	11	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1262	0	0
T2	1786	6	0	0
T3	5420	0	0	0
T4	11173	63	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	4	0	0
T23	0	51	0	0
T24	0	483	0	0
T26	0	10	0	0
T27	0	36	0	0
T29	0	60	0	0
T66	0	13	0	0
T67	0	10	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1481	0	0
T2	1786	20	0	0
T3	5420	0	0	0
T4	11173	74	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	18	0	0
T23	0	48	0	0
T24	0	445	0	0
T26	0	10	0	0
T27	0	55	0	0
T29	0	96	0	0
T66	0	8	0	0
T67	0	17	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1397	0	0
T2	1786	9	0	0
T3	5420	0	0	0
T4	11173	68	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	12	0	0
T23	0	40	0	0
T24	0	420	0	0
T26	0	5	0	0
T27	0	49	0	0
T29	0	102	0	0
T66	0	9	0	0
T67	0	34	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1383	0	0
T2	1786	15	0	0
T3	5420	0	0	0
T4	11173	44	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	17	0	0
T23	0	78	0	0
T24	0	475	0	0
T26	0	7	0	0
T27	0	22	0	0
T29	0	72	0	0
T66	0	4	0	0
T67	0	19	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1401	0	0
T2	1786	30	0	0
T3	5420	0	0	0
T4	11173	35	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	18	0	0
T23	0	82	0	0
T24	0	412	0	0
T26	0	6	0	0
T27	0	45	0	0
T29	0	103	0	0
T66	0	8	0	0
T67	0	22	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563253	1407	0	0
T2	1786	21	0	0
T3	5420	0	0	0
T4	11173	41	0	0
T5	1407	0	0	0
T6	2093	0	0	0
T7	1302	0	0	0
T8	1122	0	0	0
T13	6492	0	0	0
T14	1705	0	0	0
T15	4896	0	0	0
T18	0	28	0	0
T23	0	53	0	0
T24	0	482	0	0
T26	0	6	0	0
T27	0	37	0	0
T29	0	84	0	0
T66	0	3	0	0
T67	0	6	0	0