Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	100.00	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.40	99.27	96.93	100.00	95.65	98.57	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i2c_core	97.18	99.26	93.16		95.65	97.84	100.00
i2c_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	99.58	99.26	99.44	100.00		99.18	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
127	1	1
128	1	1

---

Cond Coverage for Module : i2c

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       68
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T69,T93,T94
1	0	Covered	T1,T2,T3
1	1	Covered	T69,T93,T94

---

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	45	45	100.00
Total Bits	370	370	100.00
Total Bits 0->1	185	185	100.00
Total Bits 1->0	185	185	100.00

Ports	45	45	100.00
Port Bits	370	370	100.00
Port Bits 0->1	185	185	100.00
Port Bits 1->0	185	185	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
rst_ni	Yes	Yes	T18,T19,T21	Yes	T18,T19,T20	INPUT
tl_i.d_ready	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_address[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_source[7:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_size[1:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_i.a_valid	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_o.a_ready	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_o.d_error	Yes	Yes	T18,T19,T21	Yes	T18,T19,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T18,T19,*T20	Yes	T18,T19,T20	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	OUTPUT
cio_scl_i	Yes	Yes	T18,T19,T24	Yes	T18,T19,T24	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T18,T19,T24	Yes	T18,T19,T24	OUTPUT
cio_sda_i	Yes	Yes	T20,T21,T25	Yes	T20,T21,T25	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T20,T21,T25	Yes	T20,T21,T25	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T22,T25,T27	Yes	T22,T25,T27	OUTPUT
intr_rx_threshold_o	Yes	Yes	T22,T27,T95	Yes	T22,T27,T95	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T22,T70,T96	Yes	T22,T70,T96	OUTPUT
intr_rx_overflow_o	Yes	Yes	T22,T26,T27	Yes	T22,T26,T27	OUTPUT
intr_nak_o	Yes	Yes	T22,T26,T27	Yes	T22,T26,T27	OUTPUT
intr_scl_interference_o	Yes	Yes	T26,T70,T96	Yes	T26,T70,T96	OUTPUT
intr_sda_interference_o	Yes	Yes	T26,T27,T82	Yes	T26,T27,T82	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T22,T27,T70	Yes	T22,T27,T70	OUTPUT
intr_sda_unstable_o	Yes	Yes	T22,T26,T27	Yes	T22,T26,T27	OUTPUT
intr_cmd_complete_o	Yes	Yes	T22,T26,T27	Yes	T22,T26,T27	OUTPUT
intr_tx_stretch_o	Yes	Yes	T22,T26,T27	Yes	T22,T26,T27	OUTPUT
intr_tx_overflow_o	Yes	Yes	T27,T70,T95	Yes	T27,T70,T95	OUTPUT
intr_acq_full_o	Yes	Yes	T22,T26,T27	Yes	T22,T26,T27	OUTPUT
intr_unexp_stop_o	Yes	Yes	T27,T96,T97	Yes	T27,T96,T97	OUTPUT
intr_host_timeout_o	Yes	Yes	T26,T27,T70	Yes	T26,T27,T70	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : i2c

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	544713160	544528772	0	0
CioSclEnKnownO_A	544713160	544528772	0	0
CioSclKnownO_A	544713160	544528772	0	0
CioSdaEnKnownO_A	544713160	544528772	0	0
CioSdaKnownO_A	544713160	544528772	0	0
FpvSecCmRegWeOnehotCheck_A	544713160	70	0	0
IntrAcqFulllwKnownO_A	544713160	544528772	0	0
IntrCommandCompleteKnownO_A	544713160	544528772	0	0
IntrFmtOflwKnownO_A	544713160	544528772	0	0
IntrFmtWtmkKnownO_A	544713160	544528772	0	0
IntrHostTimeoutKnownO_A	544713160	544528772	0	0
IntrNakKnownO_A	544713160	544528772	0	0
IntrRxOflwKnownO_A	544713160	544528772	0	0
IntrRxWtmkKnownO_A	544713160	544528772	0	0
IntrSclInterfKnownO_A	544713160	544528772	0	0
IntrSdaInterfKnownO_A	544713160	544528772	0	0
IntrSdaUnstableKnownO_A	544713160	544528772	0	0
IntrStretchTimeoutKnownO_A	544713160	544528772	0	0
IntrTxOflwKnownO_A	544713160	544528772	0	0
IntrTxStretchKnownO_A	544713160	544528772	0	0
IntrUnexpStopKnownO_A	544713160	544528772	0	0
TlAReadyKnownO_A	544713160	544528772	0	0
TlDValidKnownO_A	544713160	544528772	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

CioSclEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

CioSclKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

CioSdaEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

CioSdaKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	70	0	0
T79	3586	10	0	0
T80	0	10	0	0
T81	0	10	0	0
T98	0	20	0	0
T99	0	20	0	0
T100	183924	0	0	0
T101	692074	0	0	0
T102	242787	0	0	0
T103	176181	0	0	0
T104	643661	0	0	0
T105	98657	0	0	0
T106	21596	0	0	0
T107	3248	0	0	0
T108	219877	0	0	0

IntrAcqFulllwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrCommandCompleteKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrFmtOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrFmtWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrHostTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrNakKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrRxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrRxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrSclInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrSdaInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrSdaUnstableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrStretchTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrTxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrTxStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

IntrUnexpStopKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544713160	544528772	0	0
T1	440538	440468	0	0
T2	562230	562156	0	0
T3	52576	52506	0	0
T7	82987	82896	0	0
T8	970166	970116	0	0
T10	405817	405719	0	0
T46	3470	2685	0	0
T54	5974	5876	0	0
T68	23406	23352	0	0
T69	1213	1125	0	0