Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	545275427	38265	0	0
ctrl_rd_A	545275427	2093	0	0
fifo_ctrl_rd_A	545275427	5556	0	0
host_timeout_ctrl_rd_A	545275427	1527	0	0
intr_enable_rd_A	545275427	4275	0	0
ovrd_rd_A	545275427	2481	0	0
target_id_rd_A	545275427	2088	0	0
timeout_ctrl_rd_A	545275427	1649	0	0
timing0_rd_A	545275427	1747	0	0
timing1_rd_A	545275427	1804	0	0
timing2_rd_A	545275427	1891	0	0
timing3_rd_A	545275427	1592	0	0
timing4_rd_A	545275427	1696	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	38265	0	0
T18	1862	18	0	0
T19	2234	140	0	0
T20	6501	0	0	0
T21	1125	1	0	0
T22	1388	0	0	0
T23	4339	634	0	0
T24	2290	31	0	0
T25	2647	0	0	0
T26	975	0	0	0
T27	1381	0	0	0
T77	0	629	0	0
T78	0	5	0	0
T82	0	6	0	0
T84	0	519	0	0
T85	0	160	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	2093	0	0
T20	6501	83	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	39	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	169	0	0
T83	0	90	0	0
T110	0	857	0	0
T112	0	8	0	0
T114	0	5	0	0
T117	0	5	0	0
T120	0	6	0	0
T121	0	15	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	5556	0	0
T1	0	122	0	0
T20	6501	94	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	7	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T74	0	84	0	0
T76	0	125	0	0
T77	3872	0	0	0
T78	0	282	0	0
T143	0	161	0	0
T144	0	85	0	0
T145	0	134	0	0
T146	0	116	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	1527	0	0
T20	6501	90	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	35	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	70	0	0
T83	0	50	0	0
T110	0	556	0	0
T112	0	8	0	0
T114	0	7	0	0
T117	0	6	0	0
T120	0	10	0	0
T121	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	4275	0	0
T20	6501	83	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	6	0	0
T26	975	0	0	0
T27	1381	26	0	0
T51	0	19	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	550	0	0
T97	0	9	0	0
T141	0	21	0	0
T142	0	31	0	0
T147	0	8	0	0
T148	0	54	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	2481	0	0
T5	0	41	0	0
T20	6501	65	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	31	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	176	0	0
T149	0	3	0	0
T150	0	61	0	0
T151	0	49	0	0
T152	0	31	0	0
T153	0	57	0	0
T154	0	58	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	2088	0	0
T20	6501	59	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	0	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	196	0	0
T83	0	100	0	0
T92	0	188	0	0
T110	0	693	0	0
T112	0	3	0	0
T117	0	3	0	0
T120	0	27	0	0
T155	0	97	0	0
T156	0	4	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	1649	0	0
T20	6501	68	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	16	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	119	0	0
T83	0	56	0	0
T110	0	626	0	0
T112	0	5	0	0
T114	0	1	0	0
T117	0	9	0	0
T120	0	7	0	0
T121	0	11	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	1747	0	0
T20	6501	116	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	22	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	103	0	0
T83	0	52	0	0
T110	0	696	0	0
T112	0	3	0	0
T114	0	6	0	0
T117	0	5	0	0
T120	0	14	0	0
T121	0	11	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	1804	0	0
T20	6501	53	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	19	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	129	0	0
T83	0	44	0	0
T110	0	786	0	0
T112	0	5	0	0
T114	0	1	0	0
T117	0	3	0	0
T120	0	19	0	0
T121	0	11	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	1891	0	0
T20	6501	83	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	12	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	112	0	0
T83	0	54	0	0
T110	0	743	0	0
T112	0	4	0	0
T114	0	4	0	0
T120	0	7	0	0
T121	0	17	0	0
T155	0	70	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	1592	0	0
T20	6501	95	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	14	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	108	0	0
T83	0	49	0	0
T110	0	558	0	0
T114	0	5	0	0
T117	0	9	0	0
T120	0	7	0	0
T121	0	3	0	0
T155	0	56	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545275427	1696	0	0
T20	6501	67	0	0
T21	1125	0	0	0
T22	1388	0	0	0
T23	4339	0	0	0
T24	2290	0	0	0
T25	2647	8	0	0
T26	975	0	0	0
T27	1381	0	0	0
T70	1730	0	0	0
T77	3872	0	0	0
T78	0	97	0	0
T83	0	49	0	0
T110	0	692	0	0
T112	0	3	0	0
T114	0	9	0	0
T120	0	17	0	0
T121	0	7	0	0
T155	0	89	0	0