Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6603751	1			T17	1		T19	8		T24	5
all_values[1]	6603751	1			T17	1		T19	8		T24	5
all_values[2]	6603751	1			T17	1		T19	8		T24	5
all_values[3]	6603751	1			T17	1		T19	8		T24	5
all_values[4]	6603751	1			T17	1		T19	8		T24	5
all_values[5]	6603751	1			T17	1		T19	8		T24	5
all_values[6]	6603751	1			T17	1		T19	8		T24	5
all_values[7]	6603751	1			T17	1		T19	8		T24	5
all_values[8]	6603751	1			T17	1		T19	8		T24	5
all_values[9]	6603751	1			T17	1		T19	8		T24	5
all_values[10]	6603751	1			T17	1		T19	8		T24	5
all_values[11]	6603751	1			T17	1		T19	8		T24	5
all_values[12]	6603751	1			T17	1		T19	8		T24	5
all_values[13]	6603751	1			T17	1		T19	8		T24	5
all_values[14]	6603751	1			T17	1		T19	8		T24	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93488409

1

T17

15

T19

74

T24

53

auto[1]

5567856

1

T19

46

T24

22

T68

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86475239

1

T17

15

T19

10

T24

20

auto[1]

12581026

1

T19

110

T24

55

T68

97

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	5037184	1			T17	1		T76	1		T69	1
all_values[0]	auto[0]	auto[1]	697219	1			T19	7		T24	4		T68	1
all_values[0]	auto[1]	auto[0]	710545	1			T2	1		T3	1		T9	6
all_values[0]	auto[1]	auto[1]	158803	1			T19	1		T24	1		T68	7
all_values[1]	auto[0]	auto[0]	5265603	1			T17	1		T76	1		T68	4
all_values[1]	auto[0]	auto[1]	749577	1			T19	4		T24	4		T68	1
all_values[1]	auto[1]	auto[0]	471719	1			T9	103		T10	77		T11	19
all_values[1]	auto[1]	auto[1]	116852	1			T19	4		T24	1		T68	3
all_values[2]	auto[0]	auto[0]	5755832	1			T17	1		T24	5		T76	1
all_values[2]	auto[0]	auto[1]	847718	1			T19	4		T68	4		T69	7
all_values[2]	auto[1]	auto[1]	201	1			T19	4		T69	1		T93	1
all_values[3]	auto[0]	auto[0]	5760215	1			T17	1		T76	1		T80	1
all_values[3]	auto[0]	auto[1]	843317	1			T19	6		T24	4		T68	5
all_values[3]	auto[1]	auto[1]	219	1			T19	2		T24	1		T68	3
all_values[4]	auto[0]	auto[0]	5768502	1			T17	1		T19	3		T76	1
all_values[4]	auto[0]	auto[1]	834965	1			T19	1		T24	1		T68	4
all_values[4]	auto[1]	auto[0]	57	1			T47	52		T50	1		T155	2
all_values[4]	auto[1]	auto[1]	227	1			T19	4		T24	4		T68	4
all_values[5]	auto[0]	auto[0]	5843963	1			T17	1		T19	2		T24	1
all_values[5]	auto[0]	auto[1]	759582	1			T19	5		T24	1		T68	4
all_values[5]	auto[1]	auto[1]	206	1			T19	1		T24	3		T68	4
all_values[6]	auto[0]	auto[0]	4993377	1			T17	1		T19	1		T24	2
all_values[6]	auto[0]	auto[1]	669160	1			T19	3		T24	1		T68	2
all_values[6]	auto[1]	auto[0]	787640	1			T2	1		T3	1		T9	23
all_values[6]	auto[1]	auto[1]	153574	1			T19	4		T24	2		T68	5
all_values[7]	auto[0]	auto[0]	5487775	1			T17	1		T76	1		T68	1
all_values[7]	auto[0]	auto[1]	796965	1			T19	4		T24	1		T68	2
all_values[7]	auto[1]	auto[0]	297148	1			T2	1		T3	1		T9	838
all_values[7]	auto[1]	auto[1]	21863	1			T19	4		T24	4		T68	5
all_values[8]	auto[0]	auto[0]	4860856	1			T17	1		T24	2		T76	1
all_values[8]	auto[0]	auto[1]	621670	1			T19	2		T24	3		T68	4
all_values[8]	auto[1]	auto[0]	942583	1			T2	1		T3	1		T9	209
all_values[8]	auto[1]	auto[1]	178642	1			T19	6		T69	3		T93	7
all_values[9]	auto[0]	auto[0]	4810676	1			T17	1		T19	1		T24	2
all_values[9]	auto[0]	auto[1]	696670	1			T19	4		T24	1		T68	5
all_values[9]	auto[1]	auto[0]	926659	1			T1	1076		T2	1		T3	1
all_values[9]	auto[1]	auto[1]	169746	1			T19	3		T24	2		T68	2
all_values[10]	auto[0]	auto[0]	5584134	1			T17	1		T24	1		T76	1
all_values[10]	auto[0]	auto[1]	866208	1			T19	5		T24	2		T68	2
all_values[10]	auto[1]	auto[0]	153214	1			T1	1718		T15	2383		T63	3177
all_values[10]	auto[1]	auto[1]	195	1			T19	3		T24	2		T68	2
all_values[11]	auto[0]	auto[0]	5278974	1			T17	1		T24	5		T76	1
all_values[11]	auto[0]	auto[1]	847691	1			T19	5		T68	5		T69	7
all_values[11]	auto[1]	auto[0]	476855	1			T1	5682		T15	4554		T16	4560
all_values[11]	auto[1]	auto[1]	231	1			T19	3		T68	2		T69	1
all_values[12]	auto[0]	auto[0]	5737337	1			T17	1		T19	2		T24	1
all_values[12]	auto[0]	auto[1]	866214	1			T19	4		T24	3		T68	4
all_values[12]	auto[1]	auto[1]	200	1			T19	2		T24	1		T68	4
all_values[13]	auto[0]	auto[0]	5755818	1			T17	1		T19	1		T76	1
all_values[13]	auto[0]	auto[1]	847692	1			T19	5		T24	4		T68	4
all_values[13]	auto[1]	auto[0]	10	1			T174	1		T168	1		T169	1
all_values[13]	auto[1]	auto[1]	231	1			T19	2		T24	1		T68	1
all_values[14]	auto[0]	auto[0]	5768563	1			T17	1		T24	1		T76	1
all_values[14]	auto[0]	auto[1]	834952	1			T19	5		T24	4		T68	1
all_values[14]	auto[1]	auto[1]	236	1			T19	3		T68	7		T69	5