Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.88 99.17 96.65 100.00 98.26 98.24 100.00 92.86


Total tests in report: 1625
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
55.70 55.70 47.95 47.95 35.81 35.81 78.64 78.64 98.26 98.26 33.37 33.37 77.48 77.48 18.38 18.38 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3089712832
75.27 19.57 86.67 38.72 59.91 24.10 83.13 4.49 98.26 0.00 65.42 32.05 92.76 15.28 40.76 22.37 /workspace/coverage/default/48.i2c_host_smoke.3198278522
83.13 7.86 89.89 3.22 76.64 16.73 93.33 10.19 98.26 0.00 82.55 17.12 95.98 3.22 45.27 4.52 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3254535857
88.87 5.74 96.63 6.74 83.60 6.96 97.57 4.25 98.26 0.00 92.43 9.88 97.32 1.34 56.30 11.03 /workspace/coverage/default/40.i2c_target_stress_all.461381351
92.67 3.80 97.22 0.59 88.15 4.55 98.79 1.21 98.26 0.00 95.06 2.63 97.59 0.27 73.63 17.33 /workspace/coverage/cover_reg_top/3.i2c_intr_test.297896524
94.45 1.78 97.56 0.34 93.11 4.95 99.27 0.49 98.26 0.00 95.94 0.88 97.59 0.00 79.41 5.78 /workspace/coverage/default/11.i2c_host_stress_all.3261688165
95.09 0.64 97.90 0.34 93.51 0.40 99.27 0.00 98.26 0.00 96.16 0.22 97.86 0.27 82.67 3.26 /workspace/coverage/default/49.i2c_host_fifo_overflow.3307048934
95.49 0.40 97.90 0.00 94.11 0.60 99.27 0.00 98.26 0.00 96.16 0.00 97.86 0.00 84.87 2.21 /workspace/coverage/default/0.i2c_host_stress_all.2990951288
95.88 0.39 98.58 0.68 94.65 0.54 99.27 0.00 98.26 0.00 97.26 1.10 97.86 0.00 85.29 0.42 /workspace/coverage/default/33.i2c_target_stress_all.3925136400
96.18 0.30 98.58 0.00 94.78 0.13 99.51 0.24 98.26 0.00 97.48 0.22 97.86 0.00 86.76 1.47 /workspace/coverage/default/13.i2c_host_override.1117919284
96.44 0.27 98.58 0.00 94.78 0.00 99.51 0.00 98.26 0.00 97.48 0.00 99.73 1.88 86.76 0.00 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.433624461
96.61 0.17 98.58 0.00 94.91 0.13 99.51 0.00 98.26 0.00 97.48 0.00 99.73 0.00 87.82 1.05 /workspace/coverage/default/0.i2c_target_glitch.1284726648
96.77 0.16 98.58 0.00 95.05 0.13 100.00 0.49 98.26 0.00 97.48 0.00 100.00 0.27 88.03 0.21 /workspace/coverage/default/0.i2c_sec_cm.1168455230
96.90 0.13 98.63 0.05 95.18 0.13 100.00 0.00 98.26 0.00 97.59 0.11 100.00 0.00 88.66 0.63 /workspace/coverage/default/17.i2c_host_stress_all.3280864515
97.03 0.13 98.97 0.34 95.31 0.13 100.00 0.00 98.26 0.00 97.91 0.33 100.00 0.00 88.76 0.11 /workspace/coverage/default/27.i2c_host_mode_toggle.1001302281
97.15 0.11 98.97 0.00 95.38 0.07 100.00 0.00 98.26 0.00 97.91 0.00 100.00 0.00 89.50 0.74 /workspace/coverage/default/27.i2c_target_tx_ovf.155441950
97.21 0.07 99.07 0.10 95.65 0.27 100.00 0.00 98.26 0.00 98.02 0.11 100.00 0.00 89.50 0.00 /workspace/coverage/default/12.i2c_host_stress_all_with_rand_reset.1719731700
97.28 0.06 99.07 0.00 95.78 0.13 100.00 0.00 98.26 0.00 98.02 0.00 100.00 0.00 89.81 0.32 /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3972218053
97.34 0.06 99.07 0.00 95.78 0.00 100.00 0.00 98.26 0.00 98.02 0.00 100.00 0.00 90.23 0.42 /workspace/coverage/default/19.i2c_host_stress_all.2948311204
97.39 0.05 99.07 0.00 95.85 0.07 100.00 0.00 98.26 0.00 98.02 0.00 100.00 0.00 90.55 0.32 /workspace/coverage/default/15.i2c_host_stress_all.1968694728
97.44 0.05 99.12 0.05 96.05 0.20 100.00 0.00 98.26 0.00 98.13 0.11 100.00 0.00 90.55 0.00 /workspace/coverage/default/0.i2c_target_bad_addr.3097648095
97.49 0.05 99.12 0.00 96.05 0.00 100.00 0.00 98.26 0.00 98.13 0.00 100.00 0.00 90.86 0.32 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2913755346
97.52 0.03 99.12 0.00 96.18 0.13 100.00 0.00 98.26 0.00 98.13 0.00 100.00 0.00 90.97 0.11 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1860858460
97.55 0.03 99.12 0.00 96.18 0.00 100.00 0.00 98.26 0.00 98.13 0.00 100.00 0.00 91.18 0.21 /workspace/coverage/default/10.i2c_host_override.21755222
97.58 0.03 99.12 0.00 96.18 0.00 100.00 0.00 98.26 0.00 98.13 0.00 100.00 0.00 91.39 0.21 /workspace/coverage/default/12.i2c_target_hrst.347785544
97.61 0.03 99.12 0.00 96.18 0.00 100.00 0.00 98.26 0.00 98.13 0.00 100.00 0.00 91.60 0.21 /workspace/coverage/default/13.i2c_host_fifo_overflow.3430170966
97.64 0.03 99.12 0.00 96.18 0.00 100.00 0.00 98.26 0.00 98.13 0.00 100.00 0.00 91.81 0.21 /workspace/coverage/default/18.i2c_host_stress_all.732905586
97.67 0.03 99.17 0.05 96.32 0.13 100.00 0.00 98.26 0.00 98.13 0.00 100.00 0.00 91.81 0.00 /workspace/coverage/default/0.i2c_alert_test.3722148557
97.70 0.03 99.17 0.00 96.39 0.07 100.00 0.00 98.26 0.00 98.24 0.11 100.00 0.00 91.81 0.00 /workspace/coverage/default/0.i2c_target_stretch.3040084749
97.71 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 91.91 0.11 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.142792190
97.73 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.02 0.11 /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2151475183
97.74 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.12 0.11 /workspace/coverage/default/10.i2c_target_hrst.3295880798
97.76 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.23 0.11 /workspace/coverage/default/12.i2c_host_fifo_full.3982919100
97.77 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.33 0.11 /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3538737359
97.79 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.44 0.11 /workspace/coverage/default/21.i2c_target_fifo_reset_acq.982024627
97.80 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.54 0.11 /workspace/coverage/default/28.i2c_host_stress_all.2976400557
97.82 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.65 0.11 /workspace/coverage/default/28.i2c_target_unexp_stop.3403513463
97.83 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.75 0.11 /workspace/coverage/default/34.i2c_host_stress_all.2963531942
97.85 0.02 99.17 0.00 96.39 0.00 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.86 0.11 /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.4171615370
97.85 0.01 99.17 0.00 96.45 0.07 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.86 0.00 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1669605569
97.86 0.01 99.17 0.00 96.52 0.07 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.86 0.00 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2323934162
97.87 0.01 99.17 0.00 96.59 0.07 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.86 0.00 /workspace/coverage/default/24.i2c_target_fifo_reset_acq.921937162
97.88 0.01 99.17 0.00 96.65 0.07 100.00 0.00 98.26 0.00 98.24 0.00 100.00 0.00 92.86 0.00 /workspace/coverage/default/30.i2c_host_mode_toggle.3737586098


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3312472894
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3819358986
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.799917099
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1043471981
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.3107919140
/workspace/coverage/cover_reg_top/0.i2c_intr_test.3305127879
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2115646538
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2002245367
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3022634197
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2410230107
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1371744917
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3181021382
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.2635541058
/workspace/coverage/cover_reg_top/1.i2c_intr_test.1042592323
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2013205286
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3817427562
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3909571426
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1881867449
/workspace/coverage/cover_reg_top/10.i2c_intr_test.2927742630
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.873438251
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1252730499
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.872097798
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.3835024673
/workspace/coverage/cover_reg_top/11.i2c_intr_test.1652130724
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2286286931
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.991513200
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.136272772
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.616194396
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.302451817
/workspace/coverage/cover_reg_top/12.i2c_intr_test.1235223044
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2499605985
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.3648981434
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1593200193
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.412298579
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.3669853090
/workspace/coverage/cover_reg_top/13.i2c_intr_test.2485596399
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.1872516910
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.482015195
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1327175680
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1190621213
/workspace/coverage/cover_reg_top/14.i2c_intr_test.1180634084
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.1142528607
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.801238296
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1464403643
/workspace/coverage/cover_reg_top/15.i2c_intr_test.738014524
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2131465572
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.126192380
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2545859200
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1927877627
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.334780362
/workspace/coverage/cover_reg_top/16.i2c_intr_test.1804304806
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.879577618
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2043760040
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2528676657
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1650806971
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.1651883443
/workspace/coverage/cover_reg_top/17.i2c_intr_test.2552169367
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2477768437
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.2227109786
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3728122395
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.2356862817
/workspace/coverage/cover_reg_top/18.i2c_intr_test.2486620224
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2835419105
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.608239799
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3259879709
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1612050544
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.1307768469
/workspace/coverage/cover_reg_top/19.i2c_intr_test.2175659704
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3178864979
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.3094678427
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2857190187
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.68291424
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2354408331
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.384508141
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1282220428
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.3860905859
/workspace/coverage/cover_reg_top/2.i2c_intr_test.406402746
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.836101073
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3604388807
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2002401802
/workspace/coverage/cover_reg_top/21.i2c_intr_test.812306088
/workspace/coverage/cover_reg_top/22.i2c_intr_test.2189181660
/workspace/coverage/cover_reg_top/23.i2c_intr_test.811540400
/workspace/coverage/cover_reg_top/24.i2c_intr_test.98314599
/workspace/coverage/cover_reg_top/25.i2c_intr_test.3760621772
/workspace/coverage/cover_reg_top/26.i2c_intr_test.76381225
/workspace/coverage/cover_reg_top/27.i2c_intr_test.3957365726
/workspace/coverage/cover_reg_top/28.i2c_intr_test.1082785425
/workspace/coverage/cover_reg_top/29.i2c_intr_test.3409949061
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4293832853
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4122651268
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1451974499
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.74484919
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.293102000
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1804750959
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.1266426554
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2787292395
/workspace/coverage/cover_reg_top/30.i2c_intr_test.1752497799
/workspace/coverage/cover_reg_top/31.i2c_intr_test.1587661441
/workspace/coverage/cover_reg_top/32.i2c_intr_test.4178077633
/workspace/coverage/cover_reg_top/33.i2c_intr_test.837465267
/workspace/coverage/cover_reg_top/34.i2c_intr_test.1582796170
/workspace/coverage/cover_reg_top/35.i2c_intr_test.2913766103
/workspace/coverage/cover_reg_top/36.i2c_intr_test.2610493229
/workspace/coverage/cover_reg_top/37.i2c_intr_test.3750018525
/workspace/coverage/cover_reg_top/38.i2c_intr_test.3121005362
/workspace/coverage/cover_reg_top/39.i2c_intr_test.3062528091
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1157294046
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1670366256
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.555060411
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.258945116
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2466728690
/workspace/coverage/cover_reg_top/4.i2c_intr_test.3168976771
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.212605283
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.3311625793
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1537024760
/workspace/coverage/cover_reg_top/40.i2c_intr_test.2727782251
/workspace/coverage/cover_reg_top/41.i2c_intr_test.3585875753
/workspace/coverage/cover_reg_top/42.i2c_intr_test.751875825
/workspace/coverage/cover_reg_top/43.i2c_intr_test.2665290202
/workspace/coverage/cover_reg_top/44.i2c_intr_test.3254290195
/workspace/coverage/cover_reg_top/45.i2c_intr_test.2375017668
/workspace/coverage/cover_reg_top/46.i2c_intr_test.600871165
/workspace/coverage/cover_reg_top/47.i2c_intr_test.561204017
/workspace/coverage/cover_reg_top/48.i2c_intr_test.2532187975
/workspace/coverage/cover_reg_top/49.i2c_intr_test.4186969371
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3139935299
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3267551053
/workspace/coverage/cover_reg_top/5.i2c_intr_test.1126767821
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1836873204
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.3157229351
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3372667046
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3812495731
/workspace/coverage/cover_reg_top/6.i2c_intr_test.19853586
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.998982970
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3205627400
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1405533877
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2243202561
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.1109094241
/workspace/coverage/cover_reg_top/7.i2c_intr_test.2888535661
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1716843578
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.930147384
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1064998227
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2363167266
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.2935493646
/workspace/coverage/cover_reg_top/8.i2c_intr_test.3521666979
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4101422953
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2923810122
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Total test records in report: 1625
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T17 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3089712832 Jan 24 12:54:46 PM PST 24 Jan 24 12:54:57 PM PST 24 111892885 ps
T18 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2323934162 Jan 24 12:55:47 PM PST 24 Jan 24 12:56:23 PM PST 24 613026937 ps
T19 /workspace/coverage/cover_reg_top/3.i2c_intr_test.297896524 Jan 24 12:55:01 PM PST 24 Jan 24 12:55:15 PM PST 24 18684731 ps
T20 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4122651268 Jan 24 12:54:59 PM PST 24 Jan 24 12:55:14 PM PST 24 2549784625 ps
T21 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3254535857 Jan 24 12:55:45 PM PST 24 Jan 24 12:56:20 PM PST 24 237187231 ps
T22 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2787292395 Jan 24 12:55:00 PM PST 24 Jan 24 12:55:14 PM PST 24 116383053 ps
T23 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3909571426 Jan 24 12:59:09 PM PST 24 Jan 24 12:59:36 PM PST 24 87796984 ps
T24 /workspace/coverage/cover_reg_top/36.i2c_intr_test.2610493229 Jan 24 12:56:08 PM PST 24 Jan 24 12:56:38 PM PST 24 18638380 ps
T25 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2013205286 Jan 24 12:55:00 PM PST 24 Jan 24 12:55:14 PM PST 24 30431122 ps
T26 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1612050544 Jan 24 12:55:58 PM PST 24 Jan 24 12:56:33 PM PST 24 20329211 ps
T92 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.433624461 Jan 24 12:55:25 PM PST 24 Jan 24 12:55:56 PM PST 24 52140247 ps
T106 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.998982970 Jan 24 12:55:17 PM PST 24 Jan 24 12:55:49 PM PST 24 60665039 ps
T76 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3604388807 Jan 24 12:55:10 PM PST 24 Jan 24 12:55:39 PM PST 24 267150606 ps
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