---

Detail Report for Assertions

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	535604339	535423943	0	0
tb.dut.CioSclEnKnownO_A	0	0	535604339	535423943	0	0
tb.dut.CioSclKnownO_A	0	0	535604339	535423943	0	0
tb.dut.CioSdaEnKnownO_A	0	0	535604339	535423943	0	0
tb.dut.CioSdaKnownO_A	0	0	535604339	535423943	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	535604339	80	0	0
tb.dut.IntrAcqFulllwKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrCommandCompleteKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrFmtOflwKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrFmtWtmkKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrHostTimeoutKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrNakKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrRxOflwKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrRxWtmkKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrSclInterfKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrSdaInterfKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrSdaUnstableKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrStretchTimeoutKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrTxOflwKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrTxStretchKnownO_A	0	0	535604339	535423943	0	0
tb.dut.IntrUnexpStopKnownO_A	0	0	535604339	535423943	0	0
tb.dut.TlAReadyKnownO_A	0	0	535604339	535423943	0	0
tb.dut.TlDValidKnownO_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.intr_hw_acq_overflow.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_cmd_complete.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_fmt_overflow.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_fmt_threshold.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_host_timeout.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_nak.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_rx_overflow.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_rx_threshold.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_scl_interference.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_sda_interference.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_sda_unstable.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_stretch_timeout.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_tx_overflow.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_tx_stretch.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.intr_hw_unexp_stop.IntrTKind_A	0	0	1463	1463	0	0
tb.dut.i2c_core.u_i2c_acqfifo.DataKnown_A	0	0	535604339	261421582	0	0
tb.dut.i2c_core.u_i2c_acqfifo.DepthKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_acqfifo.RvalidKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_acqfifo.WreadyKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_acqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	535604339	261421582	0	0
tb.dut.i2c_core.u_i2c_fmtfifo.DataKnown_A	0	0	535604339	187455343	0	0
tb.dut.i2c_core.u_i2c_fmtfifo.DepthKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_fmtfifo.RvalidKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_fmtfifo.WreadyKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_fmtfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	535604339	187455343	0	0
tb.dut.i2c_core.u_i2c_fsm.AcqDepthRdCheck_A	0	0	535604339	4457283	0	0
tb.dut.i2c_core.u_i2c_fsm.SclInputGlitch_A	0	0	520962456	11548679	0	0
tb.dut.i2c_core.u_i2c_fsm.SclOutputGlitch_A	0	0	535604339	5677535	0	0
tb.dut.i2c_core.u_i2c_fsm.SclSdaChangeNotSimultaneous_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_rxfifo.DataKnown_A	0	0	535604339	42116768	0	0
tb.dut.i2c_core.u_i2c_rxfifo.DepthKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_rxfifo.RvalidKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_rxfifo.WreadyKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_rxfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	535604339	42116768	0	0
tb.dut.i2c_core.u_i2c_txfifo.DataKnown_A	0	0	535604339	160098201	0	0
tb.dut.i2c_core.u_i2c_txfifo.DepthKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_txfifo.RvalidKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_txfifo.WreadyKnown_A	0	0	535604339	535423943	0	0
tb.dut.i2c_core.u_i2c_txfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	535604339	160098201	0	0
tb.dut.i2c_csr_assert.TlulOOBAddrErr_A	0	0	536229817	94369	0	0
tb.dut.i2c_csr_assert.ctrl_rd_A	0	0	536229817	3805	0	0
tb.dut.i2c_csr_assert.fifo_ctrl_rd_A	0	0	536229817	6801	0	0
tb.dut.i2c_csr_assert.host_timeout_ctrl_rd_A	0	0	536229817	3109	0	0
tb.dut.i2c_csr_assert.intr_enable_rd_A	0	0	536229817	5157	0	0
tb.dut.i2c_csr_assert.ovrd_rd_A	0	0	536229817	4544	0	0
tb.dut.i2c_csr_assert.target_id_rd_A	0	0	536229817	3761	0	0
tb.dut.i2c_csr_assert.timeout_ctrl_rd_A	0	0	536229817	3268	0	0
tb.dut.i2c_csr_assert.timing0_rd_A	0	0	536229817	3470	0	0
tb.dut.i2c_csr_assert.timing1_rd_A	0	0	536229817	3185	0	0
tb.dut.i2c_csr_assert.timing2_rd_A	0	0	536229817	3757	0	0
tb.dut.i2c_csr_assert.timing3_rd_A	0	0	536229817	3085	0	0
tb.dut.i2c_csr_assert.timing4_rd_A	0	0	536229817	3614	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	536229817	84493013	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	536229817	536015321	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	536229817	536015321	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	536229817	99116725	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	536229817	536015321	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	536229817	536015321	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
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tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1625	1625	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	536230812	11569497	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	536229817	50983	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	536230812	75349920	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	536230812	82466765	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	536229817	56197	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	536230812	84493108	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	536230812	99116857	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	536230812	84493108	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	536230812	99116857	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	536230812	99116857	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	536230812	99116857	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	536229817	31666	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	536229817	23880	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1625	1625	0	0
tb.dut.u_reg.en2addrHit	0	0	536229817	62974075	0	0
tb.dut.u_reg.reAfterRv	0	0	536229817	62973908	0	0
tb.dut.u_reg.rePulse	0	0	536229817	55924464	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1625	1625	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1625	1625	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1625	1625	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1625	1625	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1625	1625	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1625	1625	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1625	1625	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1625	1625	0	0
tb.dut.u_reg.wePulse	0	0	536229817	7049444	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	536230812	1094262	1094262	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	536230812	80	80	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	536230812	85	85	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	536230812	59	59	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	536230812	11	11	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	536230812	42	42	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	536230812	52	52	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	536230812	2766	2766	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	536230812	13724706	13724706	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	536230812	23030992	23030992	1599

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	536230812	1094262	1094262	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	536230812	80	80	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	536230812	85	85	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	536230812	59	59	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	536230812	11	11	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	536230812	42	42	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	536230812	52	52	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	536230812	2766	2766	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	536230812	13724706	13724706	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	536230812	23030992	23030992	1599