Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6603751	1			T17	1		T19	8		T24	5
all_pins[1]	6603751	1			T17	1		T19	8		T24	5
all_pins[2]	6603751	1			T17	1		T19	8		T24	5
all_pins[3]	6603751	1			T17	1		T19	8		T24	5
all_pins[4]	6603751	1			T17	1		T19	8		T24	5
all_pins[5]	6603751	1			T17	1		T19	8		T24	5
all_pins[6]	6603751	1			T17	1		T19	8		T24	5
all_pins[7]	6603751	1			T17	1		T19	8		T24	5
all_pins[8]	6603751	1			T17	1		T19	8		T24	5
all_pins[9]	6603751	1			T17	1		T19	8		T24	5
all_pins[10]	6603751	1			T17	1		T19	8		T24	5
all_pins[11]	6603751	1			T17	1		T19	8		T24	5
all_pins[12]	6603751	1			T17	1		T19	8		T24	5
all_pins[13]	6603751	1			T17	1		T19	8		T24	5
all_pins[14]	6603751	1			T17	1		T19	8		T24	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	93417693	1			T17	15		T19	97		T24	64
values[0x1]	5638572	1			T19	23		T24	11		T68	19
transitions[0x0=>0x1]	3862226	1			T19	19		T24	11		T68	15
transitions[0x1=>0x0]	3862233	1			T19	19		T24	11		T68	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	5734238	1			T17	1		T19	8		T24	5
all_pins[0]	values[0x1]	869513	1			T69	1		T93	2		T140	2
all_pins[0]	transitions[0x0=>0x1]	311047	1			T69	1		T93	1		T140	2
all_pins[0]	transitions[0x1=>0x0]	32648	1			T19	3		T24	1		T9	113
all_pins[1]	values[0x0]	6012637	1			T17	1		T19	5		T24	4
all_pins[1]	values[0x1]	591114	1			T19	3		T24	1		T93	1
all_pins[1]	transitions[0x0=>0x1]	591082	1			T19	3		T24	1		T93	1
all_pins[1]	transitions[0x1=>0x0]	77	1			T19	1		T69	1		T112	2
all_pins[2]	values[0x0]	6603642	1			T17	1		T19	7		T24	5
all_pins[2]	values[0x1]	109	1			T19	1		T69	1		T112	2
all_pins[2]	transitions[0x0=>0x1]	77	1			T19	1		T69	1		T112	2
all_pins[2]	transitions[0x1=>0x0]	86	1			T19	2		T24	1		T69	1
all_pins[3]	values[0x0]	6603633	1			T17	1		T19	6		T24	4
all_pins[3]	values[0x1]	118	1			T19	2		T24	1		T69	1
all_pins[3]	transitions[0x0=>0x1]	86	1			T19	2		T24	1		T69	1
all_pins[3]	transitions[0x1=>0x0]	164	1			T19	4		T24	1		T68	2
all_pins[4]	values[0x0]	6603555	1			T17	1		T19	4		T24	4
all_pins[4]	values[0x1]	196	1			T19	4		T24	1		T68	2
all_pins[4]	transitions[0x0=>0x1]	152	1			T19	4		T24	1		T93	4
all_pins[4]	transitions[0x1=>0x0]	83	1			T24	2		T68	1		T69	1
all_pins[5]	values[0x0]	6603624	1			T17	1		T19	8		T24	3
all_pins[5]	values[0x1]	127	1			T24	2		T68	3		T69	2
all_pins[5]	transitions[0x0=>0x1]	85	1			T24	2		T68	2		T69	1
all_pins[5]	transitions[0x1=>0x0]	944616	1			T19	3		T68	1		T69	2
all_pins[6]	values[0x0]	5659093	1			T17	1		T19	5		T24	5
all_pins[6]	values[0x1]	944658	1			T19	3		T68	2		T69	3
all_pins[6]	transitions[0x0=>0x1]	922559	1			T19	3		T68	2		T69	3
all_pins[6]	transitions[0x1=>0x0]	335847	1			T19	1		T24	3		T68	3
all_pins[7]	values[0x0]	6245805	1			T17	1		T19	7		T24	2
all_pins[7]	values[0x1]	357946	1			T19	1		T24	3		T68	3
all_pins[7]	transitions[0x0=>0x1]	293172	1			T19	1		T24	3		T68	3
all_pins[7]	transitions[0x1=>0x0]	1081712	1			T19	2		T93	1		T9	205
all_pins[8]	values[0x0]	5457265	1			T17	1		T19	6		T24	5
all_pins[8]	values[0x1]	1146486	1			T19	2		T93	2		T2	1
all_pins[8]	transitions[0x0=>0x1]	243587	1			T93	2		T9	222		T10	2845
all_pins[8]	transitions[0x1=>0x0]	194520	1			T68	1		T112	4		T1	1077
all_pins[9]	values[0x0]	5506332	1			T17	1		T19	6		T24	5
all_pins[9]	values[0x1]	1097419	1			T19	2		T68	1		T112	4
all_pins[9]	transitions[0x0=>0x1]	1019607	1			T19	1		T68	1		T112	3
all_pins[9]	transitions[0x1=>0x0]	75777	1			T19	1		T24	2		T68	2
all_pins[10]	values[0x0]	6450162	1			T17	1		T19	6		T24	3
all_pins[10]	values[0x1]	153589	1			T19	2		T24	2		T68	2
all_pins[10]	transitions[0x0=>0x1]	3582	1			T19	1		T24	2		T68	2
all_pins[10]	transitions[0x1=>0x0]	326964	1			T19	1		T68	1		T93	3
all_pins[11]	values[0x0]	6126780	1			T17	1		T19	6		T24	5
all_pins[11]	values[0x1]	476971	1			T19	2		T68	1		T93	3
all_pins[11]	transitions[0x0=>0x1]	476951	1			T19	2		T68	1		T93	1
all_pins[11]	transitions[0x1=>0x0]	89	1			T24	1		T68	2		T69	1
all_pins[12]	values[0x0]	6603642	1			T17	1		T19	8		T24	4
all_pins[12]	values[0x1]	109	1			T24	1		T68	2		T69	1
all_pins[12]	transitions[0x0=>0x1]	83	1			T24	1		T68	2		T69	1
all_pins[12]	transitions[0x1=>0x0]	80	1			T68	1		T140	2		T49	2
all_pins[13]	values[0x0]	6603645	1			T17	1		T19	8		T24	5
all_pins[13]	values[0x1]	106	1			T68	1		T140	2		T30	1
all_pins[13]	transitions[0x0=>0x1]	77	1			T68	1		T49	2		T130	3
all_pins[13]	transitions[0x1=>0x0]	82	1			T19	1		T68	2		T69	3
all_pins[14]	values[0x0]	6603640	1			T17	1		T19	7		T24	5
all_pins[14]	values[0x1]	111	1			T19	1		T68	2		T69	3
all_pins[14]	transitions[0x0=>0x1]	79	1			T19	1		T68	1		T69	3
all_pins[14]	transitions[0x1=>0x0]	869488	1			T69	1		T93	2		T140	1