Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	475	1			T19	7		T24	4		T68	7
all_values[1]	475	1			T19	7		T24	4		T68	7
all_values[2]	475	1			T19	7		T24	4		T68	7
all_values[3]	475	1			T19	7		T24	4		T68	7
all_values[4]	475	1			T19	7		T24	4		T68	7
all_values[5]	475	1			T19	7		T24	4		T68	7
all_values[6]	475	1			T19	7		T24	4		T68	7
all_values[7]	475	1			T19	7		T24	4		T68	7
all_values[8]	475	1			T19	7		T24	4		T68	7
all_values[9]	475	1			T19	7		T24	4		T68	7
all_values[10]	475	1			T19	7		T24	4		T68	7
all_values[11]	475	1			T19	7		T24	4		T68	7
all_values[12]	475	1			T19	7		T24	4		T68	7
all_values[13]	475	1			T19	7		T24	4		T68	7
all_values[14]	475	1			T19	7		T24	4		T68	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3653

1

T19

55

T24

25

T68

60

auto[1]

3472

1

T19

50

T24

35

T68

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T19

10

T24

18

T68

23

auto[1]

6003

1

T19

95

T24

42

T68

82

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4172

1

T19

59

T24

41

T68

64

auto[1]

2953

1

T19

46

T24

19

T68

41

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1			T130	2		T187	1		T163	1
all_values[0]	auto[0]	auto[0]	auto[1]	95	1			T19	3		T24	1		T68	1
all_values[0]	auto[0]	auto[1]	auto[0]	25	1			T69	1		T188	1		T187	1
all_values[0]	auto[0]	auto[1]	auto[1]	89	1			T19	1		T24	1		T69	1
all_values[0]	auto[1]	auto[0]	auto[1]	128	1			T19	2		T24	2		T68	6
all_values[0]	auto[1]	auto[1]	auto[1]	105	1			T19	1		T69	1		T93	2
all_values[1]	auto[0]	auto[0]	auto[0]	35	1			T68	2		T140	2		T30	1
all_values[1]	auto[0]	auto[0]	auto[1]	129	1			T19	2		T24	1		T68	2
all_values[1]	auto[0]	auto[1]	auto[0]	32	1			T68	2		T69	2		T140	2
all_values[1]	auto[0]	auto[1]	auto[1]	93	1			T19	2		T24	2		T69	1
all_values[1]	auto[1]	auto[0]	auto[1]	105	1			T19	2		T69	1		T93	4
all_values[1]	auto[1]	auto[1]	auto[1]	81	1			T19	1		T24	1		T68	1
all_values[2]	auto[0]	auto[0]	auto[0]	33	1			T24	1		T68	2		T140	1
all_values[2]	auto[0]	auto[0]	auto[1]	105	1			T19	1		T68	2		T93	4
all_values[2]	auto[0]	auto[1]	auto[0]	38	1			T24	3		T68	2		T112	1
all_values[2]	auto[0]	auto[1]	auto[1]	109	1			T69	5		T93	1		T112	2
all_values[2]	auto[1]	auto[0]	auto[1]	99	1			T19	5		T68	1		T69	1
all_values[2]	auto[1]	auto[1]	auto[1]	91	1			T19	1		T69	1		T112	1
all_values[3]	auto[0]	auto[0]	auto[0]	40	1			T49	2		T32	1		T189	1
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T19	1		T24	1		T68	2
all_values[3]	auto[0]	auto[1]	auto[0]	36	1			T30	1		T49	2		T32	1
all_values[3]	auto[0]	auto[1]	auto[1]	121	1			T19	3		T24	2		T68	2
all_values[3]	auto[1]	auto[0]	auto[1]	109	1			T19	1		T68	3		T69	2
all_values[3]	auto[1]	auto[1]	auto[1]	81	1			T19	2		T24	1		T93	1
all_values[4]	auto[0]	auto[0]	auto[0]	36	1			T19	1		T112	2		T140	1
all_values[4]	auto[0]	auto[0]	auto[1]	93	1			T24	1		T68	1		T69	1
all_values[4]	auto[0]	auto[1]	auto[0]	37	1			T19	2		T112	2		T129	3
all_values[4]	auto[0]	auto[1]	auto[1]	110	1			T19	1		T68	3		T69	3
all_values[4]	auto[1]	auto[0]	auto[1]	99	1			T24	2		T68	1		T93	2
all_values[4]	auto[1]	auto[1]	auto[1]	100	1			T19	3		T24	1		T68	2
all_values[5]	auto[0]	auto[0]	auto[0]	41	1			T19	1		T93	1		T112	2
all_values[5]	auto[0]	auto[0]	auto[1]	85	1			T19	3		T129	1		T32	2
all_values[5]	auto[0]	auto[1]	auto[0]	47	1			T19	1		T24	1		T93	1
all_values[5]	auto[0]	auto[1]	auto[1]	116	1			T24	1		T68	3		T69	2
all_values[5]	auto[1]	auto[0]	auto[1]	103	1			T19	2		T24	1		T69	2
all_values[5]	auto[1]	auto[1]	auto[1]	83	1			T24	1		T68	4		T69	3
all_values[6]	auto[0]	auto[0]	auto[0]	42	1			T19	1		T24	2		T68	1
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T19	2		T24	1		T68	1
all_values[6]	auto[0]	auto[1]	auto[0]	24	1			T140	1		T129	2		T49	2
all_values[6]	auto[0]	auto[1]	auto[1]	114	1			T19	2		T68	1		T69	1
all_values[6]	auto[1]	auto[0]	auto[1]	87	1			T24	1		T68	1		T69	2
all_values[6]	auto[1]	auto[1]	auto[1]	120	1			T19	2		T68	3		T69	3
all_values[7]	auto[0]	auto[0]	auto[0]	41	1			T30	2		T188	1		T142	2
all_values[7]	auto[0]	auto[0]	auto[1]	108	1			T19	2		T24	1		T68	2
all_values[7]	auto[0]	auto[1]	auto[0]	32	1			T68	1		T69	1		T112	4
all_values[7]	auto[0]	auto[1]	auto[1]	98	1			T19	1		T24	1		T68	2
all_values[7]	auto[1]	auto[0]	auto[1]	100	1			T19	3		T24	1		T68	2
all_values[7]	auto[1]	auto[1]	auto[1]	96	1			T19	1		T24	1		T69	1
all_values[8]	auto[0]	auto[0]	auto[0]	47	1			T68	3		T30	1		T129	1
all_values[8]	auto[0]	auto[0]	auto[1]	110	1			T19	3		T69	2		T93	3
all_values[8]	auto[0]	auto[1]	auto[0]	36	1			T24	2		T68	1		T69	2
all_values[8]	auto[0]	auto[1]	auto[1]	94	1			T24	1		T68	2		T69	1
all_values[8]	auto[1]	auto[0]	auto[1]	100	1			T19	1		T69	1		T93	2
all_values[8]	auto[1]	auto[1]	auto[1]	88	1			T19	3		T24	1		T68	1
all_values[9]	auto[0]	auto[0]	auto[0]	41	1			T68	1		T140	1		T129	1
all_values[9]	auto[0]	auto[0]	auto[1]	110	1			T19	1		T24	1		T68	3
all_values[9]	auto[0]	auto[1]	auto[0]	40	1			T19	1		T24	2		T69	3
all_values[9]	auto[0]	auto[1]	auto[1]	96	1			T19	1		T69	3		T112	2
all_values[9]	auto[1]	auto[0]	auto[1]	106	1			T19	2		T24	1		T68	1
all_values[9]	auto[1]	auto[1]	auto[1]	82	1			T19	2		T68	2		T69	1
all_values[10]	auto[0]	auto[0]	auto[0]	45	1			T68	4		T49	1		T32	1
all_values[10]	auto[0]	auto[0]	auto[1]	83	1			T19	3		T69	2		T93	2
all_values[10]	auto[0]	auto[1]	auto[0]	46	1			T24	1		T93	1		T188	1
all_values[10]	auto[0]	auto[1]	auto[1]	106	1			T19	1		T24	1		T68	1
all_values[10]	auto[1]	auto[0]	auto[1]	88	1			T68	1		T69	1		T93	1
all_values[10]	auto[1]	auto[1]	auto[1]	107	1			T19	3		T24	2		T68	1
all_values[11]	auto[0]	auto[0]	auto[0]	37	1			T24	2		T112	2		T140	2
all_values[11]	auto[0]	auto[0]	auto[1]	113	1			T19	2		T68	3		T69	3
all_values[11]	auto[0]	auto[1]	auto[0]	30	1			T24	2		T68	1		T112	2
all_values[11]	auto[0]	auto[1]	auto[1]	97	1			T19	2		T68	1		T69	2
all_values[11]	auto[1]	auto[0]	auto[1]	107	1			T19	2		T68	1		T69	2
all_values[11]	auto[1]	auto[1]	auto[1]	91	1			T19	1		T68	1		T93	1
all_values[12]	auto[0]	auto[0]	auto[0]	46	1			T19	1		T69	2		T112	4
all_values[12]	auto[0]	auto[0]	auto[1]	84	1			T19	1		T24	1		T68	2
all_values[12]	auto[0]	auto[1]	auto[0]	35	1			T19	1		T24	1		T69	3
all_values[12]	auto[0]	auto[1]	auto[1]	110	1			T19	2		T24	1		T68	1
all_values[12]	auto[1]	auto[0]	auto[1]	102	1			T19	1		T68	3		T69	1
all_values[12]	auto[1]	auto[1]	auto[1]	98	1			T19	1		T24	1		T68	1
all_values[13]	auto[0]	auto[0]	auto[0]	37	1			T19	1		T68	2		T93	1
all_values[13]	auto[0]	auto[0]	auto[1]	122	1			T19	1		T24	3		T69	3
all_values[13]	auto[0]	auto[1]	auto[0]	30	1			T68	1		T112	2		T188	1
all_values[13]	auto[0]	auto[1]	auto[1]	86	1			T19	3		T68	3		T69	1
all_values[13]	auto[1]	auto[0]	auto[1]	112	1			T19	2		T24	1		T69	3
all_values[13]	auto[1]	auto[1]	auto[1]	88	1			T68	1		T93	1		T140	1
all_values[14]	auto[0]	auto[0]	auto[0]	43	1			T93	1		T112	2		T140	1
all_values[14]	auto[0]	auto[0]	auto[1]	83	1			T68	3		T69	2		T30	1
all_values[14]	auto[0]	auto[1]	auto[0]	37	1			T24	1		T69	2		T140	1
all_values[14]	auto[0]	auto[1]	auto[1]	115	1			T19	5		T24	2		T69	1
all_values[14]	auto[1]	auto[0]	auto[1]	115	1			T19	2		T68	3		T93	3
all_values[14]	auto[1]	auto[1]	auto[1]	82	1			T24	1		T68	1		T69	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal