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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.88 99.17 96.65 100.00 98.26 98.24 100.00 92.86


Total test records in report: 1625
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T114 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1651883443 Jan 24 12:55:58 PM PST 24 Jan 24 12:56:33 PM PST 24 44974763 ps
T126 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4101422953 Jan 24 12:55:46 PM PST 24 Jan 24 12:56:20 PM PST 24 39726005 ps
T1519 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1180634084 Jan 24 01:33:56 PM PST 24 Jan 24 01:34:34 PM PST 24 50252047 ps
T1520 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.801238296 Jan 24 12:55:49 PM PST 24 Jan 24 12:56:25 PM PST 24 86534772 ps
T1521 /workspace/coverage/cover_reg_top/9.i2c_intr_test.3151572598 Jan 24 12:55:45 PM PST 24 Jan 24 12:56:20 PM PST 24 50596427 ps
T1522 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.930147384 Jan 24 01:29:37 PM PST 24 Jan 24 01:29:52 PM PST 24 146555882 ps
T1523 /workspace/coverage/cover_reg_top/23.i2c_intr_test.811540400 Jan 24 12:56:12 PM PST 24 Jan 24 12:56:42 PM PST 24 18021562 ps
T127 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2131465572 Jan 24 12:55:50 PM PST 24 Jan 24 12:56:27 PM PST 24 108883412 ps
T1524 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1703083110 Jan 24 12:55:38 PM PST 24 Jan 24 12:56:09 PM PST 24 57979867 ps
T1525 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2363167266 Jan 24 01:04:13 PM PST 24 Jan 24 01:04:58 PM PST 24 18808250 ps
T128 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.212605283 Jan 24 12:55:02 PM PST 24 Jan 24 12:55:17 PM PST 24 49884494 ps
T1526 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3817427562 Jan 24 12:54:50 PM PST 24 Jan 24 12:55:00 PM PST 24 221677504 ps
T1527 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2835419105 Jan 24 12:55:59 PM PST 24 Jan 24 12:56:33 PM PST 24 42113665 ps
T1528 /workspace/coverage/cover_reg_top/31.i2c_intr_test.1587661441 Jan 24 12:56:22 PM PST 24 Jan 24 12:56:53 PM PST 24 70576528 ps
T1529 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3819358986 Jan 24 12:54:51 PM PST 24 Jan 24 12:55:02 PM PST 24 1475490739 ps
T172 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1064998227 Jan 24 12:55:22 PM PST 24 Jan 24 12:55:56 PM PST 24 47425401 ps
T1530 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2410230107 Jan 24 12:54:44 PM PST 24 Jan 24 12:54:54 PM PST 24 282140323 ps
T1531 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3168976771 Jan 24 01:58:19 PM PST 24 Jan 24 01:58:34 PM PST 24 129750523 ps
T1532 /workspace/coverage/cover_reg_top/19.i2c_intr_test.2175659704 Jan 24 12:56:00 PM PST 24 Jan 24 12:56:33 PM PST 24 37062527 ps
T1533 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2857190187 Jan 24 12:56:08 PM PST 24 Jan 24 12:56:38 PM PST 24 88384612 ps
T1534 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3311625793 Jan 24 12:55:08 PM PST 24 Jan 24 12:55:36 PM PST 24 32188174 ps
T1535 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3139935299 Jan 24 12:55:16 PM PST 24 Jan 24 12:55:47 PM PST 24 69971248 ps
T1536 /workspace/coverage/cover_reg_top/5.i2c_intr_test.1126767821 Jan 24 12:55:10 PM PST 24 Jan 24 12:55:38 PM PST 24 19752992 ps
T1537 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3409949061 Jan 24 12:56:11 PM PST 24 Jan 24 12:56:42 PM PST 24 17021010 ps
T1538 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.873438251 Jan 24 12:55:46 PM PST 24 Jan 24 12:56:20 PM PST 24 35579252 ps
T1539 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2635541058 Jan 24 12:54:47 PM PST 24 Jan 24 12:54:56 PM PST 24 27374397 ps
T1540 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1307768469 Jan 24 12:55:58 PM PST 24 Jan 24 12:56:33 PM PST 24 38324665 ps
T173 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.136272772 Jan 24 12:55:44 PM PST 24 Jan 24 12:56:20 PM PST 24 506553012 ps
T1541 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3648981434 Jan 24 12:55:35 PM PST 24 Jan 24 12:56:06 PM PST 24 46644187 ps
T1542 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2356862817 Jan 24 12:55:56 PM PST 24 Jan 24 12:56:33 PM PST 24 41611973 ps
T115 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1157294046 Jan 24 12:55:08 PM PST 24 Jan 24 12:55:37 PM PST 24 121154817 ps
T1543 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.555060411 Jan 24 12:55:20 PM PST 24 Jan 24 12:55:51 PM PST 24 23949884 ps
T1544 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1652130724 Jan 24 01:26:00 PM PST 24 Jan 24 01:26:52 PM PST 24 38862892 ps
T1545 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3254290195 Jan 24 12:56:21 PM PST 24 Jan 24 12:56:52 PM PST 24 14873792 ps
T1546 /workspace/coverage/cover_reg_top/33.i2c_intr_test.837465267 Jan 24 12:56:18 PM PST 24 Jan 24 12:56:48 PM PST 24 18485951 ps
T116 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3312472894 Jan 24 12:54:58 PM PST 24 Jan 24 12:55:08 PM PST 24 24416400 ps
T1547 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1252730499 Jan 24 12:55:45 PM PST 24 Jan 24 12:56:20 PM PST 24 206711146 ps
T83 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1860858460 Jan 24 12:56:06 PM PST 24 Jan 24 12:56:38 PM PST 24 143706533 ps
T1548 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3846365746 Jan 24 12:55:31 PM PST 24 Jan 24 12:56:00 PM PST 24 126140178 ps
T1549 /workspace/coverage/cover_reg_top/42.i2c_intr_test.751875825 Jan 24 12:56:19 PM PST 24 Jan 24 12:56:50 PM PST 24 29808546 ps
T1550 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1836873204 Jan 24 01:28:37 PM PST 24 Jan 24 01:29:00 PM PST 24 41914969 ps
T88 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3259879709 Jan 24 12:56:09 PM PST 24 Jan 24 12:56:41 PM PST 24 420349925 ps
T117 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3107919140 Jan 24 12:54:58 PM PST 24 Jan 24 12:55:08 PM PST 24 36070542 ps
T1551 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3760621772 Jan 24 12:56:13 PM PST 24 Jan 24 12:56:43 PM PST 24 19361734 ps
T1552 /workspace/coverage/cover_reg_top/6.i2c_intr_test.19853586 Jan 24 12:55:21 PM PST 24 Jan 24 12:55:55 PM PST 24 15554321 ps
T1553 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3305127879 Jan 24 12:54:50 PM PST 24 Jan 24 12:54:58 PM PST 24 24223353 ps
T1554 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2665290202 Jan 24 12:56:18 PM PST 24 Jan 24 12:56:48 PM PST 24 17940921 ps
T1555 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3585875753 Jan 24 02:24:03 PM PST 24 Jan 24 02:24:16 PM PST 24 32814792 ps
T1556 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.74484919 Jan 24 12:55:02 PM PST 24 Jan 24 12:55:17 PM PST 24 31364637 ps
T1557 /workspace/coverage/cover_reg_top/26.i2c_intr_test.76381225 Jan 24 12:56:14 PM PST 24 Jan 24 12:56:45 PM PST 24 20022408 ps
T1558 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3121005362 Jan 24 12:56:21 PM PST 24 Jan 24 12:56:53 PM PST 24 56087554 ps
T1559 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2923810122 Jan 24 12:55:31 PM PST 24 Jan 24 12:56:01 PM PST 24 94242447 ps
T1560 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3181021382 Jan 24 12:55:09 PM PST 24 Jan 24 12:55:36 PM PST 24 92549473 ps
T1561 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.608239799 Jan 24 12:55:58 PM PST 24 Jan 24 12:56:35 PM PST 24 222103289 ps
T1562 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1650806971 Jan 24 12:55:59 PM PST 24 Jan 24 12:56:33 PM PST 24 36115488 ps
T1563 /workspace/coverage/cover_reg_top/22.i2c_intr_test.2189181660 Jan 24 12:56:14 PM PST 24 Jan 24 12:56:45 PM PST 24 59454482 ps
T118 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3022634197 Jan 24 12:54:59 PM PST 24 Jan 24 12:55:11 PM PST 24 22326519 ps
T1564 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2466728690 Jan 24 12:55:20 PM PST 24 Jan 24 12:55:51 PM PST 24 41837223 ps
T1565 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.302451817 Jan 24 01:09:13 PM PST 24 Jan 24 01:09:52 PM PST 24 47982579 ps
T84 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2002245367 Jan 24 12:54:58 PM PST 24 Jan 24 12:55:09 PM PST 24 62027375 ps
T1566 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3157229351 Jan 24 12:55:20 PM PST 24 Jan 24 12:55:51 PM PST 24 84378925 ps
T1567 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1043471981 Jan 24 12:54:46 PM PST 24 Jan 24 12:54:55 PM PST 24 29556751 ps
T1568 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.293102000 Jan 24 12:55:00 PM PST 24 Jan 24 12:55:14 PM PST 24 40774270 ps
T1569 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1804750959 Jan 24 12:55:05 PM PST 24 Jan 24 12:55:19 PM PST 24 101543163 ps
T1570 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1266426554 Jan 24 12:54:59 PM PST 24 Jan 24 12:55:13 PM PST 24 48013216 ps
T1571 /workspace/coverage/cover_reg_top/46.i2c_intr_test.600871165 Jan 24 01:19:52 PM PST 24 Jan 24 01:20:54 PM PST 24 38683269 ps
T1572 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.482015195 Jan 24 01:22:48 PM PST 24 Jan 24 01:23:45 PM PST 24 1109847319 ps
T1573 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1927877627 Jan 24 12:56:00 PM PST 24 Jan 24 12:56:34 PM PST 24 23159543 ps
T1574 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3669853090 Jan 24 12:55:56 PM PST 24 Jan 24 12:56:32 PM PST 24 22113645 ps
T1575 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3728122395 Jan 24 12:55:57 PM PST 24 Jan 24 12:56:33 PM PST 24 22041906 ps
T1576 /workspace/coverage/cover_reg_top/8.i2c_intr_test.3521666979 Jan 24 12:55:36 PM PST 24 Jan 24 12:56:04 PM PST 24 17195764 ps
T1577 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1109094241 Jan 24 12:55:32 PM PST 24 Jan 24 12:56:00 PM PST 24 19704060 ps
T1578 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2888535661 Jan 24 12:55:16 PM PST 24 Jan 24 12:55:46 PM PST 24 77438383 ps
T1579 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3835024673 Jan 24 12:55:44 PM PST 24 Jan 24 12:56:19 PM PST 24 27148997 ps
T119 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2935493646 Jan 24 12:55:28 PM PST 24 Jan 24 12:55:56 PM PST 24 37855370 ps
T1580 /workspace/coverage/cover_reg_top/2.i2c_intr_test.406402746 Jan 24 12:55:00 PM PST 24 Jan 24 12:55:14 PM PST 24 17972444 ps
T1581 /workspace/coverage/cover_reg_top/21.i2c_intr_test.812306088 Jan 24 12:56:18 PM PST 24 Jan 24 12:56:48 PM PST 24 32079030 ps
T1582 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2499605985 Jan 24 01:02:32 PM PST 24 Jan 24 01:02:39 PM PST 24 44608476 ps
T1583 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3178864979 Jan 24 12:55:58 PM PST 24 Jan 24 12:56:33 PM PST 24 28109435 ps
T1584 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3267551053 Jan 24 12:55:08 PM PST 24 Jan 24 12:55:34 PM PST 24 39323591 ps
T120 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4161592237 Jan 24 01:28:55 PM PST 24 Jan 24 01:29:13 PM PST 24 18802050 ps
T1585 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2927742630 Jan 24 12:55:42 PM PST 24 Jan 24 12:56:14 PM PST 24 31917727 ps
T1586 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1582796170 Jan 24 12:56:12 PM PST 24 Jan 24 12:56:42 PM PST 24 64800791 ps
T1587 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.836101073 Jan 24 12:55:10 PM PST 24 Jan 24 12:55:38 PM PST 24 31993826 ps
T1588 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.412298579 Jan 24 01:00:11 PM PST 24 Jan 24 01:00:32 PM PST 24 39537275 ps
T1589 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1752497799 Jan 24 12:56:08 PM PST 24 Jan 24 12:56:39 PM PST 24 27276726 ps
T1590 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2115646538 Jan 24 12:54:46 PM PST 24 Jan 24 12:54:56 PM PST 24 148505982 ps
T1591 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.142792190 Jan 24 01:04:55 PM PST 24 Jan 24 01:05:43 PM PST 24 97121960 ps
T1592 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1190621213 Jan 24 01:23:25 PM PST 24 Jan 24 01:24:13 PM PST 24 17741003 ps
T1593 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2727782251 Jan 24 12:56:21 PM PST 24 Jan 24 12:56:53 PM PST 24 81260935 ps
T1594 /workspace/coverage/cover_reg_top/1.i2c_intr_test.1042592323 Jan 24 12:54:44 PM PST 24 Jan 24 12:54:51 PM PST 24 15638556 ps
T1595 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.991513200 Jan 24 12:55:45 PM PST 24 Jan 24 12:56:21 PM PST 24 34758595 ps
T1596 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2286286931 Jan 24 01:32:11 PM PST 24 Jan 24 01:32:56 PM PST 24 146790127 ps
T1597 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1872516910 Jan 24 01:31:31 PM PST 24 Jan 24 01:32:22 PM PST 24 142033685 ps
T1598 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2552169367 Jan 24 12:56:09 PM PST 24 Jan 24 12:56:40 PM PST 24 24852754 ps
T90 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2528676657 Jan 24 12:55:47 PM PST 24 Jan 24 12:56:22 PM PST 24 383997259 ps
T1599 /workspace/coverage/cover_reg_top/15.i2c_intr_test.738014524 Jan 24 01:08:16 PM PST 24 Jan 24 01:08:55 PM PST 24 18554617 ps
T1600 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1804304806 Jan 24 12:55:49 PM PST 24 Jan 24 12:56:24 PM PST 24 52003979 ps
T1601 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3062528091 Jan 24 12:56:17 PM PST 24 Jan 24 12:56:47 PM PST 24 25620074 ps
T123 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1881867449 Jan 24 12:55:40 PM PST 24 Jan 24 12:56:11 PM PST 24 27770836 ps
T1602 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2354408331 Jan 24 12:55:00 PM PST 24 Jan 24 12:55:16 PM PST 24 379610177 ps
T1603 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1282220428 Jan 24 12:54:55 PM PST 24 Jan 24 12:55:02 PM PST 24 72879076 ps
T1604 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2485596399 Jan 24 01:06:21 PM PST 24 Jan 24 01:07:18 PM PST 24 18709978 ps
T1605 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2002401802 Jan 24 12:54:59 PM PST 24 Jan 24 12:55:11 PM PST 24 49037516 ps
T1606 /workspace/coverage/cover_reg_top/27.i2c_intr_test.3957365726 Jan 24 01:04:29 PM PST 24 Jan 24 01:05:10 PM PST 24 18094671 ps
T122 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1371744917 Jan 24 12:54:47 PM PST 24 Jan 24 12:54:56 PM PST 24 18282622 ps
T1607 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2375017668 Jan 24 01:12:37 PM PST 24 Jan 24 01:13:30 PM PST 24 43562626 ps
T1608 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.384508141 Jan 24 12:54:58 PM PST 24 Jan 24 12:55:08 PM PST 24 51025737 ps
T1609 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3860905859 Jan 24 12:54:56 PM PST 24 Jan 24 12:55:03 PM PST 24 20439051 ps
T1610 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1716843578 Jan 24 12:55:30 PM PST 24 Jan 24 12:56:01 PM PST 24 41968692 ps
T1611 /workspace/coverage/cover_reg_top/35.i2c_intr_test.2913766103 Jan 24 12:56:12 PM PST 24 Jan 24 12:56:43 PM PST 24 18702453 ps
T1612 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.334780362 Jan 24 12:55:59 PM PST 24 Jan 24 12:56:33 PM PST 24 36274595 ps
T1613 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3094678427 Jan 24 12:56:09 PM PST 24 Jan 24 12:56:40 PM PST 24 169354440 ps
T1614 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.258945116 Jan 24 12:55:20 PM PST 24 Jan 24 12:55:51 PM PST 24 24412881 ps
T1615 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2043760040 Jan 24 12:55:50 PM PST 24 Jan 24 12:56:29 PM PST 24 460631403 ps
T1616 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2545859200 Jan 24 12:55:55 PM PST 24 Jan 24 12:56:32 PM PST 24 393982996 ps
T1617 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.616194396 Jan 24 12:55:49 PM PST 24 Jan 24 12:56:26 PM PST 24 66997754 ps
T1618 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2608306389 Jan 24 12:55:45 PM PST 24 Jan 24 12:56:21 PM PST 24 84293813 ps
T1619 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3205627400 Jan 24 12:55:20 PM PST 24 Jan 24 12:55:53 PM PST 24 344630019 ps
T1620 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2227109786 Jan 24 12:55:56 PM PST 24 Jan 24 12:56:34 PM PST 24 135610425 ps
T1621 /workspace/coverage/cover_reg_top/28.i2c_intr_test.1082785425 Jan 24 12:56:11 PM PST 24 Jan 24 12:56:42 PM PST 24 64310554 ps
T1622 /workspace/coverage/cover_reg_top/47.i2c_intr_test.561204017 Jan 24 12:56:26 PM PST 24 Jan 24 12:56:58 PM PST 24 18365744 ps
T1623 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2486620224 Jan 24 12:56:09 PM PST 24 Jan 24 12:56:39 PM PST 24 28164152 ps
T1624 /workspace/coverage/cover_reg_top/49.i2c_intr_test.4186969371 Jan 24 01:08:18 PM PST 24 Jan 24 01:08:56 PM PST 24 37958871 ps
T1625 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.68291424 Jan 24 12:54:58 PM PST 24 Jan 24 12:55:09 PM PST 24 62178219 ps

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3089712832
Short name T17
Test name
Test status
Simulation time 111892885 ps
CPU time 1.42 seconds
Started Jan 24 12:54:46 PM PST 24
Finished Jan 24 12:54:57 PM PST 24
Peak memory 203448 kb
Host smart-6ffb32c4-683d-4d5d-9454-e85f000e446e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089712832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3089712832
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3198278522
Short name T9
Test name
Test status
Simulation time 2141727441 ps
CPU time 53.53 seconds
Started Jan 24 11:30:18 PM PST 24
Finished Jan 24 11:31:15 PM PST 24
Peak memory 255256 kb
Host smart-a36c5e02-fb61-440e-b331-ea4e04a2c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198278522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3198278522
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3254535857
Short name T21
Test name
Test status
Simulation time 237187231 ps
CPU time 1.81 seconds
Started Jan 24 12:55:45 PM PST 24
Finished Jan 24 12:56:20 PM PST 24
Peak memory 203276 kb
Host smart-a44bd53c-a4e5-4dd0-a9bf-6afee0dac3af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254535857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3254535857
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.461381351
Short name T16
Test name
Test status
Simulation time 70436657280 ps
CPU time 87.44 seconds
Started Jan 24 10:30:47 PM PST 24
Finished Jan 24 10:32:16 PM PST 24
Peak memory 261740 kb
Host smart-010f392a-5979-4ee3-b3fb-754e7e043002
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461381351 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.i2c_target_stress_all.461381351
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.297896524
Short name T19
Test name
Test status
Simulation time 18684731 ps
CPU time 0.72 seconds
Started Jan 24 12:55:01 PM PST 24
Finished Jan 24 12:55:15 PM PST 24
Peak memory 203080 kb
Host smart-3825ba9c-bb04-4766-bc96-6094d24adc32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297896524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.297896524
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3261688165
Short name T30
Test name
Test status
Simulation time 163818825788 ps
CPU time 3409.51 seconds
Started Jan 25 12:26:25 AM PST 24
Finished Jan 25 01:23:16 AM PST 24
Peak memory 1779260 kb
Host smart-a529c863-7e0e-486d-ba49-08236b3af12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261688165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3261688165
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3307048934
Short name T12
Test name
Test status
Simulation time 17234206980 ps
CPU time 210.03 seconds
Started Jan 24 10:38:54 PM PST 24
Finished Jan 24 10:42:25 PM PST 24
Peak memory 1193664 kb
Host smart-616f0233-2770-4400-9c37-06fb463d837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307048934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3307048934
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2990951288
Short name T187
Test name
Test status
Simulation time 50289731134 ps
CPU time 1752.17 seconds
Started Jan 24 09:55:06 PM PST 24
Finished Jan 24 10:24:28 PM PST 24
Peak memory 910596 kb
Host smart-473f781b-99a6-430a-baa4-a59348c6b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990951288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2990951288
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.3925136400
Short name T156
Test name
Test status
Simulation time 36527389041 ps
CPU time 947.02 seconds
Started Jan 24 10:24:05 PM PST 24
Finished Jan 24 10:39:53 PM PST 24
Peak memory 2948640 kb
Host smart-10bbbd09-c3a6-45c5-918a-b6e75a0f7857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925136400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.3925136400
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_override.1117919284
Short name T143
Test name
Test status
Simulation time 21472160 ps
CPU time 0.66 seconds
Started Jan 24 10:03:51 PM PST 24
Finished Jan 24 10:03:58 PM PST 24
Peak memory 201444 kb
Host smart-811edac3-58ff-4cd7-afa5-241d8cf666a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117919284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1117919284
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.433624461
Short name T92
Test name
Test status
Simulation time 52140247 ps
CPU time 0.75 seconds
Started Jan 24 12:55:25 PM PST 24
Finished Jan 24 12:55:56 PM PST 24
Peak memory 203080 kb
Host smart-ecb5e742-de92-4d3f-b5bf-484464cb8641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433624461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.433624461
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1284726648
Short name T54
Test name
Test status
Simulation time 828957301 ps
CPU time 3.97 seconds
Started Jan 24 09:55:01 PM PST 24
Finished Jan 24 09:55:08 PM PST 24
Peak memory 202840 kb
Host smart-615b51d9-7754-4ad5-a92a-d71313c4d804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284726648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1284726648
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1168455230
Short name T77
Test name
Test status
Simulation time 158429174 ps
CPU time 0.82 seconds
Started Jan 24 09:55:23 PM PST 24
Finished Jan 24 09:55:25 PM PST 24
Peak memory 218452 kb
Host smart-e5bbe8da-1e45-497e-ba81-ea80a3393c21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168455230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1168455230
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.3280864515
Short name T49
Test name
Test status
Simulation time 11374094762 ps
CPU time 781.6 seconds
Started Jan 24 10:07:40 PM PST 24
Finished Jan 24 10:20:43 PM PST 24
Peak memory 1499016 kb
Host smart-4fd24f4f-316e-4aca-9f82-d28877dda986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280864515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3280864515
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1001302281
Short name T259
Test name
Test status
Simulation time 8829729014 ps
CPU time 77.11 seconds
Started Jan 24 10:18:22 PM PST 24
Finished Jan 24 10:19:40 PM PST 24
Peak memory 325972 kb
Host smart-eef61353-de9a-4de7-99f1-bd6bdc028e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001302281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1001302281
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_target_tx_ovf.155441950
Short name T63
Test name
Test status
Simulation time 12345575038 ps
CPU time 183.17 seconds
Started Jan 25 12:51:10 AM PST 24
Finished Jan 25 12:54:15 AM PST 24
Peak memory 373992 kb
Host smart-27940664-438a-489c-bfd7-f844fafb6821
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155441950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_tx_ovf.155441950
Directory /workspace/27.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all_with_rand_reset.1719731700
Short name T43
Test name
Test status
Simulation time 31790063127 ps
CPU time 959.04 seconds
Started Jan 24 10:03:43 PM PST 24
Finished Jan 24 10:19:44 PM PST 24
Peak memory 1345416 kb
Host smart-c9204320-28ee-410f-84dd-5af55d09770d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719731700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.i2c_host_stress_all_with_rand_reset.1719731700
Directory /workspace/12.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3972218053
Short name T200
Test name
Test status
Simulation time 348028465 ps
CPU time 0.91 seconds
Started Jan 24 11:11:49 PM PST 24
Finished Jan 24 11:11:52 PM PST 24
Peak memory 202368 kb
Host smart-4f915bc6-383e-4c81-bd8a-4ac634c103f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972218053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3972218053
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2948311204
Short name T50
Test name
Test status
Simulation time 108349017415 ps
CPU time 1597.62 seconds
Started Jan 24 10:55:44 PM PST 24
Finished Jan 24 11:22:25 PM PST 24
Peak memory 2487988 kb
Host smart-d50c6a05-e443-42d0-aace-44d40257c524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948311204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2948311204
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1968694728
Short name T166
Test name
Test status
Simulation time 65737726935 ps
CPU time 941.09 seconds
Started Jan 24 10:05:54 PM PST 24
Finished Jan 24 10:21:36 PM PST 24
Peak memory 1360284 kb
Host smart-8591f520-da22-45e8-afd9-112819af2bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968694728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1968694728
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3097648095
Short name T40
Test name
Test status
Simulation time 4045884767 ps
CPU time 4.18 seconds
Started Jan 24 09:55:34 PM PST 24
Finished Jan 24 09:55:40 PM PST 24
Peak memory 202680 kb
Host smart-0f74f0b8-7e5c-46cb-94d2-6d3ae9726cb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097648095 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3097648095
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2913755346
Short name T140
Test name
Test status
Simulation time 30878794 ps
CPU time 0.65 seconds
Started Jan 24 12:55:57 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203076 kb
Host smart-d91e6844-f99a-4fef-ad63-74d808575bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913755346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2913755346
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1860858460
Short name T83
Test name
Test status
Simulation time 143706533 ps
CPU time 1.72 seconds
Started Jan 24 12:56:06 PM PST 24
Finished Jan 24 12:56:38 PM PST 24
Peak memory 203404 kb
Host smart-de073efc-d0aa-4046-8ba7-f8c57611b79e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860858460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1860858460
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_host_override.21755222
Short name T164
Test name
Test status
Simulation time 30511382 ps
CPU time 0.65 seconds
Started Jan 24 10:00:55 PM PST 24
Finished Jan 24 10:01:01 PM PST 24
Peak memory 201504 kb
Host smart-0510dbe2-9eee-4971-9239-9ffb81c7cbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21755222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.21755222
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.347785544
Short name T1304
Test name
Test status
Simulation time 2086138934 ps
CPU time 2.76 seconds
Started Jan 24 10:03:47 PM PST 24
Finished Jan 24 10:03:58 PM PST 24
Peak memory 202620 kb
Host smart-82b6113a-a350-419c-81fe-bb898ca6cbbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347785544 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.i2c_target_hrst.347785544
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3430170966
Short name T182
Test name
Test status
Simulation time 19204901213 ps
CPU time 246.06 seconds
Started Jan 24 10:04:05 PM PST 24
Finished Jan 24 10:08:15 PM PST 24
Peak memory 1356160 kb
Host smart-6ba23f5d-d520-409d-a652-b8d2d8b7324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430170966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3430170966
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.732905586
Short name T129
Test name
Test status
Simulation time 16958669109 ps
CPU time 1378.75 seconds
Started Jan 24 10:08:15 PM PST 24
Finished Jan 24 10:31:16 PM PST 24
Peak memory 2522796 kb
Host smart-fa9bbc7b-3945-4bca-a1b2-122b5b23cc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732905586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.732905586
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3722148557
Short name T345
Test name
Test status
Simulation time 19442194 ps
CPU time 0.62 seconds
Started Jan 24 09:55:23 PM PST 24
Finished Jan 24 09:55:26 PM PST 24
Peak memory 202036 kb
Host smart-cc9308bf-cc9f-4f4e-bbc3-abc973975588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722148557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3722148557
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3040084749
Short name T391
Test name
Test status
Simulation time 47348487416 ps
CPU time 1510.84 seconds
Started Jan 24 09:55:09 PM PST 24
Finished Jan 24 10:20:27 PM PST 24
Peak memory 4260776 kb
Host smart-3b3739d6-9824-49bc-af42-6be434e1769b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040084749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3040084749
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.142792190
Short name T1591
Test name
Test status
Simulation time 97121960 ps
CPU time 1.77 seconds
Started Jan 24 01:04:55 PM PST 24
Finished Jan 24 01:05:43 PM PST 24
Peak memory 203460 kb
Host smart-3e86a829-67cc-4d93-bb62-fd9b64312e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142792190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.142792190
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2151475183
Short name T371
Test name
Test status
Simulation time 852561848 ps
CPU time 5.09 seconds
Started Jan 24 09:55:28 PM PST 24
Finished Jan 24 09:55:34 PM PST 24
Peak memory 202260 kb
Host smart-fd26d7fa-0a47-4794-9362-c2c85e0efbca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151475183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2151475183
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3295880798
Short name T160
Test name
Test status
Simulation time 585007603 ps
CPU time 2.91 seconds
Started Jan 24 10:02:27 PM PST 24
Finished Jan 24 10:02:30 PM PST 24
Peak memory 202572 kb
Host smart-fc727c01-3280-4b43-b0cd-4c918ed96f4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295880798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3295880798
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3982919100
Short name T177
Test name
Test status
Simulation time 5081108252 ps
CPU time 217.48 seconds
Started Jan 24 10:03:05 PM PST 24
Finished Jan 24 10:06:43 PM PST 24
Peak memory 860880 kb
Host smart-71ad110f-597c-46ec-a5dc-e15d9f036038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982919100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3982919100
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3538737359
Short name T192
Test name
Test status
Simulation time 10123008339 ps
CPU time 71.77 seconds
Started Jan 24 10:03:46 PM PST 24
Finished Jan 24 10:04:59 PM PST 24
Peak memory 547668 kb
Host smart-d7044179-fa1f-4a4a-a893-176b1c57fb4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538737359 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3538737359
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.982024627
Short name T191
Test name
Test status
Simulation time 10166774882 ps
CPU time 9.64 seconds
Started Jan 24 10:11:45 PM PST 24
Finished Jan 24 10:11:55 PM PST 24
Peak memory 267768 kb
Host smart-5b1c523d-f9cd-449a-8640-f904cb3d9c70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982024627 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.982024627
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.2976400557
Short name T163
Test name
Test status
Simulation time 22185405787 ps
CPU time 198.49 seconds
Started Jan 24 10:18:39 PM PST 24
Finished Jan 24 10:21:58 PM PST 24
Peak memory 413504 kb
Host smart-93cbd7c5-104e-4aaa-be41-0cb024f8dc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976400557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.2976400557
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.3403513463
Short name T175
Test name
Test status
Simulation time 1522157923 ps
CPU time 8.04 seconds
Started Jan 24 10:18:56 PM PST 24
Finished Jan 24 10:19:06 PM PST 24
Peak memory 207992 kb
Host smart-6688f919-af92-4e66-986d-91b3f7cee78c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403513463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.i2c_target_unexp_stop.3403513463
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2963531942
Short name T142
Test name
Test status
Simulation time 41979200396 ps
CPU time 2102.73 seconds
Started Jan 24 10:24:16 PM PST 24
Finished Jan 24 10:59:20 PM PST 24
Peak memory 4353556 kb
Host smart-a347dbb9-1e16-4e4b-b561-82b4ad3473aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963531942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2963531942
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.4171615370
Short name T202
Test name
Test status
Simulation time 179467980 ps
CPU time 0.99 seconds
Started Jan 24 10:25:06 PM PST 24
Finished Jan 24 10:25:08 PM PST 24
Peak memory 202336 kb
Host smart-152229d9-cf2d-4dcd-88e4-3e8d79e2cfb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171615370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.4171615370
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1669605569
Short name T86
Test name
Test status
Simulation time 327837623 ps
CPU time 1.66 seconds
Started Jan 24 12:54:43 PM PST 24
Finished Jan 24 12:54:50 PM PST 24
Peak memory 203312 kb
Host smart-397491a9-bd96-474b-a854-e885e694d809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669605569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1669605569
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2323934162
Short name T18
Test name
Test status
Simulation time 613026937 ps
CPU time 1.87 seconds
Started Jan 24 12:55:47 PM PST 24
Finished Jan 24 12:56:23 PM PST 24
Peak memory 203276 kb
Host smart-10d146c4-a85e-4bdc-b7f4-8c5cf01cbdcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323934162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2323934162
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.921937162
Short name T72
Test name
Test status
Simulation time 10173418881 ps
CPU time 29.7 seconds
Started Jan 24 10:15:16 PM PST 24
Finished Jan 24 10:15:48 PM PST 24
Peak memory 424752 kb
Host smart-3ce5321f-f9a7-4b00-a411-458dafcd5bc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921937162 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.921937162
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3737586098
Short name T46
Test name
Test status
Simulation time 2215344395 ps
CPU time 106.47 seconds
Started Jan 24 10:21:00 PM PST 24
Finished Jan 24 10:22:47 PM PST 24
Peak memory 226384 kb
Host smart-76b0a346-9286-463e-bf0b-8735c6cdd6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737586098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3737586098
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3312472894
Short name T116
Test name
Test status
Simulation time 24416400 ps
CPU time 0.94 seconds
Started Jan 24 12:54:58 PM PST 24
Finished Jan 24 12:55:08 PM PST 24
Peak memory 203056 kb
Host smart-d1d23074-5cd8-4ea5-b255-0e6613081b4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312472894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3312472894
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3819358986
Short name T1529
Test name
Test status
Simulation time 1475490739 ps
CPU time 4.33 seconds
Started Jan 24 12:54:51 PM PST 24
Finished Jan 24 12:55:02 PM PST 24
Peak memory 203316 kb
Host smart-6d7fd9b6-75ca-458c-b9ec-93ee7cbbd7fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819358986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3819358986
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.799917099
Short name T110
Test name
Test status
Simulation time 16291359 ps
CPU time 0.69 seconds
Started Jan 24 12:54:56 PM PST 24
Finished Jan 24 12:55:05 PM PST 24
Peak memory 202964 kb
Host smart-4ae4582f-2407-4489-bf7e-07caa8cc55dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799917099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.799917099
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1043471981
Short name T1567
Test name
Test status
Simulation time 29556751 ps
CPU time 1.37 seconds
Started Jan 24 12:54:46 PM PST 24
Finished Jan 24 12:54:55 PM PST 24
Peak memory 203488 kb
Host smart-1eef8041-b010-4f7d-94b3-bc0b9cb67eb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043471981 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1043471981
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3107919140
Short name T117
Test name
Test status
Simulation time 36070542 ps
CPU time 0.72 seconds
Started Jan 24 12:54:58 PM PST 24
Finished Jan 24 12:55:08 PM PST 24
Peak memory 203068 kb
Host smart-49523d09-8438-4de0-a15c-813b45cd6a07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107919140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3107919140
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3305127879
Short name T1553
Test name
Test status
Simulation time 24223353 ps
CPU time 0.66 seconds
Started Jan 24 12:54:50 PM PST 24
Finished Jan 24 12:54:58 PM PST 24
Peak memory 203044 kb
Host smart-62a0c9f3-7cef-4713-84fc-93c286959136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305127879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3305127879
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2115646538
Short name T1590
Test name
Test status
Simulation time 148505982 ps
CPU time 1 seconds
Started Jan 24 12:54:46 PM PST 24
Finished Jan 24 12:54:56 PM PST 24
Peak memory 203416 kb
Host smart-79a9ee40-17d7-43ce-8395-d184e0e26b90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115646538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2115646538
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2002245367
Short name T84
Test name
Test status
Simulation time 62027375 ps
CPU time 1.23 seconds
Started Jan 24 12:54:58 PM PST 24
Finished Jan 24 12:55:09 PM PST 24
Peak memory 203416 kb
Host smart-46c76b90-b806-4a90-8ddc-3f29abf9709c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002245367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2002245367
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3022634197
Short name T118
Test name
Test status
Simulation time 22326519 ps
CPU time 0.89 seconds
Started Jan 24 12:54:59 PM PST 24
Finished Jan 24 12:55:11 PM PST 24
Peak memory 203008 kb
Host smart-c3e9a536-e10a-4063-9914-bf7a84e44c91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022634197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3022634197
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2410230107
Short name T1530
Test name
Test status
Simulation time 282140323 ps
CPU time 3.91 seconds
Started Jan 24 12:54:44 PM PST 24
Finished Jan 24 12:54:54 PM PST 24
Peak memory 203404 kb
Host smart-0e7c242f-4eaa-4d0f-a7e2-a565e400826d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410230107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2410230107
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1371744917
Short name T122
Test name
Test status
Simulation time 18282622 ps
CPU time 0.66 seconds
Started Jan 24 12:54:47 PM PST 24
Finished Jan 24 12:54:56 PM PST 24
Peak memory 203060 kb
Host smart-952abbb2-4927-492f-adbe-7401588ef660
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371744917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1371744917
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3181021382
Short name T1560
Test name
Test status
Simulation time 92549473 ps
CPU time 0.85 seconds
Started Jan 24 12:55:09 PM PST 24
Finished Jan 24 12:55:36 PM PST 24
Peak memory 203160 kb
Host smart-df8bf067-f6f7-412a-8ecd-8eb2c9b8950c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181021382 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3181021382
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2635541058
Short name T1539
Test name
Test status
Simulation time 27374397 ps
CPU time 0.72 seconds
Started Jan 24 12:54:47 PM PST 24
Finished Jan 24 12:54:56 PM PST 24
Peak memory 203060 kb
Host smart-fbc404d6-f834-452c-8524-882fcbaebd4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635541058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2635541058
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1042592323
Short name T1594
Test name
Test status
Simulation time 15638556 ps
CPU time 0.64 seconds
Started Jan 24 12:54:44 PM PST 24
Finished Jan 24 12:54:51 PM PST 24
Peak memory 203112 kb
Host smart-c8a8b697-96f5-4c07-838f-1a41786f5a41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042592323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1042592323
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2013205286
Short name T25
Test name
Test status
Simulation time 30431122 ps
CPU time 0.76 seconds
Started Jan 24 12:55:00 PM PST 24
Finished Jan 24 12:55:14 PM PST 24
Peak memory 203044 kb
Host smart-be14fa23-54f4-457d-a2e8-7a52c786fa45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013205286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2013205286
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3817427562
Short name T1526
Test name
Test status
Simulation time 221677504 ps
CPU time 2.42 seconds
Started Jan 24 12:54:50 PM PST 24
Finished Jan 24 12:55:00 PM PST 24
Peak memory 203464 kb
Host smart-f74d8060-29e4-40b5-899f-67744b25bc53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817427562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3817427562
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3909571426
Short name T23
Test name
Test status
Simulation time 87796984 ps
CPU time 0.86 seconds
Started Jan 24 12:59:09 PM PST 24
Finished Jan 24 12:59:36 PM PST 24
Peak memory 203216 kb
Host smart-35081651-3bc9-42ce-9fe9-3c2d38554eaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909571426 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3909571426
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1881867449
Short name T123
Test name
Test status
Simulation time 27770836 ps
CPU time 0.69 seconds
Started Jan 24 12:55:40 PM PST 24
Finished Jan 24 12:56:11 PM PST 24
Peak memory 202964 kb
Host smart-92eff8ca-a534-46f9-9330-87a2626d48ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881867449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1881867449
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2927742630
Short name T1585
Test name
Test status
Simulation time 31917727 ps
CPU time 0.64 seconds
Started Jan 24 12:55:42 PM PST 24
Finished Jan 24 12:56:14 PM PST 24
Peak memory 202908 kb
Host smart-4b76e00a-5348-47f5-ba39-850cdf680d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927742630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2927742630
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.873438251
Short name T1538
Test name
Test status
Simulation time 35579252 ps
CPU time 0.94 seconds
Started Jan 24 12:55:46 PM PST 24
Finished Jan 24 12:56:20 PM PST 24
Peak memory 203336 kb
Host smart-9576f74e-94d1-40a5-84e7-501f81aab22e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873438251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.873438251
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1252730499
Short name T1547
Test name
Test status
Simulation time 206711146 ps
CPU time 2.29 seconds
Started Jan 24 12:55:45 PM PST 24
Finished Jan 24 12:56:20 PM PST 24
Peak memory 203336 kb
Host smart-c59ccbdd-aa6d-4543-8b81-69a1bb289fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252730499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1252730499
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.872097798
Short name T131
Test name
Test status
Simulation time 87005696 ps
CPU time 0.82 seconds
Started Jan 24 12:55:39 PM PST 24
Finished Jan 24 12:56:11 PM PST 24
Peak memory 203228 kb
Host smart-f608c607-a7ef-48bd-8221-119bc3c3e9dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872097798 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.872097798
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3835024673
Short name T1579
Test name
Test status
Simulation time 27148997 ps
CPU time 0.72 seconds
Started Jan 24 12:55:44 PM PST 24
Finished Jan 24 12:56:19 PM PST 24
Peak memory 202844 kb
Host smart-92993b4c-18b7-4012-b393-031de432954a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835024673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3835024673
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1652130724
Short name T1544
Test name
Test status
Simulation time 38862892 ps
CPU time 0.64 seconds
Started Jan 24 01:26:00 PM PST 24
Finished Jan 24 01:26:52 PM PST 24
Peak memory 203120 kb
Host smart-7aa093b8-1075-42bd-a221-d585388f0f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652130724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1652130724
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2286286931
Short name T1596
Test name
Test status
Simulation time 146790127 ps
CPU time 0.98 seconds
Started Jan 24 01:32:11 PM PST 24
Finished Jan 24 01:32:56 PM PST 24
Peak memory 203464 kb
Host smart-e4282e04-7f86-4ea2-b795-658b200734a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286286931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2286286931
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.991513200
Short name T1595
Test name
Test status
Simulation time 34758595 ps
CPU time 1.52 seconds
Started Jan 24 12:55:45 PM PST 24
Finished Jan 24 12:56:21 PM PST 24
Peak memory 203472 kb
Host smart-3054856e-d259-4ee9-942e-162718b56204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991513200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.991513200
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.136272772
Short name T173
Test name
Test status
Simulation time 506553012 ps
CPU time 1.68 seconds
Started Jan 24 12:55:44 PM PST 24
Finished Jan 24 12:56:20 PM PST 24
Peak memory 203276 kb
Host smart-d1789aaf-e310-46f7-8878-f0da20f47daa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136272772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.136272772
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.616194396
Short name T1617
Test name
Test status
Simulation time 66997754 ps
CPU time 1.07 seconds
Started Jan 24 12:55:49 PM PST 24
Finished Jan 24 12:56:26 PM PST 24
Peak memory 202540 kb
Host smart-1e474c6c-7fe7-4bdb-828c-2d594235940d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616194396 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.616194396
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.302451817
Short name T1565
Test name
Test status
Simulation time 47982579 ps
CPU time 0.63 seconds
Started Jan 24 01:09:13 PM PST 24
Finished Jan 24 01:09:52 PM PST 24
Peak memory 203092 kb
Host smart-789223a3-c587-4b51-821f-abb8d6e6473f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302451817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.302451817
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1235223044
Short name T93
Test name
Test status
Simulation time 48777383 ps
CPU time 0.69 seconds
Started Jan 24 12:59:03 PM PST 24
Finished Jan 24 12:59:28 PM PST 24
Peak memory 203124 kb
Host smart-05e08674-3737-4cf3-b3b6-038b79d90313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235223044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1235223044
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2499605985
Short name T1582
Test name
Test status
Simulation time 44608476 ps
CPU time 1.03 seconds
Started Jan 24 01:02:32 PM PST 24
Finished Jan 24 01:02:39 PM PST 24
Peak memory 203400 kb
Host smart-d4d4da4d-83a7-4d48-abeb-406420eef27a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499605985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2499605985
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3648981434
Short name T1541
Test name
Test status
Simulation time 46644187 ps
CPU time 2.11 seconds
Started Jan 24 12:55:35 PM PST 24
Finished Jan 24 12:56:06 PM PST 24
Peak memory 203392 kb
Host smart-367debab-f3b3-4570-9d4c-6813812d400e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648981434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3648981434
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1593200193
Short name T1515
Test name
Test status
Simulation time 413653307 ps
CPU time 1.29 seconds
Started Jan 24 12:59:02 PM PST 24
Finished Jan 24 12:59:28 PM PST 24
Peak memory 203424 kb
Host smart-40a69dfe-915e-4994-9e48-3849227aaffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593200193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1593200193
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.412298579
Short name T1588
Test name
Test status
Simulation time 39537275 ps
CPU time 0.75 seconds
Started Jan 24 01:00:11 PM PST 24
Finished Jan 24 01:00:32 PM PST 24
Peak memory 203172 kb
Host smart-0b693715-e15e-4011-94f5-ffe94394fc69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412298579 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.412298579
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3669853090
Short name T1574
Test name
Test status
Simulation time 22113645 ps
CPU time 0.67 seconds
Started Jan 24 12:55:56 PM PST 24
Finished Jan 24 12:56:32 PM PST 24
Peak memory 203056 kb
Host smart-e8839ed3-e7ef-4220-b96f-8015c47a77af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669853090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3669853090
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2485596399
Short name T1604
Test name
Test status
Simulation time 18709978 ps
CPU time 0.66 seconds
Started Jan 24 01:06:21 PM PST 24
Finished Jan 24 01:07:18 PM PST 24
Peak memory 203168 kb
Host smart-6f528402-730e-430f-9994-ad446bbad9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485596399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2485596399
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1872516910
Short name T1597
Test name
Test status
Simulation time 142033685 ps
CPU time 1.34 seconds
Started Jan 24 01:31:31 PM PST 24
Finished Jan 24 01:32:22 PM PST 24
Peak memory 203528 kb
Host smart-d0813534-07a1-4163-9855-30272dea1aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872516910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1872516910
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.482015195
Short name T1572
Test name
Test status
Simulation time 1109847319 ps
CPU time 1.21 seconds
Started Jan 24 01:22:48 PM PST 24
Finished Jan 24 01:23:45 PM PST 24
Peak memory 203424 kb
Host smart-8b173c6d-46e5-4056-89a4-3973405a741e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482015195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.482015195
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1327175680
Short name T132
Test name
Test status
Simulation time 67429634 ps
CPU time 0.72 seconds
Started Jan 24 12:55:56 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203152 kb
Host smart-3ad43f02-ab44-4b44-8d37-9aa09d94417f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327175680 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1327175680
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1190621213
Short name T1592
Test name
Test status
Simulation time 17741003 ps
CPU time 0.66 seconds
Started Jan 24 01:23:25 PM PST 24
Finished Jan 24 01:24:13 PM PST 24
Peak memory 203156 kb
Host smart-03deefe2-0062-44d9-a2ee-800e15809feb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190621213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1190621213
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1180634084
Short name T1519
Test name
Test status
Simulation time 50252047 ps
CPU time 0.64 seconds
Started Jan 24 01:33:56 PM PST 24
Finished Jan 24 01:34:34 PM PST 24
Peak memory 203156 kb
Host smart-5a97559b-e406-4a64-b23f-1379bfc4b6b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180634084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1180634084
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1142528607
Short name T80
Test name
Test status
Simulation time 80343422 ps
CPU time 1.7 seconds
Started Jan 24 12:55:47 PM PST 24
Finished Jan 24 12:56:23 PM PST 24
Peak memory 203280 kb
Host smart-60c36921-21b0-420d-acd6-00c3400a4f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142528607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1142528607
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.801238296
Short name T1520
Test name
Test status
Simulation time 86534772 ps
CPU time 0.87 seconds
Started Jan 24 12:55:49 PM PST 24
Finished Jan 24 12:56:25 PM PST 24
Peak memory 203224 kb
Host smart-073b30b8-220b-443c-9104-4d9bf738a93b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801238296 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.801238296
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1464403643
Short name T124
Test name
Test status
Simulation time 19290674 ps
CPU time 0.71 seconds
Started Jan 24 02:09:32 PM PST 24
Finished Jan 24 02:09:37 PM PST 24
Peak memory 203204 kb
Host smart-5a81a350-0bf3-4384-9083-86ee5b50b514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464403643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1464403643
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.738014524
Short name T1599
Test name
Test status
Simulation time 18554617 ps
CPU time 0.67 seconds
Started Jan 24 01:08:16 PM PST 24
Finished Jan 24 01:08:55 PM PST 24
Peak memory 203172 kb
Host smart-dd69d562-0c2d-454a-b786-9c31affd3f0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738014524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.738014524
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2131465572
Short name T127
Test name
Test status
Simulation time 108883412 ps
CPU time 0.79 seconds
Started Jan 24 12:55:50 PM PST 24
Finished Jan 24 12:56:27 PM PST 24
Peak memory 203064 kb
Host smart-527f9288-62a4-4ca0-9934-ce9f0e2dd48d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131465572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2131465572
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.126192380
Short name T1518
Test name
Test status
Simulation time 48648927 ps
CPU time 1.13 seconds
Started Jan 24 12:55:49 PM PST 24
Finished Jan 24 12:56:26 PM PST 24
Peak memory 202260 kb
Host smart-f2b49bc5-9b3a-4309-92a4-69f8f5d80a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126192380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.126192380
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2545859200
Short name T1616
Test name
Test status
Simulation time 393982996 ps
CPU time 1.23 seconds
Started Jan 24 12:55:55 PM PST 24
Finished Jan 24 12:56:32 PM PST 24
Peak memory 203372 kb
Host smart-1653034b-1f03-406a-bb80-e4a1449f6537
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545859200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2545859200
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1927877627
Short name T1573
Test name
Test status
Simulation time 23159543 ps
CPU time 0.81 seconds
Started Jan 24 12:56:00 PM PST 24
Finished Jan 24 12:56:34 PM PST 24
Peak memory 203140 kb
Host smart-4a4584c0-a367-4371-8af0-2f57c777a389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927877627 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1927877627
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.334780362
Short name T1612
Test name
Test status
Simulation time 36274595 ps
CPU time 0.71 seconds
Started Jan 24 12:55:59 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203204 kb
Host smart-b6b60a84-0c96-4f3b-8354-478dacb10c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334780362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.334780362
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1804304806
Short name T1600
Test name
Test status
Simulation time 52003979 ps
CPU time 0.7 seconds
Started Jan 24 12:55:49 PM PST 24
Finished Jan 24 12:56:24 PM PST 24
Peak memory 203100 kb
Host smart-c287fb0f-0125-4092-a097-ceed78088c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804304806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1804304806
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.879577618
Short name T111
Test name
Test status
Simulation time 171748643 ps
CPU time 0.79 seconds
Started Jan 24 12:55:58 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203080 kb
Host smart-ccd92a2a-c974-4f50-84b7-536c4e028efc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879577618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.879577618
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2043760040
Short name T1615
Test name
Test status
Simulation time 460631403 ps
CPU time 2.75 seconds
Started Jan 24 12:55:50 PM PST 24
Finished Jan 24 12:56:29 PM PST 24
Peak memory 203336 kb
Host smart-57a8e752-129b-4916-8b99-98e680cd208c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043760040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2043760040
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2528676657
Short name T90
Test name
Test status
Simulation time 383997259 ps
CPU time 1.84 seconds
Started Jan 24 12:55:47 PM PST 24
Finished Jan 24 12:56:22 PM PST 24
Peak memory 203320 kb
Host smart-5558861e-f4f5-4b19-b8fb-ba72f7491426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528676657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2528676657
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1650806971
Short name T1562
Test name
Test status
Simulation time 36115488 ps
CPU time 0.9 seconds
Started Jan 24 12:55:59 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203284 kb
Host smart-cd0b44f5-2715-4610-9def-bef64b9f3083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650806971 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1650806971
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1651883443
Short name T114
Test name
Test status
Simulation time 44974763 ps
CPU time 0.65 seconds
Started Jan 24 12:55:58 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 202544 kb
Host smart-6f32ddd1-cac9-4822-8b5a-96486686bb89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651883443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1651883443
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2552169367
Short name T1598
Test name
Test status
Simulation time 24852754 ps
CPU time 0.63 seconds
Started Jan 24 12:56:09 PM PST 24
Finished Jan 24 12:56:40 PM PST 24
Peak memory 203120 kb
Host smart-d6d5c0b4-e41d-4627-8902-ec69103a17c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552169367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2552169367
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2477768437
Short name T125
Test name
Test status
Simulation time 75705882 ps
CPU time 0.92 seconds
Started Jan 24 12:55:58 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203152 kb
Host smart-b1c8be12-10b3-4ddf-815b-b7e21f98a75f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477768437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2477768437
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2227109786
Short name T1620
Test name
Test status
Simulation time 135610425 ps
CPU time 1.95 seconds
Started Jan 24 12:55:56 PM PST 24
Finished Jan 24 12:56:34 PM PST 24
Peak memory 203384 kb
Host smart-bd9e7039-a07a-4a69-9d0c-ba7f8e9ada20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227109786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2227109786
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3728122395
Short name T1575
Test name
Test status
Simulation time 22041906 ps
CPU time 0.95 seconds
Started Jan 24 12:55:57 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203232 kb
Host smart-4b69b98b-c491-4f38-9b8c-ce4ac1924f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728122395 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3728122395
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2356862817
Short name T1542
Test name
Test status
Simulation time 41611973 ps
CPU time 0.72 seconds
Started Jan 24 12:55:56 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203148 kb
Host smart-6e187f36-b823-4741-98d8-dadf6722e805
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356862817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2356862817
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2486620224
Short name T1623
Test name
Test status
Simulation time 28164152 ps
CPU time 0.63 seconds
Started Jan 24 12:56:09 PM PST 24
Finished Jan 24 12:56:39 PM PST 24
Peak memory 203120 kb
Host smart-e5700593-1793-410f-876d-2e6edb60f690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486620224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2486620224
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2835419105
Short name T1527
Test name
Test status
Simulation time 42113665 ps
CPU time 0.86 seconds
Started Jan 24 12:55:59 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203180 kb
Host smart-264f4a06-314f-4812-ac97-6b4f126baf0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835419105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2835419105
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.608239799
Short name T1561
Test name
Test status
Simulation time 222103289 ps
CPU time 2.26 seconds
Started Jan 24 12:55:58 PM PST 24
Finished Jan 24 12:56:35 PM PST 24
Peak memory 203468 kb
Host smart-7653d1de-e5d7-43f3-b6b0-41782a53a743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608239799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.608239799
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3259879709
Short name T88
Test name
Test status
Simulation time 420349925 ps
CPU time 1.81 seconds
Started Jan 24 12:56:09 PM PST 24
Finished Jan 24 12:56:41 PM PST 24
Peak memory 203460 kb
Host smart-c2dd642d-87ae-4c9e-9b80-64feeef81d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259879709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3259879709
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1612050544
Short name T26
Test name
Test status
Simulation time 20329211 ps
CPU time 0.66 seconds
Started Jan 24 12:55:58 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203076 kb
Host smart-5aba85fe-20b7-416f-82ee-3913f6fc1e83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612050544 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1612050544
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1307768469
Short name T1540
Test name
Test status
Simulation time 38324665 ps
CPU time 0.69 seconds
Started Jan 24 12:55:58 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203096 kb
Host smart-87f58c21-dfb1-4f15-9770-64ff100e7738
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307768469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1307768469
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2175659704
Short name T1532
Test name
Test status
Simulation time 37062527 ps
CPU time 0.65 seconds
Started Jan 24 12:56:00 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203128 kb
Host smart-d156156d-19a4-45ae-8639-c4ea3aa66608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175659704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2175659704
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3178864979
Short name T1583
Test name
Test status
Simulation time 28109435 ps
CPU time 0.79 seconds
Started Jan 24 12:55:58 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 203112 kb
Host smart-db6f29d2-aaba-4864-93e6-7820ca3fdb0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178864979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3178864979
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3094678427
Short name T1613
Test name
Test status
Simulation time 169354440 ps
CPU time 1.16 seconds
Started Jan 24 12:56:09 PM PST 24
Finished Jan 24 12:56:40 PM PST 24
Peak memory 203408 kb
Host smart-2f9f417f-811d-43bf-a016-5e2eabf88832
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094678427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3094678427
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2857190187
Short name T1533
Test name
Test status
Simulation time 88384612 ps
CPU time 1.11 seconds
Started Jan 24 12:56:08 PM PST 24
Finished Jan 24 12:56:38 PM PST 24
Peak memory 203432 kb
Host smart-7beb1403-9f78-4548-bf41-dc607a1d06d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857190187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2857190187
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.68291424
Short name T1625
Test name
Test status
Simulation time 62178219 ps
CPU time 1.3 seconds
Started Jan 24 12:54:58 PM PST 24
Finished Jan 24 12:55:09 PM PST 24
Peak memory 203364 kb
Host smart-9220b032-d255-492f-8329-d86369db5121
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68291424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.68291424
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2354408331
Short name T1602
Test name
Test status
Simulation time 379610177 ps
CPU time 3.56 seconds
Started Jan 24 12:55:00 PM PST 24
Finished Jan 24 12:55:16 PM PST 24
Peak memory 203104 kb
Host smart-20fd74ec-bce4-4891-90d1-8733f5406d4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354408331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2354408331
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.384508141
Short name T1608
Test name
Test status
Simulation time 51025737 ps
CPU time 0.64 seconds
Started Jan 24 12:54:58 PM PST 24
Finished Jan 24 12:55:08 PM PST 24
Peak memory 202348 kb
Host smart-bfd1bd88-6040-4c87-967d-e151986a519c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384508141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.384508141
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1282220428
Short name T1603
Test name
Test status
Simulation time 72879076 ps
CPU time 0.82 seconds
Started Jan 24 12:54:55 PM PST 24
Finished Jan 24 12:55:02 PM PST 24
Peak memory 203152 kb
Host smart-3402415a-b476-40ee-a910-b20e2b845610
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282220428 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1282220428
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3860905859
Short name T1609
Test name
Test status
Simulation time 20439051 ps
CPU time 0.65 seconds
Started Jan 24 12:54:56 PM PST 24
Finished Jan 24 12:55:03 PM PST 24
Peak memory 203196 kb
Host smart-2a18b2c5-ab56-4e34-b40b-49932d562f09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860905859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3860905859
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.406402746
Short name T1580
Test name
Test status
Simulation time 17972444 ps
CPU time 0.68 seconds
Started Jan 24 12:55:00 PM PST 24
Finished Jan 24 12:55:14 PM PST 24
Peak memory 202984 kb
Host smart-91771158-6ecb-4bed-9269-15d1163654e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406402746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.406402746
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.836101073
Short name T1587
Test name
Test status
Simulation time 31993826 ps
CPU time 0.83 seconds
Started Jan 24 12:55:10 PM PST 24
Finished Jan 24 12:55:38 PM PST 24
Peak memory 203068 kb
Host smart-01f0fe44-af7c-4172-83bd-84a22708c99e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836101073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_out
standing.836101073
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3604388807
Short name T76
Test name
Test status
Simulation time 267150606 ps
CPU time 1.74 seconds
Started Jan 24 12:55:10 PM PST 24
Finished Jan 24 12:55:39 PM PST 24
Peak memory 203312 kb
Host smart-5959d951-5d53-458f-9673-1ca9d2134e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604388807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3604388807
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2002401802
Short name T1605
Test name
Test status
Simulation time 49037516 ps
CPU time 1.25 seconds
Started Jan 24 12:54:59 PM PST 24
Finished Jan 24 12:55:11 PM PST 24
Peak memory 203260 kb
Host smart-794bb669-a315-4496-ae77-da79e3e4dce0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002401802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2002401802
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.812306088
Short name T1581
Test name
Test status
Simulation time 32079030 ps
CPU time 0.65 seconds
Started Jan 24 12:56:18 PM PST 24
Finished Jan 24 12:56:48 PM PST 24
Peak memory 203060 kb
Host smart-108fab76-94c9-4c9a-aa05-83045cae64a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812306088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.812306088
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2189181660
Short name T1563
Test name
Test status
Simulation time 59454482 ps
CPU time 0.65 seconds
Started Jan 24 12:56:14 PM PST 24
Finished Jan 24 12:56:45 PM PST 24
Peak memory 203012 kb
Host smart-fcbf5c81-fbf2-49ac-adb2-d6e04910cda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189181660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2189181660
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.811540400
Short name T1523
Test name
Test status
Simulation time 18021562 ps
CPU time 0.63 seconds
Started Jan 24 12:56:12 PM PST 24
Finished Jan 24 12:56:42 PM PST 24
Peak memory 203076 kb
Host smart-f711f1dc-d8f7-45c4-ad50-381a1f29b918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811540400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.811540400
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.98314599
Short name T68
Test name
Test status
Simulation time 17818294 ps
CPU time 0.69 seconds
Started Jan 24 12:56:15 PM PST 24
Finished Jan 24 12:56:45 PM PST 24
Peak memory 203036 kb
Host smart-140a3c5a-b878-4a55-be80-b1a09fd85c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98314599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.98314599
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3760621772
Short name T1551
Test name
Test status
Simulation time 19361734 ps
CPU time 0.68 seconds
Started Jan 24 12:56:13 PM PST 24
Finished Jan 24 12:56:43 PM PST 24
Peak memory 203076 kb
Host smart-16e82c30-8c9e-473e-806b-d4f45191d44c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760621772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3760621772
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.76381225
Short name T1557
Test name
Test status
Simulation time 20022408 ps
CPU time 0.62 seconds
Started Jan 24 12:56:14 PM PST 24
Finished Jan 24 12:56:45 PM PST 24
Peak memory 201048 kb
Host smart-05824ab0-d3d8-4847-8b2d-bb8f6657e177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76381225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.76381225
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3957365726
Short name T1606
Test name
Test status
Simulation time 18094671 ps
CPU time 0.64 seconds
Started Jan 24 01:04:29 PM PST 24
Finished Jan 24 01:05:10 PM PST 24
Peak memory 203084 kb
Host smart-622fab15-79b7-46a6-898c-e540c3802489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957365726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3957365726
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1082785425
Short name T1621
Test name
Test status
Simulation time 64310554 ps
CPU time 0.68 seconds
Started Jan 24 12:56:11 PM PST 24
Finished Jan 24 12:56:42 PM PST 24
Peak memory 202912 kb
Host smart-712eb026-388b-48bf-b693-786dde26bc87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082785425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1082785425
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3409949061
Short name T1537
Test name
Test status
Simulation time 17021010 ps
CPU time 0.68 seconds
Started Jan 24 12:56:11 PM PST 24
Finished Jan 24 12:56:42 PM PST 24
Peak memory 203120 kb
Host smart-774a9182-603a-4692-aef9-0a8c98a2db36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409949061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3409949061
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4293832853
Short name T113
Test name
Test status
Simulation time 157124813 ps
CPU time 0.95 seconds
Started Jan 24 12:55:02 PM PST 24
Finished Jan 24 12:55:16 PM PST 24
Peak memory 203080 kb
Host smart-fc2b2fbc-306f-40d8-a647-b558da9bcda4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293832853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.4293832853
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.4122651268
Short name T20
Test name
Test status
Simulation time 2549784625 ps
CPU time 4.43 seconds
Started Jan 24 12:54:59 PM PST 24
Finished Jan 24 12:55:14 PM PST 24
Peak memory 203292 kb
Host smart-a9944536-96be-4223-83a0-1fd86d7166d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122651268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.4122651268
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1451974499
Short name T109
Test name
Test status
Simulation time 20933840 ps
CPU time 0.71 seconds
Started Jan 24 12:55:01 PM PST 24
Finished Jan 24 12:55:15 PM PST 24
Peak memory 203156 kb
Host smart-90e2ca08-02cc-43f7-83a7-748658276c86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451974499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1451974499
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.74484919
Short name T1556
Test name
Test status
Simulation time 31364637 ps
CPU time 0.87 seconds
Started Jan 24 12:55:02 PM PST 24
Finished Jan 24 12:55:17 PM PST 24
Peak memory 203128 kb
Host smart-0a66397a-9318-4876-8de0-ca25c7cc5ead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74484919 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.74484919
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.293102000
Short name T1568
Test name
Test status
Simulation time 40774270 ps
CPU time 0.67 seconds
Started Jan 24 12:55:00 PM PST 24
Finished Jan 24 12:55:14 PM PST 24
Peak memory 202360 kb
Host smart-8fa85251-f48a-4487-a7ea-7fa9e4a93a8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293102000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.293102000
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1804750959
Short name T1569
Test name
Test status
Simulation time 101543163 ps
CPU time 0.77 seconds
Started Jan 24 12:55:05 PM PST 24
Finished Jan 24 12:55:19 PM PST 24
Peak memory 203092 kb
Host smart-9f5413e2-c203-4e41-9076-5c3ff01e7871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804750959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1804750959
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1266426554
Short name T1570
Test name
Test status
Simulation time 48013216 ps
CPU time 2.19 seconds
Started Jan 24 12:54:59 PM PST 24
Finished Jan 24 12:55:13 PM PST 24
Peak memory 203464 kb
Host smart-930234b0-a3d8-4976-bb03-2ccd8c9f9f70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266426554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1266426554
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2787292395
Short name T22
Test name
Test status
Simulation time 116383053 ps
CPU time 1.31 seconds
Started Jan 24 12:55:00 PM PST 24
Finished Jan 24 12:55:14 PM PST 24
Peak memory 203248 kb
Host smart-210781e1-ac84-4f21-b4ef-52a263a1f382
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787292395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2787292395
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1752497799
Short name T1589
Test name
Test status
Simulation time 27276726 ps
CPU time 0.66 seconds
Started Jan 24 12:56:08 PM PST 24
Finished Jan 24 12:56:39 PM PST 24
Peak memory 203044 kb
Host smart-029d5a45-ec8b-46a5-8ac0-7054a504a0fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752497799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1752497799
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.1587661441
Short name T1528
Test name
Test status
Simulation time 70576528 ps
CPU time 0.69 seconds
Started Jan 24 12:56:22 PM PST 24
Finished Jan 24 12:56:53 PM PST 24
Peak memory 202964 kb
Host smart-cba11a81-60d4-4d40-b72b-b3ec1618b714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587661441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1587661441
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.4178077633
Short name T112
Test name
Test status
Simulation time 26278768 ps
CPU time 0.68 seconds
Started Jan 24 12:56:11 PM PST 24
Finished Jan 24 12:56:42 PM PST 24
Peak memory 202912 kb
Host smart-09c100e8-03fa-4539-8364-3ae843dba7a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178077633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.4178077633
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.837465267
Short name T1546
Test name
Test status
Simulation time 18485951 ps
CPU time 0.66 seconds
Started Jan 24 12:56:18 PM PST 24
Finished Jan 24 12:56:48 PM PST 24
Peak memory 203056 kb
Host smart-26ec350e-e868-41af-be21-89690aa9355d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837465267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.837465267
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1582796170
Short name T1586
Test name
Test status
Simulation time 64800791 ps
CPU time 0.65 seconds
Started Jan 24 12:56:12 PM PST 24
Finished Jan 24 12:56:42 PM PST 24
Peak memory 203100 kb
Host smart-5eb4146d-54fc-4251-8ddc-491e360a6885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582796170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1582796170
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.2913766103
Short name T1611
Test name
Test status
Simulation time 18702453 ps
CPU time 0.64 seconds
Started Jan 24 12:56:12 PM PST 24
Finished Jan 24 12:56:43 PM PST 24
Peak memory 203084 kb
Host smart-0b9c5402-a63e-4b1a-bef1-dbb5b63e92af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913766103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2913766103
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2610493229
Short name T24
Test name
Test status
Simulation time 18638380 ps
CPU time 0.65 seconds
Started Jan 24 12:56:08 PM PST 24
Finished Jan 24 12:56:38 PM PST 24
Peak memory 203052 kb
Host smart-65aa334f-f87b-4a16-9cf4-7d6ba3b7b754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610493229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2610493229
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3750018525
Short name T1516
Test name
Test status
Simulation time 88763169 ps
CPU time 0.66 seconds
Started Jan 24 12:56:22 PM PST 24
Finished Jan 24 12:56:53 PM PST 24
Peak memory 202968 kb
Host smart-ca0c17b0-c240-4bb2-b244-23bd192ab8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750018525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3750018525
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3121005362
Short name T1558
Test name
Test status
Simulation time 56087554 ps
CPU time 0.64 seconds
Started Jan 24 12:56:21 PM PST 24
Finished Jan 24 12:56:53 PM PST 24
Peak memory 202672 kb
Host smart-59ae48a6-df22-43cd-8079-558495d1d760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121005362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3121005362
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3062528091
Short name T1601
Test name
Test status
Simulation time 25620074 ps
CPU time 0.65 seconds
Started Jan 24 12:56:17 PM PST 24
Finished Jan 24 12:56:47 PM PST 24
Peak memory 203024 kb
Host smart-0b2f39cf-8fa3-45ba-8889-206cf2899726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062528091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3062528091
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1157294046
Short name T115
Test name
Test status
Simulation time 121154817 ps
CPU time 0.97 seconds
Started Jan 24 12:55:08 PM PST 24
Finished Jan 24 12:55:37 PM PST 24
Peak memory 203116 kb
Host smart-881c904e-da04-4521-943d-a3146e591ade
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157294046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1157294046
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1670366256
Short name T121
Test name
Test status
Simulation time 92418062 ps
CPU time 3.69 seconds
Started Jan 24 12:55:20 PM PST 24
Finished Jan 24 12:55:54 PM PST 24
Peak memory 203396 kb
Host smart-13763cf0-43e4-4953-9469-b5936fee07dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670366256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1670366256
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.555060411
Short name T1543
Test name
Test status
Simulation time 23949884 ps
CPU time 0.73 seconds
Started Jan 24 12:55:20 PM PST 24
Finished Jan 24 12:55:51 PM PST 24
Peak memory 202540 kb
Host smart-bab063b4-b375-4555-93db-abaa4e53d182
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555060411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.555060411
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.258945116
Short name T1614
Test name
Test status
Simulation time 24412881 ps
CPU time 0.86 seconds
Started Jan 24 12:55:20 PM PST 24
Finished Jan 24 12:55:51 PM PST 24
Peak memory 202892 kb
Host smart-35f5c422-497f-4825-af7b-5195cfa42fe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258945116 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.258945116
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2466728690
Short name T1564
Test name
Test status
Simulation time 41837223 ps
CPU time 0.75 seconds
Started Jan 24 12:55:20 PM PST 24
Finished Jan 24 12:55:51 PM PST 24
Peak memory 203208 kb
Host smart-710d97d9-79a6-4b01-afd0-94956b428734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466728690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2466728690
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3168976771
Short name T1531
Test name
Test status
Simulation time 129750523 ps
CPU time 0.7 seconds
Started Jan 24 01:58:19 PM PST 24
Finished Jan 24 01:58:34 PM PST 24
Peak memory 203184 kb
Host smart-b7d0db8c-f405-456d-a906-0d48616859a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168976771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3168976771
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.212605283
Short name T128
Test name
Test status
Simulation time 49884494 ps
CPU time 0.93 seconds
Started Jan 24 12:55:02 PM PST 24
Finished Jan 24 12:55:17 PM PST 24
Peak memory 202744 kb
Host smart-3c49ce25-e4c1-46db-beeb-0c56b070ab16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212605283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.212605283
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3311625793
Short name T1534
Test name
Test status
Simulation time 32188174 ps
CPU time 1.42 seconds
Started Jan 24 12:55:08 PM PST 24
Finished Jan 24 12:55:36 PM PST 24
Peak memory 203440 kb
Host smart-faecaa2e-b8cf-482e-958c-afe438e86447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311625793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3311625793
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1537024760
Short name T108
Test name
Test status
Simulation time 240399358 ps
CPU time 1.26 seconds
Started Jan 24 12:55:03 PM PST 24
Finished Jan 24 12:55:18 PM PST 24
Peak memory 203288 kb
Host smart-730fe487-0358-490b-a60f-89b8d83f66d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537024760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1537024760
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2727782251
Short name T1593
Test name
Test status
Simulation time 81260935 ps
CPU time 0.69 seconds
Started Jan 24 12:56:21 PM PST 24
Finished Jan 24 12:56:53 PM PST 24
Peak memory 202640 kb
Host smart-02a912e6-7239-4680-b546-c47e6a6871ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727782251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2727782251
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3585875753
Short name T1555
Test name
Test status
Simulation time 32814792 ps
CPU time 0.68 seconds
Started Jan 24 02:24:03 PM PST 24
Finished Jan 24 02:24:16 PM PST 24
Peak memory 203160 kb
Host smart-7cd97b2d-778b-4d25-84a8-0c2562d5cfb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585875753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3585875753
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.751875825
Short name T1549
Test name
Test status
Simulation time 29808546 ps
CPU time 0.7 seconds
Started Jan 24 12:56:19 PM PST 24
Finished Jan 24 12:56:50 PM PST 24
Peak memory 203036 kb
Host smart-a285d231-c9dd-4507-9fe8-003b9d110768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751875825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.751875825
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2665290202
Short name T1554
Test name
Test status
Simulation time 17940921 ps
CPU time 0.7 seconds
Started Jan 24 12:56:18 PM PST 24
Finished Jan 24 12:56:48 PM PST 24
Peak memory 203060 kb
Host smart-9adec50f-c77e-4898-9d28-23deedb73974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665290202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2665290202
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3254290195
Short name T1545
Test name
Test status
Simulation time 14873792 ps
CPU time 0.64 seconds
Started Jan 24 12:56:21 PM PST 24
Finished Jan 24 12:56:52 PM PST 24
Peak memory 203140 kb
Host smart-3a97933c-e10d-4f78-98d6-f30faa14e70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254290195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3254290195
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2375017668
Short name T1607
Test name
Test status
Simulation time 43562626 ps
CPU time 0.73 seconds
Started Jan 24 01:12:37 PM PST 24
Finished Jan 24 01:13:30 PM PST 24
Peak memory 203204 kb
Host smart-85128798-507d-40c9-9d89-14948af96dcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375017668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2375017668
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.600871165
Short name T1571
Test name
Test status
Simulation time 38683269 ps
CPU time 0.66 seconds
Started Jan 24 01:19:52 PM PST 24
Finished Jan 24 01:20:54 PM PST 24
Peak memory 203144 kb
Host smart-07b9bed2-2ed7-44a8-8e6c-51fae829fa3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600871165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.600871165
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.561204017
Short name T1622
Test name
Test status
Simulation time 18365744 ps
CPU time 0.64 seconds
Started Jan 24 12:56:26 PM PST 24
Finished Jan 24 12:56:58 PM PST 24
Peak memory 203108 kb
Host smart-1131a1d8-ae2d-4e21-b17e-4916846181c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561204017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.561204017
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2532187975
Short name T69
Test name
Test status
Simulation time 119093051 ps
CPU time 0.67 seconds
Started Jan 24 12:56:30 PM PST 24
Finished Jan 24 12:57:01 PM PST 24
Peak memory 203120 kb
Host smart-9c3758d0-84de-4db9-baa1-b6cad454b8da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532187975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2532187975
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.4186969371
Short name T1624
Test name
Test status
Simulation time 37958871 ps
CPU time 0.63 seconds
Started Jan 24 01:08:18 PM PST 24
Finished Jan 24 01:08:56 PM PST 24
Peak memory 203160 kb
Host smart-53992845-8fff-48e8-a8d8-3291902069af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186969371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.4186969371
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3139935299
Short name T1535
Test name
Test status
Simulation time 69971248 ps
CPU time 0.79 seconds
Started Jan 24 12:55:16 PM PST 24
Finished Jan 24 12:55:47 PM PST 24
Peak memory 203152 kb
Host smart-45424c05-5391-42c1-af81-8d47ef2f739a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139935299 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3139935299
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3267551053
Short name T1584
Test name
Test status
Simulation time 39323591 ps
CPU time 0.71 seconds
Started Jan 24 12:55:08 PM PST 24
Finished Jan 24 12:55:34 PM PST 24
Peak memory 203196 kb
Host smart-39ff0532-7a8d-412c-92ae-0aaed6e07896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267551053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3267551053
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1126767821
Short name T1536
Test name
Test status
Simulation time 19752992 ps
CPU time 0.69 seconds
Started Jan 24 12:55:10 PM PST 24
Finished Jan 24 12:55:38 PM PST 24
Peak memory 203004 kb
Host smart-39ca6ad6-0e80-441e-81a1-49021cf0a364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126767821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1126767821
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1836873204
Short name T1550
Test name
Test status
Simulation time 41914969 ps
CPU time 1.03 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:29:00 PM PST 24
Peak memory 203468 kb
Host smart-96668322-35ad-4ae3-b5e4-99485a47c2c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836873204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1836873204
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3157229351
Short name T1566
Test name
Test status
Simulation time 84378925 ps
CPU time 1.68 seconds
Started Jan 24 12:55:20 PM PST 24
Finished Jan 24 12:55:51 PM PST 24
Peak memory 203456 kb
Host smart-28902999-474c-42c4-b3a3-080aa84f775f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157229351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3157229351
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3372667046
Short name T87
Test name
Test status
Simulation time 2041364853 ps
CPU time 1.73 seconds
Started Jan 24 12:55:20 PM PST 24
Finished Jan 24 12:55:52 PM PST 24
Peak memory 203452 kb
Host smart-a1c93e81-d352-4bfd-be38-804ead5770b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372667046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3372667046
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3812495731
Short name T85
Test name
Test status
Simulation time 26412883 ps
CPU time 0.72 seconds
Started Jan 24 12:55:17 PM PST 24
Finished Jan 24 12:55:49 PM PST 24
Peak memory 203156 kb
Host smart-5569b306-758c-44df-9dc6-4955eee96f49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812495731 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3812495731
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.19853586
Short name T1552
Test name
Test status
Simulation time 15554321 ps
CPU time 0.67 seconds
Started Jan 24 12:55:21 PM PST 24
Finished Jan 24 12:55:55 PM PST 24
Peak memory 202908 kb
Host smart-00ca6225-3aaa-44c1-9434-d3c7d828ed7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19853586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.19853586
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.998982970
Short name T106
Test name
Test status
Simulation time 60665039 ps
CPU time 0.92 seconds
Started Jan 24 12:55:17 PM PST 24
Finished Jan 24 12:55:49 PM PST 24
Peak memory 203100 kb
Host smart-ee495866-14c3-4552-abd3-c26628e501f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998982970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.998982970
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3205627400
Short name T1619
Test name
Test status
Simulation time 344630019 ps
CPU time 1.93 seconds
Started Jan 24 12:55:20 PM PST 24
Finished Jan 24 12:55:53 PM PST 24
Peak memory 203408 kb
Host smart-47125f06-f62b-436b-bd30-7b1708561825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205627400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3205627400
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1405533877
Short name T89
Test name
Test status
Simulation time 166381490 ps
CPU time 1.21 seconds
Started Jan 24 12:55:16 PM PST 24
Finished Jan 24 12:55:47 PM PST 24
Peak memory 203436 kb
Host smart-dc4ae767-993a-4a9d-95b1-823e97a28a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405533877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1405533877
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2243202561
Short name T1517
Test name
Test status
Simulation time 139594951 ps
CPU time 0.92 seconds
Started Jan 24 12:55:29 PM PST 24
Finished Jan 24 12:55:56 PM PST 24
Peak memory 203208 kb
Host smart-63099743-b43a-42de-930f-e5e9cfcdf172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243202561 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2243202561
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1109094241
Short name T1577
Test name
Test status
Simulation time 19704060 ps
CPU time 0.73 seconds
Started Jan 24 12:55:32 PM PST 24
Finished Jan 24 12:56:00 PM PST 24
Peak memory 202868 kb
Host smart-1ca83664-a1b0-4689-a25d-6bd45207c7e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109094241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1109094241
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2888535661
Short name T1578
Test name
Test status
Simulation time 77438383 ps
CPU time 0.68 seconds
Started Jan 24 12:55:16 PM PST 24
Finished Jan 24 12:55:46 PM PST 24
Peak memory 203124 kb
Host smart-8c7a61f0-0e9e-4267-97b8-86f3ec1cecb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888535661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2888535661
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1716843578
Short name T1610
Test name
Test status
Simulation time 41968692 ps
CPU time 0.93 seconds
Started Jan 24 12:55:30 PM PST 24
Finished Jan 24 12:56:01 PM PST 24
Peak memory 203324 kb
Host smart-8b2fc2af-2025-41f1-a8ee-b22b9e8215e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716843578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1716843578
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.930147384
Short name T1522
Test name
Test status
Simulation time 146555882 ps
CPU time 1.68 seconds
Started Jan 24 01:29:37 PM PST 24
Finished Jan 24 01:29:52 PM PST 24
Peak memory 203508 kb
Host smart-91bf2e83-5ecd-41b6-9237-92dcaf12a273
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930147384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.930147384
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1064998227
Short name T172
Test name
Test status
Simulation time 47425401 ps
CPU time 1.19 seconds
Started Jan 24 12:55:22 PM PST 24
Finished Jan 24 12:55:56 PM PST 24
Peak memory 203220 kb
Host smart-79d7310e-9d2a-4852-8243-d18431a158fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064998227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1064998227
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2363167266
Short name T1525
Test name
Test status
Simulation time 18808250 ps
CPU time 0.68 seconds
Started Jan 24 01:04:13 PM PST 24
Finished Jan 24 01:04:58 PM PST 24
Peak memory 203204 kb
Host smart-2f7bcfd1-4672-4172-a416-8eaa6d439c63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363167266 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2363167266
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2935493646
Short name T119
Test name
Test status
Simulation time 37855370 ps
CPU time 0.63 seconds
Started Jan 24 12:55:28 PM PST 24
Finished Jan 24 12:55:56 PM PST 24
Peak memory 202984 kb
Host smart-1c607457-27dd-4c84-9e82-aaa8454239a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935493646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2935493646
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3521666979
Short name T1576
Test name
Test status
Simulation time 17195764 ps
CPU time 0.65 seconds
Started Jan 24 12:55:36 PM PST 24
Finished Jan 24 12:56:04 PM PST 24
Peak memory 203040 kb
Host smart-bb1b7fd7-541b-4027-8c68-d4731652f601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521666979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3521666979
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4101422953
Short name T126
Test name
Test status
Simulation time 39726005 ps
CPU time 0.91 seconds
Started Jan 24 12:55:46 PM PST 24
Finished Jan 24 12:56:20 PM PST 24
Peak memory 203404 kb
Host smart-a0c9d9d3-8b58-44b1-ba2a-48cd349f745f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101422953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.4101422953
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2923810122
Short name T1559
Test name
Test status
Simulation time 94242447 ps
CPU time 2.01 seconds
Started Jan 24 12:55:31 PM PST 24
Finished Jan 24 12:56:01 PM PST 24
Peak memory 203340 kb
Host smart-9c9734ee-595e-49f4-b067-1522e53d93d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923810122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2923810122
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3846365746
Short name T1548
Test name
Test status
Simulation time 126140178 ps
CPU time 1.27 seconds
Started Jan 24 12:55:31 PM PST 24
Finished Jan 24 12:56:00 PM PST 24
Peak memory 203288 kb
Host smart-5aa3f38f-c5ea-4d7f-b7a1-a93cbe316147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846365746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3846365746
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1703083110
Short name T1524
Test name
Test status
Simulation time 57979867 ps
CPU time 0.92 seconds
Started Jan 24 12:55:38 PM PST 24
Finished Jan 24 12:56:09 PM PST 24
Peak memory 203260 kb
Host smart-d01303a6-d45b-4880-9bd7-a2bada07d380
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703083110 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1703083110
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4161592237
Short name T120
Test name
Test status
Simulation time 18802050 ps
CPU time 0.73 seconds
Started Jan 24 01:28:55 PM PST 24
Finished Jan 24 01:29:13 PM PST 24
Peak memory 203276 kb
Host smart-63f0f8bc-fafa-4a9f-a8e8-49a37d6337a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161592237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.4161592237
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3151572598
Short name T1521
Test name
Test status
Simulation time 50596427 ps
CPU time 0.63 seconds
Started Jan 24 12:55:45 PM PST 24
Finished Jan 24 12:56:20 PM PST 24
Peak memory 203020 kb
Host smart-11780389-49f3-4ab2-893e-ae2a3157c764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151572598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3151572598
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2608306389
Short name T1618
Test name
Test status
Simulation time 84293813 ps
CPU time 1.9 seconds
Started Jan 24 12:55:45 PM PST 24
Finished Jan 24 12:56:21 PM PST 24
Peak memory 203360 kb
Host smart-14d47e0c-2d91-4ffc-ae77-2c63d44ffe42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608306389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2608306389
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2242661064
Short name T62
Test name
Test status
Simulation time 163419247 ps
CPU time 1.41 seconds
Started Jan 24 09:55:06 PM PST 24
Finished Jan 24 09:55:17 PM PST 24
Peak memory 210728 kb
Host smart-31b5c793-6c42-4c4d-b6a2-caca0292e072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242661064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2242661064
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3174059360
Short name T1287
Test name
Test status
Simulation time 1981985397 ps
CPU time 25.37 seconds
Started Jan 24 09:55:05 PM PST 24
Finished Jan 24 09:55:41 PM PST 24
Peak memory 262464 kb
Host smart-051ca391-440c-454b-af1e-eb4564e20a88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174059360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3174059360
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.1012896435
Short name T526
Test name
Test status
Simulation time 8849176056 ps
CPU time 172.59 seconds
Started Jan 24 09:55:13 PM PST 24
Finished Jan 24 09:58:12 PM PST 24
Peak memory 753892 kb
Host smart-8115dd0f-5d2f-436b-b2ae-ee476bfd4a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012896435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.1012896435
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.1660442506
Short name T392
Test name
Test status
Simulation time 3475923762 ps
CPU time 287.86 seconds
Started Jan 24 09:55:15 PM PST 24
Finished Jan 24 10:00:08 PM PST 24
Peak memory 893420 kb
Host smart-8f45acaf-8c51-42b8-9cb1-0e52b412baaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660442506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1660442506
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.700823925
Short name T601
Test name
Test status
Simulation time 136498787 ps
CPU time 0.85 seconds
Started Jan 24 09:55:07 PM PST 24
Finished Jan 24 09:55:18 PM PST 24
Peak memory 202332 kb
Host smart-c94cb56a-3ce5-4720-b4ce-d2918d60ec05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700823925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.700823925
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1799655565
Short name T517
Test name
Test status
Simulation time 434620344 ps
CPU time 6.46 seconds
Started Jan 24 09:55:02 PM PST 24
Finished Jan 24 09:55:11 PM PST 24
Peak memory 243384 kb
Host smart-9eb2c6f5-8dfa-4456-b2d3-e1249a918534
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799655565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1799655565
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3004266900
Short name T794
Test name
Test status
Simulation time 3597866147 ps
CPU time 330.27 seconds
Started Jan 24 09:55:06 PM PST 24
Finished Jan 24 10:00:46 PM PST 24
Peak memory 1062816 kb
Host smart-6e111103-1512-4383-92b2-d6f7c2b6f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004266900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3004266900
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.2135898820
Short name T981
Test name
Test status
Simulation time 3503785386 ps
CPU time 33.37 seconds
Started Jan 24 09:55:21 PM PST 24
Finished Jan 24 09:55:56 PM PST 24
Peak memory 251028 kb
Host smart-0306704c-d317-4be2-9b60-622afd46f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135898820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.2135898820
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.459655720
Short name T496
Test name
Test status
Simulation time 24987456 ps
CPU time 0.64 seconds
Started Jan 24 09:55:07 PM PST 24
Finished Jan 24 09:55:16 PM PST 24
Peak memory 201492 kb
Host smart-a43f46ac-6cd2-4f0d-a3b2-a1b8526c9ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459655720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.459655720
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.378864350
Short name T991
Test name
Test status
Simulation time 2953514440 ps
CPU time 98.84 seconds
Started Jan 24 09:55:03 PM PST 24
Finished Jan 24 09:56:50 PM PST 24
Peak memory 328508 kb
Host smart-5aa81ae8-b774-47e0-ac72-81d9003857e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378864350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.378864350
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_rx_oversample.3923258226
Short name T457
Test name
Test status
Simulation time 5217274167 ps
CPU time 104.34 seconds
Started Jan 24 09:55:05 PM PST 24
Finished Jan 24 09:57:00 PM PST 24
Peak memory 248368 kb
Host smart-7604c191-8503-424c-8a8f-f72498453303
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923258226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_rx_oversample.
3923258226
Directory /workspace/0.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1779603446
Short name T1182
Test name
Test status
Simulation time 10208106349 ps
CPU time 159.67 seconds
Started Jan 24 09:55:07 PM PST 24
Finished Jan 24 09:57:57 PM PST 24
Peak memory 277220 kb
Host smart-2c122c6d-0caf-41bb-b684-282ee5d74ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779603446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1779603446
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2056017184
Short name T1269
Test name
Test status
Simulation time 3383330740 ps
CPU time 10.97 seconds
Started Jan 24 09:55:02 PM PST 24
Finished Jan 24 09:55:15 PM PST 24
Peak memory 210816 kb
Host smart-316b9e2a-3c19-447d-8d07-b29342d7c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056017184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2056017184
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3502036276
Short name T213
Test name
Test status
Simulation time 10439731046 ps
CPU time 15.37 seconds
Started Jan 24 09:55:23 PM PST 24
Finished Jan 24 09:55:40 PM PST 24
Peak memory 305956 kb
Host smart-9a36fd59-ba9b-4bff-8645-7187ab881f2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502036276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3502036276
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1019092368
Short name T1244
Test name
Test status
Simulation time 10149470316 ps
CPU time 76.65 seconds
Started Jan 24 09:55:19 PM PST 24
Finished Jan 24 09:56:38 PM PST 24
Peak memory 675928 kb
Host smart-aa72d4d1-5119-4669-b6f3-eaa8cd5c34f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019092368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1019092368
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3334054747
Short name T813
Test name
Test status
Simulation time 1433942739 ps
CPU time 1.91 seconds
Started Jan 24 09:55:23 PM PST 24
Finished Jan 24 09:55:26 PM PST 24
Peak memory 202660 kb
Host smart-864715b3-cdff-401a-8550-ee2253ab482b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334054747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3334054747
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.4094396917
Short name T225
Test name
Test status
Simulation time 1595309617 ps
CPU time 6.15 seconds
Started Jan 24 09:55:17 PM PST 24
Finished Jan 24 09:55:26 PM PST 24
Peak memory 202652 kb
Host smart-7e9be89d-a4e5-492e-9289-69bf32dc7a67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094396917 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.4094396917
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.559711110
Short name T1349
Test name
Test status
Simulation time 10272795719 ps
CPU time 239.46 seconds
Started Jan 24 09:55:19 PM PST 24
Finished Jan 24 09:59:21 PM PST 24
Peak memory 2334456 kb
Host smart-fad2146e-f7db-411d-9cee-c834a3ae9a5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559711110 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.559711110
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.2393963252
Short name T825
Test name
Test status
Simulation time 4624268748 ps
CPU time 4.11 seconds
Started Jan 24 09:55:34 PM PST 24
Finished Jan 24 09:55:40 PM PST 24
Peak memory 202636 kb
Host smart-b92ec4db-790a-4407-8caa-bafce2dc3025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393963252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.2393963252
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1371623509
Short name T1427
Test name
Test status
Simulation time 677725483 ps
CPU time 7.3 seconds
Started Jan 24 09:55:08 PM PST 24
Finished Jan 24 09:55:23 PM PST 24
Peak memory 202600 kb
Host smart-b316ed56-883d-446a-b2df-381994cf93b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371623509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1371623509
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.2584354156
Short name T1032
Test name
Test status
Simulation time 97525742076 ps
CPU time 1918.93 seconds
Started Jan 24 09:55:34 PM PST 24
Finished Jan 24 10:27:35 PM PST 24
Peak memory 1004728 kb
Host smart-2ccf2fe2-19e4-4db8-96ed-82b9a98376c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584354156 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_stress_all.2584354156
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1131256237
Short name T583
Test name
Test status
Simulation time 4463428721 ps
CPU time 20.91 seconds
Started Jan 24 09:55:09 PM PST 24
Finished Jan 24 09:55:36 PM PST 24
Peak memory 209988 kb
Host smart-9ab12ed1-c2af-418f-bf9c-40f57d29ff26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131256237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1131256237
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.3456101972
Short name T323
Test name
Test status
Simulation time 18297648837 ps
CPU time 37.27 seconds
Started Jan 24 09:55:13 PM PST 24
Finished Jan 24 09:55:56 PM PST 24
Peak memory 885548 kb
Host smart-406ffce8-3e01-438e-8cb9-033683da6e89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456101972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.3456101972
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3898057228
Short name T1097
Test name
Test status
Simulation time 2000335661 ps
CPU time 8.25 seconds
Started Jan 24 09:55:19 PM PST 24
Finished Jan 24 09:55:30 PM PST 24
Peak memory 206384 kb
Host smart-b4396dcf-a4e1-4890-970a-f4c962fc01c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898057228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3898057228
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_ovf.1234650901
Short name T1415
Test name
Test status
Simulation time 6323855261 ps
CPU time 162.19 seconds
Started Jan 24 09:55:34 PM PST 24
Finished Jan 24 09:58:18 PM PST 24
Peak memory 370160 kb
Host smart-a85d9552-7b1c-4794-b0be-25755b32cc7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234650901 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_tx_ovf.1234650901
Directory /workspace/0.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.2032030368
Short name T1115
Test name
Test status
Simulation time 2498297231 ps
CPU time 6.96 seconds
Started Jan 24 09:55:23 PM PST 24
Finished Jan 24 09:55:32 PM PST 24
Peak memory 202712 kb
Host smart-368d54e7-da77-470c-b29d-17f44d6a9c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032030368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.i2c_target_unexp_stop.2032030368
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2743879724
Short name T387
Test name
Test status
Simulation time 106944206 ps
CPU time 0.63 seconds
Started Jan 24 11:22:53 PM PST 24
Finished Jan 24 11:22:55 PM PST 24
Peak memory 201148 kb
Host smart-1c608262-4532-4acd-b84c-74e52288c46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743879724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2743879724
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.328726377
Short name T774
Test name
Test status
Simulation time 147724765 ps
CPU time 2.04 seconds
Started Jan 24 09:55:28 PM PST 24
Finished Jan 24 09:55:32 PM PST 24
Peak memory 210616 kb
Host smart-ed54381f-893b-4eb9-8685-5a1065f3dced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328726377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.328726377
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2535967531
Short name T1378
Test name
Test status
Simulation time 770053159 ps
CPU time 6.92 seconds
Started Jan 24 09:55:25 PM PST 24
Finished Jan 24 09:55:34 PM PST 24
Peak memory 257120 kb
Host smart-4db8725b-3fba-4fdd-b94c-329a9e362fef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535967531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2535967531
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2505756645
Short name T232
Test name
Test status
Simulation time 8379004305 ps
CPU time 116.25 seconds
Started Jan 24 09:55:25 PM PST 24
Finished Jan 24 09:57:24 PM PST 24
Peak memory 374772 kb
Host smart-d4369b4d-a829-42bb-8eb1-55193d121f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505756645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2505756645
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3822022797
Short name T341
Test name
Test status
Simulation time 4599001999 ps
CPU time 616.11 seconds
Started Jan 24 09:55:22 PM PST 24
Finished Jan 24 10:05:40 PM PST 24
Peak memory 1309100 kb
Host smart-7346655a-2d69-4c74-a205-d54d26959680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822022797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3822022797
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2270732608
Short name T384
Test name
Test status
Simulation time 84535239 ps
CPU time 0.93 seconds
Started Jan 24 09:55:25 PM PST 24
Finished Jan 24 09:55:28 PM PST 24
Peak memory 202268 kb
Host smart-6b0ad911-9ac2-491a-858c-bb27dc18fd2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270732608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2270732608
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2089476994
Short name T937
Test name
Test status
Simulation time 6757094017 ps
CPU time 361.94 seconds
Started Jan 24 09:55:21 PM PST 24
Finished Jan 24 10:01:25 PM PST 24
Peak memory 1797484 kb
Host smart-0a0b4c70-3725-416b-ae58-895775a0ec6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089476994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2089476994
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.3190690263
Short name T1353
Test name
Test status
Simulation time 4785498203 ps
CPU time 62.62 seconds
Started Jan 24 09:55:55 PM PST 24
Finished Jan 24 09:56:59 PM PST 24
Peak memory 218884 kb
Host smart-190ede4f-62b4-4464-a105-859c9346342a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190690263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.3190690263
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.3291185116
Short name T1060
Test name
Test status
Simulation time 45115324 ps
CPU time 0.67 seconds
Started Jan 24 09:55:28 PM PST 24
Finished Jan 24 09:55:30 PM PST 24
Peak memory 201276 kb
Host smart-13fbb4db-145f-455c-b65a-228e23e59e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291185116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.3291185116
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2498024028
Short name T1369
Test name
Test status
Simulation time 55649858871 ps
CPU time 220.22 seconds
Started Jan 24 09:55:19 PM PST 24
Finished Jan 24 09:59:02 PM PST 24
Peak memory 378576 kb
Host smart-58314088-16ed-4d5b-9823-0eda0c080e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498024028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2498024028
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_rx_oversample.507870336
Short name T179
Test name
Test status
Simulation time 7562236119 ps
CPU time 236.14 seconds
Started Jan 24 09:55:34 PM PST 24
Finished Jan 24 09:59:32 PM PST 24
Peak memory 316288 kb
Host smart-53a965fe-7c25-4094-8552-57b50fc3d625
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507870336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_rx_oversample.507870336
Directory /workspace/1.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2043541161
Short name T827
Test name
Test status
Simulation time 1905273279 ps
CPU time 45.84 seconds
Started Jan 24 09:55:19 PM PST 24
Finished Jan 24 09:56:08 PM PST 24
Peak memory 303928 kb
Host smart-9dcfbbc7-962d-438d-ac43-3ef5b1044650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043541161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2043541161
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.1539499864
Short name T138
Test name
Test status
Simulation time 10400979517 ps
CPU time 454.92 seconds
Started Jan 24 09:55:25 PM PST 24
Finished Jan 24 10:03:02 PM PST 24
Peak memory 1509076 kb
Host smart-f2cc9b71-851e-4c9d-a939-72fb9f0b6300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539499864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.1539499864
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.3535516808
Short name T950
Test name
Test status
Simulation time 1151678646 ps
CPU time 51.7 seconds
Started Jan 24 09:55:25 PM PST 24
Finished Jan 24 09:56:19 PM PST 24
Peak memory 210688 kb
Host smart-7dc9890c-666f-4d9a-8fd4-d3b31c3bc7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535516808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3535516808
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.185138336
Short name T95
Test name
Test status
Simulation time 152664586 ps
CPU time 0.8 seconds
Started Jan 24 09:56:02 PM PST 24
Finished Jan 24 09:56:03 PM PST 24
Peak memory 218412 kb
Host smart-284b979a-7952-4dfb-90b6-d6a7f2257c71
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185138336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.185138336
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.588262547
Short name T1408
Test name
Test status
Simulation time 8526398261 ps
CPU time 4.55 seconds
Started Jan 24 09:55:40 PM PST 24
Finished Jan 24 09:55:46 PM PST 24
Peak memory 202636 kb
Host smart-29e8c9e9-f5ef-4ce8-bcb2-79202104288c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588262547 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.588262547
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3511248502
Short name T206
Test name
Test status
Simulation time 10218686281 ps
CPU time 23.94 seconds
Started Jan 24 09:55:40 PM PST 24
Finished Jan 24 09:56:05 PM PST 24
Peak memory 319344 kb
Host smart-855db764-4742-4c83-8445-86428cfd4136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511248502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3511248502
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3251854635
Short name T721
Test name
Test status
Simulation time 10142376599 ps
CPU time 21.48 seconds
Started Jan 24 09:55:37 PM PST 24
Finished Jan 24 09:55:59 PM PST 24
Peak memory 351960 kb
Host smart-5a89f5e2-b638-402b-b14e-38b31e8ab57e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251854635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3251854635
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1925926456
Short name T55
Test name
Test status
Simulation time 4203156789 ps
CPU time 5.22 seconds
Started Jan 24 09:55:28 PM PST 24
Finished Jan 24 09:55:35 PM PST 24
Peak memory 202912 kb
Host smart-72816609-e1fe-444b-a32e-a9882a219396
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925926456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1925926456
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.357435292
Short name T1270
Test name
Test status
Simulation time 477778648 ps
CPU time 2.64 seconds
Started Jan 24 09:55:44 PM PST 24
Finished Jan 24 09:55:47 PM PST 24
Peak memory 202648 kb
Host smart-12d0882e-48c0-4c6c-8b21-b711ea155a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357435292 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.357435292
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3252693547
Short name T1360
Test name
Test status
Simulation time 829786572 ps
CPU time 4.14 seconds
Started Jan 24 09:55:28 PM PST 24
Finished Jan 24 09:55:34 PM PST 24
Peak memory 201848 kb
Host smart-a5e96c84-a41f-406d-be6d-d9f68fef1ac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252693547 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3252693547
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.1718672804
Short name T778
Test name
Test status
Simulation time 6888399748 ps
CPU time 30.39 seconds
Started Jan 24 10:04:32 PM PST 24
Finished Jan 24 10:05:09 PM PST 24
Peak memory 780788 kb
Host smart-d37f82ff-3473-4a50-8d4c-dd1c01096ae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718672804 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.1718672804
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.4227690316
Short name T534
Test name
Test status
Simulation time 7741164001 ps
CPU time 3.75 seconds
Started Jan 24 09:55:44 PM PST 24
Finished Jan 24 09:55:48 PM PST 24
Peak memory 202640 kb
Host smart-10142e85-18b8-41ae-8c7a-ae54cd3203d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227690316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.4227690316
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.555594683
Short name T100
Test name
Test status
Simulation time 7043707771 ps
CPU time 41.22 seconds
Started Jan 24 09:55:21 PM PST 24
Finished Jan 24 09:56:04 PM PST 24
Peak memory 202628 kb
Host smart-79daa154-fefa-4320-9e8f-d9e83051ea29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555594683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.555594683
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.2947470252
Short name T533
Test name
Test status
Simulation time 51906801891 ps
CPU time 65.03 seconds
Started Jan 24 09:55:39 PM PST 24
Finished Jan 24 09:56:45 PM PST 24
Peak memory 281576 kb
Host smart-4e317da8-a651-4096-bc44-2bfc76132957
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947470252 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.2947470252
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.999447687
Short name T402
Test name
Test status
Simulation time 1078198105 ps
CPU time 8.02 seconds
Started Jan 24 09:55:21 PM PST 24
Finished Jan 24 09:55:31 PM PST 24
Peak memory 202580 kb
Host smart-ae527e06-caf5-488f-86b4-b00ece421cc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999447687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_rd.999447687
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.1764982994
Short name T296
Test name
Test status
Simulation time 16485769147 ps
CPU time 30.07 seconds
Started Jan 24 09:55:21 PM PST 24
Finished Jan 24 09:55:53 PM PST 24
Peak memory 790888 kb
Host smart-b2f068b9-6230-4b82-a6e8-487511640f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764982994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.1764982994
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.2941475199
Short name T823
Test name
Test status
Simulation time 21090482184 ps
CPU time 499.21 seconds
Started Jan 24 09:55:34 PM PST 24
Finished Jan 24 10:03:55 PM PST 24
Peak memory 1456392 kb
Host smart-44d0b5fb-4314-47c8-a39e-8e0b739e0015
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941475199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.2941475199
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.3139170550
Short name T690
Test name
Test status
Simulation time 10918592519 ps
CPU time 8.74 seconds
Started Jan 24 09:55:45 PM PST 24
Finished Jan 24 09:55:55 PM PST 24
Peak memory 202664 kb
Host smart-0ed9ba94-826b-4d3d-bed9-55c37d48ad37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139170550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.3139170550
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_ovf.3399421669
Short name T444
Test name
Test status
Simulation time 5063006465 ps
CPU time 42.24 seconds
Started Jan 24 09:55:34 PM PST 24
Finished Jan 24 09:56:18 PM PST 24
Peak memory 218292 kb
Host smart-9479955d-3dca-45d3-9a87-3e903b32e2c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399421669 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_tx_ovf.3399421669
Directory /workspace/1.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.3525041112
Short name T1166
Test name
Test status
Simulation time 1384844800 ps
CPU time 7.73 seconds
Started Jan 24 09:55:32 PM PST 24
Finished Jan 24 09:55:42 PM PST 24
Peak memory 202568 kb
Host smart-d96fc700-fe12-44fa-a6f8-1d8d21eb234c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525041112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.i2c_target_unexp_stop.3525041112
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2477656596
Short name T569
Test name
Test status
Simulation time 24571484 ps
CPU time 0.65 seconds
Started Jan 24 10:02:29 PM PST 24
Finished Jan 24 10:02:31 PM PST 24
Peak memory 200944 kb
Host smart-268c2d73-1de4-4e30-b009-95f27d4a5073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477656596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2477656596
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2029760947
Short name T958
Test name
Test status
Simulation time 57668134 ps
CPU time 1.16 seconds
Started Jan 24 10:02:23 PM PST 24
Finished Jan 24 10:02:25 PM PST 24
Peak memory 210732 kb
Host smart-7e4f2de9-2f8e-4260-ae2d-5f078c81138c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029760947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2029760947
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3324110589
Short name T1293
Test name
Test status
Simulation time 453268986 ps
CPU time 22.72 seconds
Started Jan 24 10:00:59 PM PST 24
Finished Jan 24 10:01:24 PM PST 24
Peak memory 281708 kb
Host smart-d7eb0e3d-3af1-4cd3-bf3a-6898d3b53d5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324110589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3324110589
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2084699668
Short name T1062
Test name
Test status
Simulation time 5856220235 ps
CPU time 79.82 seconds
Started Jan 24 10:01:50 PM PST 24
Finished Jan 24 10:03:10 PM PST 24
Peak memory 518492 kb
Host smart-f0e2ae56-3255-4b75-ba5c-81dbf6f29120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084699668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2084699668
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1949635756
Short name T238
Test name
Test status
Simulation time 17188438479 ps
CPU time 289.38 seconds
Started Jan 24 10:00:57 PM PST 24
Finished Jan 24 10:05:51 PM PST 24
Peak memory 1406236 kb
Host smart-c4ba5122-82d4-4846-8145-164c4db5b106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949635756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1949635756
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1478848047
Short name T314
Test name
Test status
Simulation time 120055684 ps
CPU time 0.95 seconds
Started Jan 24 10:00:58 PM PST 24
Finished Jan 24 10:01:02 PM PST 24
Peak memory 202364 kb
Host smart-2fd31eb3-a0bd-4cc4-9b03-7165ea31dc01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478848047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1478848047
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3431483221
Short name T1039
Test name
Test status
Simulation time 308907749 ps
CPU time 8.69 seconds
Started Jan 24 10:00:58 PM PST 24
Finished Jan 24 10:01:10 PM PST 24
Peak memory 202564 kb
Host smart-6dbb6b34-6e18-4af2-ba39-8357ff7d2856
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431483221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3431483221
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2700571490
Short name T1010
Test name
Test status
Simulation time 9767077361 ps
CPU time 635 seconds
Started Jan 24 10:00:58 PM PST 24
Finished Jan 24 10:11:37 PM PST 24
Peak memory 1522476 kb
Host smart-552f9007-b70b-4a2a-80f1-b510348c6519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700571490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2700571490
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2595888064
Short name T247
Test name
Test status
Simulation time 2156056027 ps
CPU time 104.72 seconds
Started Jan 24 10:02:23 PM PST 24
Finished Jan 24 10:04:09 PM PST 24
Peak memory 243284 kb
Host smart-cc2f6c62-6dcc-44ef-9eb3-dd113ed29b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595888064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2595888064
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_perf.684609642
Short name T150
Test name
Test status
Simulation time 50124255923 ps
CPU time 921.3 seconds
Started Jan 24 10:01:47 PM PST 24
Finished Jan 24 10:17:09 PM PST 24
Peak memory 210808 kb
Host smart-80a631ff-79f0-46ca-a1d8-b418bba1531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684609642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.684609642
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_rx_oversample.603678580
Short name T742
Test name
Test status
Simulation time 3867294910 ps
CPU time 174.33 seconds
Started Jan 24 10:00:58 PM PST 24
Finished Jan 24 10:03:56 PM PST 24
Peak memory 308416 kb
Host smart-5df13a4f-af78-431d-b007-bca2379e0621
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603678580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_rx_oversample.
603678580
Directory /workspace/10.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.763921095
Short name T1368
Test name
Test status
Simulation time 6564803805 ps
CPU time 57.7 seconds
Started Jan 24 10:01:00 PM PST 24
Finished Jan 24 10:02:01 PM PST 24
Peak memory 310620 kb
Host smart-a69b0512-2347-46f1-856f-05f191b54cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763921095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.763921095
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.895048490
Short name T593
Test name
Test status
Simulation time 17057894787 ps
CPU time 1143.02 seconds
Started Jan 24 10:02:23 PM PST 24
Finished Jan 24 10:21:27 PM PST 24
Peak memory 2254572 kb
Host smart-f5b6b3d4-82c6-4483-bdea-d14572706608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895048490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.895048490
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1040444853
Short name T985
Test name
Test status
Simulation time 1116082253 ps
CPU time 11.18 seconds
Started Jan 24 10:01:46 PM PST 24
Finished Jan 24 10:01:58 PM PST 24
Peak memory 210724 kb
Host smart-3650bd5a-0dec-4d7f-832b-dc69d61fe0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040444853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1040444853
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1787856434
Short name T1422
Test name
Test status
Simulation time 595005866 ps
CPU time 2.97 seconds
Started Jan 24 10:02:28 PM PST 24
Finished Jan 24 10:02:32 PM PST 24
Peak memory 202540 kb
Host smart-f2fb1af3-3163-442b-af9d-4f143ff573a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787856434 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1787856434
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1761161499
Short name T1177
Test name
Test status
Simulation time 10547679663 ps
CPU time 10.39 seconds
Started Jan 24 10:02:22 PM PST 24
Finished Jan 24 10:02:34 PM PST 24
Peak memory 262056 kb
Host smart-167a138e-aaf2-4773-998f-6aece9da50dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761161499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1761161499
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.202316752
Short name T468
Test name
Test status
Simulation time 10350868161 ps
CPU time 31.32 seconds
Started Jan 24 10:02:29 PM PST 24
Finished Jan 24 10:03:01 PM PST 24
Peak memory 402916 kb
Host smart-ffbaa025-50ef-4e35-aeb2-3eafee07cca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202316752 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.202316752
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1594840046
Short name T1313
Test name
Test status
Simulation time 1164480612 ps
CPU time 5.63 seconds
Started Jan 24 10:02:22 PM PST 24
Finished Jan 24 10:02:29 PM PST 24
Peak memory 202592 kb
Host smart-7cc07974-dd0a-49d5-9210-1f46f32ee742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594840046 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1594840046
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1437084459
Short name T1164
Test name
Test status
Simulation time 8886503721 ps
CPU time 160.3 seconds
Started Jan 24 10:02:26 PM PST 24
Finished Jan 24 10:05:08 PM PST 24
Peak memory 2048056 kb
Host smart-855154bf-ae18-4989-8a64-69acb15de6b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437084459 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1437084459
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.2201296529
Short name T1150
Test name
Test status
Simulation time 3745731049 ps
CPU time 4.98 seconds
Started Jan 24 10:02:26 PM PST 24
Finished Jan 24 10:02:32 PM PST 24
Peak memory 202612 kb
Host smart-b795e289-f5b5-4917-8da5-3366172bd229
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201296529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.2201296529
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2489884253
Short name T761
Test name
Test status
Simulation time 2853337154 ps
CPU time 13.68 seconds
Started Jan 24 10:02:21 PM PST 24
Finished Jan 24 10:02:37 PM PST 24
Peak memory 202656 kb
Host smart-9698b703-a7e6-4390-84cb-76e0698d4a79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489884253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2489884253
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.1905071726
Short name T243
Test name
Test status
Simulation time 33331627430 ps
CPU time 168.01 seconds
Started Jan 24 10:02:29 PM PST 24
Finished Jan 24 10:05:18 PM PST 24
Peak memory 1367156 kb
Host smart-51e19942-32d8-49cf-945e-710f75a7f611
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905071726 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.1905071726
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.1879694394
Short name T215
Test name
Test status
Simulation time 9964613083 ps
CPU time 23.1 seconds
Started Jan 24 10:02:25 PM PST 24
Finished Jan 24 10:02:50 PM PST 24
Peak memory 221364 kb
Host smart-ee55654a-b52f-4792-a497-dee843686f0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879694394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.1879694394
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.3539595206
Short name T945
Test name
Test status
Simulation time 29723032969 ps
CPU time 56.19 seconds
Started Jan 24 10:02:19 PM PST 24
Finished Jan 24 10:03:17 PM PST 24
Peak memory 1022052 kb
Host smart-ed774476-e8c1-42c8-9c56-69d50f2babcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539595206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.3539595206
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.4248108173
Short name T1094
Test name
Test status
Simulation time 38181664419 ps
CPU time 888.27 seconds
Started Jan 24 10:02:23 PM PST 24
Finished Jan 24 10:17:13 PM PST 24
Peak memory 1922308 kb
Host smart-824411c5-d0df-47ad-97d6-4bf571505e94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248108173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.4248108173
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3736005302
Short name T1266
Test name
Test status
Simulation time 1679003284 ps
CPU time 7.31 seconds
Started Jan 24 10:02:29 PM PST 24
Finished Jan 24 10:02:37 PM PST 24
Peak memory 202540 kb
Host smart-6e9f1145-3aeb-4ae5-b8be-3c538a98c3f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736005302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3736005302
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_ovf.2659770440
Short name T1046
Test name
Test status
Simulation time 2928835518 ps
CPU time 137.6 seconds
Started Jan 24 10:02:20 PM PST 24
Finished Jan 24 10:04:39 PM PST 24
Peak memory 429424 kb
Host smart-7330c100-19b8-413d-b9a1-8266efc7a011
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659770440 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_tx_ovf.2659770440
Directory /workspace/10.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/10.i2c_target_unexp_stop.4132716972
Short name T595
Test name
Test status
Simulation time 1226477787 ps
CPU time 5.75 seconds
Started Jan 24 10:02:25 PM PST 24
Finished Jan 24 10:02:33 PM PST 24
Peak memory 204532 kb
Host smart-489d4d9c-0d80-4fb8-b473-de288c5a5376
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132716972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.i2c_target_unexp_stop.4132716972
Directory /workspace/10.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/11.i2c_alert_test.4233556573
Short name T883
Test name
Test status
Simulation time 14688086 ps
CPU time 0.6 seconds
Started Jan 24 10:52:56 PM PST 24
Finished Jan 24 10:52:58 PM PST 24
Peak memory 201164 kb
Host smart-99686da4-fbac-414d-baae-c8f301affe48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233556573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.4233556573
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1762858418
Short name T943
Test name
Test status
Simulation time 35174212 ps
CPU time 1.52 seconds
Started Jan 24 10:02:52 PM PST 24
Finished Jan 24 10:02:54 PM PST 24
Peak memory 210812 kb
Host smart-338f94ff-e46d-46f3-84aa-e4d3936943d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762858418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1762858418
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.3202238179
Short name T1456
Test name
Test status
Simulation time 335256561 ps
CPU time 16.25 seconds
Started Jan 24 10:02:44 PM PST 24
Finished Jan 24 10:03:01 PM PST 24
Peak memory 262872 kb
Host smart-b8699321-f2da-4162-95b0-013350eae7bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202238179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.3202238179
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.3935796871
Short name T837
Test name
Test status
Simulation time 9656578056 ps
CPU time 69.98 seconds
Started Jan 24 10:02:46 PM PST 24
Finished Jan 24 10:03:57 PM PST 24
Peak memory 588320 kb
Host smart-04ea7058-ea4f-461c-a3e0-b6814e3aab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935796871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3935796871
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2733572585
Short name T594
Test name
Test status
Simulation time 16867031051 ps
CPU time 195.14 seconds
Started Jan 24 10:02:46 PM PST 24
Finished Jan 24 10:06:03 PM PST 24
Peak memory 1130580 kb
Host smart-909882b5-960a-48ce-9dcf-c51b252f17c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733572585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2733572585
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3697802524
Short name T227
Test name
Test status
Simulation time 572666355 ps
CPU time 8.75 seconds
Started Jan 24 10:02:53 PM PST 24
Finished Jan 24 10:03:02 PM PST 24
Peak memory 262924 kb
Host smart-f01cb775-8523-4a46-a39f-56dc7ce15f3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697802524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3697802524
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.349633684
Short name T1470
Test name
Test status
Simulation time 6805409674 ps
CPU time 431.77 seconds
Started Jan 24 10:02:29 PM PST 24
Finished Jan 24 10:09:42 PM PST 24
Peak memory 1931744 kb
Host smart-02acbdca-8b3c-4010-aead-559ae387e5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349633684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.349633684
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.2090459773
Short name T679
Test name
Test status
Simulation time 1967044254 ps
CPU time 47.5 seconds
Started Jan 24 10:03:05 PM PST 24
Finished Jan 24 10:03:54 PM PST 24
Peak memory 307364 kb
Host smart-9ecc0683-66b4-41e9-b6c0-5ed5d600317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090459773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.2090459773
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.779438855
Short name T1225
Test name
Test status
Simulation time 20835153 ps
CPU time 0.65 seconds
Started Jan 24 10:48:50 PM PST 24
Finished Jan 24 10:48:51 PM PST 24
Peak memory 201476 kb
Host smart-2264b704-409c-452b-b7fa-d12f47450866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779438855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.779438855
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2616933907
Short name T47
Test name
Test status
Simulation time 6835823203 ps
CPU time 60.63 seconds
Started Jan 24 10:02:46 PM PST 24
Finished Jan 24 10:03:47 PM PST 24
Peak memory 218064 kb
Host smart-7129820e-60b5-4289-a7a4-40d5d68a058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616933907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2616933907
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_rx_oversample.66673771
Short name T777
Test name
Test status
Simulation time 1862017818 ps
CPU time 136.27 seconds
Started Jan 24 10:02:29 PM PST 24
Finished Jan 24 10:04:46 PM PST 24
Peak memory 259560 kb
Host smart-d198e001-86e0-42bc-9c90-db31d1a17b90
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66673771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_rx_oversample.66673771
Directory /workspace/11.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1766728215
Short name T1472
Test name
Test status
Simulation time 2365375267 ps
CPU time 25.86 seconds
Started Jan 24 10:02:28 PM PST 24
Finished Jan 24 10:02:55 PM PST 24
Peak memory 251624 kb
Host smart-77706ef1-4fc7-4d5a-9d4f-fba5139157b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766728215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1766728215
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.4096179979
Short name T585
Test name
Test status
Simulation time 1755202982 ps
CPU time 34.85 seconds
Started Jan 24 10:02:44 PM PST 24
Finished Jan 24 10:03:20 PM PST 24
Peak memory 210728 kb
Host smart-58ea427a-85d5-4d01-9e1e-f3cbe6622b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096179979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.4096179979
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.380128491
Short name T367
Test name
Test status
Simulation time 1040840638 ps
CPU time 4.03 seconds
Started Jan 24 11:57:42 PM PST 24
Finished Jan 24 11:57:48 PM PST 24
Peak memory 202616 kb
Host smart-445110ff-e69f-4873-ab7f-fc79fa6ccf97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380128491 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.380128491
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1125927149
Short name T564
Test name
Test status
Simulation time 10068957268 ps
CPU time 49.19 seconds
Started Jan 24 10:02:46 PM PST 24
Finished Jan 24 10:03:36 PM PST 24
Peak memory 492232 kb
Host smart-8800b57f-23e4-4ac6-b87e-71e69c8ef8f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125927149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1125927149
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.4255286653
Short name T918
Test name
Test status
Simulation time 10145876859 ps
CPU time 69.63 seconds
Started Jan 24 10:02:48 PM PST 24
Finished Jan 24 10:03:59 PM PST 24
Peak memory 556732 kb
Host smart-077398a3-31a0-4d14-8ba9-ccc62880c2e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255286653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.4255286653
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.906413058
Short name T274
Test name
Test status
Simulation time 2015684380 ps
CPU time 2.45 seconds
Started Jan 24 10:03:05 PM PST 24
Finished Jan 24 10:03:09 PM PST 24
Peak memory 202344 kb
Host smart-5aa81fb6-8261-4d2a-98b1-f5dcacd55f55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906413058 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.906413058
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1893973729
Short name T1088
Test name
Test status
Simulation time 10788876535 ps
CPU time 3.6 seconds
Started Jan 24 10:02:45 PM PST 24
Finished Jan 24 10:02:50 PM PST 24
Peak memory 202660 kb
Host smart-2118a205-918f-4452-a598-e102df4b34e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893973729 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1893973729
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.53346019
Short name T369
Test name
Test status
Simulation time 12352948773 ps
CPU time 238.3 seconds
Started Jan 24 10:40:51 PM PST 24
Finished Jan 24 10:44:52 PM PST 24
Peak memory 2425928 kb
Host smart-1a7b61b6-3557-4b9c-84bf-0384e74fd5d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53346019 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.53346019
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.3073710698
Short name T1136
Test name
Test status
Simulation time 691838691 ps
CPU time 3.84 seconds
Started Jan 24 10:53:55 PM PST 24
Finished Jan 24 10:54:00 PM PST 24
Peak memory 202588 kb
Host smart-05a257ee-bd7b-4805-b63d-6c6c7d0d5730
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073710698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.3073710698
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.1273387564
Short name T859
Test name
Test status
Simulation time 6052997155 ps
CPU time 15.01 seconds
Started Jan 24 10:02:46 PM PST 24
Finished Jan 24 10:03:03 PM PST 24
Peak memory 202652 kb
Host smart-1b6978a7-803c-4621-9279-43a2f958538e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273387564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.1273387564
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.776252045
Short name T413
Test name
Test status
Simulation time 115950228292 ps
CPU time 1805.5 seconds
Started Jan 24 11:32:55 PM PST 24
Finished Jan 25 12:03:02 AM PST 24
Peak memory 5071900 kb
Host smart-574f776b-7009-4ab5-94c6-33a9e52ce213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776252045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_target_stress_all.776252045
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3177836752
Short name T826
Test name
Test status
Simulation time 2259485017 ps
CPU time 9.39 seconds
Started Jan 24 10:02:46 PM PST 24
Finished Jan 24 10:02:57 PM PST 24
Peak memory 202628 kb
Host smart-2acfdbf3-05d0-4e96-acb9-be319004ae26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177836752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3177836752
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1282007499
Short name T1279
Test name
Test status
Simulation time 65676827018 ps
CPU time 447.85 seconds
Started Jan 25 01:11:21 AM PST 24
Finished Jan 25 01:18:54 AM PST 24
Peak memory 2944192 kb
Host smart-4d7ac192-ae60-4ece-9106-2d1572ed5ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282007499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1282007499
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.632951159
Short name T1275
Test name
Test status
Simulation time 22423831941 ps
CPU time 8.17 seconds
Started Jan 24 11:21:34 PM PST 24
Finished Jan 24 11:21:44 PM PST 24
Peak memory 216308 kb
Host smart-40211b89-65f0-4016-ad89-cc3489b73d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632951159 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.632951159
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_ovf.1252825410
Short name T1512
Test name
Test status
Simulation time 4574196797 ps
CPU time 49.23 seconds
Started Jan 24 10:02:45 PM PST 24
Finished Jan 24 10:03:35 PM PST 24
Peak memory 218716 kb
Host smart-6c0fc199-8297-4c0f-8598-70aa7809f482
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252825410 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_tx_ovf.1252825410
Directory /workspace/11.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/11.i2c_target_unexp_stop.507253792
Short name T1162
Test name
Test status
Simulation time 11289333838 ps
CPU time 4.9 seconds
Started Jan 24 10:02:46 PM PST 24
Finished Jan 24 10:02:53 PM PST 24
Peak memory 203532 kb
Host smart-24eeae68-e578-4205-8c49-7fa6854b91bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507253792 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_unexp_stop.507253792
Directory /workspace/11.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2434789757
Short name T1401
Test name
Test status
Simulation time 40692348 ps
CPU time 0.64 seconds
Started Jan 24 10:03:42 PM PST 24
Finished Jan 24 10:03:44 PM PST 24
Peak memory 201124 kb
Host smart-73748ae7-4c22-48a7-9877-10670abe35ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434789757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2434789757
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3860342845
Short name T664
Test name
Test status
Simulation time 58230400 ps
CPU time 1.78 seconds
Started Jan 24 10:03:25 PM PST 24
Finished Jan 24 10:03:27 PM PST 24
Peak memory 210704 kb
Host smart-d5662c9d-ab77-4f7a-8209-97765cf606b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860342845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3860342845
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3793404083
Short name T1499
Test name
Test status
Simulation time 926806980 ps
CPU time 7.74 seconds
Started Jan 24 10:03:06 PM PST 24
Finished Jan 24 10:03:15 PM PST 24
Peak memory 248152 kb
Host smart-64bd5eb0-7f8c-4259-b8b2-088dfce5e602
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793404083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3793404083
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.1731062600
Short name T482
Test name
Test status
Simulation time 3575763634 ps
CPU time 179.75 seconds
Started Jan 24 10:40:53 PM PST 24
Finished Jan 24 10:43:59 PM PST 24
Peak memory 1008260 kb
Host smart-bb67e71b-723a-4e71-bd82-f24e2c3b08ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731062600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1731062600
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.1868814594
Short name T51
Test name
Test status
Simulation time 91057185 ps
CPU time 0.89 seconds
Started Jan 24 11:16:06 PM PST 24
Finished Jan 24 11:16:09 PM PST 24
Peak memory 202352 kb
Host smart-f76c0370-d636-46da-8ae5-67d837b9ce57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868814594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.1868814594
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.4249653972
Short name T771
Test name
Test status
Simulation time 379857326 ps
CPU time 4.6 seconds
Started Jan 24 10:03:03 PM PST 24
Finished Jan 24 10:03:08 PM PST 24
Peak memory 202556 kb
Host smart-f08cfc2e-cf03-4c58-96f8-bb81d01915da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249653972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.4249653972
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2458862937
Short name T285
Test name
Test status
Simulation time 37370605201 ps
CPU time 845.49 seconds
Started Jan 25 03:41:09 AM PST 24
Finished Jan 25 03:55:16 AM PST 24
Peak memory 1725040 kb
Host smart-b49f73c2-d7d8-47e3-bf5a-8e0bd9dc147a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458862937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2458862937
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3584231151
Short name T33
Test name
Test status
Simulation time 10237877330 ps
CPU time 73.81 seconds
Started Jan 24 10:03:51 PM PST 24
Finished Jan 24 10:05:11 PM PST 24
Peak memory 276724 kb
Host smart-fb797254-9c85-40e4-84b5-5d3b053aeab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584231151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3584231151
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.1100593036
Short name T965
Test name
Test status
Simulation time 35689151 ps
CPU time 0.61 seconds
Started Jan 24 10:03:05 PM PST 24
Finished Jan 24 10:03:07 PM PST 24
Peak memory 201572 kb
Host smart-d397ead3-39e6-4ea1-bfb7-04bc504dc040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100593036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1100593036
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2836246193
Short name T165
Test name
Test status
Simulation time 3458337023 ps
CPU time 18.33 seconds
Started Jan 24 10:03:27 PM PST 24
Finished Jan 24 10:03:47 PM PST 24
Peak memory 226616 kb
Host smart-24e5b1b5-c469-420f-8d80-53cee482ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836246193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2836246193
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_rx_oversample.48086952
Short name T901
Test name
Test status
Simulation time 7412836415 ps
CPU time 168.54 seconds
Started Jan 24 11:11:33 PM PST 24
Finished Jan 24 11:14:26 PM PST 24
Peak memory 289592 kb
Host smart-04d1117c-b313-4925-bf72-4ad5fac60d49
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48086952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_rx_oversample.48086952
Directory /workspace/12.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2705426991
Short name T1493
Test name
Test status
Simulation time 2810022020 ps
CPU time 161.02 seconds
Started Jan 24 10:33:17 PM PST 24
Finished Jan 24 10:35:59 PM PST 24
Peak memory 243412 kb
Host smart-26c4ce6c-b50d-407b-b903-02894c38cb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705426991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2705426991
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3171198798
Short name T980
Test name
Test status
Simulation time 1344286783 ps
CPU time 30.01 seconds
Started Jan 24 10:03:24 PM PST 24
Finished Jan 24 10:03:55 PM PST 24
Peak memory 210680 kb
Host smart-18e4f8c8-85d1-42d3-acca-4e7a94d49e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171198798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3171198798
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2436441517
Short name T1331
Test name
Test status
Simulation time 1723192669 ps
CPU time 3.47 seconds
Started Jan 24 10:03:48 PM PST 24
Finished Jan 24 10:04:01 PM PST 24
Peak memory 202660 kb
Host smart-22103f5c-78ae-4311-8602-0359c20a2dde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436441517 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2436441517
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.391047657
Short name T567
Test name
Test status
Simulation time 11740721825 ps
CPU time 4.07 seconds
Started Jan 24 10:03:45 PM PST 24
Finished Jan 24 10:03:51 PM PST 24
Peak memory 232872 kb
Host smart-63f8f4a3-cb5b-43a4-aa1b-a12e3d481fdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391047657 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.391047657
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.2937001940
Short name T362
Test name
Test status
Simulation time 3338094986 ps
CPU time 3.81 seconds
Started Jan 24 10:03:47 PM PST 24
Finished Jan 24 10:03:59 PM PST 24
Peak memory 202664 kb
Host smart-64e03f39-d4eb-4b58-9bab-bcd8461a3405
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937001940 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.2937001940
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3435444308
Short name T1110
Test name
Test status
Simulation time 17871706282 ps
CPU time 40.82 seconds
Started Jan 24 10:03:48 PM PST 24
Finished Jan 24 10:04:37 PM PST 24
Peak memory 619620 kb
Host smart-8b250ff6-8363-4f5f-ad1a-c2fc80dbe60c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435444308 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3435444308
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.1118439621
Short name T993
Test name
Test status
Simulation time 831340769 ps
CPU time 4.85 seconds
Started Jan 24 10:03:48 PM PST 24
Finished Jan 24 10:04:02 PM PST 24
Peak memory 202604 kb
Host smart-dec7dab1-3b92-4b11-af10-2a773e9fa4ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118439621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.1118439621
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3139554806
Short name T230
Test name
Test status
Simulation time 14437215007 ps
CPU time 19.35 seconds
Started Jan 24 10:03:27 PM PST 24
Finished Jan 24 10:03:48 PM PST 24
Peak memory 202680 kb
Host smart-e3eb6e26-9dc2-4916-b4c0-fea587ea0a15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139554806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3139554806
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.2051846999
Short name T577
Test name
Test status
Simulation time 29955706331 ps
CPU time 1653.95 seconds
Started Jan 24 10:03:52 PM PST 24
Finished Jan 24 10:31:32 PM PST 24
Peak memory 5915672 kb
Host smart-15dcb6a6-5ed9-4fef-a9d2-0e8e6f81c549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051846999 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.2051846999
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1946236095
Short name T425
Test name
Test status
Simulation time 388982896 ps
CPU time 6.54 seconds
Started Jan 24 10:03:25 PM PST 24
Finished Jan 24 10:03:32 PM PST 24
Peak memory 202600 kb
Host smart-77622c75-41a8-4caa-a188-8230eb38a75e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946236095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1946236095
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2308821695
Short name T1188
Test name
Test status
Simulation time 32757689090 ps
CPU time 1330.44 seconds
Started Jan 24 10:03:25 PM PST 24
Finished Jan 24 10:25:37 PM PST 24
Peak memory 7156736 kb
Host smart-1517415f-73f1-4e32-94f7-d47e207966ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308821695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2308821695
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1779756020
Short name T350
Test name
Test status
Simulation time 24055414399 ps
CPU time 278.56 seconds
Started Jan 24 10:03:44 PM PST 24
Finished Jan 24 10:08:24 PM PST 24
Peak memory 1834024 kb
Host smart-f8d85815-2739-45e3-8530-f25f090ab3f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779756020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1779756020
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3295506133
Short name T397
Test name
Test status
Simulation time 1526815506 ps
CPU time 7.16 seconds
Started Jan 24 10:03:47 PM PST 24
Finished Jan 24 10:04:00 PM PST 24
Peak memory 213696 kb
Host smart-35133fc5-6839-4eb7-9a01-8610a8cba0c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295506133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3295506133
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_ovf.2405641434
Short name T1382
Test name
Test status
Simulation time 3077982555 ps
CPU time 64.52 seconds
Started Jan 24 10:03:46 PM PST 24
Finished Jan 24 10:04:53 PM PST 24
Peak memory 291692 kb
Host smart-c571eef7-d976-4340-87ec-2bf45cae825e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405641434 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_tx_ovf.2405641434
Directory /workspace/12.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.950326185
Short name T445
Test name
Test status
Simulation time 3117295107 ps
CPU time 6.33 seconds
Started Jan 24 10:03:47 PM PST 24
Finished Jan 24 10:03:59 PM PST 24
Peak memory 202660 kb
Host smart-313afb93-9d5a-4b0b-b751-1064e85b33d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950326185 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_unexp_stop.950326185
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2769616464
Short name T635
Test name
Test status
Simulation time 15533664 ps
CPU time 0.67 seconds
Started Jan 25 02:04:06 AM PST 24
Finished Jan 25 02:04:08 AM PST 24
Peak memory 202068 kb
Host smart-87bba269-8d87-416c-90ed-97cb54c36a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769616464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2769616464
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.2507869112
Short name T1482
Test name
Test status
Simulation time 50794515 ps
CPU time 1.35 seconds
Started Jan 24 10:04:09 PM PST 24
Finished Jan 24 10:04:15 PM PST 24
Peak memory 212344 kb
Host smart-e87bfd2e-5b24-4768-b5b5-1d8f2b3a92c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507869112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2507869112
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3307237332
Short name T408
Test name
Test status
Simulation time 400858789 ps
CPU time 21.44 seconds
Started Jan 24 10:04:07 PM PST 24
Finished Jan 24 10:04:33 PM PST 24
Peak memory 291120 kb
Host smart-f4969a29-3470-4487-99fc-a2062f1715e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307237332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3307237332
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.4055948145
Short name T616
Test name
Test status
Simulation time 7655640434 ps
CPU time 326.08 seconds
Started Jan 24 10:04:04 PM PST 24
Finished Jan 24 10:09:35 PM PST 24
Peak memory 1006348 kb
Host smart-b849cb2b-4298-4ba6-afa4-43abdacdbd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055948145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.4055948145
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1965035547
Short name T1220
Test name
Test status
Simulation time 267783568 ps
CPU time 0.99 seconds
Started Jan 24 10:04:03 PM PST 24
Finished Jan 24 10:04:08 PM PST 24
Peak memory 202352 kb
Host smart-30f8e055-6b4a-40f1-893a-4b88877b7176
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965035547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1965035547
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3776266796
Short name T1463
Test name
Test status
Simulation time 217325856 ps
CPU time 12.5 seconds
Started Jan 24 10:04:03 PM PST 24
Finished Jan 24 10:04:20 PM PST 24
Peak memory 243616 kb
Host smart-24cf8310-bd6a-45eb-9b29-bf62a6dd0258
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776266796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3776266796
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.2879641990
Short name T997
Test name
Test status
Simulation time 25320175465 ps
CPU time 403.3 seconds
Started Jan 24 10:04:09 PM PST 24
Finished Jan 24 10:10:57 PM PST 24
Peak memory 1774200 kb
Host smart-0369a3ab-25bc-4789-a060-3cd6a881443c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879641990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2879641990
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.4209859496
Short name T448
Test name
Test status
Simulation time 6625072930 ps
CPU time 68.47 seconds
Started Jan 24 11:48:04 PM PST 24
Finished Jan 24 11:49:19 PM PST 24
Peak memory 280932 kb
Host smart-55e4569d-ac9f-4196-829b-fc69cd98cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209859496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.4209859496
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3940799848
Short name T695
Test name
Test status
Simulation time 75199787283 ps
CPU time 541.64 seconds
Started Jan 24 10:04:04 PM PST 24
Finished Jan 24 10:13:10 PM PST 24
Peak memory 267728 kb
Host smart-9ba2b9e3-c800-42bd-a07f-ed789c1968ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940799848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3940799848
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_rx_oversample.128811298
Short name T1025
Test name
Test status
Simulation time 4309746926 ps
CPU time 107.33 seconds
Started Jan 24 10:03:55 PM PST 24
Finished Jan 24 10:05:51 PM PST 24
Peak memory 333648 kb
Host smart-df335f6f-7189-423d-87b7-17ad98f4ee7b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128811298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_rx_oversample.
128811298
Directory /workspace/13.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.556842459
Short name T239
Test name
Test status
Simulation time 2011237549 ps
CPU time 44.36 seconds
Started Jan 24 10:03:46 PM PST 24
Finished Jan 24 10:04:32 PM PST 24
Peak memory 236976 kb
Host smart-3117848f-000b-4613-8e7d-3f9143c10a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556842459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.556842459
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1426405932
Short name T1017
Test name
Test status
Simulation time 2643585023 ps
CPU time 27.81 seconds
Started Jan 24 10:04:01 PM PST 24
Finished Jan 24 10:04:35 PM PST 24
Peak memory 210736 kb
Host smart-c512c098-97bc-476c-be4c-4b089047abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426405932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1426405932
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3888282858
Short name T1298
Test name
Test status
Simulation time 1016360845 ps
CPU time 4.43 seconds
Started Jan 24 10:19:56 PM PST 24
Finished Jan 24 10:20:01 PM PST 24
Peak memory 202644 kb
Host smart-dae6763c-a09f-46d2-a949-60bde11a0e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888282858 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3888282858
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.2234938081
Short name T66
Test name
Test status
Simulation time 10084161195 ps
CPU time 70.61 seconds
Started Jan 24 10:04:21 PM PST 24
Finished Jan 24 10:05:33 PM PST 24
Peak memory 603616 kb
Host smart-ea3421b7-e24f-4b1a-a1bc-2a72a3aca99a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234938081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.2234938081
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2075956944
Short name T1123
Test name
Test status
Simulation time 10143952619 ps
CPU time 30.32 seconds
Started Jan 24 10:04:21 PM PST 24
Finished Jan 24 10:04:52 PM PST 24
Peak memory 428512 kb
Host smart-536a334a-1b6d-459f-854a-b35117e148ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075956944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2075956944
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.2339834709
Short name T306
Test name
Test status
Simulation time 450237106 ps
CPU time 2.84 seconds
Started Jan 24 10:04:21 PM PST 24
Finished Jan 24 10:04:25 PM PST 24
Peak memory 202628 kb
Host smart-2fb124c6-0aa0-4707-9ec2-a9bb6eb5c974
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339834709 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.2339834709
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.603665280
Short name T1143
Test name
Test status
Simulation time 2365730037 ps
CPU time 5.31 seconds
Started Jan 24 10:04:05 PM PST 24
Finished Jan 24 10:04:14 PM PST 24
Peak memory 208200 kb
Host smart-7d0afecc-5cbb-48fd-adab-c92e69191a3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603665280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.603665280
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.3436388527
Short name T692
Test name
Test status
Simulation time 26714284709 ps
CPU time 1320.17 seconds
Started Jan 24 10:04:09 PM PST 24
Finished Jan 24 10:26:14 PM PST 24
Peak memory 6048888 kb
Host smart-9d608975-b561-4098-b19d-8411b7c69373
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436388527 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.3436388527
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.1674394851
Short name T787
Test name
Test status
Simulation time 4705373588 ps
CPU time 5.05 seconds
Started Jan 24 10:27:38 PM PST 24
Finished Jan 24 10:27:44 PM PST 24
Peak memory 206564 kb
Host smart-5372c485-36cd-43a6-b0f4-960b5c54500c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674394851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.1674394851
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2486666467
Short name T481
Test name
Test status
Simulation time 3587514247 ps
CPU time 12.94 seconds
Started Jan 24 11:15:15 PM PST 24
Finished Jan 24 11:15:30 PM PST 24
Peak memory 202640 kb
Host smart-912aa864-e31d-4ad6-aa25-92f2bf5011ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486666467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2486666467
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1335970125
Short name T1013
Test name
Test status
Simulation time 2158526536 ps
CPU time 8.35 seconds
Started Jan 24 10:04:05 PM PST 24
Finished Jan 24 10:04:17 PM PST 24
Peak memory 202684 kb
Host smart-c541242e-b3a2-44bd-a24b-6f0babb4a23d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335970125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1335970125
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2413557135
Short name T1363
Test name
Test status
Simulation time 56159048024 ps
CPU time 848.39 seconds
Started Jan 24 10:04:09 PM PST 24
Finished Jan 24 10:18:22 PM PST 24
Peak memory 4715712 kb
Host smart-41a16559-79b7-4a93-8e13-43c272f24e26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413557135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2413557135
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1499393966
Short name T370
Test name
Test status
Simulation time 20108633286 ps
CPU time 1131.73 seconds
Started Jan 24 10:04:05 PM PST 24
Finished Jan 24 10:23:01 PM PST 24
Peak memory 4492116 kb
Host smart-ca93406b-5ba2-4503-81d6-6e18b25f32a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499393966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1499393966
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.1736160338
Short name T29
Test name
Test status
Simulation time 12216324388 ps
CPU time 7.55 seconds
Started Jan 24 11:20:00 PM PST 24
Finished Jan 24 11:20:09 PM PST 24
Peak memory 215840 kb
Host smart-09af55e8-f449-4b34-b802-1c17253e3a9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736160338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.1736160338
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_ovf.659555559
Short name T776
Test name
Test status
Simulation time 8969609555 ps
CPU time 187.12 seconds
Started Jan 24 10:04:04 PM PST 24
Finished Jan 24 10:07:16 PM PST 24
Peak memory 478032 kb
Host smart-ebf43420-f835-4cd5-acac-491bba543a03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659555559 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_tx_ovf.659555559
Directory /workspace/13.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.2035509109
Short name T840
Test name
Test status
Simulation time 3283257042 ps
CPU time 7.7 seconds
Started Jan 24 10:04:09 PM PST 24
Finished Jan 24 10:04:21 PM PST 24
Peak memory 202688 kb
Host smart-368a88f7-354a-458f-af69-d50d65f7d6c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035509109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.i2c_target_unexp_stop.2035509109
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.360013634
Short name T830
Test name
Test status
Simulation time 24327256 ps
CPU time 0.61 seconds
Started Jan 24 10:05:29 PM PST 24
Finished Jan 24 10:05:30 PM PST 24
Peak memory 202016 kb
Host smart-3ea37567-cf4c-460e-ab04-20f37fdd6175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360013634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.360013634
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2685743870
Short name T302
Test name
Test status
Simulation time 39602304 ps
CPU time 1.17 seconds
Started Jan 25 02:35:32 AM PST 24
Finished Jan 25 02:35:34 AM PST 24
Peak memory 210752 kb
Host smart-35db123e-629a-46a1-926d-fb8a0f3fd879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685743870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2685743870
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3322083510
Short name T344
Test name
Test status
Simulation time 1806813065 ps
CPU time 9.79 seconds
Started Jan 24 10:04:59 PM PST 24
Finished Jan 24 10:05:12 PM PST 24
Peak memory 296176 kb
Host smart-8aa759ef-10e5-4df5-a867-f30a044eeb48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322083510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3322083510
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.966724810
Short name T1481
Test name
Test status
Simulation time 3342887922 ps
CPU time 190.28 seconds
Started Jan 24 10:04:55 PM PST 24
Finished Jan 24 10:08:09 PM PST 24
Peak memory 608288 kb
Host smart-2f6f19f0-d54e-42d9-9637-82a67cf4b44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966724810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.966724810
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.1173216369
Short name T821
Test name
Test status
Simulation time 5512772100 ps
CPU time 729.26 seconds
Started Jan 24 10:04:44 PM PST 24
Finished Jan 24 10:16:58 PM PST 24
Peak memory 1504680 kb
Host smart-f2759b9e-9652-4b09-bae2-67aa765173ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173216369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.1173216369
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.575440515
Short name T568
Test name
Test status
Simulation time 141513421 ps
CPU time 0.83 seconds
Started Jan 24 10:04:39 PM PST 24
Finished Jan 24 10:04:44 PM PST 24
Peak memory 202284 kb
Host smart-ee26b507-ba8f-4e78-98fb-69b59136a56f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575440515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fm
t.575440515
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2023642837
Short name T1134
Test name
Test status
Simulation time 199569532 ps
CPU time 4.24 seconds
Started Jan 24 10:05:01 PM PST 24
Finished Jan 24 10:05:07 PM PST 24
Peak memory 202556 kb
Host smart-a0c430bd-6624-4635-a835-b9c93a11b618
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023642837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2023642837
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.787270392
Short name T634
Test name
Test status
Simulation time 25270267988 ps
CPU time 352.66 seconds
Started Jan 24 10:04:38 PM PST 24
Finished Jan 24 10:10:35 PM PST 24
Peak memory 1748096 kb
Host smart-e9f15e2f-6e19-4346-bf03-a56ba8b531d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787270392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.787270392
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2654898821
Short name T554
Test name
Test status
Simulation time 9874076741 ps
CPU time 62.72 seconds
Started Jan 24 10:05:11 PM PST 24
Finished Jan 24 10:06:17 PM PST 24
Peak memory 336164 kb
Host smart-69132b6a-b352-452f-9ce2-63f8018b9279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654898821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2654898821
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1023402162
Short name T146
Test name
Test status
Simulation time 76663069 ps
CPU time 0.63 seconds
Started Jan 24 10:04:38 PM PST 24
Finished Jan 24 10:04:43 PM PST 24
Peak memory 201504 kb
Host smart-a877a4e7-916e-40c8-bdb7-a5cd9be09af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023402162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1023402162
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.799220468
Short name T493
Test name
Test status
Simulation time 7641524291 ps
CPU time 27.48 seconds
Started Jan 24 10:04:56 PM PST 24
Finished Jan 24 10:05:26 PM PST 24
Peak memory 218912 kb
Host smart-c30e3eda-1b70-4c9e-897c-a4b9a97dc814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799220468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.799220468
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_rx_oversample.2827431742
Short name T852
Test name
Test status
Simulation time 2981334830 ps
CPU time 84.53 seconds
Started Jan 24 10:04:39 PM PST 24
Finished Jan 24 10:06:08 PM PST 24
Peak memory 247980 kb
Host smart-b0f8a8ac-cf8b-46e9-a05a-d4ca1173781a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827431742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_rx_oversample
.2827431742
Directory /workspace/14.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3294646242
Short name T720
Test name
Test status
Simulation time 2305299716 ps
CPU time 43.92 seconds
Started Jan 24 10:04:41 PM PST 24
Finished Jan 24 10:05:29 PM PST 24
Peak memory 267188 kb
Host smart-a787400f-363f-42f8-be1a-e5d9e7942dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294646242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3294646242
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all_with_rand_reset.1440135486
Short name T107
Test name
Test status
Simulation time 66480196810 ps
CPU time 796.25 seconds
Started Jan 24 10:05:11 PM PST 24
Finished Jan 24 10:18:30 PM PST 24
Peak memory 1458400 kb
Host smart-53677bf9-b705-4e94-aefe-a54ec07ec0ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440135486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.i2c_host_stress_all_with_rand_reset.1440135486
Directory /workspace/14.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1727357387
Short name T252
Test name
Test status
Simulation time 1010589208 ps
CPU time 45.06 seconds
Started Jan 24 10:27:11 PM PST 24
Finished Jan 24 10:27:57 PM PST 24
Peak memory 218304 kb
Host smart-9fa2bcb8-71a9-42a2-ad01-e32caea2fc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727357387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1727357387
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3273414594
Short name T395
Test name
Test status
Simulation time 2285560635 ps
CPU time 2.48 seconds
Started Jan 24 10:05:14 PM PST 24
Finished Jan 24 10:05:18 PM PST 24
Peak memory 202652 kb
Host smart-e9f0bd47-acda-4212-9385-f3684a398489
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273414594 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3273414594
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2086005439
Short name T1311
Test name
Test status
Simulation time 10043148459 ps
CPU time 73.78 seconds
Started Jan 24 10:04:56 PM PST 24
Finished Jan 24 10:06:13 PM PST 24
Peak memory 533192 kb
Host smart-ad5117a7-8ef5-4a3c-9525-ca9b411570d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086005439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2086005439
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1201519341
Short name T1252
Test name
Test status
Simulation time 10082872710 ps
CPU time 45.66 seconds
Started Jan 24 10:05:03 PM PST 24
Finished Jan 24 10:05:51 PM PST 24
Peak memory 501936 kb
Host smart-eec96ee5-e5a8-4daf-b66a-e008d4a45c74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201519341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1201519341
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.754633482
Short name T266
Test name
Test status
Simulation time 2078095381 ps
CPU time 2.45 seconds
Started Jan 24 10:05:13 PM PST 24
Finished Jan 24 10:05:18 PM PST 24
Peak memory 202668 kb
Host smart-24a44e2c-d9bb-47c6-83c0-ade4af64ee14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754633482 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.754633482
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2164902757
Short name T984
Test name
Test status
Simulation time 7619139592 ps
CPU time 6.95 seconds
Started Jan 24 10:04:57 PM PST 24
Finished Jan 24 10:05:07 PM PST 24
Peak memory 202648 kb
Host smart-3c09e4ef-be1b-4c43-9eda-cc8461d67943
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164902757 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2164902757
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1094559391
Short name T990
Test name
Test status
Simulation time 14470162194 ps
CPU time 46.72 seconds
Started Jan 24 10:05:03 PM PST 24
Finished Jan 24 10:05:53 PM PST 24
Peak memory 844960 kb
Host smart-47fa3f99-c92a-450e-976c-41365d238fd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094559391 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1094559391
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_perf.2102170991
Short name T1072
Test name
Test status
Simulation time 1854878365 ps
CPU time 3.09 seconds
Started Jan 24 10:05:00 PM PST 24
Finished Jan 24 10:05:05 PM PST 24
Peak memory 202592 kb
Host smart-2fa8426e-ab19-4abf-a4f2-ce7284b220d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102170991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.2102170991
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.191300761
Short name T338
Test name
Test status
Simulation time 7298836891 ps
CPU time 23.09 seconds
Started Jan 24 10:05:03 PM PST 24
Finished Jan 24 10:05:29 PM PST 24
Peak memory 202664 kb
Host smart-3a7b458f-3b8b-42a5-9e41-aa3dbb9067e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191300761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.191300761
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3842742942
Short name T818
Test name
Test status
Simulation time 2962364807 ps
CPU time 19.89 seconds
Started Jan 24 10:04:59 PM PST 24
Finished Jan 24 10:05:22 PM PST 24
Peak memory 216956 kb
Host smart-fa357ca7-0dc7-4ab7-beb3-fbab3bf0105e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842742942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3842742942
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1244884265
Short name T1194
Test name
Test status
Simulation time 28029654705 ps
CPU time 244.81 seconds
Started Jan 24 10:04:55 PM PST 24
Finished Jan 24 10:09:03 PM PST 24
Peak memory 1704912 kb
Host smart-07b79220-e36a-49b5-b24c-1fc86c6650e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244884265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1244884265
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2916772207
Short name T1210
Test name
Test status
Simulation time 1618629413 ps
CPU time 6.62 seconds
Started Jan 24 10:05:04 PM PST 24
Finished Jan 24 10:05:13 PM PST 24
Peak memory 202640 kb
Host smart-daa4c40d-161b-4833-a41f-2268f1414400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916772207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2916772207
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_ovf.3467632321
Short name T850
Test name
Test status
Simulation time 3641677907 ps
CPU time 142.64 seconds
Started Jan 24 10:04:56 PM PST 24
Finished Jan 24 10:07:21 PM PST 24
Peak memory 342196 kb
Host smart-1ad13730-2d2a-4943-8e9f-6e7de512737b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467632321 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_tx_ovf.3467632321
Directory /workspace/14.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.3561359835
Short name T396
Test name
Test status
Simulation time 4398279328 ps
CPU time 7.08 seconds
Started Jan 24 10:04:55 PM PST 24
Finished Jan 24 10:05:06 PM PST 24
Peak memory 202576 kb
Host smart-852ab5ed-0198-46ed-81f5-6368f97b9c82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561359835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.i2c_target_unexp_stop.3561359835
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.729997715
Short name T1413
Test name
Test status
Simulation time 16836482 ps
CPU time 0.67 seconds
Started Jan 24 10:06:13 PM PST 24
Finished Jan 24 10:06:17 PM PST 24
Peak memory 202032 kb
Host smart-2b46401d-560a-44f5-ad3b-783c334c3ea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729997715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.729997715
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.2961838321
Short name T932
Test name
Test status
Simulation time 38443687 ps
CPU time 1.05 seconds
Started Jan 24 10:05:52 PM PST 24
Finished Jan 24 10:05:53 PM PST 24
Peak memory 202600 kb
Host smart-3fa027b3-3835-47ee-8969-243903a6a3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961838321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2961838321
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3661069601
Short name T272
Test name
Test status
Simulation time 447998067 ps
CPU time 24.58 seconds
Started Jan 24 10:05:31 PM PST 24
Finished Jan 24 10:05:57 PM PST 24
Peak memory 300000 kb
Host smart-661586ed-2f57-475e-ac73-216fa4c3baf8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661069601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3661069601
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3585599748
Short name T535
Test name
Test status
Simulation time 10693644583 ps
CPU time 89.17 seconds
Started Jan 24 10:05:49 PM PST 24
Finished Jan 24 10:07:20 PM PST 24
Peak memory 763656 kb
Host smart-ed731e44-c4e7-4b10-b6d0-858adb39b1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585599748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3585599748
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3893366040
Short name T419
Test name
Test status
Simulation time 6486657263 ps
CPU time 943.95 seconds
Started Jan 24 10:05:31 PM PST 24
Finished Jan 24 10:21:17 PM PST 24
Peak memory 1785888 kb
Host smart-231190fd-464c-4d8f-8ffc-4f9214e401ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893366040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3893366040
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2222190901
Short name T638
Test name
Test status
Simulation time 148454220 ps
CPU time 1 seconds
Started Jan 24 10:05:37 PM PST 24
Finished Jan 24 10:05:39 PM PST 24
Peak memory 202356 kb
Host smart-c1cd7b74-0918-4166-bd36-8164b8ecaea2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222190901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2222190901
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2503294263
Short name T858
Test name
Test status
Simulation time 833008166 ps
CPU time 11.29 seconds
Started Jan 24 10:05:56 PM PST 24
Finished Jan 24 10:06:08 PM PST 24
Peak memory 202540 kb
Host smart-d78b4ded-4a74-47fa-aa50-e2def2d7c595
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503294263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.2503294263
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.225980313
Short name T135
Test name
Test status
Simulation time 4499967127 ps
CPU time 214.02 seconds
Started Jan 25 04:11:40 AM PST 24
Finished Jan 25 04:15:15 AM PST 24
Peak memory 1233692 kb
Host smart-5f1abe47-4660-41d9-a3e6-d0d5b245cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225980313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.225980313
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.2206496929
Short name T790
Test name
Test status
Simulation time 2278706282 ps
CPU time 67.84 seconds
Started Jan 24 10:06:16 PM PST 24
Finished Jan 24 10:07:25 PM PST 24
Peak memory 309184 kb
Host smart-33621472-b461-401a-9472-c18da7093340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206496929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2206496929
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.4102443580
Short name T961
Test name
Test status
Simulation time 20065106 ps
CPU time 0.65 seconds
Started Jan 24 10:05:30 PM PST 24
Finished Jan 24 10:05:32 PM PST 24
Peak memory 201496 kb
Host smart-2b87dcfc-55d0-4570-b4b8-0cd26cffe683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102443580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.4102443580
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2158834747
Short name T270
Test name
Test status
Simulation time 7187223639 ps
CPU time 30.84 seconds
Started Jan 24 10:05:50 PM PST 24
Finished Jan 24 10:06:22 PM PST 24
Peak memory 218396 kb
Host smart-b2257d17-1a10-4c71-961b-10a4f41902b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158834747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2158834747
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_rx_oversample.1658964726
Short name T844
Test name
Test status
Simulation time 6542249367 ps
CPU time 112.34 seconds
Started Jan 24 10:05:31 PM PST 24
Finished Jan 24 10:07:25 PM PST 24
Peak memory 265464 kb
Host smart-db6829fe-f48d-4867-86f7-5bdbb45e3a58
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658964726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_rx_oversample
.1658964726
Directory /workspace/15.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.965905215
Short name T449
Test name
Test status
Simulation time 1751984257 ps
CPU time 103.79 seconds
Started Jan 24 10:05:28 PM PST 24
Finished Jan 24 10:07:13 PM PST 24
Peak memory 243444 kb
Host smart-164212b3-0852-4e24-829a-4a281da82736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965905215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.965905215
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.4074053373
Short name T805
Test name
Test status
Simulation time 836277277 ps
CPU time 36.67 seconds
Started Jan 24 10:05:52 PM PST 24
Finished Jan 24 10:06:29 PM PST 24
Peak memory 218912 kb
Host smart-38f55805-91d8-4262-b3a1-adf8b15e990e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074053373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.4074053373
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3892436481
Short name T857
Test name
Test status
Simulation time 776705559 ps
CPU time 3.28 seconds
Started Jan 24 10:06:13 PM PST 24
Finished Jan 24 10:06:20 PM PST 24
Peak memory 202556 kb
Host smart-f7ae7bfe-0a5f-4c38-a9fe-b02efa869cf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892436481 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3892436481
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3978392831
Short name T795
Test name
Test status
Simulation time 10049135841 ps
CPU time 64.36 seconds
Started Jan 24 10:06:13 PM PST 24
Finished Jan 24 10:07:21 PM PST 24
Peak memory 558136 kb
Host smart-96723a61-ab3f-4acd-9273-a0162360df75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978392831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3978392831
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.4276685452
Short name T598
Test name
Test status
Simulation time 10318975883 ps
CPU time 11.33 seconds
Started Jan 24 10:06:12 PM PST 24
Finished Jan 24 10:06:28 PM PST 24
Peak memory 273764 kb
Host smart-82ddef9a-d210-44fd-bd07-d8b6fc07716a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276685452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.4276685452
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.4067439618
Short name T574
Test name
Test status
Simulation time 581372465 ps
CPU time 2.76 seconds
Started Jan 24 10:06:11 PM PST 24
Finished Jan 24 10:06:15 PM PST 24
Peak memory 202572 kb
Host smart-9de4b5ef-2af2-49e6-90f4-6bf62fce9fdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067439618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.4067439618
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3221635999
Short name T1322
Test name
Test status
Simulation time 9431222708 ps
CPU time 4.05 seconds
Started Jan 24 10:05:55 PM PST 24
Finished Jan 24 10:06:00 PM PST 24
Peak memory 202492 kb
Host smart-ce2ced5e-5726-4781-8f2f-92ad6979d07d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221635999 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3221635999
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3754361510
Short name T250
Test name
Test status
Simulation time 19238902689 ps
CPU time 929.12 seconds
Started Jan 24 10:06:12 PM PST 24
Finished Jan 24 10:21:46 PM PST 24
Peak memory 4623784 kb
Host smart-2ee035d1-d3a1-488f-a15f-67a53dd2b1ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754361510 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3754361510
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.1384774457
Short name T1424
Test name
Test status
Simulation time 1453004625 ps
CPU time 4.41 seconds
Started Jan 24 10:06:11 PM PST 24
Finished Jan 24 10:06:19 PM PST 24
Peak memory 203996 kb
Host smart-dc061b6b-d1c6-4202-b279-2eeba9441a59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384774457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.1384774457
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3487882571
Short name T451
Test name
Test status
Simulation time 17067226312 ps
CPU time 32.24 seconds
Started Jan 24 10:05:55 PM PST 24
Finished Jan 24 10:06:28 PM PST 24
Peak memory 202484 kb
Host smart-528b701f-7bf1-4fb6-a435-432e6f35f529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487882571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3487882571
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.2871231331
Short name T261
Test name
Test status
Simulation time 43856927870 ps
CPU time 149.02 seconds
Started Jan 24 10:06:09 PM PST 24
Finished Jan 24 10:08:40 PM PST 24
Peak memory 1325916 kb
Host smart-e5ed811c-efe3-42c6-8dde-5041c88e8f0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871231331 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.2871231331
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1087954847
Short name T1399
Test name
Test status
Simulation time 2478039367 ps
CPU time 49.26 seconds
Started Jan 24 10:05:50 PM PST 24
Finished Jan 24 10:06:41 PM PST 24
Peak memory 202620 kb
Host smart-c2aa2e66-d0fe-46c0-b0ea-a859700d53bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087954847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1087954847
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3610160184
Short name T992
Test name
Test status
Simulation time 8700983802 ps
CPU time 102.17 seconds
Started Jan 24 10:05:51 PM PST 24
Finished Jan 24 10:07:34 PM PST 24
Peak memory 1151264 kb
Host smart-ed5ffd01-5d07-458e-ad50-3f436fc9970d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610160184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3610160184
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2352156914
Short name T1452
Test name
Test status
Simulation time 5515990424 ps
CPU time 6.37 seconds
Started Jan 24 10:06:19 PM PST 24
Finished Jan 24 10:06:27 PM PST 24
Peak memory 206284 kb
Host smart-811ddc48-3665-4306-8820-9e676dd26658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352156914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2352156914
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_ovf.3112939433
Short name T938
Test name
Test status
Simulation time 10690222044 ps
CPU time 61.77 seconds
Started Jan 24 10:06:12 PM PST 24
Finished Jan 24 10:07:18 PM PST 24
Peak memory 271504 kb
Host smart-3989aba0-9a3a-4b97-92a4-ac67ab8eec8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112939433 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_tx_ovf.3112939433
Directory /workspace/15.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.2928553440
Short name T1388
Test name
Test status
Simulation time 2512335177 ps
CPU time 10.13 seconds
Started Jan 24 10:06:10 PM PST 24
Finished Jan 24 10:06:21 PM PST 24
Peak memory 212404 kb
Host smart-c471e624-2dbc-429f-8e6d-80f6494e19da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928553440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.i2c_target_unexp_stop.2928553440
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.34300144
Short name T745
Test name
Test status
Simulation time 26113031 ps
CPU time 0.65 seconds
Started Jan 24 10:07:15 PM PST 24
Finished Jan 24 10:07:22 PM PST 24
Peak memory 200960 kb
Host smart-f2d854fb-34ba-4753-beb9-6c6803f23576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34300144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.34300144
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2441958193
Short name T342
Test name
Test status
Simulation time 135006606 ps
CPU time 1.32 seconds
Started Jan 24 10:06:48 PM PST 24
Finished Jan 24 10:06:50 PM PST 24
Peak memory 210804 kb
Host smart-18f66dcb-b287-43e9-86c2-81e1dbd3dccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441958193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2441958193
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3034549521
Short name T1411
Test name
Test status
Simulation time 330032562 ps
CPU time 6.59 seconds
Started Jan 24 10:06:36 PM PST 24
Finished Jan 24 10:06:44 PM PST 24
Peak memory 255596 kb
Host smart-fc997c5d-f73c-493c-8bb3-6104cb68e9b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034549521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3034549521
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1687477063
Short name T1240
Test name
Test status
Simulation time 9125206562 ps
CPU time 84.27 seconds
Started Jan 24 10:06:48 PM PST 24
Finished Jan 24 10:08:14 PM PST 24
Peak memory 704608 kb
Host smart-983cac51-c53d-4c87-bdd1-ada5383ea98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687477063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1687477063
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2580551366
Short name T619
Test name
Test status
Simulation time 6181362369 ps
CPU time 859.05 seconds
Started Jan 24 10:06:35 PM PST 24
Finished Jan 24 10:20:55 PM PST 24
Peak memory 1667600 kb
Host smart-20a467a2-0e5a-4873-81db-4706157e782b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580551366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2580551366
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.919738177
Short name T558
Test name
Test status
Simulation time 277469394 ps
CPU time 0.9 seconds
Started Jan 24 10:06:33 PM PST 24
Finished Jan 24 10:06:35 PM PST 24
Peak memory 202320 kb
Host smart-ba3e92f5-ec82-489c-b1e2-5d1561f1b439
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919738177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.919738177
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.4118859844
Short name T1146
Test name
Test status
Simulation time 892381403 ps
CPU time 13.21 seconds
Started Jan 24 10:06:48 PM PST 24
Finished Jan 24 10:07:02 PM PST 24
Peak memory 245668 kb
Host smart-306c3ae9-4348-401d-b0a0-039791af27d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118859844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.4118859844
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.722407625
Short name T1305
Test name
Test status
Simulation time 5598875003 ps
CPU time 501.66 seconds
Started Jan 24 10:06:32 PM PST 24
Finished Jan 24 10:14:55 PM PST 24
Peak memory 1395520 kb
Host smart-c3a1c12e-cf77-4061-b238-a2a2559f7a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722407625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.722407625
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3385498993
Short name T646
Test name
Test status
Simulation time 3088278102 ps
CPU time 106.39 seconds
Started Jan 24 10:06:54 PM PST 24
Finished Jan 24 10:08:41 PM PST 24
Peak memory 378480 kb
Host smart-1d55cd27-d025-4633-9530-e6e5d9d0a394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385498993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3385498993
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.532857390
Short name T822
Test name
Test status
Simulation time 15887249 ps
CPU time 0.66 seconds
Started Jan 24 10:06:13 PM PST 24
Finished Jan 24 10:06:17 PM PST 24
Peak memory 201452 kb
Host smart-db78bc79-80d9-419f-86b5-8f399f1b220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532857390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.532857390
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.4006858985
Short name T1198
Test name
Test status
Simulation time 7012985845 ps
CPU time 24.9 seconds
Started Jan 24 10:06:36 PM PST 24
Finished Jan 24 10:07:02 PM PST 24
Peak memory 210828 kb
Host smart-7a6cc812-8d52-4624-9dc9-d09b34fa21f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006858985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.4006858985
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_rx_oversample.281500849
Short name T750
Test name
Test status
Simulation time 2554931713 ps
CPU time 205.97 seconds
Started Jan 24 10:06:10 PM PST 24
Finished Jan 24 10:09:37 PM PST 24
Peak memory 259672 kb
Host smart-bb44b19f-0a38-4a91-bbf1-a51ce31fe26a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281500849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_rx_oversample.
281500849
Directory /workspace/16.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1146952109
Short name T842
Test name
Test status
Simulation time 7640733081 ps
CPU time 102.14 seconds
Started Jan 24 10:06:11 PM PST 24
Finished Jan 24 10:07:57 PM PST 24
Peak memory 235252 kb
Host smart-0f881117-18ca-41f3-8c29-7ee30d06d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146952109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1146952109
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.208742235
Short name T1494
Test name
Test status
Simulation time 30222980939 ps
CPU time 2467.95 seconds
Started Jan 24 10:06:48 PM PST 24
Finished Jan 24 10:47:57 PM PST 24
Peak memory 3528608 kb
Host smart-80a98867-8bd5-48ad-8a83-ecfd5132e59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208742235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.208742235
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.2551288796
Short name T295
Test name
Test status
Simulation time 898780635 ps
CPU time 40.34 seconds
Started Jan 24 10:06:48 PM PST 24
Finished Jan 24 10:07:30 PM PST 24
Peak memory 210736 kb
Host smart-6f07e8af-f4e9-4323-ba8f-926597ff9794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551288796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2551288796
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2040752536
Short name T1454
Test name
Test status
Simulation time 781520025 ps
CPU time 2.23 seconds
Started Jan 24 10:06:53 PM PST 24
Finished Jan 24 10:06:57 PM PST 24
Peak memory 202612 kb
Host smart-51394ca9-f911-4087-8a53-9780507bb289
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040752536 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2040752536
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.4014115857
Short name T636
Test name
Test status
Simulation time 10281149825 ps
CPU time 12.54 seconds
Started Jan 24 10:06:53 PM PST 24
Finished Jan 24 10:07:07 PM PST 24
Peak memory 261028 kb
Host smart-7f989bf1-29d8-47b0-93af-6aceea057e7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014115857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.4014115857
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.113681325
Short name T800
Test name
Test status
Simulation time 10133922007 ps
CPU time 12.58 seconds
Started Jan 24 10:06:51 PM PST 24
Finished Jan 24 10:07:04 PM PST 24
Peak memory 294988 kb
Host smart-78c20a8e-585f-40ea-a71c-6435f60323da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113681325 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.113681325
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.420628996
Short name T951
Test name
Test status
Simulation time 2797660524 ps
CPU time 3.11 seconds
Started Jan 24 10:06:53 PM PST 24
Finished Jan 24 10:06:57 PM PST 24
Peak memory 202732 kb
Host smart-562fc408-a682-4a98-a112-cd1fadad7d77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420628996 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.420628996
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2817101503
Short name T504
Test name
Test status
Simulation time 17742266613 ps
CPU time 4.79 seconds
Started Jan 24 10:06:48 PM PST 24
Finished Jan 24 10:06:54 PM PST 24
Peak memory 202672 kb
Host smart-86e13376-3b7c-4fce-ba61-92f122e076e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817101503 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2817101503
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3292991166
Short name T769
Test name
Test status
Simulation time 5192483537 ps
CPU time 49 seconds
Started Jan 24 10:06:33 PM PST 24
Finished Jan 24 10:07:23 PM PST 24
Peak memory 1018172 kb
Host smart-e09e3943-2d6c-4e40-85fe-746630bb1ef4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292991166 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3292991166
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.861061673
Short name T1344
Test name
Test status
Simulation time 735372672 ps
CPU time 4.26 seconds
Started Jan 24 10:06:51 PM PST 24
Finished Jan 24 10:06:56 PM PST 24
Peak memory 202576 kb
Host smart-a3737d29-e69e-4f04-9478-d654e0863f2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861061673 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_perf.861061673
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.660665582
Short name T355
Test name
Test status
Simulation time 9212931192 ps
CPU time 9.02 seconds
Started Jan 24 10:06:36 PM PST 24
Finished Jan 24 10:06:46 PM PST 24
Peak memory 202676 kb
Host smart-7359cd0e-67a6-423c-b20e-1c747809bbff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660665582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.660665582
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.3774864807
Short name T660
Test name
Test status
Simulation time 29891167053 ps
CPU time 3105.27 seconds
Started Jan 24 10:06:54 PM PST 24
Finished Jan 24 10:58:40 PM PST 24
Peak memory 3982992 kb
Host smart-c26aa2d6-0c95-4a76-925e-dad5502c4ea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774864807 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.3774864807
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.382990751
Short name T1477
Test name
Test status
Simulation time 6071917169 ps
CPU time 63.21 seconds
Started Jan 24 10:06:32 PM PST 24
Finished Jan 24 10:07:36 PM PST 24
Peak memory 203488 kb
Host smart-77fed034-cc58-4e2b-99c6-6860422246d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382990751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.382990751
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1119184858
Short name T441
Test name
Test status
Simulation time 43125629227 ps
CPU time 815.23 seconds
Started Jan 24 10:06:34 PM PST 24
Finished Jan 24 10:20:11 PM PST 24
Peak memory 4590524 kb
Host smart-807a99d9-3ff3-4019-86f9-ba7faff7d752
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119184858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1119184858
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1491574755
Short name T28
Test name
Test status
Simulation time 6564838131 ps
CPU time 7.29 seconds
Started Jan 24 10:06:48 PM PST 24
Finished Jan 24 10:06:56 PM PST 24
Peak memory 206152 kb
Host smart-2742054b-38ad-49a0-b80a-79c7cbd95cde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491574755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1491574755
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_ovf.483729824
Short name T1026
Test name
Test status
Simulation time 12768519654 ps
CPU time 78.24 seconds
Started Jan 24 10:06:48 PM PST 24
Finished Jan 24 10:08:07 PM PST 24
Peak memory 299704 kb
Host smart-72264b1c-d5f2-462a-8b36-f25e02aba64b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483729824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_tx_ovf.483729824
Directory /workspace/16.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.2508847104
Short name T1434
Test name
Test status
Simulation time 1470456368 ps
CPU time 4.53 seconds
Started Jan 24 10:06:52 PM PST 24
Finished Jan 24 10:06:57 PM PST 24
Peak memory 202580 kb
Host smart-6406fc70-f48a-4844-9a8f-71409661d829
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508847104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.i2c_target_unexp_stop.2508847104
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.497995211
Short name T1221
Test name
Test status
Simulation time 23064806 ps
CPU time 0.6 seconds
Started Jan 24 10:08:01 PM PST 24
Finished Jan 24 10:08:03 PM PST 24
Peak memory 201160 kb
Host smart-7da1db31-1cfb-404a-9801-f1117afa4b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497995211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.497995211
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.224081679
Short name T204
Test name
Test status
Simulation time 47957431 ps
CPU time 1.14 seconds
Started Jan 24 10:07:37 PM PST 24
Finished Jan 24 10:07:39 PM PST 24
Peak memory 210772 kb
Host smart-c2fda651-b9f7-4326-a78e-9cdf852c07b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224081679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.224081679
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2465603317
Short name T1501
Test name
Test status
Simulation time 1124832275 ps
CPU time 5.38 seconds
Started Jan 24 10:07:15 PM PST 24
Finished Jan 24 10:07:27 PM PST 24
Peak memory 262060 kb
Host smart-190b823c-8e27-4505-8f70-9a5b3601c1c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465603317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2465603317
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2205968751
Short name T1117
Test name
Test status
Simulation time 5626230185 ps
CPU time 215.96 seconds
Started Jan 24 10:07:11 PM PST 24
Finished Jan 24 10:10:57 PM PST 24
Peak memory 860948 kb
Host smart-76818a13-e924-4051-b300-63412ff89c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205968751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2205968751
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.910818880
Short name T485
Test name
Test status
Simulation time 3999165332 ps
CPU time 224.38 seconds
Started Jan 24 10:07:14 PM PST 24
Finished Jan 24 10:11:06 PM PST 24
Peak memory 1200612 kb
Host smart-e8cf9260-f04b-429d-ba9b-7ea7230aa5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910818880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.910818880
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.360951867
Short name T889
Test name
Test status
Simulation time 620259539 ps
CPU time 1.01 seconds
Started Jan 24 10:07:18 PM PST 24
Finished Jan 24 10:07:23 PM PST 24
Peak memory 202180 kb
Host smart-d42ef62c-1018-49e5-8018-8a77f4bad412
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360951867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.360951867
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1870645312
Short name T708
Test name
Test status
Simulation time 332354297 ps
CPU time 10.65 seconds
Started Jan 24 10:07:15 PM PST 24
Finished Jan 24 10:07:32 PM PST 24
Peak memory 233560 kb
Host smart-c2b928eb-6867-419f-b11a-047aa6e844dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870645312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1870645312
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1927112657
Short name T1014
Test name
Test status
Simulation time 19269925578 ps
CPU time 554.45 seconds
Started Jan 24 10:07:15 PM PST 24
Finished Jan 24 10:16:36 PM PST 24
Peak memory 1404936 kb
Host smart-d85ac699-9be3-4be4-ae2a-3531cb2dbb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927112657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1927112657
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2551909306
Short name T712
Test name
Test status
Simulation time 15752048489 ps
CPU time 91.68 seconds
Started Jan 24 10:08:01 PM PST 24
Finished Jan 24 10:09:34 PM PST 24
Peak memory 329688 kb
Host smart-5b621bdd-a8b9-430d-ae0e-ad14506c9d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551909306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2551909306
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.1411790107
Short name T701
Test name
Test status
Simulation time 16660006 ps
CPU time 0.62 seconds
Started Jan 24 10:07:15 PM PST 24
Finished Jan 24 10:07:22 PM PST 24
Peak memory 201448 kb
Host smart-c96f2622-dc34-4348-bbdb-b0108a7037cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411790107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1411790107
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3192265899
Short name T149
Test name
Test status
Simulation time 2955259432 ps
CPU time 26.61 seconds
Started Jan 24 10:07:39 PM PST 24
Finished Jan 24 10:08:07 PM PST 24
Peak memory 227092 kb
Host smart-2ec965e9-dc2a-46f1-9925-623410280303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192265899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3192265899
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_rx_oversample.710558702
Short name T1381
Test name
Test status
Simulation time 1550575671 ps
CPU time 58.4 seconds
Started Jan 24 10:07:16 PM PST 24
Finished Jan 24 10:08:20 PM PST 24
Peak memory 292192 kb
Host smart-e8866b64-c506-4615-b16a-aef5f700b0ea
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710558702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_rx_oversample.
710558702
Directory /workspace/17.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.158057015
Short name T288
Test name
Test status
Simulation time 1942648304 ps
CPU time 109.83 seconds
Started Jan 24 10:07:18 PM PST 24
Finished Jan 24 10:09:12 PM PST 24
Peak memory 249692 kb
Host smart-aa5e55b2-81d6-4eca-a5f3-13b435dca2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158057015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.158057015
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.3965292445
Short name T551
Test name
Test status
Simulation time 1156580788 ps
CPU time 26.82 seconds
Started Jan 24 10:07:37 PM PST 24
Finished Jan 24 10:08:05 PM PST 24
Peak memory 210728 kb
Host smart-a344574d-4736-4fb1-afde-9c2c8601814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965292445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3965292445
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1341237111
Short name T1226
Test name
Test status
Simulation time 949459860 ps
CPU time 3.97 seconds
Started Jan 24 10:07:57 PM PST 24
Finished Jan 24 10:08:02 PM PST 24
Peak memory 202628 kb
Host smart-b5dcbea1-2abc-4ee8-bc8d-275f8d63e525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341237111 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1341237111
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.761877365
Short name T1365
Test name
Test status
Simulation time 10116275489 ps
CPU time 71.3 seconds
Started Jan 24 10:07:40 PM PST 24
Finished Jan 24 10:08:53 PM PST 24
Peak memory 508404 kb
Host smart-78fea480-d30f-4028-8752-dc9840a90e9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761877365 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.761877365
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3236896769
Short name T868
Test name
Test status
Simulation time 11006045764 ps
CPU time 11.61 seconds
Started Jan 24 10:07:38 PM PST 24
Finished Jan 24 10:07:50 PM PST 24
Peak memory 303300 kb
Host smart-32a0c0b1-e6be-4b7d-92ac-d32fece7f769
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236896769 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3236896769
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1441396276
Short name T875
Test name
Test status
Simulation time 758109633 ps
CPU time 3.41 seconds
Started Jan 24 10:07:57 PM PST 24
Finished Jan 24 10:08:01 PM PST 24
Peak memory 202644 kb
Host smart-8cd95db0-823f-481e-83bb-cd6a8cf1acf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441396276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1441396276
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3802300062
Short name T1222
Test name
Test status
Simulation time 2520730598 ps
CPU time 4.52 seconds
Started Jan 24 10:07:38 PM PST 24
Finished Jan 24 10:07:44 PM PST 24
Peak memory 205268 kb
Host smart-0a79370c-41fb-45db-93fb-376869e14d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802300062 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3802300062
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.54196450
Short name T1167
Test name
Test status
Simulation time 8408332082 ps
CPU time 48.41 seconds
Started Jan 24 10:07:38 PM PST 24
Finished Jan 24 10:08:28 PM PST 24
Peak memory 984240 kb
Host smart-305223f2-7c9d-4c24-9df7-a8d2225f6de5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54196450 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.54196450
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.2975423024
Short name T463
Test name
Test status
Simulation time 3011069510 ps
CPU time 4.42 seconds
Started Jan 24 10:07:56 PM PST 24
Finished Jan 24 10:08:01 PM PST 24
Peak memory 205468 kb
Host smart-54f858f1-8d06-4445-9ec3-cf0dc3fb13cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975423024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.2975423024
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.4179800418
Short name T1308
Test name
Test status
Simulation time 5395714385 ps
CPU time 15.55 seconds
Started Jan 24 10:07:37 PM PST 24
Finished Jan 24 10:07:54 PM PST 24
Peak memory 202648 kb
Host smart-459bddfc-2e49-4636-af71-4d9e7189e8e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179800418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.4179800418
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.3478604154
Short name T170
Test name
Test status
Simulation time 18957384342 ps
CPU time 53.64 seconds
Started Jan 24 10:07:56 PM PST 24
Finished Jan 24 10:08:51 PM PST 24
Peak memory 249152 kb
Host smart-dea149c9-1244-4c2a-8e80-7aa870040d47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478604154 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.3478604154
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.728541503
Short name T460
Test name
Test status
Simulation time 3598263462 ps
CPU time 12.15 seconds
Started Jan 24 10:07:36 PM PST 24
Finished Jan 24 10:07:49 PM PST 24
Peak memory 211108 kb
Host smart-47d136be-e28f-4128-8e52-f616fc0182cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728541503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.728541503
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.918300230
Short name T157
Test name
Test status
Simulation time 33349736073 ps
CPU time 305.72 seconds
Started Jan 24 10:07:41 PM PST 24
Finished Jan 24 10:12:48 PM PST 24
Peak memory 2783864 kb
Host smart-6fb5f6f2-946b-4db9-b376-1f4e58016727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918300230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_wr.918300230
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1559086711
Short name T65
Test name
Test status
Simulation time 30577711910 ps
CPU time 509.99 seconds
Started Jan 24 10:07:35 PM PST 24
Finished Jan 24 10:16:06 PM PST 24
Peak memory 1545936 kb
Host smart-046d1ea2-3407-4bdd-bb73-3b9c65e85a81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559086711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1559086711
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.478119894
Short name T934
Test name
Test status
Simulation time 1387093500 ps
CPU time 6.19 seconds
Started Jan 24 10:07:39 PM PST 24
Finished Jan 24 10:07:47 PM PST 24
Peak memory 207124 kb
Host smart-5bb91a68-c982-441b-a76b-2c999e5fd68f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478119894 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.478119894
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_ovf.4149131169
Short name T845
Test name
Test status
Simulation time 3132094556 ps
CPU time 191.72 seconds
Started Jan 24 10:07:41 PM PST 24
Finished Jan 24 10:10:54 PM PST 24
Peak memory 484592 kb
Host smart-88db2334-2e88-4204-a980-9851d0254eb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149131169 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_tx_ovf.4149131169
Directory /workspace/17.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.1250839447
Short name T786
Test name
Test status
Simulation time 5574226861 ps
CPU time 6.6 seconds
Started Jan 24 10:07:41 PM PST 24
Finished Jan 24 10:07:49 PM PST 24
Peak memory 202676 kb
Host smart-1ac42ea1-ab06-4bab-ba6b-34582da77d96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250839447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.i2c_target_unexp_stop.1250839447
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_alert_test.188366376
Short name T546
Test name
Test status
Simulation time 18071139 ps
CPU time 0.62 seconds
Started Jan 24 10:08:55 PM PST 24
Finished Jan 24 10:08:57 PM PST 24
Peak memory 202032 kb
Host smart-87d8d8ef-02d5-4b2f-a542-7985b238fb31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188366376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.188366376
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2770203963
Short name T977
Test name
Test status
Simulation time 30418023 ps
CPU time 1.35 seconds
Started Jan 24 11:38:07 PM PST 24
Finished Jan 24 11:38:12 PM PST 24
Peak memory 210732 kb
Host smart-49e9438a-2506-4f25-9abe-71ec4006694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770203963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2770203963
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2308821032
Short name T379
Test name
Test status
Simulation time 739004331 ps
CPU time 9.7 seconds
Started Jan 24 10:08:14 PM PST 24
Finished Jan 24 10:08:26 PM PST 24
Peak memory 236680 kb
Host smart-1864f49c-4a50-4e22-867a-6d39eeec7e9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308821032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2308821032
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3226531596
Short name T979
Test name
Test status
Simulation time 12889376391 ps
CPU time 275.28 seconds
Started Jan 24 10:08:14 PM PST 24
Finished Jan 24 10:12:50 PM PST 24
Peak memory 973656 kb
Host smart-9fe237f7-349b-48ab-93dd-d0539e2044bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226531596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3226531596
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3360819329
Short name T1189
Test name
Test status
Simulation time 68343971387 ps
CPU time 461.43 seconds
Started Jan 24 10:07:58 PM PST 24
Finished Jan 24 10:15:40 PM PST 24
Peak memory 1770052 kb
Host smart-df34614c-ffb9-431a-ad43-407a2f3a5985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360819329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3360819329
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3929272014
Short name T834
Test name
Test status
Simulation time 240313346 ps
CPU time 0.95 seconds
Started Jan 25 12:03:31 AM PST 24
Finished Jan 25 12:03:33 AM PST 24
Peak memory 202372 kb
Host smart-bf76a13d-3e57-4a76-8f83-e403dfb3521e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929272014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3929272014
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3708340125
Short name T1255
Test name
Test status
Simulation time 993538051 ps
CPU time 4.07 seconds
Started Jan 25 12:09:40 AM PST 24
Finished Jan 25 12:09:45 AM PST 24
Peak memory 202572 kb
Host smart-c9761203-6176-406d-9f56-819f19f0b7a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708340125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3708340125
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3832332377
Short name T1471
Test name
Test status
Simulation time 25991776025 ps
CPU time 383.62 seconds
Started Jan 25 03:37:24 AM PST 24
Finished Jan 25 03:43:49 AM PST 24
Peak memory 1662456 kb
Host smart-f9c846db-1b60-41d0-b5cf-fcab90780e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832332377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3832332377
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1573171347
Short name T641
Test name
Test status
Simulation time 2001324441 ps
CPU time 50.75 seconds
Started Jan 24 10:48:47 PM PST 24
Finished Jan 24 10:49:38 PM PST 24
Peak memory 267016 kb
Host smart-d2c519e4-c32d-4d13-af3e-4d69d0889775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573171347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1573171347
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.3535026251
Short name T1247
Test name
Test status
Simulation time 46767998 ps
CPU time 0.63 seconds
Started Jan 24 11:56:28 PM PST 24
Finished Jan 24 11:56:30 PM PST 24
Peak memory 201496 kb
Host smart-8afb6946-491d-4f9d-9059-4ebda2892850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535026251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3535026251
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.149893274
Short name T803
Test name
Test status
Simulation time 29224996454 ps
CPU time 373.69 seconds
Started Jan 24 10:08:14 PM PST 24
Finished Jan 24 10:14:29 PM PST 24
Peak memory 202572 kb
Host smart-326ee957-1f09-407b-b26f-8a4f46f552ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149893274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.149893274
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_rx_oversample.1398216902
Short name T1232
Test name
Test status
Simulation time 4509826218 ps
CPU time 62.86 seconds
Started Jan 24 11:12:20 PM PST 24
Finished Jan 24 11:13:24 PM PST 24
Peak memory 265164 kb
Host smart-a6ff19b9-06bc-4b31-b5b2-ab52da7fac29
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398216902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_rx_oversample
.1398216902
Directory /workspace/18.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1287179906
Short name T926
Test name
Test status
Simulation time 2539918380 ps
CPU time 152.98 seconds
Started Jan 24 11:26:09 PM PST 24
Finished Jan 24 11:28:44 PM PST 24
Peak memory 246172 kb
Host smart-783e9fd0-713b-484f-aa92-fbc53e331577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287179906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1287179906
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.118342127
Short name T380
Test name
Test status
Simulation time 484346281 ps
CPU time 19.85 seconds
Started Jan 24 10:08:12 PM PST 24
Finished Jan 24 10:08:33 PM PST 24
Peak memory 210732 kb
Host smart-b932e526-64c7-49df-aa83-f3101dd38106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118342127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.118342127
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.1006940569
Short name T1131
Test name
Test status
Simulation time 4900471134 ps
CPU time 3.4 seconds
Started Jan 24 11:04:37 PM PST 24
Finished Jan 24 11:04:45 PM PST 24
Peak memory 202668 kb
Host smart-2eeb84b6-d2b7-4169-8e91-497bcdb8d23a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006940569 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.1006940569
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.4189921806
Short name T256
Test name
Test status
Simulation time 10118165352 ps
CPU time 11.71 seconds
Started Jan 24 10:08:31 PM PST 24
Finished Jan 24 10:08:44 PM PST 24
Peak memory 264492 kb
Host smart-81d658d3-2bcf-4708-9bc6-8aeb91bec15d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189921806 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.4189921806
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2980561572
Short name T572
Test name
Test status
Simulation time 11491559827 ps
CPU time 4.25 seconds
Started Jan 24 10:08:32 PM PST 24
Finished Jan 24 10:08:38 PM PST 24
Peak memory 235696 kb
Host smart-75216f92-2611-44e0-bd19-6ba9f18aeaaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980561572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2980561572
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.2278514231
Short name T195
Test name
Test status
Simulation time 810980796 ps
CPU time 3.48 seconds
Started Jan 24 10:08:33 PM PST 24
Finished Jan 24 10:08:38 PM PST 24
Peak memory 202596 kb
Host smart-86d07d70-8644-449e-ab8c-75b3adfaf356
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278514231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.2278514231
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1443321291
Short name T237
Test name
Test status
Simulation time 27312151097 ps
CPU time 6.75 seconds
Started Jan 25 12:16:41 AM PST 24
Finished Jan 25 12:16:50 AM PST 24
Peak memory 206180 kb
Host smart-4fa7754f-5a68-41ba-a0cc-4caad99bff00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443321291 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1443321291
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3814242844
Short name T433
Test name
Test status
Simulation time 23633421116 ps
CPU time 157.33 seconds
Started Jan 24 10:08:31 PM PST 24
Finished Jan 24 10:11:09 PM PST 24
Peak memory 1297768 kb
Host smart-79974599-ed6b-4a5c-aea5-f9261b7cfd64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814242844 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3814242844
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.2532651384
Short name T307
Test name
Test status
Simulation time 3578352445 ps
CPU time 5.27 seconds
Started Jan 24 10:42:56 PM PST 24
Finished Jan 24 10:43:02 PM PST 24
Peak memory 212280 kb
Host smart-6f6205a4-a31e-49df-9951-e5dc535763ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532651384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.2532651384
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3205722857
Short name T735
Test name
Test status
Simulation time 20446229552 ps
CPU time 14.44 seconds
Started Jan 24 10:08:15 PM PST 24
Finished Jan 24 10:08:31 PM PST 24
Peak memory 202652 kb
Host smart-c015f0b0-0c24-4f0b-a5b9-95d62db014d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205722857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3205722857
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.911114020
Short name T1241
Test name
Test status
Simulation time 50676530228 ps
CPU time 602.03 seconds
Started Jan 24 10:08:34 PM PST 24
Finished Jan 24 10:18:37 PM PST 24
Peak memory 604200 kb
Host smart-dcc44671-d509-43ad-84ea-a127f08f5035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911114020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.i2c_target_stress_all.911114020
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3344224340
Short name T726
Test name
Test status
Simulation time 12775448701 ps
CPU time 89.88 seconds
Started Jan 24 10:08:30 PM PST 24
Finished Jan 24 10:10:02 PM PST 24
Peak memory 204312 kb
Host smart-1c7f518b-5854-46e0-a8e6-cf82c592bbdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344224340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3344224340
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.165488633
Short name T1262
Test name
Test status
Simulation time 13536888222 ps
CPU time 29.65 seconds
Started Jan 24 10:08:12 PM PST 24
Finished Jan 24 10:08:43 PM PST 24
Peak memory 731468 kb
Host smart-f7044484-f3ec-4a94-8c79-573722f46f35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165488633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.165488633
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1185818282
Short name T706
Test name
Test status
Simulation time 42559159593 ps
CPU time 124.88 seconds
Started Jan 25 12:19:23 AM PST 24
Finished Jan 25 12:21:29 AM PST 24
Peak memory 954304 kb
Host smart-32d755af-5c4d-4cdd-90e6-60af683f3f06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185818282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1185818282
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3509374006
Short name T1206
Test name
Test status
Simulation time 9750519117 ps
CPU time 8 seconds
Started Jan 24 10:25:58 PM PST 24
Finished Jan 24 10:26:07 PM PST 24
Peak memory 209604 kb
Host smart-b0165075-9d75-4a23-8643-232acc6d233f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509374006 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3509374006
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_ovf.507944091
Short name T784
Test name
Test status
Simulation time 10795834111 ps
CPU time 27.82 seconds
Started Jan 24 10:08:30 PM PST 24
Finished Jan 24 10:08:59 PM PST 24
Peak memory 205376 kb
Host smart-5d4ec7a3-668a-4649-bc86-693853f441d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507944091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_tx_ovf.507944091
Directory /workspace/18.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.77620282
Short name T924
Test name
Test status
Simulation time 3643714851 ps
CPU time 7.1 seconds
Started Jan 24 11:32:02 PM PST 24
Finished Jan 24 11:32:11 PM PST 24
Peak memory 209380 kb
Host smart-030f8b34-5151-4083-aae8-4316108ac20f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77620282 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_unexp_stop.77620282
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2724623411
Short name T360
Test name
Test status
Simulation time 18002828 ps
CPU time 0.61 seconds
Started Jan 24 10:09:42 PM PST 24
Finished Jan 24 10:09:43 PM PST 24
Peak memory 201176 kb
Host smart-b671ddce-ec45-4654-9e81-b5665d93cb39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724623411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2724623411
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.2418651400
Short name T1055
Test name
Test status
Simulation time 58950154 ps
CPU time 1.37 seconds
Started Jan 24 10:09:07 PM PST 24
Finished Jan 24 10:09:09 PM PST 24
Peak memory 210768 kb
Host smart-96aa6ff4-d5cc-4153-aecf-eca34813a4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418651400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2418651400
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1844896359
Short name T967
Test name
Test status
Simulation time 1962642752 ps
CPU time 9.95 seconds
Started Jan 24 10:08:55 PM PST 24
Finished Jan 24 10:09:06 PM PST 24
Peak memory 300364 kb
Host smart-1ac540f1-7849-4c31-8efe-176ea0e711ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844896359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1844896359
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2894692264
Short name T1049
Test name
Test status
Simulation time 3931275098 ps
CPU time 50.31 seconds
Started Jan 24 10:09:06 PM PST 24
Finished Jan 24 10:09:57 PM PST 24
Peak memory 510328 kb
Host smart-1f41c4be-2dd1-4bb5-85d1-48267b9bab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894692264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2894692264
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1048609424
Short name T1362
Test name
Test status
Simulation time 4008736114 ps
CPU time 463.34 seconds
Started Jan 24 10:08:55 PM PST 24
Finished Jan 24 10:16:40 PM PST 24
Peak memory 1171224 kb
Host smart-3d077cb9-b037-4cd5-9641-375c1bd7f61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048609424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1048609424
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2998117591
Short name T508
Test name
Test status
Simulation time 101315759 ps
CPU time 0.93 seconds
Started Jan 24 10:08:49 PM PST 24
Finished Jan 24 10:08:52 PM PST 24
Peak memory 202352 kb
Host smart-aa0f3c60-c1b3-41df-8a58-e32b0d97eca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998117591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2998117591
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3305231671
Short name T662
Test name
Test status
Simulation time 323123510 ps
CPU time 4.29 seconds
Started Jan 24 10:08:54 PM PST 24
Finished Jan 24 10:08:59 PM PST 24
Peak memory 202524 kb
Host smart-b84f843b-afc2-4a65-b100-4fd2d2e8fbfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305231671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3305231671
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3069028939
Short name T514
Test name
Test status
Simulation time 6692584775 ps
CPU time 368.88 seconds
Started Jan 24 10:08:48 PM PST 24
Finished Jan 24 10:14:59 PM PST 24
Peak memory 1818444 kb
Host smart-88f5eafb-0020-4dc7-9128-2f02d774fa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069028939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3069028939
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.1682286856
Short name T1157
Test name
Test status
Simulation time 9005927794 ps
CPU time 43.12 seconds
Started Jan 24 10:09:43 PM PST 24
Finished Jan 24 10:10:27 PM PST 24
Peak memory 256404 kb
Host smart-cfc503d9-126e-4f59-9faf-7a34232dfaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682286856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1682286856
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.449042641
Short name T5
Test name
Test status
Simulation time 16520840 ps
CPU time 0.63 seconds
Started Jan 24 10:08:56 PM PST 24
Finished Jan 24 10:08:57 PM PST 24
Peak memory 201560 kb
Host smart-ded360cb-0b98-4be6-849e-90d49225451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449042641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.449042641
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1301244183
Short name T1034
Test name
Test status
Simulation time 32670350027 ps
CPU time 608.3 seconds
Started Jan 24 10:09:05 PM PST 24
Finished Jan 24 10:19:14 PM PST 24
Peak memory 215220 kb
Host smart-c6978c61-f2bd-48e7-af47-793c3e84b8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301244183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1301244183
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_rx_oversample.3152528503
Short name T1180
Test name
Test status
Simulation time 1980965719 ps
CPU time 91.82 seconds
Started Jan 24 10:08:54 PM PST 24
Finished Jan 24 10:10:27 PM PST 24
Peak memory 295408 kb
Host smart-018f1be9-a3df-4121-abd9-a55d71ece1c4
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152528503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_rx_oversample
.3152528503
Directory /workspace/19.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2205206403
Short name T906
Test name
Test status
Simulation time 3123130185 ps
CPU time 60.44 seconds
Started Jan 24 10:08:53 PM PST 24
Finished Jan 24 10:09:55 PM PST 24
Peak memory 275632 kb
Host smart-43e76c3f-c4a9-4662-bc13-2a381ac64bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205206403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2205206403
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1919419759
Short name T939
Test name
Test status
Simulation time 1171518234 ps
CPU time 16.6 seconds
Started Jan 24 10:09:06 PM PST 24
Finished Jan 24 10:09:24 PM PST 24
Peak memory 226976 kb
Host smart-4d354f4b-94d3-4b47-8273-e5079112236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919419759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1919419759
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1534957564
Short name T1327
Test name
Test status
Simulation time 1110010223 ps
CPU time 2.53 seconds
Started Jan 24 10:09:21 PM PST 24
Finished Jan 24 10:09:25 PM PST 24
Peak memory 202648 kb
Host smart-c077a68e-316c-4b3a-bc85-92dde196064c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534957564 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1534957564
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1564440793
Short name T864
Test name
Test status
Simulation time 10541330558 ps
CPU time 13.89 seconds
Started Jan 24 10:09:23 PM PST 24
Finished Jan 24 10:09:38 PM PST 24
Peak memory 308828 kb
Host smart-9db0cea8-d3fa-4667-b30d-4e8688ee152d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564440793 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1564440793
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1971724911
Short name T1137
Test name
Test status
Simulation time 10312128331 ps
CPU time 13.12 seconds
Started Jan 24 11:21:37 PM PST 24
Finished Jan 24 11:21:51 PM PST 24
Peak memory 290184 kb
Host smart-edf23058-5773-4c0e-b092-6b3506969b72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971724911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1971724911
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1372511517
Short name T260
Test name
Test status
Simulation time 529475716 ps
CPU time 2.62 seconds
Started Jan 24 10:09:22 PM PST 24
Finished Jan 24 10:09:26 PM PST 24
Peak memory 202644 kb
Host smart-4e9a78d9-e76a-479c-aa0f-a8694806a470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372511517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1372511517
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.455653677
Short name T1121
Test name
Test status
Simulation time 2938747218 ps
CPU time 5.87 seconds
Started Jan 24 10:09:04 PM PST 24
Finished Jan 24 10:09:10 PM PST 24
Peak memory 202664 kb
Host smart-9b1a7a32-445d-46b0-a34e-1bac2b921b77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455653677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.455653677
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.1461169297
Short name T1371
Test name
Test status
Simulation time 15189815762 ps
CPU time 71.47 seconds
Started Jan 24 10:22:52 PM PST 24
Finished Jan 24 10:24:06 PM PST 24
Peak memory 949020 kb
Host smart-ca8649dc-e092-459c-bc29-ebbe3e09990e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461169297 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.1461169297
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.3072373503
Short name T1185
Test name
Test status
Simulation time 2074438762 ps
CPU time 3.32 seconds
Started Jan 24 11:36:31 PM PST 24
Finished Jan 24 11:36:37 PM PST 24
Peak memory 203512 kb
Host smart-de4c3b92-edb7-4de3-9ddf-e1740ce61223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072373503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.3072373503
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.2301407809
Short name T1246
Test name
Test status
Simulation time 1837117095 ps
CPU time 18.55 seconds
Started Jan 24 10:24:46 PM PST 24
Finished Jan 24 10:25:05 PM PST 24
Peak memory 202548 kb
Host smart-bd415d26-427e-4b17-9ada-e483b6798eac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301407809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.2301407809
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3058941850
Short name T983
Test name
Test status
Simulation time 2110649273 ps
CPU time 40.97 seconds
Started Jan 24 10:09:07 PM PST 24
Finished Jan 24 10:09:49 PM PST 24
Peak memory 202584 kb
Host smart-c3ede886-9764-40e7-b798-3a81cf0392ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058941850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3058941850
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.542066186
Short name T349
Test name
Test status
Simulation time 35417084199 ps
CPU time 1560.79 seconds
Started Jan 24 10:09:07 PM PST 24
Finished Jan 24 10:35:09 PM PST 24
Peak memory 7720676 kb
Host smart-6fddac86-8a62-41ce-b6fd-b128f8128ee1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542066186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_wr.542066186
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1694553076
Short name T219
Test name
Test status
Simulation time 49188993504 ps
CPU time 192.26 seconds
Started Jan 24 10:09:06 PM PST 24
Finished Jan 24 10:12:19 PM PST 24
Peak memory 635308 kb
Host smart-d8cd3aaa-6809-4f3c-8b5c-52bfaf2125ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694553076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1694553076
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3345579686
Short name T835
Test name
Test status
Simulation time 24892098855 ps
CPU time 7.36 seconds
Started Jan 24 10:09:23 PM PST 24
Finished Jan 24 10:09:31 PM PST 24
Peak memory 202724 kb
Host smart-052a46f5-2696-4bb4-b576-eb6437289065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345579686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3345579686
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_ovf.2343513752
Short name T608
Test name
Test status
Simulation time 23790443612 ps
CPU time 129.55 seconds
Started Jan 24 10:09:06 PM PST 24
Finished Jan 24 10:11:16 PM PST 24
Peak memory 378124 kb
Host smart-996a7563-dece-45bb-8835-afd32325bda5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343513752 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_tx_ovf.2343513752
Directory /workspace/19.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.683347818
Short name T385
Test name
Test status
Simulation time 1656763221 ps
CPU time 5.43 seconds
Started Jan 24 10:09:23 PM PST 24
Finished Jan 24 10:09:29 PM PST 24
Peak memory 202580 kb
Host smart-fc6d92c6-77a8-4645-a815-4d4af31bb769
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683347818 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_unexp_stop.683347818
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3997479033
Short name T896
Test name
Test status
Simulation time 39976326 ps
CPU time 0.62 seconds
Started Jan 24 09:56:03 PM PST 24
Finished Jan 24 09:56:05 PM PST 24
Peak memory 202004 kb
Host smart-cdc8be3a-414d-4362-b2e9-09c7e29e7bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997479033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3997479033
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1870049176
Short name T233
Test name
Test status
Simulation time 323375766 ps
CPU time 1.6 seconds
Started Jan 24 09:56:03 PM PST 24
Finished Jan 24 09:56:05 PM PST 24
Peak memory 218944 kb
Host smart-7c685079-a143-4a00-a3f2-2370511a6194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870049176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1870049176
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.3665860449
Short name T678
Test name
Test status
Simulation time 609881756 ps
CPU time 16.64 seconds
Started Jan 24 09:55:48 PM PST 24
Finished Jan 24 09:56:05 PM PST 24
Peak memory 265236 kb
Host smart-89bf1625-e261-42b2-ad01-afbdd4d92daf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665860449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.3665860449
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.780413085
Short name T866
Test name
Test status
Simulation time 2099598236 ps
CPU time 51.73 seconds
Started Jan 24 11:13:00 PM PST 24
Finished Jan 24 11:13:53 PM PST 24
Peak memory 460420 kb
Host smart-e9ecd9e4-8c67-425c-a649-f3e0a952b9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780413085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.780413085
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3133737005
Short name T1332
Test name
Test status
Simulation time 7492681129 ps
CPU time 420.88 seconds
Started Jan 24 10:21:49 PM PST 24
Finished Jan 24 10:28:54 PM PST 24
Peak memory 1934060 kb
Host smart-a9feaa6d-2b6d-452c-a298-a1620b390ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133737005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3133737005
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.4131024589
Short name T1256
Test name
Test status
Simulation time 460306079 ps
CPU time 0.97 seconds
Started Jan 24 09:56:03 PM PST 24
Finished Jan 24 09:56:05 PM PST 24
Peak memory 202316 kb
Host smart-af169a15-11f5-4268-a1d5-c463a56420b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131024589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.4131024589
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.685079379
Short name T1158
Test name
Test status
Simulation time 1013734352 ps
CPU time 14.77 seconds
Started Jan 24 09:55:55 PM PST 24
Finished Jan 24 09:56:11 PM PST 24
Peak memory 252704 kb
Host smart-fa912b27-2853-4e1b-ab45-04fb7ed59b74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685079379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.685079379
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.2617329265
Short name T544
Test name
Test status
Simulation time 4725625923 ps
CPU time 177 seconds
Started Jan 24 09:56:03 PM PST 24
Finished Jan 24 09:59:01 PM PST 24
Peak memory 1099112 kb
Host smart-596a00d0-8bcd-44f3-99af-405638099f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617329265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.2617329265
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.2468575814
Short name T780
Test name
Test status
Simulation time 11460677632 ps
CPU time 198.22 seconds
Started Jan 24 09:56:04 PM PST 24
Finished Jan 24 09:59:24 PM PST 24
Peak memory 411844 kb
Host smart-f4114974-0b6f-424e-a835-cd785b79ed9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468575814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.2468575814
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.3998491708
Short name T962
Test name
Test status
Simulation time 27422601 ps
CPU time 0.63 seconds
Started Jan 24 09:55:56 PM PST 24
Finished Jan 24 09:55:57 PM PST 24
Peak memory 201508 kb
Host smart-84f774e7-78d1-4e4d-97c4-976a66ea0256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998491708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3998491708
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2538542989
Short name T148
Test name
Test status
Simulation time 6871437961 ps
CPU time 313.5 seconds
Started Jan 24 10:20:39 PM PST 24
Finished Jan 24 10:25:54 PM PST 24
Peak memory 210776 kb
Host smart-4e2f194d-787d-43cf-9478-254850685663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538542989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2538542989
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_rx_oversample.4145575879
Short name T484
Test name
Test status
Simulation time 5428212000 ps
CPU time 318.28 seconds
Started Jan 24 09:55:45 PM PST 24
Finished Jan 24 10:01:05 PM PST 24
Peak memory 321640 kb
Host smart-62f743b3-0246-4360-abf9-d634fcd5a66c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145575879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_rx_oversample.
4145575879
Directory /workspace/2.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2782940896
Short name T455
Test name
Test status
Simulation time 7355717850 ps
CPU time 46.76 seconds
Started Jan 24 11:45:50 PM PST 24
Finished Jan 24 11:46:38 PM PST 24
Peak memory 283892 kb
Host smart-5f88cbbf-4673-4289-9427-37d2c2d3c576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782940896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2782940896
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.1968474423
Short name T1001
Test name
Test status
Simulation time 10305521418 ps
CPU time 656.04 seconds
Started Jan 24 09:56:02 PM PST 24
Finished Jan 24 10:06:59 PM PST 24
Peak memory 1062040 kb
Host smart-c52abd8f-8596-4308-b8eb-494070db1db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968474423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.1968474423
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.912168675
Short name T1425
Test name
Test status
Simulation time 740961690 ps
CPU time 32.28 seconds
Started Jan 24 10:07:00 PM PST 24
Finished Jan 24 10:07:34 PM PST 24
Peak memory 210752 kb
Host smart-07206e32-966a-4b7e-a9b6-c79f42f588eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912168675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.912168675
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2667903865
Short name T94
Test name
Test status
Simulation time 122350932 ps
CPU time 0.95 seconds
Started Jan 24 09:56:03 PM PST 24
Finished Jan 24 09:56:05 PM PST 24
Peak memory 219468 kb
Host smart-f7003251-0268-4ba3-84a3-0e6055c350d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667903865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2667903865
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.3553951839
Short name T613
Test name
Test status
Simulation time 938349165 ps
CPU time 4.14 seconds
Started Jan 24 09:56:03 PM PST 24
Finished Jan 24 09:56:08 PM PST 24
Peak memory 202548 kb
Host smart-3884d3ea-47f6-4f68-8528-8612ca6a8647
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553951839 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3553951839
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2488485166
Short name T1191
Test name
Test status
Simulation time 10220323534 ps
CPU time 11.44 seconds
Started Jan 24 11:27:37 PM PST 24
Finished Jan 24 11:27:50 PM PST 24
Peak memory 266656 kb
Host smart-bb95a04b-7907-47db-ad91-767adfac0eeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488485166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2488485166
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3671574998
Short name T1444
Test name
Test status
Simulation time 10058029805 ps
CPU time 71.87 seconds
Started Jan 24 09:56:03 PM PST 24
Finished Jan 24 09:57:16 PM PST 24
Peak memory 602776 kb
Host smart-49880d56-e254-446c-afc7-8dfa8227b1f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671574998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3671574998
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.1262910345
Short name T1096
Test name
Test status
Simulation time 555621770 ps
CPU time 2.77 seconds
Started Jan 24 09:56:05 PM PST 24
Finished Jan 24 09:56:09 PM PST 24
Peak memory 202600 kb
Host smart-0a585fe5-0bbe-45af-b3c4-0338c8c41686
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262910345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.1262910345
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.3731284450
Short name T856
Test name
Test status
Simulation time 2738095529 ps
CPU time 3.99 seconds
Started Jan 24 10:33:08 PM PST 24
Finished Jan 24 10:33:13 PM PST 24
Peak memory 202676 kb
Host smart-87586853-0669-4ff3-a4a9-14ab2174949f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731284450 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.3731284450
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.394616902
Short name T953
Test name
Test status
Simulation time 6019550106 ps
CPU time 2.76 seconds
Started Jan 24 09:56:02 PM PST 24
Finished Jan 24 09:56:05 PM PST 24
Peak memory 204464 kb
Host smart-068c0f52-f34e-4f01-a38b-5a1372f19dac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394616902 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.394616902
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.3573064818
Short name T249
Test name
Test status
Simulation time 1262774618 ps
CPU time 2.25 seconds
Started Jan 24 09:56:02 PM PST 24
Finished Jan 24 09:56:05 PM PST 24
Peak memory 202564 kb
Host smart-14489264-2e50-4e85-8d0e-3a36e9ddb7a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573064818 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.3573064818
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1105438579
Short name T510
Test name
Test status
Simulation time 1772906298 ps
CPU time 48 seconds
Started Jan 24 09:55:54 PM PST 24
Finished Jan 24 09:56:43 PM PST 24
Peak memory 202548 kb
Host smart-91b7b0b2-a99a-4334-8c05-ed7be3ba82fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105438579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1105438579
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.3091500275
Short name T759
Test name
Test status
Simulation time 13676659359 ps
CPU time 825 seconds
Started Jan 24 09:56:02 PM PST 24
Finished Jan 24 10:09:48 PM PST 24
Peak memory 532264 kb
Host smart-f10f4583-baf1-4e3f-940c-fbf3d6c9e9bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091500275 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.3091500275
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3985631312
Short name T218
Test name
Test status
Simulation time 3116494831 ps
CPU time 12.07 seconds
Started Jan 24 09:56:03 PM PST 24
Finished Jan 24 09:56:16 PM PST 24
Peak memory 207988 kb
Host smart-e1f642c9-4160-497a-9d28-599d21edbf9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985631312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3985631312
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1971225839
Short name T1015
Test name
Test status
Simulation time 10745154042 ps
CPU time 31.81 seconds
Started Jan 24 09:56:02 PM PST 24
Finished Jan 24 09:56:34 PM PST 24
Peak memory 826780 kb
Host smart-2ea122a7-2a72-4e19-8082-7d9a5a07d488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971225839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1971225839
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.875633870
Short name T59
Test name
Test status
Simulation time 27396260346 ps
CPU time 684.4 seconds
Started Jan 24 09:56:02 PM PST 24
Finished Jan 24 10:07:27 PM PST 24
Peak memory 2809624 kb
Host smart-5e983de5-550f-4569-954c-67f5eef67d3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875633870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.875633870
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.4088133105
Short name T1140
Test name
Test status
Simulation time 1771392715 ps
CPU time 8.05 seconds
Started Jan 25 12:19:24 AM PST 24
Finished Jan 25 12:19:33 AM PST 24
Peak memory 211560 kb
Host smart-47f746b1-2e17-4f52-bfeb-0ea5bcec5063
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088133105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.4088133105
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_ovf.119172570
Short name T1276
Test name
Test status
Simulation time 6632954453 ps
CPU time 51.59 seconds
Started Jan 24 09:56:03 PM PST 24
Finished Jan 24 09:56:55 PM PST 24
Peak memory 219332 kb
Host smart-1746509e-415f-4287-8982-9a15840f64d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119172570 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_tx_ovf.119172570
Directory /workspace/2.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.1940970671
Short name T703
Test name
Test status
Simulation time 10088089357 ps
CPU time 8.25 seconds
Started Jan 24 10:02:24 PM PST 24
Finished Jan 24 10:02:34 PM PST 24
Peak memory 202660 kb
Host smart-c6f655f3-a05d-483a-9328-28c93d7b10ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940970671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.i2c_target_unexp_stop.1940970671
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.2954993350
Short name T1465
Test name
Test status
Simulation time 19338949 ps
CPU time 0.62 seconds
Started Jan 24 10:10:48 PM PST 24
Finished Jan 24 10:10:52 PM PST 24
Peak memory 201088 kb
Host smart-5a9b0d2c-f8bf-4157-b200-ea0310c59ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954993350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2954993350
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.1323868034
Short name T1319
Test name
Test status
Simulation time 183173092 ps
CPU time 1.4 seconds
Started Jan 24 10:10:10 PM PST 24
Finished Jan 24 10:10:16 PM PST 24
Peak memory 210764 kb
Host smart-ea132576-973c-489f-b66b-664b60be3309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323868034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.1323868034
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.93638317
Short name T512
Test name
Test status
Simulation time 1970606307 ps
CPU time 7.18 seconds
Started Jan 24 10:10:11 PM PST 24
Finished Jan 24 10:10:21 PM PST 24
Peak memory 261720 kb
Host smart-9514939e-dc00-4edd-a1ae-648918f3dd05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93638317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty
.93638317
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1984449549
Short name T1050
Test name
Test status
Simulation time 3212493425 ps
CPU time 76.37 seconds
Started Jan 24 10:10:11 PM PST 24
Finished Jan 24 10:11:31 PM PST 24
Peak memory 755132 kb
Host smart-15bbe977-9626-4f4c-bf7f-68dd801bacc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984449549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1984449549
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.779257107
Short name T446
Test name
Test status
Simulation time 16265946394 ps
CPU time 345.75 seconds
Started Jan 24 10:09:44 PM PST 24
Finished Jan 24 10:15:31 PM PST 24
Peak memory 1045200 kb
Host smart-e0d9d32f-48d8-41e0-8634-a22b69afc202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779257107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.779257107
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2701564676
Short name T1343
Test name
Test status
Simulation time 340963661 ps
CPU time 0.87 seconds
Started Jan 24 10:10:11 PM PST 24
Finished Jan 24 10:10:15 PM PST 24
Peak memory 202356 kb
Host smart-919f674e-f987-44e5-ae0e-d58418f9771f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701564676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2701564676
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2154168358
Short name T99
Test name
Test status
Simulation time 943487751 ps
CPU time 12.31 seconds
Started Jan 24 10:10:10 PM PST 24
Finished Jan 24 10:10:26 PM PST 24
Peak memory 202564 kb
Host smart-7495d813-9a6b-4ee3-b583-3c7ace4e1cf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154168358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2154168358
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1945090887
Short name T1181
Test name
Test status
Simulation time 8730162239 ps
CPU time 218.24 seconds
Started Jan 24 10:09:44 PM PST 24
Finished Jan 24 10:13:23 PM PST 24
Peak memory 1241476 kb
Host smart-0fbccef7-d63f-47dd-b61e-1f090dd73e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945090887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1945090887
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.4294539299
Short name T1390
Test name
Test status
Simulation time 2693751665 ps
CPU time 158.61 seconds
Started Jan 24 10:10:49 PM PST 24
Finished Jan 24 10:13:30 PM PST 24
Peak memory 260472 kb
Host smart-e477d7f6-a759-4e42-bd56-181920b38032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294539299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.4294539299
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.3391860781
Short name T1212
Test name
Test status
Simulation time 47706962 ps
CPU time 0.61 seconds
Started Jan 24 10:09:42 PM PST 24
Finished Jan 24 10:09:44 PM PST 24
Peak memory 201476 kb
Host smart-4a2db179-6d60-44e4-9920-f060d412fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391860781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3391860781
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1670137004
Short name T1024
Test name
Test status
Simulation time 48108026072 ps
CPU time 842.65 seconds
Started Jan 24 10:10:10 PM PST 24
Finished Jan 24 10:24:17 PM PST 24
Peak memory 202532 kb
Host smart-2b5ae7d5-3fbc-43e2-bf03-04026c93104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670137004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1670137004
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_rx_oversample.96682887
Short name T915
Test name
Test status
Simulation time 6296356684 ps
CPU time 153.68 seconds
Started Jan 24 10:09:43 PM PST 24
Finished Jan 24 10:12:17 PM PST 24
Peak memory 368180 kb
Host smart-043fd1ba-ba10-4d4c-8784-e90d2b1da805
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96682887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_rx_oversample.96682887
Directory /workspace/20.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.4150727043
Short name T925
Test name
Test status
Simulation time 1151142607 ps
CPU time 21.12 seconds
Started Jan 24 10:09:43 PM PST 24
Finished Jan 24 10:10:05 PM PST 24
Peak memory 243244 kb
Host smart-811221ce-5094-4ae0-bd41-4e1d1945bdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150727043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.4150727043
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3897796745
Short name T189
Test name
Test status
Simulation time 165810595915 ps
CPU time 3142.72 seconds
Started Jan 24 10:10:10 PM PST 24
Finished Jan 24 11:02:37 PM PST 24
Peak memory 4260364 kb
Host smart-76d8d438-17a8-44d1-87b1-20cbeee44fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897796745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3897796745
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.1361747550
Short name T1105
Test name
Test status
Simulation time 462477398 ps
CPU time 21.66 seconds
Started Jan 24 10:10:08 PM PST 24
Finished Jan 24 10:10:35 PM PST 24
Peak memory 210720 kb
Host smart-e2b9d097-8772-451b-b178-dc37a7960fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361747550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1361747550
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.1508594673
Short name T968
Test name
Test status
Simulation time 558880219 ps
CPU time 2.69 seconds
Started Jan 24 10:10:45 PM PST 24
Finished Jan 24 10:10:52 PM PST 24
Peak memory 202588 kb
Host smart-dfc82ba2-6a6e-4a48-ac70-b2e8d0fa8cf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508594673 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1508594673
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1274930720
Short name T366
Test name
Test status
Simulation time 10369813102 ps
CPU time 13.23 seconds
Started Jan 24 10:10:24 PM PST 24
Finished Jan 24 10:10:40 PM PST 24
Peak memory 267944 kb
Host smart-2a66cc25-5cd1-4991-90af-d82088b29447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274930720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1274930720
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2057910495
Short name T831
Test name
Test status
Simulation time 10053680941 ps
CPU time 65.67 seconds
Started Jan 24 10:10:21 PM PST 24
Finished Jan 24 10:11:32 PM PST 24
Peak memory 665420 kb
Host smart-d4ea160f-df76-4104-abc2-5975d3215ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057910495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2057910495
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1734453915
Short name T293
Test name
Test status
Simulation time 527923920 ps
CPU time 2.75 seconds
Started Jan 24 10:10:49 PM PST 24
Finished Jan 24 10:10:54 PM PST 24
Peak memory 202660 kb
Host smart-a66e38db-6e81-43bd-a8a5-3eba6a0552aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734453915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1734453915
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.4157181002
Short name T479
Test name
Test status
Simulation time 777631778 ps
CPU time 4.11 seconds
Started Jan 24 10:10:23 PM PST 24
Finished Jan 24 10:10:31 PM PST 24
Peak memory 204416 kb
Host smart-98c07927-f8bb-4ec1-b532-8bfa31fddd97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157181002 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.4157181002
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.4247823971
Short name T596
Test name
Test status
Simulation time 14899965193 ps
CPU time 209.67 seconds
Started Jan 24 10:10:27 PM PST 24
Finished Jan 24 10:14:01 PM PST 24
Peak memory 2364628 kb
Host smart-9d21ccca-2987-4047-9602-515620d88d41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247823971 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.4247823971
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_perf.3245132876
Short name T884
Test name
Test status
Simulation time 690267940 ps
CPU time 4.07 seconds
Started Jan 24 10:10:23 PM PST 24
Finished Jan 24 10:10:31 PM PST 24
Peak memory 202628 kb
Host smart-cdf677a5-155b-4076-be9e-29cdcc66a1ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245132876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.3245132876
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.418494703
Short name T96
Test name
Test status
Simulation time 1761494099 ps
CPU time 39.53 seconds
Started Jan 24 10:10:10 PM PST 24
Finished Jan 24 10:10:54 PM PST 24
Peak memory 202600 kb
Host smart-feb0ab17-8b5e-4f13-abb7-fa2ab140ba54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418494703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.418494703
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.1617187200
Short name T1103
Test name
Test status
Simulation time 20160377112 ps
CPU time 36.55 seconds
Started Jan 24 10:10:45 PM PST 24
Finished Jan 24 10:11:27 PM PST 24
Peak memory 221916 kb
Host smart-ddf2491c-1c3a-4b2d-b66e-f80ac532d990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617187200 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.1617187200
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.887524985
Short name T1152
Test name
Test status
Simulation time 1758271286 ps
CPU time 34.71 seconds
Started Jan 24 10:10:22 PM PST 24
Finished Jan 24 10:11:01 PM PST 24
Peak memory 202592 kb
Host smart-200495cd-60de-4369-94cc-7f701eaa7939
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887524985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_rd.887524985
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3545300686
Short name T1310
Test name
Test status
Simulation time 25287565693 ps
CPU time 867.35 seconds
Started Jan 24 10:10:22 PM PST 24
Finished Jan 24 10:24:54 PM PST 24
Peak memory 5361320 kb
Host smart-7819b187-75e7-4a82-877c-f256d949d6e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545300686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3545300686
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3951370968
Short name T1448
Test name
Test status
Simulation time 33166830679 ps
CPU time 265.51 seconds
Started Jan 24 10:10:27 PM PST 24
Finished Jan 24 10:14:57 PM PST 24
Peak memory 1813068 kb
Host smart-5cb8a868-5f23-4e8a-8604-57e9b5e29b04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951370968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3951370968
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2120674157
Short name T416
Test name
Test status
Simulation time 7066583259 ps
CPU time 7.64 seconds
Started Jan 24 10:10:26 PM PST 24
Finished Jan 24 10:10:39 PM PST 24
Peak memory 205652 kb
Host smart-1786919b-27a1-4cdf-a047-b74bc57f271d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120674157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2120674157
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_ovf.1174178607
Short name T1
Test name
Test status
Simulation time 9557609504 ps
CPU time 45.56 seconds
Started Jan 24 10:10:22 PM PST 24
Finished Jan 24 10:11:12 PM PST 24
Peak memory 225652 kb
Host smart-2548e364-c147-4d96-a72e-53bf85930e73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174178607 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_tx_ovf.1174178607
Directory /workspace/20.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.1191364625
Short name T518
Test name
Test status
Simulation time 1477982163 ps
CPU time 6.77 seconds
Started Jan 24 10:10:23 PM PST 24
Finished Jan 24 10:10:33 PM PST 24
Peak memory 207128 kb
Host smart-a8826fee-24fd-4e23-8ef0-71a8979f378b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191364625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.1191364625
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1365070432
Short name T760
Test name
Test status
Simulation time 18897693 ps
CPU time 0.68 seconds
Started Jan 25 01:32:41 AM PST 24
Finished Jan 25 01:32:49 AM PST 24
Peak memory 201160 kb
Host smart-422f64d5-bde9-45f0-bd66-05a29af0d7ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365070432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1365070432
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2068622181
Short name T615
Test name
Test status
Simulation time 65563828 ps
CPU time 1.56 seconds
Started Jan 24 10:11:10 PM PST 24
Finished Jan 24 10:11:14 PM PST 24
Peak memory 210764 kb
Host smart-b3e3c8af-6729-4e50-abcd-262262119091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068622181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2068622181
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.910659355
Short name T1071
Test name
Test status
Simulation time 985825984 ps
CPU time 9.01 seconds
Started Jan 24 10:11:11 PM PST 24
Finished Jan 24 10:11:21 PM PST 24
Peak memory 306312 kb
Host smart-12d60bce-5909-4366-9985-737188e85434
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910659355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empt
y.910659355
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.51591859
Short name T312
Test name
Test status
Simulation time 2551020566 ps
CPU time 210.98 seconds
Started Jan 24 10:11:05 PM PST 24
Finished Jan 24 10:14:37 PM PST 24
Peak memory 817116 kb
Host smart-bf581b28-42ea-4f08-a089-44e333ecfd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51591859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.51591859
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1292969364
Short name T1450
Test name
Test status
Simulation time 7364698456 ps
CPU time 361.79 seconds
Started Jan 24 10:11:11 PM PST 24
Finished Jan 24 10:17:14 PM PST 24
Peak memory 1009924 kb
Host smart-05a52c3f-cba3-4170-9003-7f0d27eaaae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292969364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1292969364
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1657750634
Short name T907
Test name
Test status
Simulation time 270321669 ps
CPU time 1.02 seconds
Started Jan 24 10:11:08 PM PST 24
Finished Jan 24 10:11:10 PM PST 24
Peak memory 202348 kb
Host smart-9a18062a-5959-4f71-9094-6800c21e53d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657750634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1657750634
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.321691677
Short name T698
Test name
Test status
Simulation time 407553343 ps
CPU time 6.19 seconds
Started Jan 24 10:11:11 PM PST 24
Finished Jan 24 10:11:18 PM PST 24
Peak memory 241276 kb
Host smart-a645ecbd-040e-41e1-8ea9-a9db8ab2fbe0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321691677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
321691677
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2571148575
Short name T134
Test name
Test status
Simulation time 18283207241 ps
CPU time 165 seconds
Started Jan 24 10:11:06 PM PST 24
Finished Jan 24 10:13:52 PM PST 24
Peak memory 1170004 kb
Host smart-9b682818-f8ef-4097-8851-4b905639aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571148575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2571148575
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3127681759
Short name T809
Test name
Test status
Simulation time 7964493242 ps
CPU time 54.15 seconds
Started Jan 24 10:11:46 PM PST 24
Finished Jan 24 10:12:41 PM PST 24
Peak memory 294328 kb
Host smart-4e875bd0-ae9b-4e67-adb3-ca73a2ecb602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127681759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3127681759
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.985386996
Short name T6
Test name
Test status
Simulation time 18317974 ps
CPU time 0.66 seconds
Started Jan 24 10:10:46 PM PST 24
Finished Jan 24 10:10:52 PM PST 24
Peak memory 201488 kb
Host smart-069bdc98-ec5e-4315-a65c-2b69990311bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985386996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.985386996
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.3333557108
Short name T832
Test name
Test status
Simulation time 4282157125 ps
CPU time 53.04 seconds
Started Jan 24 10:11:06 PM PST 24
Finished Jan 24 10:12:00 PM PST 24
Peak memory 218912 kb
Host smart-035114a9-06ce-4836-844f-d51d02bf6c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333557108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3333557108
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_rx_oversample.537085235
Short name T1487
Test name
Test status
Simulation time 10249517545 ps
CPU time 113.86 seconds
Started Jan 24 10:11:11 PM PST 24
Finished Jan 24 10:13:06 PM PST 24
Peak memory 335500 kb
Host smart-ec11d02b-5ec0-4929-b055-1264df0d252f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537085235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_rx_oversample.
537085235
Directory /workspace/21.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1912253772
Short name T912
Test name
Test status
Simulation time 5983082240 ps
CPU time 196.93 seconds
Started Jan 24 10:10:47 PM PST 24
Finished Jan 24 10:14:09 PM PST 24
Peak memory 275864 kb
Host smart-ac8746c2-96f7-4f02-add6-865c7b60b7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912253772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1912253772
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.2584470880
Short name T814
Test name
Test status
Simulation time 10246963395 ps
CPU time 703.37 seconds
Started Jan 24 10:11:06 PM PST 24
Finished Jan 24 10:22:51 PM PST 24
Peak memory 667804 kb
Host smart-ecce9c43-96ad-41a8-87c4-939943c348fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584470880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.2584470880
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all_with_rand_reset.2779326832
Short name T81
Test name
Test status
Simulation time 7922727351 ps
CPU time 891.79 seconds
Started Jan 24 10:11:46 PM PST 24
Finished Jan 24 10:26:39 PM PST 24
Peak memory 1091124 kb
Host smart-c1b068ca-742c-4875-aa28-8673a9774bc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779326832 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.i2c_host_stress_all_with_rand_reset.2779326832
Directory /workspace/21.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.818994351
Short name T178
Test name
Test status
Simulation time 2779155035 ps
CPU time 61.2 seconds
Started Jan 24 10:11:07 PM PST 24
Finished Jan 24 10:12:09 PM PST 24
Peak memory 218396 kb
Host smart-936c11c2-540a-4e99-bf09-e0e54bcefc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818994351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.818994351
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.122889723
Short name T1479
Test name
Test status
Simulation time 1831507684 ps
CPU time 3.8 seconds
Started Jan 24 10:11:46 PM PST 24
Finished Jan 24 10:11:51 PM PST 24
Peak memory 202668 kb
Host smart-ab403bd1-6903-402c-9378-d0e14498f3e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122889723 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.122889723
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.2964284757
Short name T686
Test name
Test status
Simulation time 10025761788 ps
CPU time 85.14 seconds
Started Jan 24 10:11:45 PM PST 24
Finished Jan 24 10:13:11 PM PST 24
Peak memory 714696 kb
Host smart-711baedf-11df-41af-8709-03a57e95905a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964284757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.2964284757
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.1035131607
Short name T689
Test name
Test status
Simulation time 980317183 ps
CPU time 2.66 seconds
Started Jan 24 10:11:45 PM PST 24
Finished Jan 24 10:11:49 PM PST 24
Peak memory 202652 kb
Host smart-1fa53a0e-7f8f-4ef3-9241-2d09c6e7a897
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035131607 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.1035131607
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3415396315
Short name T359
Test name
Test status
Simulation time 3377438740 ps
CPU time 4.13 seconds
Started Jan 24 10:11:26 PM PST 24
Finished Jan 24 10:11:32 PM PST 24
Peak memory 202704 kb
Host smart-4b33ed4c-076c-49d6-beee-dc62728d5e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415396315 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3415396315
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1212950079
Short name T1261
Test name
Test status
Simulation time 11214054883 ps
CPU time 105.09 seconds
Started Jan 24 10:11:31 PM PST 24
Finished Jan 24 10:13:17 PM PST 24
Peak memory 1373204 kb
Host smart-195faad0-9581-47fc-b1af-c25d751e477f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212950079 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1212950079
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.1281837407
Short name T427
Test name
Test status
Simulation time 1116396165 ps
CPU time 4.32 seconds
Started Jan 24 10:11:45 PM PST 24
Finished Jan 24 10:11:50 PM PST 24
Peak memory 205240 kb
Host smart-45ade164-0f55-474a-8c83-49b5e410a007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281837407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.1281837407
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3474937950
Short name T1286
Test name
Test status
Simulation time 4713530053 ps
CPU time 30.82 seconds
Started Jan 24 10:11:28 PM PST 24
Finished Jan 24 10:12:01 PM PST 24
Peak memory 202676 kb
Host smart-f5490a38-5502-40c5-87e3-159512c5b0cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474937950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3474937950
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.992132188
Short name T632
Test name
Test status
Simulation time 20720713056 ps
CPU time 2412.06 seconds
Started Jan 24 10:11:48 PM PST 24
Finished Jan 24 10:52:02 PM PST 24
Peak memory 2554204 kb
Host smart-8cfacd0f-4f0f-4570-99d8-a79b91473086
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992132188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_stress_all.992132188
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.3868286850
Short name T1144
Test name
Test status
Simulation time 1638447037 ps
CPU time 69.63 seconds
Started Jan 24 10:11:28 PM PST 24
Finished Jan 24 10:12:40 PM PST 24
Peak memory 202584 kb
Host smart-e18cc286-abc9-42a0-8988-bf5c53ff3623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868286850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.3868286850
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.1461886086
Short name T405
Test name
Test status
Simulation time 36055209627 ps
CPU time 1564.52 seconds
Started Jan 24 10:11:27 PM PST 24
Finished Jan 24 10:37:33 PM PST 24
Peak memory 7881392 kb
Host smart-2f50f37e-086c-49e7-b5dd-e3e338967aed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461886086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.1461886086
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.105817218
Short name T60
Test name
Test status
Simulation time 21667699169 ps
CPU time 137.03 seconds
Started Jan 24 10:11:28 PM PST 24
Finished Jan 24 10:13:46 PM PST 24
Peak memory 1065388 kb
Host smart-4bd7d566-c1b0-42dd-be8a-a5166ed4e093
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105817218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.105817218
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2588937752
Short name T492
Test name
Test status
Simulation time 4450100890 ps
CPU time 7.65 seconds
Started Jan 24 10:11:25 PM PST 24
Finished Jan 24 10:11:33 PM PST 24
Peak memory 207056 kb
Host smart-c79b94e5-780f-4d05-9ecb-d3fa99f1d596
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588937752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2588937752
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_ovf.1927638263
Short name T599
Test name
Test status
Simulation time 12742178458 ps
CPU time 70.56 seconds
Started Jan 24 10:11:26 PM PST 24
Finished Jan 24 10:12:38 PM PST 24
Peak memory 296056 kb
Host smart-f0429a92-4803-4851-8298-2ed7d5bce50d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927638263 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_tx_ovf.1927638263
Directory /workspace/21.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.1939284959
Short name T903
Test name
Test status
Simulation time 2733864475 ps
CPU time 5.96 seconds
Started Jan 24 10:11:45 PM PST 24
Finished Jan 24 10:11:52 PM PST 24
Peak memory 202624 kb
Host smart-7e99c09d-0512-4d9a-ac8c-0ae59de81fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939284959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.i2c_target_unexp_stop.1939284959
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3692191830
Short name T1145
Test name
Test status
Simulation time 47654091 ps
CPU time 0.61 seconds
Started Jan 24 11:06:01 PM PST 24
Finished Jan 24 11:06:03 PM PST 24
Peak memory 201168 kb
Host smart-5813945d-6d46-4042-846d-5bed7067a891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692191830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3692191830
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.4143540860
Short name T606
Test name
Test status
Simulation time 32973324 ps
CPU time 1.46 seconds
Started Jan 24 11:21:35 PM PST 24
Finished Jan 24 11:21:38 PM PST 24
Peak memory 210780 kb
Host smart-200f7978-24b1-45e6-b69e-1300499ad6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143540860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.4143540860
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3702332498
Short name T1389
Test name
Test status
Simulation time 262258578 ps
CPU time 4.95 seconds
Started Jan 24 10:12:06 PM PST 24
Finished Jan 24 10:12:12 PM PST 24
Peak memory 252608 kb
Host smart-a5edfcbd-45d1-4446-963f-5298cbd3554b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702332498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3702332498
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3601890162
Short name T1126
Test name
Test status
Simulation time 3670823098 ps
CPU time 322.19 seconds
Started Jan 24 10:12:04 PM PST 24
Finished Jan 24 10:17:27 PM PST 24
Peak memory 1088604 kb
Host smart-9712cdb5-4e8d-43d6-b5b7-ce81ba3d1bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601890162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3601890162
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2456905392
Short name T779
Test name
Test status
Simulation time 6439568480 ps
CPU time 429.57 seconds
Started Jan 25 04:18:58 AM PST 24
Finished Jan 25 04:26:14 AM PST 24
Peak memory 1734376 kb
Host smart-65c585e3-1c46-4991-b2fd-218b81072c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456905392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2456905392
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.191350928
Short name T1223
Test name
Test status
Simulation time 120132634 ps
CPU time 0.98 seconds
Started Jan 24 10:12:07 PM PST 24
Finished Jan 24 10:12:09 PM PST 24
Peak memory 202496 kb
Host smart-ef0e1189-f22f-4878-9166-a62221779a1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191350928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fm
t.191350928
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2708825697
Short name T715
Test name
Test status
Simulation time 2507184743 ps
CPU time 5.91 seconds
Started Jan 24 10:12:03 PM PST 24
Finished Jan 24 10:12:10 PM PST 24
Peak memory 249404 kb
Host smart-c4e81c87-d7fb-4c17-bc93-f5ad7b330fb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708825697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2708825697
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1365540943
Short name T808
Test name
Test status
Simulation time 3101226629 ps
CPU time 270.39 seconds
Started Jan 24 10:12:08 PM PST 24
Finished Jan 24 10:16:39 PM PST 24
Peak memory 958828 kb
Host smart-e2f6fafa-a782-4a67-9131-fb4a018527fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365540943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1365540943
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_override.907948235
Short name T412
Test name
Test status
Simulation time 26757585 ps
CPU time 0.68 seconds
Started Jan 24 10:12:04 PM PST 24
Finished Jan 24 10:12:06 PM PST 24
Peak memory 201488 kb
Host smart-d4d1ebbe-6c97-42e3-8594-1dab44d4b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907948235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.907948235
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3619456468
Short name T31
Test name
Test status
Simulation time 52381947878 ps
CPU time 174.9 seconds
Started Jan 24 10:12:08 PM PST 24
Finished Jan 24 10:15:04 PM PST 24
Peak memory 202620 kb
Host smart-f4b39d6d-95db-4ed5-aa42-c42e72800be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619456468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3619456468
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_rx_oversample.994721460
Short name T1208
Test name
Test status
Simulation time 10018723781 ps
CPU time 210.65 seconds
Started Jan 24 10:12:00 PM PST 24
Finished Jan 24 10:15:32 PM PST 24
Peak memory 287496 kb
Host smart-001a7b7f-4cc2-4372-a3a4-1ed1c18c643b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994721460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_rx_oversample.
994721460
Directory /workspace/22.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.2355776493
Short name T1113
Test name
Test status
Simulation time 6555720393 ps
CPU time 84.66 seconds
Started Jan 24 10:12:04 PM PST 24
Finished Jan 24 10:13:30 PM PST 24
Peak memory 230796 kb
Host smart-fcc5ced8-d666-4035-8fae-d4e6cc8eefe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355776493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2355776493
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.939645306
Short name T1090
Test name
Test status
Simulation time 41183037770 ps
CPU time 1652.49 seconds
Started Jan 24 10:12:21 PM PST 24
Finished Jan 24 10:39:54 PM PST 24
Peak memory 3634600 kb
Host smart-c891a90c-5d6b-4278-81b9-a41a193ab644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939645306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.939645306
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2297333390
Short name T1107
Test name
Test status
Simulation time 1855876118 ps
CPU time 39.81 seconds
Started Jan 25 12:59:24 AM PST 24
Finished Jan 25 01:00:04 AM PST 24
Peak memory 210768 kb
Host smart-859ec859-f826-45b4-ac3f-c5e738d01023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297333390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2297333390
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.776857095
Short name T473
Test name
Test status
Simulation time 2691723593 ps
CPU time 3.9 seconds
Started Jan 25 01:00:14 AM PST 24
Finished Jan 25 01:00:18 AM PST 24
Peak memory 202688 kb
Host smart-3c42a56a-40d5-41df-a691-3a5f6bee86d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776857095 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.776857095
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1440195213
Short name T1406
Test name
Test status
Simulation time 10176750349 ps
CPU time 3.29 seconds
Started Jan 24 10:13:26 PM PST 24
Finished Jan 24 10:13:31 PM PST 24
Peak memory 207444 kb
Host smart-02827f69-9e27-4721-bdef-055a836966ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440195213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1440195213
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3173721447
Short name T1111
Test name
Test status
Simulation time 10104076772 ps
CPU time 9.47 seconds
Started Jan 24 10:13:26 PM PST 24
Finished Jan 24 10:13:37 PM PST 24
Peak memory 278916 kb
Host smart-71e7f1e2-cdc0-47ab-9cb8-5e3b722a9bc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173721447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3173721447
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.415922458
Short name T1380
Test name
Test status
Simulation time 694286020 ps
CPU time 2.89 seconds
Started Jan 24 11:02:24 PM PST 24
Finished Jan 24 11:03:02 PM PST 24
Peak memory 202668 kb
Host smart-b9fcf593-c82e-4cf7-ba86-9cbd25aa243d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415922458 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.415922458
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3895360697
Short name T1104
Test name
Test status
Simulation time 3498736939 ps
CPU time 4.38 seconds
Started Jan 25 12:24:14 AM PST 24
Finished Jan 25 12:24:25 AM PST 24
Peak memory 204608 kb
Host smart-325a2b87-9f05-4b85-8e4d-9dfabc5035ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895360697 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3895360697
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_perf.1031125784
Short name T847
Test name
Test status
Simulation time 1648696148 ps
CPU time 5.43 seconds
Started Jan 25 01:34:55 AM PST 24
Finished Jan 25 01:35:02 AM PST 24
Peak memory 206772 kb
Host smart-6a83725c-a4c4-4e2c-afc9-bf3f54d95c41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031125784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.1031125784
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.1255688425
Short name T673
Test name
Test status
Simulation time 6825291522 ps
CPU time 47.1 seconds
Started Jan 24 11:11:04 PM PST 24
Finished Jan 24 11:11:52 PM PST 24
Peak memory 202676 kb
Host smart-77eb88ff-8837-419a-bb06-cc664c77774b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255688425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.1255688425
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.2468685304
Short name T886
Test name
Test status
Simulation time 25934064927 ps
CPU time 766.26 seconds
Started Jan 24 10:13:25 PM PST 24
Finished Jan 24 10:26:14 PM PST 24
Peak memory 3762204 kb
Host smart-ec2d4806-d814-42d9-8cbc-f8f4ccecffb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468685304 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.2468685304
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1234255056
Short name T1190
Test name
Test status
Simulation time 2964762165 ps
CPU time 10.43 seconds
Started Jan 24 10:12:21 PM PST 24
Finished Jan 24 10:12:33 PM PST 24
Peak memory 208212 kb
Host smart-b52c73ff-b0a9-4392-ab3e-5e36a89a91e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234255056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1234255056
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2574694851
Short name T246
Test name
Test status
Simulation time 54106809803 ps
CPU time 1305.17 seconds
Started Jan 24 10:26:57 PM PST 24
Finished Jan 24 10:48:43 PM PST 24
Peak memory 6376324 kb
Host smart-f256266a-26d8-4ff0-b891-759ac59a4d86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574694851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2574694851
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3141915442
Short name T584
Test name
Test status
Simulation time 24994203627 ps
CPU time 203.5 seconds
Started Jan 24 10:12:20 PM PST 24
Finished Jan 24 10:15:45 PM PST 24
Peak memory 1505976 kb
Host smart-3713761d-e16b-4fe3-8bdc-f67ffe75da40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141915442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3141915442
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.995998589
Short name T500
Test name
Test status
Simulation time 2642350753 ps
CPU time 9.13 seconds
Started Jan 24 10:13:25 PM PST 24
Finished Jan 24 10:13:37 PM PST 24
Peak memory 211912 kb
Host smart-afb78d16-b409-43c0-9f12-6a24a050ec91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995998589 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.995998589
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_ovf.1882032828
Short name T921
Test name
Test status
Simulation time 7126043439 ps
CPU time 178.01 seconds
Started Jan 24 10:13:25 PM PST 24
Finished Jan 24 10:16:26 PM PST 24
Peak memory 425836 kb
Host smart-ff7f0df0-4e6f-41ee-9981-4ddf81131e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882032828 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_tx_ovf.1882032828
Directory /workspace/22.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.2190930278
Short name T1473
Test name
Test status
Simulation time 1729719792 ps
CPU time 5.36 seconds
Started Jan 24 10:13:27 PM PST 24
Finished Jan 24 10:13:37 PM PST 24
Peak memory 202572 kb
Host smart-f2bd87c4-f6e8-400b-a46b-2251fc8c0bf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190930278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.i2c_target_unexp_stop.2190930278
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.3163455309
Short name T1433
Test name
Test status
Simulation time 19377002 ps
CPU time 0.63 seconds
Started Jan 24 10:14:23 PM PST 24
Finished Jan 24 10:14:25 PM PST 24
Peak memory 201104 kb
Host smart-00dd3c3b-b98e-44f5-8155-1655bec13299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163455309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3163455309
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.648822287
Short name T1278
Test name
Test status
Simulation time 152974556 ps
CPU time 1.99 seconds
Started Jan 24 10:13:46 PM PST 24
Finished Jan 24 10:13:50 PM PST 24
Peak memory 214408 kb
Host smart-927869fb-8ec6-4cc1-8918-b43571d4df26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648822287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.648822287
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.1240164489
Short name T275
Test name
Test status
Simulation time 384050976 ps
CPU time 4.67 seconds
Started Jan 24 10:32:00 PM PST 24
Finished Jan 24 10:32:05 PM PST 24
Peak memory 239944 kb
Host smart-d4c379a3-3553-4873-bb70-eaa08df10968
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240164489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.1240164489
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2844249077
Short name T363
Test name
Test status
Simulation time 27412159728 ps
CPU time 85.77 seconds
Started Jan 24 10:13:45 PM PST 24
Finished Jan 24 10:15:12 PM PST 24
Peak memory 750184 kb
Host smart-067d2a47-b156-4b50-9a44-c42967461a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844249077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2844249077
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3351101780
Short name T681
Test name
Test status
Simulation time 4662308181 ps
CPU time 293.6 seconds
Started Jan 25 03:29:50 AM PST 24
Finished Jan 25 03:34:45 AM PST 24
Peak memory 1286240 kb
Host smart-a612334c-7dc6-454e-b2e6-c2a9e5cdf025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351101780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3351101780
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3035599297
Short name T52
Test name
Test status
Simulation time 552791797 ps
CPU time 0.93 seconds
Started Jan 24 11:18:58 PM PST 24
Finished Jan 24 11:19:00 PM PST 24
Peak memory 202296 kb
Host smart-b8698e58-bb90-4113-8dd6-bea15fe12008
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035599297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3035599297
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2015830428
Short name T1133
Test name
Test status
Simulation time 172825410 ps
CPU time 10.42 seconds
Started Jan 24 10:13:46 PM PST 24
Finished Jan 24 10:13:58 PM PST 24
Peak memory 233184 kb
Host smart-28342f5c-314d-43e2-934c-88fbfc617a62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015830428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2015830428
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3186489753
Short name T136
Test name
Test status
Simulation time 6233084352 ps
CPU time 339.03 seconds
Started Jan 24 10:27:58 PM PST 24
Finished Jan 24 10:33:38 PM PST 24
Peak memory 1725956 kb
Host smart-6196e813-c403-41d3-8945-fe70e009a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186489753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3186489753
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3636095506
Short name T792
Test name
Test status
Simulation time 1232598099 ps
CPU time 26.92 seconds
Started Jan 24 10:14:27 PM PST 24
Finished Jan 24 10:14:55 PM PST 24
Peak memory 274312 kb
Host smart-b2b31a00-17f6-46cb-9c56-398e612adbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636095506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3636095506
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.2536150634
Short name T768
Test name
Test status
Simulation time 19824901 ps
CPU time 0.62 seconds
Started Jan 24 10:13:25 PM PST 24
Finished Jan 24 10:13:29 PM PST 24
Peak memory 201568 kb
Host smart-ed507c36-02a4-43c4-a2ab-69254a9d58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536150634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2536150634
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3320476636
Short name T509
Test name
Test status
Simulation time 3197066674 ps
CPU time 63.71 seconds
Started Jan 24 10:13:44 PM PST 24
Finished Jan 24 10:14:49 PM PST 24
Peak memory 324480 kb
Host smart-7cebabf5-f930-401f-b5f0-b45074f16c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320476636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3320476636
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_rx_oversample.991208286
Short name T1245
Test name
Test status
Simulation time 9304477757 ps
CPU time 134.04 seconds
Started Jan 24 10:13:25 PM PST 24
Finished Jan 24 10:15:42 PM PST 24
Peak memory 362028 kb
Host smart-dec6dd70-a049-4cff-9e17-c9736029baed
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991208286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_rx_oversample.
991208286
Directory /workspace/23.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3718712506
Short name T234
Test name
Test status
Simulation time 2088686378 ps
CPU time 80.6 seconds
Started Jan 24 10:13:25 PM PST 24
Finished Jan 24 10:14:49 PM PST 24
Peak memory 328448 kb
Host smart-66de879e-331a-4523-a3be-2e03a7cb493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718712506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3718712506
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1347578418
Short name T949
Test name
Test status
Simulation time 547643276 ps
CPU time 10.37 seconds
Started Jan 24 11:07:50 PM PST 24
Finished Jan 24 11:08:02 PM PST 24
Peak memory 218832 kb
Host smart-3ad800e5-b00e-4fae-9cba-088bcf97a560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347578418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1347578418
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.79699493
Short name T1315
Test name
Test status
Simulation time 7127376700 ps
CPU time 5.03 seconds
Started Jan 24 10:14:20 PM PST 24
Finished Jan 24 10:14:25 PM PST 24
Peak memory 202620 kb
Host smart-35aa96ff-758c-4076-a500-9bc2c832fc59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79699493 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_bad_addr.79699493
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2756005494
Short name T885
Test name
Test status
Simulation time 10121232907 ps
CPU time 62.52 seconds
Started Jan 24 10:14:02 PM PST 24
Finished Jan 24 10:15:05 PM PST 24
Peak memory 483824 kb
Host smart-7b9bfb67-f688-4889-abd6-cfd3aad293e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756005494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2756005494
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.791736578
Short name T725
Test name
Test status
Simulation time 10186940108 ps
CPU time 73.09 seconds
Started Jan 24 10:14:06 PM PST 24
Finished Jan 24 10:15:20 PM PST 24
Peak memory 553432 kb
Host smart-931a3441-6b8c-42e5-a1fb-33ff122b66b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791736578 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.791736578
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.1224153969
Short name T459
Test name
Test status
Simulation time 1252245398 ps
CPU time 2.9 seconds
Started Jan 24 10:14:27 PM PST 24
Finished Jan 24 10:14:31 PM PST 24
Peak memory 202656 kb
Host smart-ba0ca334-63d7-4b84-af92-044e4af36302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224153969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.1224153969
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.370548664
Short name T970
Test name
Test status
Simulation time 1475799304 ps
CPU time 5.86 seconds
Started Jan 24 10:14:04 PM PST 24
Finished Jan 24 10:14:10 PM PST 24
Peak memory 205780 kb
Host smart-faf0b10b-ad4b-4ef5-b331-20df67b33d92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370548664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.370548664
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.4193805765
Short name T1498
Test name
Test status
Simulation time 11591810377 ps
CPU time 258.23 seconds
Started Jan 24 10:14:07 PM PST 24
Finished Jan 24 10:18:26 PM PST 24
Peak memory 2588788 kb
Host smart-263452c2-feb0-4d68-b60b-9bb8a8fb5f16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193805765 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.4193805765
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.3712545279
Short name T1073
Test name
Test status
Simulation time 1262455644 ps
CPU time 4.02 seconds
Started Jan 24 10:14:04 PM PST 24
Finished Jan 24 10:14:08 PM PST 24
Peak memory 202532 kb
Host smart-e4eca630-2a95-47de-8154-9fd083ea025c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712545279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.3712545279
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2581597626
Short name T503
Test name
Test status
Simulation time 1017438977 ps
CPU time 13.11 seconds
Started Jan 24 10:13:46 PM PST 24
Finished Jan 24 10:14:01 PM PST 24
Peak memory 202620 kb
Host smart-d32f65f7-7f49-4f62-a1a2-928c1e2a10a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581597626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2581597626
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.803528356
Short name T1361
Test name
Test status
Simulation time 66342130280 ps
CPU time 2141.3 seconds
Started Jan 24 10:14:04 PM PST 24
Finished Jan 24 10:49:46 PM PST 24
Peak memory 773468 kb
Host smart-49eeb550-deea-4488-a4a6-29987dffe9ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803528356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.i2c_target_stress_all.803528356
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3775490002
Short name T1081
Test name
Test status
Simulation time 10195590024 ps
CPU time 44.52 seconds
Started Jan 24 10:14:06 PM PST 24
Finished Jan 24 10:14:52 PM PST 24
Peak memory 221744 kb
Host smart-a7ce00fd-4c45-41d3-982e-1df31f59016d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775490002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3775490002
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2436849377
Short name T57
Test name
Test status
Simulation time 13583974203 ps
CPU time 158.93 seconds
Started Jan 24 10:14:06 PM PST 24
Finished Jan 24 10:16:46 PM PST 24
Peak memory 2355512 kb
Host smart-eec7446c-10b7-4cff-a3ca-bdbd3b8461bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436849377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2436849377
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1839459301
Short name T1387
Test name
Test status
Simulation time 19012000537 ps
CPU time 88.23 seconds
Started Jan 24 10:14:04 PM PST 24
Finished Jan 24 10:15:33 PM PST 24
Peak memory 869392 kb
Host smart-b0a7d36b-1b5a-4808-a8a2-d5a3e92b3c5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839459301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1839459301
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1798693849
Short name T668
Test name
Test status
Simulation time 1562514123 ps
CPU time 6.55 seconds
Started Jan 24 10:14:06 PM PST 24
Finished Jan 24 10:14:14 PM PST 24
Peak memory 202600 kb
Host smart-8184b783-7cd8-42b1-8c72-3d71b00e916a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798693849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1798693849
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_ovf.690531782
Short name T1341
Test name
Test status
Simulation time 2428574061 ps
CPU time 37.97 seconds
Started Jan 24 10:14:05 PM PST 24
Finished Jan 24 10:14:44 PM PST 24
Peak memory 212844 kb
Host smart-f898baab-bedb-4716-a231-baa01e7ecd57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690531782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_tx_ovf.690531782
Directory /workspace/23.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.1724199696
Short name T1075
Test name
Test status
Simulation time 7640010215 ps
CPU time 9.38 seconds
Started Jan 24 10:14:06 PM PST 24
Finished Jan 24 10:14:16 PM PST 24
Peak memory 202668 kb
Host smart-93887d9e-749b-4aea-80dd-9ae0ffdde418
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724199696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.i2c_target_unexp_stop.1724199696
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2373773384
Short name T74
Test name
Test status
Simulation time 20923863 ps
CPU time 0.62 seconds
Started Jan 24 10:15:34 PM PST 24
Finished Jan 24 10:15:36 PM PST 24
Peak memory 201148 kb
Host smart-c84c623f-121d-4667-85f6-a7f2b5558e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373773384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2373773384
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.396603286
Short name T1356
Test name
Test status
Simulation time 49061501 ps
CPU time 1.29 seconds
Started Jan 24 10:14:38 PM PST 24
Finished Jan 24 10:14:40 PM PST 24
Peak memory 210804 kb
Host smart-eaa416ae-09e4-48b0-bd3e-0e5cf8dce000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396603286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.396603286
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.198458136
Short name T1346
Test name
Test status
Simulation time 238923085 ps
CPU time 4.19 seconds
Started Jan 24 10:14:38 PM PST 24
Finished Jan 24 10:14:43 PM PST 24
Peak memory 244620 kb
Host smart-7efac887-4fff-4e60-86ef-b670bab09049
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198458136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.198458136
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2242837904
Short name T1116
Test name
Test status
Simulation time 15790158350 ps
CPU time 151.92 seconds
Started Jan 24 10:14:37 PM PST 24
Finished Jan 24 10:17:10 PM PST 24
Peak memory 1070400 kb
Host smart-660a4237-16c5-43a2-b11b-a57b2f288c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242837904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2242837904
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2809971979
Short name T13
Test name
Test status
Simulation time 6134919301 ps
CPU time 752.13 seconds
Started Jan 24 10:14:40 PM PST 24
Finished Jan 24 10:27:14 PM PST 24
Peak memory 1530356 kb
Host smart-5fea7855-7882-4d9e-aa11-660c6290a06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809971979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2809971979
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2317651772
Short name T836
Test name
Test status
Simulation time 797060490 ps
CPU time 0.8 seconds
Started Jan 24 10:14:37 PM PST 24
Finished Jan 24 10:14:39 PM PST 24
Peak memory 202360 kb
Host smart-71f2e008-b71e-43a0-8dbf-c5eebadcff21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317651772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2317651772
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.4267960655
Short name T378
Test name
Test status
Simulation time 619543427 ps
CPU time 5.53 seconds
Started Jan 24 10:14:37 PM PST 24
Finished Jan 24 10:14:44 PM PST 24
Peak memory 202508 kb
Host smart-eb2394c7-903e-4045-877f-efb4d203dbc1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267960655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.4267960655
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2910088311
Short name T1384
Test name
Test status
Simulation time 26406475098 ps
CPU time 804.35 seconds
Started Jan 24 10:14:38 PM PST 24
Finished Jan 24 10:28:03 PM PST 24
Peak memory 1880352 kb
Host smart-d6e251dd-ccbc-414f-996f-b6c37fde9602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910088311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2910088311
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1281355999
Short name T1417
Test name
Test status
Simulation time 4890164525 ps
CPU time 146.92 seconds
Started Jan 24 11:18:51 PM PST 24
Finished Jan 24 11:21:21 PM PST 24
Peak memory 263560 kb
Host smart-f5371ced-cb40-4a85-958a-cb90053800a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281355999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1281355999
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.716497953
Short name T98
Test name
Test status
Simulation time 15333906 ps
CPU time 0.6 seconds
Started Jan 24 10:14:21 PM PST 24
Finished Jan 24 10:14:22 PM PST 24
Peak memory 201500 kb
Host smart-81a4fffe-5837-4609-8c2a-b39575614577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716497953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.716497953
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3088299332
Short name T326
Test name
Test status
Simulation time 4441672026 ps
CPU time 12.06 seconds
Started Jan 24 10:14:36 PM PST 24
Finished Jan 24 10:14:49 PM PST 24
Peak memory 213704 kb
Host smart-593ac146-f2f6-44f3-9237-1c746d1b3b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088299332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3088299332
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_rx_oversample.2739834876
Short name T37
Test name
Test status
Simulation time 6655256119 ps
CPU time 59.93 seconds
Started Jan 24 10:14:39 PM PST 24
Finished Jan 24 10:15:40 PM PST 24
Peak memory 291740 kb
Host smart-57900e52-70c5-4f11-ad23-c6815235fb71
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739834876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_rx_oversample
.2739834876
Directory /workspace/24.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1636454866
Short name T538
Test name
Test status
Simulation time 6392774431 ps
CPU time 67.86 seconds
Started Jan 24 10:14:21 PM PST 24
Finished Jan 24 10:15:30 PM PST 24
Peak memory 303540 kb
Host smart-5bbf56f2-1afb-415d-9bac-63e70c4273a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636454866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1636454866
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3562762778
Short name T1154
Test name
Test status
Simulation time 4182003334 ps
CPU time 48.51 seconds
Started Jan 24 10:14:38 PM PST 24
Finished Jan 24 10:15:28 PM PST 24
Peak memory 218248 kb
Host smart-f67320c6-b3f4-4e1b-b95a-9d734bf07acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562762778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3562762778
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.114929519
Short name T929
Test name
Test status
Simulation time 2753471172 ps
CPU time 4.86 seconds
Started Jan 24 10:15:15 PM PST 24
Finished Jan 24 10:15:21 PM PST 24
Peak memory 202672 kb
Host smart-5e1771dd-e9be-4754-8fe3-9ee71b1f6a1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114929519 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.114929519
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.434313012
Short name T521
Test name
Test status
Simulation time 10603350999 ps
CPU time 15.45 seconds
Started Jan 24 10:15:15 PM PST 24
Finished Jan 24 10:15:31 PM PST 24
Peak memory 298628 kb
Host smart-54f05c99-df34-44f9-9a84-89b269fc6634
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434313012 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_tx.434313012
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.1908804632
Short name T652
Test name
Test status
Simulation time 546917184 ps
CPU time 2.65 seconds
Started Jan 24 10:15:15 PM PST 24
Finished Jan 24 10:15:20 PM PST 24
Peak memory 202676 kb
Host smart-dbbabbd7-6d9b-4b82-8272-a45e9ccf6636
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908804632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.1908804632
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2760128337
Short name T322
Test name
Test status
Simulation time 1530840561 ps
CPU time 6.79 seconds
Started Jan 24 10:14:58 PM PST 24
Finished Jan 24 10:15:05 PM PST 24
Peak memory 208492 kb
Host smart-831297d6-0145-4a88-b94a-0def3a6c0f45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760128337 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2760128337
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.3489255630
Short name T1195
Test name
Test status
Simulation time 11703928560 ps
CPU time 102.58 seconds
Started Jan 24 10:14:58 PM PST 24
Finished Jan 24 10:16:41 PM PST 24
Peak memory 1396236 kb
Host smart-1c93b7af-b2b9-4f8d-b17f-ed1459bef10d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489255630 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.3489255630
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.1420320886
Short name T431
Test name
Test status
Simulation time 2364447353 ps
CPU time 3.63 seconds
Started Jan 24 10:15:17 PM PST 24
Finished Jan 24 10:15:22 PM PST 24
Peak memory 202664 kb
Host smart-d7522642-5a77-4345-acd0-fd307fb959f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420320886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.1420320886
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.4061863093
Short name T730
Test name
Test status
Simulation time 1143927440 ps
CPU time 29.29 seconds
Started Jan 24 10:14:38 PM PST 24
Finished Jan 24 10:15:09 PM PST 24
Peak memory 202592 kb
Host smart-d2f27e03-ba98-421f-b5de-a4c0f0d48e50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061863093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.4061863093
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.3709998400
Short name T27
Test name
Test status
Simulation time 48087015888 ps
CPU time 528.35 seconds
Started Jan 24 10:15:15 PM PST 24
Finished Jan 24 10:24:04 PM PST 24
Peak memory 594824 kb
Host smart-1092cba7-c764-4bf9-be68-195285d7cce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709998400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_stress_all.3709998400
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2286131258
Short name T244
Test name
Test status
Simulation time 1500129295 ps
CPU time 24.4 seconds
Started Jan 25 02:49:23 AM PST 24
Finished Jan 25 02:49:48 AM PST 24
Peak memory 216080 kb
Host smart-d4407993-00f5-4b47-bfe3-c4ecd1dd88db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286131258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2286131258
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1449516311
Short name T1118
Test name
Test status
Simulation time 32884424447 ps
CPU time 1406.94 seconds
Started Jan 24 10:14:56 PM PST 24
Finished Jan 24 10:38:24 PM PST 24
Peak memory 7018596 kb
Host smart-6dc1601a-32b0-4a9b-8af3-e766c91d007a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449516311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1449516311
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1141726201
Short name T1027
Test name
Test status
Simulation time 19026521843 ps
CPU time 997.17 seconds
Started Jan 24 11:31:04 PM PST 24
Finished Jan 24 11:47:42 PM PST 24
Peak memory 4488296 kb
Host smart-30f29541-d973-4d40-9f23-e44b5fcdb872
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141726201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1141726201
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2602820221
Short name T364
Test name
Test status
Simulation time 11472425143 ps
CPU time 8.04 seconds
Started Jan 24 10:14:44 PM PST 24
Finished Jan 24 10:14:53 PM PST 24
Peak memory 205900 kb
Host smart-9663f853-7b67-4fbb-b387-c44d85f94c8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602820221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2602820221
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_ovf.361897241
Short name T299
Test name
Test status
Simulation time 2966203232 ps
CPU time 36.2 seconds
Started Jan 24 10:14:54 PM PST 24
Finished Jan 24 10:15:31 PM PST 24
Peak memory 215076 kb
Host smart-7a5d0b48-3ce4-4cb4-be00-ff31d4eeb841
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361897241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_tx_ovf.361897241
Directory /workspace/24.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.221352540
Short name T746
Test name
Test status
Simulation time 3636763825 ps
CPU time 5.87 seconds
Started Jan 24 10:15:14 PM PST 24
Finished Jan 24 10:15:20 PM PST 24
Peak memory 206196 kb
Host smart-216a0cfb-923d-46a0-a336-a4ad8267d4ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221352540 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_unexp_stop.221352540
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2878093266
Short name T434
Test name
Test status
Simulation time 29976886 ps
CPU time 0.63 seconds
Started Jan 24 10:16:39 PM PST 24
Finished Jan 24 10:16:40 PM PST 24
Peak memory 201148 kb
Host smart-3db28a4e-b9e0-480c-89d8-7a0309bb82b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878093266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2878093266
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1950195804
Short name T303
Test name
Test status
Simulation time 46953930 ps
CPU time 1.33 seconds
Started Jan 25 01:07:27 AM PST 24
Finished Jan 25 01:07:29 AM PST 24
Peak memory 210784 kb
Host smart-504e8e00-9c3a-46e2-b26b-e0ece89ee5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950195804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1950195804
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3744330043
Short name T44
Test name
Test status
Simulation time 421630586 ps
CPU time 22.38 seconds
Started Jan 24 10:15:54 PM PST 24
Finished Jan 24 10:16:17 PM PST 24
Peak memory 291648 kb
Host smart-f2e88f4e-179f-4898-b4e0-7203bdaed7b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744330043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3744330043
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1838863241
Short name T1335
Test name
Test status
Simulation time 2610804038 ps
CPU time 140.43 seconds
Started Jan 24 11:11:03 PM PST 24
Finished Jan 24 11:13:25 PM PST 24
Peak memory 349348 kb
Host smart-e9c0e64e-9811-47aa-ab72-ff2c5a943ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838863241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1838863241
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3192741392
Short name T649
Test name
Test status
Simulation time 6668967107 ps
CPU time 542.01 seconds
Started Jan 24 10:15:34 PM PST 24
Finished Jan 24 10:24:37 PM PST 24
Peak memory 1758624 kb
Host smart-c4bbf085-970c-4fac-9c23-9d3aeae77e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192741392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3192741392
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3899911195
Short name T1179
Test name
Test status
Simulation time 239013006 ps
CPU time 0.93 seconds
Started Jan 24 10:15:57 PM PST 24
Finished Jan 24 10:15:58 PM PST 24
Peak memory 202332 kb
Host smart-c80de316-34b6-4ae7-b591-9dfc2e176e14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899911195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3899911195
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1788845909
Short name T221
Test name
Test status
Simulation time 495647311 ps
CPU time 6.62 seconds
Started Jan 24 10:15:53 PM PST 24
Finished Jan 24 10:16:01 PM PST 24
Peak memory 253720 kb
Host smart-c5941041-2f41-465a-8aa2-0bb4907bbd1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788845909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1788845909
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2716696085
Short name T180
Test name
Test status
Simulation time 4057361912 ps
CPU time 368.59 seconds
Started Jan 24 10:15:37 PM PST 24
Finished Jan 24 10:21:47 PM PST 24
Peak memory 1062912 kb
Host smart-895b5d6f-6cfc-4d7b-92ac-4dcfa626d1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716696085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2716696085
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3622365116
Short name T659
Test name
Test status
Simulation time 5015634230 ps
CPU time 180 seconds
Started Jan 25 12:37:49 AM PST 24
Finished Jan 25 12:40:53 AM PST 24
Peak memory 270216 kb
Host smart-715f0f96-f41b-4be8-aa6b-9fadbec307eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622365116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3622365116
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2844674604
Short name T1505
Test name
Test status
Simulation time 45649463 ps
CPU time 0.62 seconds
Started Jan 24 10:44:33 PM PST 24
Finished Jan 24 10:44:35 PM PST 24
Peak memory 201580 kb
Host smart-c9f81a17-19fe-4282-9a5b-de8be22fdba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844674604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2844674604
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1293453495
Short name T184
Test name
Test status
Simulation time 55248233250 ps
CPU time 579.27 seconds
Started Jan 24 10:15:57 PM PST 24
Finished Jan 24 10:25:37 PM PST 24
Peak memory 218700 kb
Host smart-8c278137-84a8-4289-9af7-f3043f27bb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293453495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1293453495
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_rx_oversample.2423223240
Short name T1065
Test name
Test status
Simulation time 6017863641 ps
CPU time 112.98 seconds
Started Jan 24 10:15:37 PM PST 24
Finished Jan 24 10:17:30 PM PST 24
Peak memory 282096 kb
Host smart-d9bd5fcd-4550-4f9e-973b-107ece76353e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423223240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_rx_oversample
.2423223240
Directory /workspace/25.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1278253274
Short name T1491
Test name
Test status
Simulation time 9567885092 ps
CPU time 129.8 seconds
Started Jan 24 10:15:37 PM PST 24
Finished Jan 24 10:17:47 PM PST 24
Peak memory 243380 kb
Host smart-ae7427c3-8ed3-4aa7-b3e6-2b4d6149ce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278253274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1278253274
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.749674787
Short name T738
Test name
Test status
Simulation time 1745696490 ps
CPU time 34.43 seconds
Started Jan 24 10:15:55 PM PST 24
Finished Jan 24 10:16:30 PM PST 24
Peak memory 210724 kb
Host smart-da853dae-25ad-4c6d-a63a-50eebb5554f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749674787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.749674787
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2170325215
Short name T491
Test name
Test status
Simulation time 6381953638 ps
CPU time 5.53 seconds
Started Jan 24 10:16:16 PM PST 24
Finished Jan 24 10:16:24 PM PST 24
Peak memory 202468 kb
Host smart-33a88479-58ad-44c4-8b7c-05ef3fe30a89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170325215 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2170325215
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1670862314
Short name T560
Test name
Test status
Simulation time 10086646323 ps
CPU time 61.79 seconds
Started Jan 24 10:16:14 PM PST 24
Finished Jan 24 10:17:19 PM PST 24
Peak memory 551072 kb
Host smart-7291a9e7-368c-43e4-8c29-98cb0faad444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670862314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1670862314
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1050740714
Short name T1509
Test name
Test status
Simulation time 10054609474 ps
CPU time 61.19 seconds
Started Jan 24 10:16:15 PM PST 24
Finished Jan 24 10:17:19 PM PST 24
Peak memory 586256 kb
Host smart-d4a35543-1f3e-46ac-9574-7ed4727544e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050740714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1050740714
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.3532760121
Short name T674
Test name
Test status
Simulation time 2481332634 ps
CPU time 2.74 seconds
Started Jan 24 10:16:15 PM PST 24
Finished Jan 24 10:16:21 PM PST 24
Peak memory 202676 kb
Host smart-6ad2c868-b8fa-439f-ba9a-36d891e234f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532760121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.3532760121
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1163693841
Short name T888
Test name
Test status
Simulation time 1322934255 ps
CPU time 5.67 seconds
Started Jan 24 10:15:55 PM PST 24
Finished Jan 24 10:16:01 PM PST 24
Peak memory 202644 kb
Host smart-b760e678-173b-4063-a383-e4eb35e9a50b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163693841 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1163693841
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_perf.560115655
Short name T442
Test name
Test status
Simulation time 2865473537 ps
CPU time 4.62 seconds
Started Jan 24 10:16:14 PM PST 24
Finished Jan 24 10:16:22 PM PST 24
Peak memory 202636 kb
Host smart-f01c4dde-83c4-44d9-89e1-2bc6fb880831
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560115655 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_perf.560115655
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1417394597
Short name T740
Test name
Test status
Simulation time 4340972795 ps
CPU time 27.9 seconds
Started Jan 24 10:15:54 PM PST 24
Finished Jan 24 10:16:22 PM PST 24
Peak memory 202640 kb
Host smart-0ace2a3d-f0ee-4887-b3bd-160892b804d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417394597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1417394597
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.2063697870
Short name T772
Test name
Test status
Simulation time 46353007375 ps
CPU time 104.74 seconds
Started Jan 24 10:16:16 PM PST 24
Finished Jan 24 10:18:03 PM PST 24
Peak memory 1042964 kb
Host smart-090fcc7b-740e-42ad-b505-7ba8cd7fbefa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063697870 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.2063697870
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2493821871
Short name T1514
Test name
Test status
Simulation time 9812517344 ps
CPU time 40.2 seconds
Started Jan 24 10:15:54 PM PST 24
Finished Jan 24 10:16:35 PM PST 24
Peak memory 221940 kb
Host smart-6c8f1b7e-e30e-4e10-a9e6-6c4797e5071b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493821871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2493821871
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3619400377
Short name T733
Test name
Test status
Simulation time 7892291493 ps
CPU time 8.83 seconds
Started Jan 24 11:35:22 PM PST 24
Finished Jan 24 11:35:32 PM PST 24
Peak memory 365068 kb
Host smart-9ec4e6ac-832b-4638-93b9-9a951bb19c9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619400377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3619400377
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3617854841
Short name T833
Test name
Test status
Simulation time 46312017164 ps
CPU time 3020.74 seconds
Started Jan 24 10:15:57 PM PST 24
Finished Jan 24 11:06:19 PM PST 24
Peak memory 4023760 kb
Host smart-cf9f0e4a-dc4d-4556-b3c6-bbfce7881b62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617854841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3617854841
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.1717695329
Short name T898
Test name
Test status
Simulation time 3531537056 ps
CPU time 7.37 seconds
Started Jan 24 10:17:23 PM PST 24
Finished Jan 24 10:17:33 PM PST 24
Peak memory 202696 kb
Host smart-fedba396-95b0-4644-867e-e937c3ae6ab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717695329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.1717695329
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_ovf.1351506658
Short name T1393
Test name
Test status
Simulation time 6162857895 ps
CPU time 163.83 seconds
Started Jan 24 10:15:54 PM PST 24
Finished Jan 24 10:18:39 PM PST 24
Peak memory 423780 kb
Host smart-98318e07-6454-4faf-a4b6-173b834f22ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351506658 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_tx_ovf.1351506658
Directory /workspace/25.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.2312435659
Short name T580
Test name
Test status
Simulation time 835368527 ps
CPU time 4.16 seconds
Started Jan 24 10:16:13 PM PST 24
Finished Jan 24 10:16:21 PM PST 24
Peak memory 202568 kb
Host smart-39472d06-de58-4897-bab9-e7b47cbd6c74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312435659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.2312435659
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.469725918
Short name T575
Test name
Test status
Simulation time 36905954 ps
CPU time 0.6 seconds
Started Jan 25 01:18:37 AM PST 24
Finished Jan 25 01:18:39 AM PST 24
Peak memory 201044 kb
Host smart-5ed075cc-1491-436e-bed0-502bb04ceb7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469725918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.469725918
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.3929540017
Short name T998
Test name
Test status
Simulation time 83378110 ps
CPU time 1.14 seconds
Started Jan 24 10:16:30 PM PST 24
Finished Jan 24 10:16:33 PM PST 24
Peak memory 202520 kb
Host smart-c9ebf47b-64f4-436f-8d41-109ca56b0f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929540017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3929540017
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2855912267
Short name T1392
Test name
Test status
Simulation time 876078554 ps
CPU time 8.21 seconds
Started Jan 24 10:16:36 PM PST 24
Finished Jan 24 10:16:46 PM PST 24
Peak memory 279704 kb
Host smart-552928c5-2287-4928-b58f-1cdc4f952fa1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855912267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2855912267
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3749394694
Short name T908
Test name
Test status
Simulation time 7025327850 ps
CPU time 139.69 seconds
Started Jan 24 10:16:35 PM PST 24
Finished Jan 24 10:18:57 PM PST 24
Peak memory 674512 kb
Host smart-99300125-850e-41fc-b681-0a4c5ac38538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749394694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3749394694
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2535654359
Short name T1292
Test name
Test status
Simulation time 4147674113 ps
CPU time 194.29 seconds
Started Jan 24 10:16:39 PM PST 24
Finished Jan 24 10:19:54 PM PST 24
Peak memory 1146924 kb
Host smart-70557529-7b04-4cbf-b7d8-0498e2de4f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535654359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2535654359
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.294532081
Short name T874
Test name
Test status
Simulation time 310395162 ps
CPU time 0.84 seconds
Started Jan 24 10:16:33 PM PST 24
Finished Jan 24 10:16:36 PM PST 24
Peak memory 202336 kb
Host smart-e8fa9d7f-fce2-4b60-8e7e-6723cde32586
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294532081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fm
t.294532081
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1608766274
Short name T159
Test name
Test status
Simulation time 149796477 ps
CPU time 3.76 seconds
Started Jan 24 10:16:34 PM PST 24
Finished Jan 24 10:16:39 PM PST 24
Peak memory 226996 kb
Host smart-c5fa2177-a860-4368-9b7b-bf3c1dbb1d96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608766274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1608766274
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2876890887
Short name T327
Test name
Test status
Simulation time 3859443427 ps
CPU time 321.85 seconds
Started Jan 24 10:45:16 PM PST 24
Finished Jan 24 10:50:39 PM PST 24
Peak memory 989164 kb
Host smart-74e8b5b2-0520-43b6-a5b8-8515ddbffdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876890887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2876890887
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1169602732
Short name T548
Test name
Test status
Simulation time 19088016883 ps
CPU time 79.63 seconds
Started Jan 24 10:17:22 PM PST 24
Finished Jan 24 10:18:44 PM PST 24
Peak memory 322716 kb
Host smart-b67d1c35-b9e9-41f7-a12a-0a15c9187fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169602732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1169602732
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.569843677
Short name T1272
Test name
Test status
Simulation time 17232286 ps
CPU time 0.65 seconds
Started Jan 24 10:16:34 PM PST 24
Finished Jan 24 10:16:37 PM PST 24
Peak memory 201532 kb
Host smart-f785b540-04ec-4fad-b023-830820e9d5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569843677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.569843677
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.15993522
Short name T282
Test name
Test status
Simulation time 6710684789 ps
CPU time 81.11 seconds
Started Jan 24 10:16:39 PM PST 24
Finished Jan 24 10:18:01 PM PST 24
Peak memory 222380 kb
Host smart-903962ab-60d8-40e3-b84a-249aea2b60aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15993522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.15993522
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_rx_oversample.1690366525
Short name T531
Test name
Test status
Simulation time 11181812924 ps
CPU time 174.66 seconds
Started Jan 24 10:16:34 PM PST 24
Finished Jan 24 10:19:30 PM PST 24
Peak memory 253896 kb
Host smart-59a73495-4a8e-496d-9d3c-a6750e42152d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690366525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_rx_oversample
.1690366525
Directory /workspace/26.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.4105585849
Short name T1474
Test name
Test status
Simulation time 2133182617 ps
CPU time 56.08 seconds
Started Jan 25 01:07:23 AM PST 24
Finished Jan 25 01:08:20 AM PST 24
Peak memory 276072 kb
Host smart-6532224d-61e3-4d79-8b01-4a5bbf126b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105585849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.4105585849
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.176767274
Short name T1074
Test name
Test status
Simulation time 1057542320 ps
CPU time 18.17 seconds
Started Jan 24 10:16:33 PM PST 24
Finished Jan 24 10:16:54 PM PST 24
Peak memory 214496 kb
Host smart-3f575984-0f01-4676-9da5-090d245d95e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176767274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.176767274
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3978486084
Short name T1242
Test name
Test status
Simulation time 1086017124 ps
CPU time 2.54 seconds
Started Jan 24 10:17:24 PM PST 24
Finished Jan 24 10:17:28 PM PST 24
Peak memory 202620 kb
Host smart-96654637-2746-4235-9352-c16d89951689
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978486084 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3978486084
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2545602292
Short name T193
Test name
Test status
Simulation time 10066984113 ps
CPU time 67.16 seconds
Started Jan 24 10:17:08 PM PST 24
Finished Jan 24 10:18:18 PM PST 24
Peak memory 476352 kb
Host smart-3b3c6105-1ca2-43aa-8c35-f0eb70aab09d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545602292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.2545602292
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.892369664
Short name T207
Test name
Test status
Simulation time 10424472663 ps
CPU time 6.5 seconds
Started Jan 24 10:17:08 PM PST 24
Finished Jan 24 10:17:17 PM PST 24
Peak memory 247176 kb
Host smart-0c691f69-d7ed-4ba3-95ae-15f6abb01e7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892369664 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.892369664
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.860325968
Short name T872
Test name
Test status
Simulation time 3187897695 ps
CPU time 2.63 seconds
Started Jan 24 10:17:23 PM PST 24
Finished Jan 24 10:17:27 PM PST 24
Peak memory 202660 kb
Host smart-2f1b383d-bc91-423c-a6d1-1630d101bbc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860325968 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_hrst.860325968
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1708052323
Short name T817
Test name
Test status
Simulation time 6661318364 ps
CPU time 6.26 seconds
Started Jan 24 10:16:46 PM PST 24
Finished Jan 24 10:16:53 PM PST 24
Peak memory 204992 kb
Host smart-43d4cfde-77f5-4e28-9b93-815eca10004f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708052323 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1708052323
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.3727436397
Short name T1199
Test name
Test status
Simulation time 21009341233 ps
CPU time 115.03 seconds
Started Jan 24 10:16:49 PM PST 24
Finished Jan 24 10:18:45 PM PST 24
Peak memory 1480208 kb
Host smart-ad63c4f0-fb48-410d-8d2b-bd43bffe19d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727436397 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.3727436397
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.3884426267
Short name T1374
Test name
Test status
Simulation time 501680486 ps
CPU time 2.99 seconds
Started Jan 24 10:17:11 PM PST 24
Finished Jan 24 10:17:23 PM PST 24
Peak memory 202576 kb
Host smart-28529397-e163-4179-be0a-5ef79d67f631
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884426267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.3884426267
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.3410194995
Short name T582
Test name
Test status
Simulation time 3214495564 ps
CPU time 19.28 seconds
Started Jan 24 10:16:49 PM PST 24
Finished Jan 24 10:17:10 PM PST 24
Peak memory 202604 kb
Host smart-48f2eb90-f6b7-44b2-91d7-b514dc2e531b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410194995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.3410194995
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.2185487375
Short name T1267
Test name
Test status
Simulation time 58223364364 ps
CPU time 2260.46 seconds
Started Jan 24 10:17:07 PM PST 24
Finished Jan 24 10:54:50 PM PST 24
Peak memory 1750932 kb
Host smart-5715fe47-4fd8-4063-9904-911a3f41a59a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185487375 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.2185487375
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.928848956
Short name T978
Test name
Test status
Simulation time 3059793789 ps
CPU time 30.57 seconds
Started Jan 24 10:16:48 PM PST 24
Finished Jan 24 10:17:20 PM PST 24
Peak memory 202624 kb
Host smart-b433d3f7-907f-4572-96c1-70eacce580d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928848956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_rd.928848956
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1057620076
Short name T498
Test name
Test status
Simulation time 41364786830 ps
CPU time 168.63 seconds
Started Jan 24 10:16:49 PM PST 24
Finished Jan 24 10:19:39 PM PST 24
Peak memory 1836432 kb
Host smart-e32892f1-f221-42a2-b081-c76fd8e57668
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057620076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1057620076
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3731014898
Short name T1483
Test name
Test status
Simulation time 19270181750 ps
CPU time 413.5 seconds
Started Jan 24 10:16:50 PM PST 24
Finished Jan 24 10:23:45 PM PST 24
Peak memory 2233824 kb
Host smart-c6f86cc5-ab1e-432f-9499-8a06e4c663c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731014898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3731014898
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2768466851
Short name T781
Test name
Test status
Simulation time 1772749079 ps
CPU time 7.05 seconds
Started Jan 24 10:17:10 PM PST 24
Finished Jan 24 10:17:25 PM PST 24
Peak memory 202596 kb
Host smart-aaa225ec-3956-4a1d-8436-23720e4d9836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768466851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2768466851
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_ovf.3943563063
Short name T603
Test name
Test status
Simulation time 5788029476 ps
CPU time 53.67 seconds
Started Jan 24 10:16:46 PM PST 24
Finished Jan 24 10:17:41 PM PST 24
Peak memory 231036 kb
Host smart-e76b1ed5-57b1-4ec2-85c1-143e22dadefa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943563063 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_tx_ovf.3943563063
Directory /workspace/26.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.1526925580
Short name T865
Test name
Test status
Simulation time 3355726933 ps
CPU time 7.43 seconds
Started Jan 24 10:17:09 PM PST 24
Finished Jan 24 10:17:18 PM PST 24
Peak memory 202620 kb
Host smart-e068bc12-8ee7-47ca-9495-0065e3305774
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526925580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.1526925580
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2556395118
Short name T793
Test name
Test status
Simulation time 14201764 ps
CPU time 0.61 seconds
Started Jan 24 10:18:20 PM PST 24
Finished Jan 24 10:18:22 PM PST 24
Peak memory 201148 kb
Host smart-95b1d9fe-277b-4565-9c98-d3a3454d6017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556395118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2556395118
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2322591616
Short name T1030
Test name
Test status
Simulation time 38825543 ps
CPU time 1.63 seconds
Started Jan 24 10:17:42 PM PST 24
Finished Jan 24 10:17:44 PM PST 24
Peak memory 210756 kb
Host smart-577f0f42-94ea-4030-9288-f3d46d2b5e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322591616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2322591616
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3399465130
Short name T222
Test name
Test status
Simulation time 788922814 ps
CPU time 20.96 seconds
Started Jan 24 10:17:45 PM PST 24
Finished Jan 24 10:18:07 PM PST 24
Peak memory 286316 kb
Host smart-b56c52f0-c133-4374-bfbe-8cade77ca960
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399465130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3399465130
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.283847520
Short name T1467
Test name
Test status
Simulation time 13658140547 ps
CPU time 277.94 seconds
Started Jan 24 10:17:42 PM PST 24
Finished Jan 24 10:22:21 PM PST 24
Peak memory 978784 kb
Host smart-ca90b547-d742-45e9-aa50-0503d39f42f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283847520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.283847520
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.59681712
Short name T1209
Test name
Test status
Simulation time 10596505860 ps
CPU time 699.55 seconds
Started Jan 24 10:17:21 PM PST 24
Finished Jan 24 10:29:04 PM PST 24
Peak memory 1525820 kb
Host smart-74888daf-a4d0-4f74-97be-e64c84e5c23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59681712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.59681712
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3311410823
Short name T1248
Test name
Test status
Simulation time 199398297 ps
CPU time 0.93 seconds
Started Jan 24 10:17:24 PM PST 24
Finished Jan 24 10:17:27 PM PST 24
Peak memory 202304 kb
Host smart-de75d578-4a71-42ba-913b-a1b8929f0863
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311410823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3311410823
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2354689141
Short name T994
Test name
Test status
Simulation time 398361828 ps
CPU time 4.96 seconds
Started Jan 24 10:17:39 PM PST 24
Finished Jan 24 10:17:45 PM PST 24
Peak memory 202556 kb
Host smart-67a2163d-b39e-4d48-b53c-d073c49ae8ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354689141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2354689141
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3917641089
Short name T429
Test name
Test status
Simulation time 42870034969 ps
CPU time 341.27 seconds
Started Jan 25 12:00:52 AM PST 24
Finished Jan 25 12:06:36 AM PST 24
Peak memory 1517804 kb
Host smart-3754db9c-e28c-4d95-a550-3306e1c88e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917641089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3917641089
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_override.1194422302
Short name T209
Test name
Test status
Simulation time 55413044 ps
CPU time 0.61 seconds
Started Jan 24 10:17:24 PM PST 24
Finished Jan 24 10:17:27 PM PST 24
Peak memory 201456 kb
Host smart-eeb95bc2-5296-44e9-95fa-de2627ae7229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194422302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1194422302
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.3012138765
Short name T155
Test name
Test status
Simulation time 9103617347 ps
CPU time 9.62 seconds
Started Jan 24 10:17:43 PM PST 24
Finished Jan 24 10:17:53 PM PST 24
Peak memory 218940 kb
Host smart-6bd3b32b-c023-4192-8487-a983b1ce90ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012138765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3012138765
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_rx_oversample.1079479315
Short name T452
Test name
Test status
Simulation time 11270595662 ps
CPU time 201.4 seconds
Started Jan 24 10:17:23 PM PST 24
Finished Jan 24 10:20:47 PM PST 24
Peak memory 379700 kb
Host smart-9c2f68fb-bf6d-4d42-bdb5-6011b9726df2
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079479315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_rx_oversample
.1079479315
Directory /workspace/27.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.4163935236
Short name T718
Test name
Test status
Simulation time 2123049755 ps
CPU time 61.95 seconds
Started Jan 24 10:17:22 PM PST 24
Finished Jan 24 10:18:26 PM PST 24
Peak memory 322352 kb
Host smart-8f62bd0a-623d-4df1-9e62-907a6642dcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163935236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.4163935236
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1736873191
Short name T618
Test name
Test status
Simulation time 16138382905 ps
CPU time 18.2 seconds
Started Jan 24 10:32:31 PM PST 24
Finished Jan 24 10:32:50 PM PST 24
Peak memory 218940 kb
Host smart-56f6d42d-ac4b-4504-ab80-537673f5870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736873191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1736873191
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.818364269
Short name T1059
Test name
Test status
Simulation time 4505433352 ps
CPU time 4.62 seconds
Started Jan 24 10:18:24 PM PST 24
Finished Jan 24 10:18:30 PM PST 24
Peak memory 202652 kb
Host smart-754ebd4c-9987-486e-90c5-9e4be454bd1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818364269 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.818364269
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1804890142
Short name T194
Test name
Test status
Simulation time 10325975770 ps
CPU time 15.04 seconds
Started Jan 24 11:43:52 PM PST 24
Finished Jan 24 11:44:09 PM PST 24
Peak memory 311352 kb
Host smart-f5220e5e-8da9-405b-a369-01989961efad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804890142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1804890142
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2855421440
Short name T1218
Test name
Test status
Simulation time 10149695193 ps
CPU time 27.48 seconds
Started Jan 24 10:18:07 PM PST 24
Finished Jan 24 10:18:35 PM PST 24
Peak memory 434536 kb
Host smart-4ad05cbf-c549-4b6b-a337-ea96b387afbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855421440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2855421440
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1824454258
Short name T798
Test name
Test status
Simulation time 687289278 ps
CPU time 3.17 seconds
Started Jan 24 10:18:22 PM PST 24
Finished Jan 24 10:18:26 PM PST 24
Peak memory 202624 kb
Host smart-54ca2e7a-268c-49e6-995f-3023093d6982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824454258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1824454258
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3924108607
Short name T657
Test name
Test status
Simulation time 1689905140 ps
CPU time 6.44 seconds
Started Jan 24 10:17:47 PM PST 24
Finished Jan 24 10:17:55 PM PST 24
Peak memory 203824 kb
Host smart-9d8fb3e1-59b2-4c4c-bb76-241962056765
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924108607 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3924108607
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3892227567
Short name T381
Test name
Test status
Simulation time 14402736918 ps
CPU time 392.69 seconds
Started Jan 24 10:17:45 PM PST 24
Finished Jan 24 10:24:18 PM PST 24
Peak memory 3226232 kb
Host smart-e411cf16-f215-4dc0-8dc6-b6ac6cad3b3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892227567 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3892227567
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.9848787
Short name T775
Test name
Test status
Simulation time 594225459 ps
CPU time 3.7 seconds
Started Jan 24 10:18:06 PM PST 24
Finished Jan 24 10:18:10 PM PST 24
Peak memory 202696 kb
Host smart-add8e607-312f-4727-b2d3-18102057f2ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9848787 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.i2c_target_perf.9848787
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1585651895
Short name T1170
Test name
Test status
Simulation time 5324731671 ps
CPU time 10.87 seconds
Started Jan 24 10:17:42 PM PST 24
Finished Jan 24 10:17:54 PM PST 24
Peak memory 202604 kb
Host smart-ba4c6e9d-6cf9-479f-b75b-d54c334a7ddb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585651895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1585651895
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3292962454
Short name T1201
Test name
Test status
Simulation time 764613456 ps
CPU time 29.66 seconds
Started Jan 24 10:17:45 PM PST 24
Finished Jan 24 10:18:16 PM PST 24
Peak memory 202656 kb
Host smart-5271528b-c70a-4dac-88aa-46ca340395d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292962454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3292962454
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.4060565873
Short name T417
Test name
Test status
Simulation time 62590719177 ps
CPU time 1710.05 seconds
Started Jan 24 10:17:47 PM PST 24
Finished Jan 24 10:46:18 PM PST 24
Peak memory 7395368 kb
Host smart-347e2fd4-6fdc-48a6-962c-a598ef147e5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060565873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.4060565873
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.604016778
Short name T1497
Test name
Test status
Simulation time 13588288581 ps
CPU time 140.78 seconds
Started Jan 24 10:17:46 PM PST 24
Finished Jan 24 10:20:08 PM PST 24
Peak memory 680124 kb
Host smart-004ab925-92dd-44f8-aaac-667cfd2184fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604016778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_t
arget_stretch.604016778
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2169332576
Short name T1012
Test name
Test status
Simulation time 1694166350 ps
CPU time 7.33 seconds
Started Jan 24 10:17:43 PM PST 24
Finished Jan 24 10:17:51 PM PST 24
Peak memory 202632 kb
Host smart-a8e1fefc-b428-419f-b3f1-0c329c922d2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169332576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2169332576
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.3113226036
Short name T722
Test name
Test status
Simulation time 8661537054 ps
CPU time 7.03 seconds
Started Jan 25 03:20:09 AM PST 24
Finished Jan 25 03:20:17 AM PST 24
Peak memory 206928 kb
Host smart-ebbe45c2-1fea-4252-9275-3d3d1224e21b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113226036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.i2c_target_unexp_stop.3113226036
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/28.i2c_alert_test.944494203
Short name T1227
Test name
Test status
Simulation time 16446438 ps
CPU time 0.59 seconds
Started Jan 24 10:19:14 PM PST 24
Finished Jan 24 10:19:16 PM PST 24
Peak memory 201080 kb
Host smart-1ba5185a-1d05-4a76-a055-748321ed39e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944494203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.944494203
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3000617785
Short name T611
Test name
Test status
Simulation time 35415403 ps
CPU time 1.05 seconds
Started Jan 24 10:18:36 PM PST 24
Finished Jan 24 10:18:38 PM PST 24
Peak memory 202524 kb
Host smart-a72e0411-be08-4e44-ad2a-7a51018bc22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000617785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3000617785
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.374910956
Short name T1377
Test name
Test status
Simulation time 348060430 ps
CPU time 18.5 seconds
Started Jan 24 10:18:20 PM PST 24
Finished Jan 24 10:18:39 PM PST 24
Peak memory 268880 kb
Host smart-f71e8716-36dc-491f-b991-2e5931cf4ed1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374910956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.374910956
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2284069514
Short name T36
Test name
Test status
Simulation time 13738997236 ps
CPU time 298.49 seconds
Started Jan 24 10:18:36 PM PST 24
Finished Jan 24 10:23:36 PM PST 24
Peak memory 1058232 kb
Host smart-feb5a5c3-b05f-4527-b87e-c9d8919f3862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284069514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2284069514
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3481901623
Short name T1047
Test name
Test status
Simulation time 4569447482 ps
CPU time 268.45 seconds
Started Jan 24 10:18:24 PM PST 24
Finished Jan 24 10:22:54 PM PST 24
Peak memory 1266984 kb
Host smart-0df2b85b-2dde-4060-878b-b178a8bf790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481901623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3481901623
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2116222929
Short name T1176
Test name
Test status
Simulation time 147497375 ps
CPU time 0.98 seconds
Started Jan 24 10:18:22 PM PST 24
Finished Jan 24 10:18:24 PM PST 24
Peak memory 202332 kb
Host smart-1e502bf0-5bf2-4ff7-9940-4e0a67699cae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116222929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2116222929
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.3167063859
Short name T1128
Test name
Test status
Simulation time 1215775134 ps
CPU time 4.02 seconds
Started Jan 25 01:53:23 AM PST 24
Finished Jan 25 01:53:28 AM PST 24
Peak memory 202564 kb
Host smart-93b4fbb6-0617-4454-a91c-ad4d53bdb4a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167063859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.3167063859
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3167307435
Short name T284
Test name
Test status
Simulation time 28264842894 ps
CPU time 479.99 seconds
Started Jan 24 11:20:18 PM PST 24
Finished Jan 24 11:28:21 PM PST 24
Peak memory 1815364 kb
Host smart-8594898a-f23b-4727-b679-b37e3ab81aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167307435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3167307435
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2573270528
Short name T900
Test name
Test status
Simulation time 5750737072 ps
CPU time 218.13 seconds
Started Jan 24 10:19:17 PM PST 24
Finished Jan 24 10:22:56 PM PST 24
Peak memory 360952 kb
Host smart-24ccae6f-a1b8-49b7-a7bc-0166fa89ec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573270528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2573270528
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.3130418329
Short name T144
Test name
Test status
Simulation time 66730519 ps
CPU time 0.63 seconds
Started Jan 24 10:18:22 PM PST 24
Finished Jan 24 10:18:24 PM PST 24
Peak memory 202204 kb
Host smart-f34848c2-4cb4-4353-8293-8a941f171a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130418329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3130418329
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1420603792
Short name T713
Test name
Test status
Simulation time 5272788864 ps
CPU time 91.38 seconds
Started Jan 25 01:06:00 AM PST 24
Finished Jan 25 01:07:32 AM PST 24
Peak memory 220540 kb
Host smart-21e1847c-acb8-4594-8c43-ae6e375d4ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420603792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1420603792
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_rx_oversample.926340257
Short name T1018
Test name
Test status
Simulation time 2925533404 ps
CPU time 283.17 seconds
Started Jan 24 10:18:19 PM PST 24
Finished Jan 24 10:23:04 PM PST 24
Peak memory 312496 kb
Host smart-1f2dc9cd-03f0-4325-b9c1-bdf1b2c16aa1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926340257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_rx_oversample.
926340257
Directory /workspace/28.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.3691889537
Short name T351
Test name
Test status
Simulation time 9390720396 ps
CPU time 79.91 seconds
Started Jan 24 10:42:09 PM PST 24
Finished Jan 24 10:43:30 PM PST 24
Peak memory 363008 kb
Host smart-c72f99c9-5cee-49f9-a97a-af2ac63d12f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691889537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3691889537
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.560261280
Short name T1496
Test name
Test status
Simulation time 1027172281 ps
CPU time 23.74 seconds
Started Jan 24 11:46:33 PM PST 24
Finished Jan 24 11:47:00 PM PST 24
Peak memory 210760 kb
Host smart-bcbaab9b-fe11-4806-a7eb-d0359edebdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560261280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.560261280
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1675337588
Short name T1328
Test name
Test status
Simulation time 2340722153 ps
CPU time 4.33 seconds
Started Jan 24 10:50:48 PM PST 24
Finished Jan 24 10:50:53 PM PST 24
Peak memory 202660 kb
Host smart-b2f97d75-cb46-4c05-bae9-0706877d21a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675337588 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1675337588
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.327655099
Short name T1489
Test name
Test status
Simulation time 12115942220 ps
CPU time 3.59 seconds
Started Jan 24 10:18:54 PM PST 24
Finished Jan 24 10:19:02 PM PST 24
Peak memory 209088 kb
Host smart-2edb5147-b7c2-4ad1-b4d0-a3f2dcb2418f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327655099 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.327655099
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.32918046
Short name T430
Test name
Test status
Simulation time 10207680488 ps
CPU time 15.49 seconds
Started Jan 24 10:18:54 PM PST 24
Finished Jan 24 10:19:14 PM PST 24
Peak memory 327440 kb
Host smart-6aacc57e-f676-490a-862a-f381092d7fe8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918046 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_fifo_reset_tx.32918046
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3381551520
Short name T169
Test name
Test status
Simulation time 1090473210 ps
CPU time 2.75 seconds
Started Jan 24 10:18:55 PM PST 24
Finished Jan 24 10:19:01 PM PST 24
Peak memory 202696 kb
Host smart-32d9c77d-9b2c-4760-b046-96bb108237e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381551520 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3381551520
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.324566277
Short name T1458
Test name
Test status
Simulation time 4803611250 ps
CPU time 5.85 seconds
Started Jan 24 10:18:52 PM PST 24
Finished Jan 24 10:19:02 PM PST 24
Peak memory 202664 kb
Host smart-8da3dddf-8ec5-4b3b-8433-4329dcbf91c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324566277 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.324566277
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1519145692
Short name T879
Test name
Test status
Simulation time 3762275398 ps
CPU time 4.41 seconds
Started Jan 24 10:18:54 PM PST 24
Finished Jan 24 10:19:03 PM PST 24
Peak memory 262696 kb
Host smart-a5f230ab-adc8-41a5-add6-6f45fd81f0f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519145692 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1519145692
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.4011430799
Short name T334
Test name
Test status
Simulation time 3830273743 ps
CPU time 4.46 seconds
Started Jan 24 10:18:54 PM PST 24
Finished Jan 24 10:19:03 PM PST 24
Peak memory 202672 kb
Host smart-918750e9-2e72-4942-a89f-fb563598159c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011430799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.4011430799
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1919044371
Short name T1291
Test name
Test status
Simulation time 1050720246 ps
CPU time 13.67 seconds
Started Jan 24 11:16:40 PM PST 24
Finished Jan 24 11:16:57 PM PST 24
Peak memory 202596 kb
Host smart-dff60686-0d10-409f-9eb1-1b19cc79291d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919044371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1919044371
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.2101699979
Short name T815
Test name
Test status
Simulation time 5449954388 ps
CPU time 23.98 seconds
Started Jan 24 10:18:56 PM PST 24
Finished Jan 24 10:19:22 PM PST 24
Peak memory 238496 kb
Host smart-b01a8b1a-6840-45f5-90ed-b829934d5136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101699979 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_stress_all.2101699979
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2306006214
Short name T928
Test name
Test status
Simulation time 763112724 ps
CPU time 11.8 seconds
Started Jan 24 10:18:39 PM PST 24
Finished Jan 24 10:18:52 PM PST 24
Peak memory 205476 kb
Host smart-b7ff134a-5e01-4a8b-ba6e-21afffba0373
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306006214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2306006214
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1260617816
Short name T1277
Test name
Test status
Simulation time 45466862925 ps
CPU time 966.59 seconds
Started Jan 24 10:18:38 PM PST 24
Finished Jan 24 10:34:46 PM PST 24
Peak memory 5290944 kb
Host smart-a86fe394-37e8-4eb8-8cfe-c2fda15e8fbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260617816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1260617816
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2244748429
Short name T1383
Test name
Test status
Simulation time 36127774047 ps
CPU time 3274.37 seconds
Started Jan 24 10:18:39 PM PST 24
Finished Jan 24 11:13:15 PM PST 24
Peak memory 6880252 kb
Host smart-a38d426b-2d31-4ff9-abaa-50a348d92f5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244748429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2244748429
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1632424841
Short name T331
Test name
Test status
Simulation time 1858233422 ps
CPU time 7.66 seconds
Started Jan 24 10:42:00 PM PST 24
Finished Jan 24 10:42:09 PM PST 24
Peak memory 209276 kb
Host smart-bb560195-d2f2-4af2-9794-8769076ae05c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632424841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1632424841
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_ovf.35155769
Short name T631
Test name
Test status
Simulation time 31787343289 ps
CPU time 128.34 seconds
Started Jan 24 10:18:54 PM PST 24
Finished Jan 24 10:21:07 PM PST 24
Peak memory 365536 kb
Host smart-13fa4708-3596-4204-b6d5-5bb75063ffd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35155769 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_tx_ovf.35155769
Directory /workspace/28.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3586596351
Short name T1233
Test name
Test status
Simulation time 16392829 ps
CPU time 0.63 seconds
Started Jan 25 02:07:27 AM PST 24
Finished Jan 25 02:07:28 AM PST 24
Peak memory 201160 kb
Host smart-79a7d78e-c4e1-4f6c-b362-fe53f0158692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586596351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3586596351
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1162172020
Short name T931
Test name
Test status
Simulation time 38864363 ps
CPU time 1.68 seconds
Started Jan 25 02:52:14 AM PST 24
Finished Jan 25 02:52:17 AM PST 24
Peak memory 211972 kb
Host smart-18dd6271-faa3-41fb-8952-fa143b72d128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162172020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1162172020
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.3405424584
Short name T1205
Test name
Test status
Simulation time 384926515 ps
CPU time 7.17 seconds
Started Jan 24 10:19:34 PM PST 24
Finished Jan 24 10:19:42 PM PST 24
Peak memory 231616 kb
Host smart-37176c71-1615-45e6-9885-7dbd6520f46a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405424584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.3405424584
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2246541640
Short name T588
Test name
Test status
Simulation time 6588094793 ps
CPU time 166.52 seconds
Started Jan 24 10:19:31 PM PST 24
Finished Jan 24 10:22:19 PM PST 24
Peak memory 210820 kb
Host smart-9f9abd0a-4b70-4c7a-81ae-de138fe22691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246541640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2246541640
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2919349350
Short name T561
Test name
Test status
Simulation time 16860821611 ps
CPU time 277.76 seconds
Started Jan 24 10:19:34 PM PST 24
Finished Jan 24 10:24:12 PM PST 24
Peak memory 1214276 kb
Host smart-e2c5e53c-83c8-4ef1-b21a-3127b3e1a9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919349350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2919349350
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.2922316875
Short name T566
Test name
Test status
Simulation time 211174824 ps
CPU time 0.92 seconds
Started Jan 24 10:19:30 PM PST 24
Finished Jan 24 10:19:33 PM PST 24
Peak memory 202340 kb
Host smart-8045115c-cafe-44b2-b178-ac71d918d74f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922316875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.2922316875
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.903687427
Short name T522
Test name
Test status
Simulation time 1016670668 ps
CPU time 3.62 seconds
Started Jan 24 10:19:31 PM PST 24
Finished Jan 24 10:19:36 PM PST 24
Peak memory 202528 kb
Host smart-0f1d8cb2-b9d0-4694-92bc-4b1484e5bae6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903687427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
903687427
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1317520993
Short name T1038
Test name
Test status
Simulation time 69899751154 ps
CPU time 214.53 seconds
Started Jan 24 10:19:32 PM PST 24
Finished Jan 24 10:23:07 PM PST 24
Peak memory 1210404 kb
Host smart-7d3f7a62-0e91-499d-8a18-c3330473e801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317520993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1317520993
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.2409548183
Short name T922
Test name
Test status
Simulation time 2769347279 ps
CPU time 102.24 seconds
Started Jan 24 10:20:07 PM PST 24
Finished Jan 24 10:21:52 PM PST 24
Peak memory 363224 kb
Host smart-de23426d-e08f-4e96-b58a-a18102bc9a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409548183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.2409548183
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.1522127481
Short name T145
Test name
Test status
Simulation time 75029825 ps
CPU time 0.64 seconds
Started Jan 24 10:52:00 PM PST 24
Finished Jan 24 10:52:02 PM PST 24
Peak memory 201496 kb
Host smart-628a7bac-2332-45f5-bfb2-997868d929c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522127481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1522127481
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.2838937548
Short name T711
Test name
Test status
Simulation time 3429223322 ps
CPU time 15.19 seconds
Started Jan 24 10:19:30 PM PST 24
Finished Jan 24 10:19:47 PM PST 24
Peak memory 221808 kb
Host smart-b007b75c-7a04-4b04-9f61-b8483bb10011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838937548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2838937548
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_rx_oversample.3525347521
Short name T1119
Test name
Test status
Simulation time 4525132569 ps
CPU time 107.99 seconds
Started Jan 24 10:19:40 PM PST 24
Finished Jan 24 10:21:29 PM PST 24
Peak memory 308608 kb
Host smart-bb02fcb6-f3b5-4cbf-931d-f314f7fb80d2
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525347521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_rx_oversample
.3525347521
Directory /workspace/29.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3465318054
Short name T691
Test name
Test status
Simulation time 4602606514 ps
CPU time 133.81 seconds
Started Jan 24 10:19:16 PM PST 24
Finished Jan 24 10:21:31 PM PST 24
Peak memory 243464 kb
Host smart-fd200a45-c5fc-44c0-a9f0-aafac4d0add9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465318054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3465318054
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.1328554559
Short name T555
Test name
Test status
Simulation time 1167229613 ps
CPU time 20.78 seconds
Started Jan 24 10:19:31 PM PST 24
Finished Jan 24 10:19:53 PM PST 24
Peak memory 218932 kb
Host smart-b0cc0a1b-4759-43bc-8b2b-40496beafb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328554559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1328554559
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.901498146
Short name T869
Test name
Test status
Simulation time 1505427705 ps
CPU time 5.71 seconds
Started Jan 24 10:20:08 PM PST 24
Finished Jan 24 10:20:19 PM PST 24
Peak memory 202528 kb
Host smart-32690e00-b213-4504-9f3a-92781ec41cea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901498146 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.901498146
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.4158323735
Short name T386
Test name
Test status
Simulation time 10163318035 ps
CPU time 56.68 seconds
Started Jan 24 10:19:47 PM PST 24
Finished Jan 24 10:20:45 PM PST 24
Peak memory 512892 kb
Host smart-15b24ade-42c1-4289-b044-84ee1f4a4658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158323735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.4158323735
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1214338554
Short name T377
Test name
Test status
Simulation time 10025499059 ps
CPU time 72.21 seconds
Started Jan 24 10:54:08 PM PST 24
Finished Jan 24 10:55:22 PM PST 24
Peak memory 541972 kb
Host smart-c64357aa-92b1-476e-a176-36e77e402828
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214338554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1214338554
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.3149368310
Short name T1446
Test name
Test status
Simulation time 535727414 ps
CPU time 2.75 seconds
Started Jan 24 10:20:08 PM PST 24
Finished Jan 24 10:20:15 PM PST 24
Peak memory 202664 kb
Host smart-b7bfd876-971f-44e6-adf6-c0113533b3f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149368310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.3149368310
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.541537073
Short name T1511
Test name
Test status
Simulation time 2566600209 ps
CPU time 8.15 seconds
Started Jan 24 11:11:16 PM PST 24
Finished Jan 24 11:11:25 PM PST 24
Peak memory 208880 kb
Host smart-6a5232b8-9348-40a6-81da-28db04d3e770
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541537073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.541537073
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2025924476
Short name T1464
Test name
Test status
Simulation time 13630444530 ps
CPU time 50.54 seconds
Started Jan 24 10:19:46 PM PST 24
Finished Jan 24 10:20:38 PM PST 24
Peak memory 866012 kb
Host smart-0db485e3-b2e2-48d9-bfb0-ccb8085e63eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025924476 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2025924476
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.1720770102
Short name T1173
Test name
Test status
Simulation time 846155154 ps
CPU time 4.85 seconds
Started Jan 24 10:20:06 PM PST 24
Finished Jan 24 10:20:15 PM PST 24
Peak memory 205120 kb
Host smart-c7e6d701-75da-4f2b-b6b1-39e99df3a0be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720770102 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.1720770102
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.3508805968
Short name T1239
Test name
Test status
Simulation time 1045806104 ps
CPU time 25.56 seconds
Started Jan 24 10:19:50 PM PST 24
Finished Jan 24 10:20:17 PM PST 24
Peak memory 202568 kb
Host smart-b0ca86b2-3daf-43e8-a760-7fe9ddab2551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508805968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.3508805968
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.4108085051
Short name T332
Test name
Test status
Simulation time 40984570917 ps
CPU time 1442.46 seconds
Started Jan 24 11:03:44 PM PST 24
Finished Jan 24 11:27:48 PM PST 24
Peak memory 6753108 kb
Host smart-db52d5d8-850b-4e15-8277-2c04593aaff8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108085051 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.4108085051
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3786685947
Short name T957
Test name
Test status
Simulation time 2620144404 ps
CPU time 51.84 seconds
Started Jan 24 10:19:50 PM PST 24
Finished Jan 24 10:20:44 PM PST 24
Peak memory 202620 kb
Host smart-22589c24-7bf1-46fa-83eb-fc39e906d4c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786685947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3786685947
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2382663080
Short name T56
Test name
Test status
Simulation time 61831026522 ps
CPU time 2109.64 seconds
Started Jan 25 12:44:43 AM PST 24
Finished Jan 25 01:19:54 AM PST 24
Peak memory 7297224 kb
Host smart-7f925d93-9bc5-40a9-ada6-e226a8ba6bff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382663080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2382663080
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.3086183856
Short name T389
Test name
Test status
Simulation time 20833339637 ps
CPU time 151.75 seconds
Started Jan 24 10:19:48 PM PST 24
Finished Jan 24 10:22:21 PM PST 24
Peak memory 1188812 kb
Host smart-0362ec59-5271-4e95-b92d-8e80bb06a9fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086183856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.3086183856
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.1014767111
Short name T747
Test name
Test status
Simulation time 3458820306 ps
CPU time 8.06 seconds
Started Jan 24 10:19:47 PM PST 24
Finished Jan 24 10:19:57 PM PST 24
Peak memory 210128 kb
Host smart-ca87b1c8-3795-43b6-a3f2-8cff9d8b9459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014767111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.1014767111
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_ovf.2973626647
Short name T196
Test name
Test status
Simulation time 7870428055 ps
CPU time 86.98 seconds
Started Jan 24 10:19:48 PM PST 24
Finished Jan 24 10:21:17 PM PST 24
Peak memory 331560 kb
Host smart-deb1df16-e82a-4239-ba2d-1b39e06722b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973626647 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_tx_ovf.2973626647
Directory /workspace/29.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.1994909772
Short name T648
Test name
Test status
Simulation time 1265326193 ps
CPU time 5.28 seconds
Started Jan 24 10:19:47 PM PST 24
Finished Jan 24 10:19:54 PM PST 24
Peak memory 202656 kb
Host smart-7efb05cb-0569-4971-8386-c45636b81653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994909772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.i2c_target_unexp_stop.1994909772
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.819684369
Short name T589
Test name
Test status
Simulation time 15857670 ps
CPU time 0.62 seconds
Started Jan 24 09:56:38 PM PST 24
Finished Jan 24 09:56:39 PM PST 24
Peak memory 201112 kb
Host smart-697af00b-8f48-436f-a5c1-ac05b3053e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819684369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.819684369
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.2959735980
Short name T576
Test name
Test status
Simulation time 193363641 ps
CPU time 1.51 seconds
Started Jan 24 09:56:15 PM PST 24
Finished Jan 24 09:56:18 PM PST 24
Peak memory 210764 kb
Host smart-b6780861-ecb9-42a9-9048-20be67e6d27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959735980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.2959735980
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.664831379
Short name T1019
Test name
Test status
Simulation time 2452421005 ps
CPU time 7.96 seconds
Started Jan 24 09:56:17 PM PST 24
Finished Jan 24 09:56:26 PM PST 24
Peak memory 245304 kb
Host smart-006fc870-cebd-45c4-a6e4-2f89eed8eb26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664831379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.664831379
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3473418806
Short name T1475
Test name
Test status
Simulation time 7129189072 ps
CPU time 94.1 seconds
Started Jan 24 09:56:26 PM PST 24
Finished Jan 24 09:58:02 PM PST 24
Peak memory 771832 kb
Host smart-4df50d00-450d-41b9-a5d8-0d1a312170dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473418806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3473418806
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.3381951656
Short name T666
Test name
Test status
Simulation time 4857266258 ps
CPU time 606 seconds
Started Jan 24 09:56:16 PM PST 24
Finished Jan 24 10:06:23 PM PST 24
Peak memory 1364024 kb
Host smart-ffd2827b-8498-4393-bfea-83c2891276de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381951656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.3381951656
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1306532051
Short name T919
Test name
Test status
Simulation time 471940462 ps
CPU time 0.97 seconds
Started Jan 24 09:56:17 PM PST 24
Finished Jan 24 09:56:19 PM PST 24
Peak memory 202356 kb
Host smart-9aa599e0-9663-4991-88c2-355929c91210
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306532051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1306532051
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.481864753
Short name T1130
Test name
Test status
Simulation time 785188495 ps
CPU time 11.87 seconds
Started Jan 24 09:56:14 PM PST 24
Finished Jan 24 09:56:27 PM PST 24
Peak memory 242168 kb
Host smart-94a29f96-12bc-4264-9205-98c2877c700b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481864753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.481864753
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.4096280860
Short name T873
Test name
Test status
Simulation time 8246263508 ps
CPU time 427.49 seconds
Started Jan 24 09:56:15 PM PST 24
Finished Jan 24 10:03:23 PM PST 24
Peak memory 1190500 kb
Host smart-6d8bdba2-86b9-4bdc-988b-bd9f6e912342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096280860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.4096280860
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.338370899
Short name T904
Test name
Test status
Simulation time 13594243202 ps
CPU time 283.53 seconds
Started Jan 24 09:56:51 PM PST 24
Finished Jan 24 10:01:36 PM PST 24
Peak memory 345820 kb
Host smart-f0744c44-6e3d-447d-83bb-916837792a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338370899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.338370899
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.76404172
Short name T1457
Test name
Test status
Simulation time 60441482 ps
CPU time 0.62 seconds
Started Jan 24 09:56:04 PM PST 24
Finished Jan 24 09:56:05 PM PST 24
Peak memory 201504 kb
Host smart-43d8a56a-e395-40b5-b8b4-2d2350aef66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76404172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.76404172
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3638398986
Short name T1478
Test name
Test status
Simulation time 7646355848 ps
CPU time 22.5 seconds
Started Jan 24 09:56:26 PM PST 24
Finished Jan 24 09:56:50 PM PST 24
Peak memory 222080 kb
Host smart-0b1a865a-f297-421b-9486-09a74865a3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638398986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3638398986
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_rx_oversample.1105914203
Short name T190
Test name
Test status
Simulation time 1553564253 ps
CPU time 54.51 seconds
Started Jan 24 09:56:04 PM PST 24
Finished Jan 24 09:57:00 PM PST 24
Peak memory 260100 kb
Host smart-50fd88f9-2166-4e67-8ef7-86ff2fb41a52
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105914203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_rx_oversample.
1105914203
Directory /workspace/3.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3338662132
Short name T1445
Test name
Test status
Simulation time 2170882774 ps
CPU time 118.12 seconds
Started Jan 24 09:56:05 PM PST 24
Finished Jan 24 09:58:05 PM PST 24
Peak memory 243516 kb
Host smart-1709bbc7-2ba9-4b58-9eb2-744df071d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338662132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3338662132
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.2617213584
Short name T1007
Test name
Test status
Simulation time 735341801 ps
CPU time 30.67 seconds
Started Jan 24 09:56:14 PM PST 24
Finished Jan 24 09:56:45 PM PST 24
Peak memory 210736 kb
Host smart-9452158c-d4ea-45a9-bc71-506f62e60891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617213584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.2617213584
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.767886251
Short name T79
Test name
Test status
Simulation time 112429122 ps
CPU time 0.93 seconds
Started Jan 25 04:46:40 AM PST 24
Finished Jan 25 04:46:46 AM PST 24
Peak memory 219356 kb
Host smart-73999c6f-4499-40f2-86db-2493c517c2ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767886251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.767886251
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1175060419
Short name T680
Test name
Test status
Simulation time 3239434785 ps
CPU time 4.81 seconds
Started Jan 24 09:56:29 PM PST 24
Finished Jan 24 09:56:36 PM PST 24
Peak memory 202084 kb
Host smart-1e40ba22-be04-4bda-b0a9-3b83fffdf80f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175060419 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1175060419
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.326780048
Short name T748
Test name
Test status
Simulation time 10660643841 ps
CPU time 9.52 seconds
Started Jan 24 09:56:28 PM PST 24
Finished Jan 24 09:56:38 PM PST 24
Peak memory 248256 kb
Host smart-45b365e4-c013-4e23-8b39-ae31883d3287
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326780048 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.326780048
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1377933320
Short name T268
Test name
Test status
Simulation time 10038740154 ps
CPU time 59.4 seconds
Started Jan 24 09:56:27 PM PST 24
Finished Jan 24 09:57:27 PM PST 24
Peak memory 592132 kb
Host smart-b65a6947-08ec-48ae-a466-bcbac3a6edc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377933320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1377933320
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.2029328009
Short name T161
Test name
Test status
Simulation time 751081723 ps
CPU time 2.15 seconds
Started Jan 24 09:56:45 PM PST 24
Finished Jan 24 09:56:49 PM PST 24
Peak memory 202640 kb
Host smart-25df45e4-012c-4afb-89fb-a31771cd2016
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029328009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.2029328009
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3188312242
Short name T914
Test name
Test status
Simulation time 4382207411 ps
CPU time 4.6 seconds
Started Jan 24 09:56:24 PM PST 24
Finished Jan 24 09:56:30 PM PST 24
Peak memory 203160 kb
Host smart-d20422ab-a10d-4ac3-913e-4c5c4cd642f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188312242 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3188312242
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2872535450
Short name T437
Test name
Test status
Simulation time 16590316896 ps
CPU time 231.83 seconds
Started Jan 24 09:56:30 PM PST 24
Finished Jan 24 10:00:24 PM PST 24
Peak memory 2119840 kb
Host smart-93347df6-36e9-4b8e-9846-ce87699ed1bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872535450 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2872535450
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.3120640999
Short name T333
Test name
Test status
Simulation time 5657095266 ps
CPU time 5.14 seconds
Started Jan 24 09:56:29 PM PST 24
Finished Jan 24 09:56:36 PM PST 24
Peak memory 208980 kb
Host smart-b6f27286-464a-4042-94b6-cf8d01efe5bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120640999 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.3120640999
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1606206783
Short name T1358
Test name
Test status
Simulation time 1526704257 ps
CPU time 14.85 seconds
Started Jan 24 09:56:29 PM PST 24
Finished Jan 24 09:56:46 PM PST 24
Peak memory 202280 kb
Host smart-5f85923c-3b46-4f04-b9ef-8145d5be171f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606206783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1606206783
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.1675890267
Short name T640
Test name
Test status
Simulation time 87098108545 ps
CPU time 949.13 seconds
Started Jan 24 09:56:25 PM PST 24
Finished Jan 24 10:12:15 PM PST 24
Peak memory 1485184 kb
Host smart-edfa99a0-188b-44b1-b1b4-51692274f1b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675890267 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.1675890267
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.4119813021
Short name T375
Test name
Test status
Simulation time 518814681 ps
CPU time 8.77 seconds
Started Jan 24 09:56:28 PM PST 24
Finished Jan 24 09:56:37 PM PST 24
Peak memory 204064 kb
Host smart-896ba413-41df-4cb7-9384-b23fd66b5c3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119813021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.4119813021
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.4052173223
Short name T672
Test name
Test status
Simulation time 58763423889 ps
CPU time 539.08 seconds
Started Jan 24 09:56:24 PM PST 24
Finished Jan 24 10:05:25 PM PST 24
Peak memory 3318564 kb
Host smart-6618df8c-e75f-4507-809a-eccb45f92564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052173223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.4052173223
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.315207451
Short name T211
Test name
Test status
Simulation time 20526353046 ps
CPU time 332.42 seconds
Started Jan 24 09:56:28 PM PST 24
Finished Jan 24 10:02:01 PM PST 24
Peak memory 2273300 kb
Host smart-9ddbfce6-7c10-4ef6-9c65-3c02ce54c248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315207451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.315207451
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1458967337
Short name T902
Test name
Test status
Simulation time 6093092644 ps
CPU time 7.31 seconds
Started Jan 24 09:56:27 PM PST 24
Finished Jan 24 09:56:36 PM PST 24
Peak memory 213816 kb
Host smart-8f42c582-85d3-49a8-8150-b4f894d1ea0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458967337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1458967337
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_ovf.1355019422
Short name T489
Test name
Test status
Simulation time 16245118107 ps
CPU time 48.05 seconds
Started Jan 24 09:56:29 PM PST 24
Finished Jan 24 09:57:19 PM PST 24
Peak memory 291372 kb
Host smart-d5924f4d-09c8-44f1-9d94-e1de081c3379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355019422 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_tx_ovf.1355019422
Directory /workspace/3.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.995014882
Short name T592
Test name
Test status
Simulation time 1329958989 ps
CPU time 8.35 seconds
Started Jan 24 09:56:25 PM PST 24
Finished Jan 24 09:56:35 PM PST 24
Peak memory 202544 kb
Host smart-c5f41807-c83e-4e84-9912-594652bf1507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995014882 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_unexp_stop.995014882
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2679521128
Short name T1023
Test name
Test status
Simulation time 19704613 ps
CPU time 0.62 seconds
Started Jan 24 10:21:00 PM PST 24
Finished Jan 24 10:21:02 PM PST 24
Peak memory 201148 kb
Host smart-aa7751e5-d5c6-4c24-b669-2260d1c77865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679521128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2679521128
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1528540016
Short name T909
Test name
Test status
Simulation time 210154245 ps
CPU time 1.07 seconds
Started Jan 24 10:20:25 PM PST 24
Finished Jan 24 10:20:28 PM PST 24
Peak memory 202580 kb
Host smart-e57dd940-92bf-4a92-bb87-30760a1cb220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528540016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1528540016
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3510750109
Short name T851
Test name
Test status
Simulation time 738643082 ps
CPU time 9.65 seconds
Started Jan 24 10:20:30 PM PST 24
Finished Jan 24 10:20:42 PM PST 24
Peak memory 295328 kb
Host smart-7c275360-4cab-466e-ac59-d7b01d37477a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510750109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3510750109
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.3399495770
Short name T1302
Test name
Test status
Simulation time 7439895274 ps
CPU time 46.31 seconds
Started Jan 24 10:20:25 PM PST 24
Finished Jan 24 10:21:12 PM PST 24
Peak memory 448008 kb
Host smart-502336cb-8e67-4431-be26-cbfcba5247fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399495770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3399495770
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3175892318
Short name T14
Test name
Test status
Simulation time 12210790873 ps
CPU time 506.19 seconds
Started Jan 24 10:20:27 PM PST 24
Finished Jan 24 10:28:55 PM PST 24
Peak memory 1188696 kb
Host smart-b303f821-4ee8-4ed8-9a1f-0f1754165e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175892318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3175892318
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2403617234
Short name T198
Test name
Test status
Simulation time 1072607840 ps
CPU time 1.16 seconds
Started Jan 24 10:20:30 PM PST 24
Finished Jan 24 10:20:34 PM PST 24
Peak memory 202032 kb
Host smart-6f2bf75f-9735-4a4c-8562-229aaebd27cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403617234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2403617234
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3422790537
Short name T423
Test name
Test status
Simulation time 158524177 ps
CPU time 9.83 seconds
Started Jan 24 10:20:28 PM PST 24
Finished Jan 24 10:20:40 PM PST 24
Peak memory 230948 kb
Host smart-07fcc301-4a17-4d72-84ba-ea0d87ded0a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422790537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3422790537
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1193006870
Short name T248
Test name
Test status
Simulation time 7987478178 ps
CPU time 194.44 seconds
Started Jan 24 10:20:27 PM PST 24
Finished Jan 24 10:23:44 PM PST 24
Peak memory 1163896 kb
Host smart-b14186ca-cc3c-4b24-8427-576d4fc6d34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193006870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1193006870
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_override.837593850
Short name T1284
Test name
Test status
Simulation time 50947343 ps
CPU time 0.61 seconds
Started Jan 24 11:15:23 PM PST 24
Finished Jan 24 11:15:25 PM PST 24
Peak memory 201496 kb
Host smart-5172be6a-a752-4758-bbf0-a7f2a5c2bdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837593850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.837593850
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2153013560
Short name T1235
Test name
Test status
Simulation time 3290660279 ps
CPU time 30.87 seconds
Started Jan 24 10:20:28 PM PST 24
Finished Jan 24 10:21:01 PM PST 24
Peak memory 227116 kb
Host smart-ac317523-513a-4d51-8b05-24745df02d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153013560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2153013560
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_rx_oversample.765945311
Short name T253
Test name
Test status
Simulation time 4237984178 ps
CPU time 76.28 seconds
Started Jan 24 10:20:09 PM PST 24
Finished Jan 24 10:21:29 PM PST 24
Peak memory 283872 kb
Host smart-630d8a79-b926-4cba-acba-9182c6dcd037
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765945311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_rx_oversample.
765945311
Directory /workspace/30.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3220050626
Short name T1042
Test name
Test status
Simulation time 2903919092 ps
CPU time 120.85 seconds
Started Jan 24 10:40:58 PM PST 24
Finished Jan 24 10:43:01 PM PST 24
Peak memory 272832 kb
Host smart-a44cf609-983c-4246-acc0-42226af701aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220050626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3220050626
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.1916099614
Short name T682
Test name
Test status
Simulation time 16076707124 ps
CPU time 12.38 seconds
Started Jan 24 10:20:30 PM PST 24
Finished Jan 24 10:20:45 PM PST 24
Peak memory 218448 kb
Host smart-f2328cd3-42a2-47bc-a9f3-5d99c4bfe229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916099614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1916099614
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1822330211
Short name T340
Test name
Test status
Simulation time 9052827880 ps
CPU time 6.06 seconds
Started Jan 24 10:21:01 PM PST 24
Finished Jan 24 10:21:08 PM PST 24
Peak memory 202752 kb
Host smart-9d4e8cce-f8ce-4e04-94dc-7a774de9fa04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822330211 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1822330211
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2523157214
Short name T1423
Test name
Test status
Simulation time 10035046684 ps
CPU time 48.41 seconds
Started Jan 24 10:20:46 PM PST 24
Finished Jan 24 10:21:36 PM PST 24
Peak memory 449728 kb
Host smart-642f02cd-0bed-4f92-a495-c2b348288d19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523157214 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2523157214
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.4028145935
Short name T318
Test name
Test status
Simulation time 10147176833 ps
CPU time 65.68 seconds
Started Jan 24 10:20:46 PM PST 24
Finished Jan 24 10:21:53 PM PST 24
Peak memory 544948 kb
Host smart-e9d66382-602d-42cf-ab1e-3c92a780387c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028145935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.4028145935
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.1972923964
Short name T267
Test name
Test status
Simulation time 1991926073 ps
CPU time 2.47 seconds
Started Jan 24 10:20:59 PM PST 24
Finished Jan 24 10:21:02 PM PST 24
Peak memory 202644 kb
Host smart-5a723be8-3993-4412-ac7f-19847a775592
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972923964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.1972923964
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.686501619
Short name T1193
Test name
Test status
Simulation time 1052994460 ps
CPU time 5.1 seconds
Started Jan 24 10:20:42 PM PST 24
Finished Jan 24 10:20:48 PM PST 24
Peak memory 207152 kb
Host smart-ff74fab5-915d-4a22-9bda-10632fcdaa6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686501619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.686501619
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.2553828783
Short name T1440
Test name
Test status
Simulation time 65630731585 ps
CPU time 1943.41 seconds
Started Jan 24 10:20:41 PM PST 24
Finished Jan 24 10:53:06 PM PST 24
Peak memory 7902352 kb
Host smart-f8598d54-d0d8-40c5-a851-1ada2f684c66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553828783 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.2553828783
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.976413147
Short name T394
Test name
Test status
Simulation time 4694604275 ps
CPU time 3.2 seconds
Started Jan 24 10:20:45 PM PST 24
Finished Jan 24 10:20:49 PM PST 24
Peak memory 202668 kb
Host smart-c82644d2-1360-46ae-a6a3-ddcf9049227a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976413147 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_perf.976413147
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1850685256
Short name T212
Test name
Test status
Simulation time 987027090 ps
CPU time 9.94 seconds
Started Jan 24 10:20:24 PM PST 24
Finished Jan 24 10:20:35 PM PST 24
Peak memory 202524 kb
Host smart-b9bcaacb-a36a-4c7c-b95b-dfe4e58ed78d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850685256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1850685256
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.3442918204
Short name T941
Test name
Test status
Simulation time 32192220824 ps
CPU time 907.86 seconds
Started Jan 24 10:20:56 PM PST 24
Finished Jan 24 10:36:04 PM PST 24
Peak memory 3910356 kb
Host smart-25f13fbb-bbe0-4946-bf06-d6be7dc4a819
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442918204 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.3442918204
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2796000873
Short name T1172
Test name
Test status
Simulation time 6445215567 ps
CPU time 23.65 seconds
Started Jan 24 10:20:41 PM PST 24
Finished Jan 24 10:21:06 PM PST 24
Peak memory 227152 kb
Host smart-d0e0e42e-0e23-4957-bf3e-1334a3cd5399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796000873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2796000873
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.2024110184
Short name T710
Test name
Test status
Simulation time 50823049599 ps
CPU time 477.4 seconds
Started Jan 24 10:20:45 PM PST 24
Finished Jan 24 10:28:44 PM PST 24
Peak memory 3424068 kb
Host smart-14db18c9-ca22-4a98-a2c4-98652949a897
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024110184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.2024110184
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.4149899854
Short name T217
Test name
Test status
Simulation time 22590184004 ps
CPU time 1255.07 seconds
Started Jan 24 10:20:45 PM PST 24
Finished Jan 24 10:41:41 PM PST 24
Peak memory 2723960 kb
Host smart-86f15a35-5ebf-4268-8953-f82369952355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149899854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.4149899854
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.661156302
Short name T415
Test name
Test status
Simulation time 16424356008 ps
CPU time 5.69 seconds
Started Jan 24 10:20:41 PM PST 24
Finished Jan 24 10:20:48 PM PST 24
Peak memory 202704 kb
Host smart-8cd84506-4986-4c19-b935-e95ffa131321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661156302 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.661156302
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_ovf.989650016
Short name T696
Test name
Test status
Simulation time 6765305436 ps
CPU time 176.62 seconds
Started Jan 24 10:20:43 PM PST 24
Finished Jan 24 10:23:41 PM PST 24
Peak memory 420732 kb
Host smart-664cef8c-fcf0-47ae-bff6-b79b6a75bee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989650016 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_tx_ovf.989650016
Directory /workspace/30.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.1772293777
Short name T409
Test name
Test status
Simulation time 7982685509 ps
CPU time 5.72 seconds
Started Jan 24 10:40:03 PM PST 24
Finished Jan 24 10:40:09 PM PST 24
Peak memory 207952 kb
Host smart-210b872c-0dab-420a-af77-77d77fbafea5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772293777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.1772293777
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1072795816
Short name T1078
Test name
Test status
Simulation time 47200643 ps
CPU time 0.61 seconds
Started Jan 24 10:22:18 PM PST 24
Finished Jan 24 10:22:21 PM PST 24
Peak memory 201136 kb
Host smart-8760661d-9389-4dc1-a625-64a3e4971240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072795816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1072795816
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1075290595
Short name T1420
Test name
Test status
Simulation time 115476041 ps
CPU time 1.68 seconds
Started Jan 24 10:21:41 PM PST 24
Finished Jan 24 10:21:44 PM PST 24
Peak memory 202568 kb
Host smart-b0ab5aee-56f7-415f-ac05-dbb08a3d076d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075290595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1075290595
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3503632879
Short name T626
Test name
Test status
Simulation time 809668867 ps
CPU time 18.87 seconds
Started Jan 24 10:21:18 PM PST 24
Finished Jan 24 10:21:37 PM PST 24
Peak memory 383176 kb
Host smart-a527590c-0ec8-428b-ac84-d4fb62397b9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503632879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3503632879
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1032123111
Short name T1379
Test name
Test status
Simulation time 2045523528 ps
CPU time 79.93 seconds
Started Jan 24 10:36:21 PM PST 24
Finished Jan 24 10:37:42 PM PST 24
Peak memory 690508 kb
Host smart-510dd4c4-5578-4a8a-9056-119a821bfd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032123111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1032123111
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2647343222
Short name T946
Test name
Test status
Simulation time 30511970300 ps
CPU time 741.17 seconds
Started Jan 24 10:21:20 PM PST 24
Finished Jan 24 10:33:42 PM PST 24
Peak memory 1640172 kb
Host smart-251044e3-0215-4d9c-bee7-a08af46b38d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647343222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2647343222
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2911626248
Short name T788
Test name
Test status
Simulation time 125116435 ps
CPU time 1 seconds
Started Jan 24 10:21:17 PM PST 24
Finished Jan 24 10:21:19 PM PST 24
Peak memory 202340 kb
Host smart-51e399d5-06d5-4d8d-a1a4-2c6f07b0102a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911626248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2911626248
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.3900471763
Short name T1029
Test name
Test status
Simulation time 593977105 ps
CPU time 10.27 seconds
Started Jan 24 10:21:18 PM PST 24
Finished Jan 24 10:21:29 PM PST 24
Peak memory 233120 kb
Host smart-b79805c2-7f0e-42ab-b360-4ffa834f2936
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900471763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.3900471763
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1318001442
Short name T183
Test name
Test status
Simulation time 25246633076 ps
CPU time 331.37 seconds
Started Jan 24 10:21:18 PM PST 24
Finished Jan 24 10:26:50 PM PST 24
Peak memory 1704264 kb
Host smart-597fd9fd-afc3-4daa-9f5b-4a31385f9d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318001442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1318001442
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.4007430026
Short name T647
Test name
Test status
Simulation time 7752374395 ps
CPU time 152.98 seconds
Started Jan 25 02:48:17 AM PST 24
Finished Jan 25 02:50:51 AM PST 24
Peak memory 324024 kb
Host smart-5998308d-e093-4c3d-9a45-961936be4892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007430026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.4007430026
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1670863594
Short name T1476
Test name
Test status
Simulation time 19457900 ps
CPU time 0.65 seconds
Started Jan 24 10:20:59 PM PST 24
Finished Jan 24 10:21:01 PM PST 24
Peak memory 201508 kb
Host smart-1ab86a0f-25c7-44c4-b88c-957c23e61428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670863594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1670863594
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1060086567
Short name T1336
Test name
Test status
Simulation time 15192180553 ps
CPU time 44.82 seconds
Started Jan 24 10:53:56 PM PST 24
Finished Jan 24 10:54:42 PM PST 24
Peak memory 218820 kb
Host smart-ce8b346d-6cd8-42f1-9782-555f6512b97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060086567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1060086567
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_rx_oversample.4138083634
Short name T181
Test name
Test status
Simulation time 11261053297 ps
CPU time 302.83 seconds
Started Jan 25 12:55:17 AM PST 24
Finished Jan 25 01:00:20 AM PST 24
Peak memory 310932 kb
Host smart-8fa85bd9-bc3d-4c80-b2a2-2d679e484493
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138083634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_rx_oversample
.4138083634
Directory /workspace/31.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1363974605
Short name T1385
Test name
Test status
Simulation time 21319315957 ps
CPU time 71.38 seconds
Started Jan 24 10:20:57 PM PST 24
Finished Jan 24 10:22:10 PM PST 24
Peak memory 235392 kb
Host smart-c4ba9564-f6e1-4c36-84f7-865c9de117c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363974605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1363974605
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.592282043
Short name T996
Test name
Test status
Simulation time 822020402 ps
CPU time 15.33 seconds
Started Jan 24 10:21:37 PM PST 24
Finished Jan 24 10:21:53 PM PST 24
Peak memory 218632 kb
Host smart-0e290990-55b8-4342-a013-3a95c21e6fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592282043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.592282043
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.382604079
Short name T524
Test name
Test status
Simulation time 719987046 ps
CPU time 3.31 seconds
Started Jan 25 03:14:09 AM PST 24
Finished Jan 25 03:14:13 AM PST 24
Peak memory 202656 kb
Host smart-938a9b2c-a131-4cdd-bbe1-99de47b36f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382604079 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.382604079
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2536227024
Short name T1513
Test name
Test status
Simulation time 10053717426 ps
CPU time 59.17 seconds
Started Jan 24 10:21:58 PM PST 24
Finished Jan 24 10:22:58 PM PST 24
Peak memory 471316 kb
Host smart-16e3f5ad-d3ad-425e-a1bb-87e60ebb361b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536227024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2536227024
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2074968228
Short name T676
Test name
Test status
Simulation time 10065636955 ps
CPU time 67.99 seconds
Started Jan 24 10:21:59 PM PST 24
Finished Jan 24 10:23:07 PM PST 24
Peak memory 579300 kb
Host smart-cd9cb28f-9a86-4e09-b76b-a3b4fd6d877a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074968228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2074968228
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1841742584
Short name T174
Test name
Test status
Simulation time 980589655 ps
CPU time 2.32 seconds
Started Jan 24 10:21:56 PM PST 24
Finished Jan 24 10:22:01 PM PST 24
Peak memory 202668 kb
Host smart-b80bee84-ac15-48e4-8c09-675f0d46c4db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841742584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1841742584
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3457161948
Short name T439
Test name
Test status
Simulation time 6733011758 ps
CPU time 6.25 seconds
Started Jan 24 10:34:28 PM PST 24
Finished Jan 24 10:34:36 PM PST 24
Peak memory 204140 kb
Host smart-3b978462-57b8-4245-b7e9-d2b9bded001d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457161948 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3457161948
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.370526594
Short name T849
Test name
Test status
Simulation time 23056589811 ps
CPU time 1204.02 seconds
Started Jan 24 10:21:56 PM PST 24
Finished Jan 24 10:42:03 PM PST 24
Peak memory 5499304 kb
Host smart-2cb5c1bd-bb2e-450d-b8be-e3f3abb1c608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370526594 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.370526594
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_perf.2757805816
Short name T254
Test name
Test status
Simulation time 1026629441 ps
CPU time 6.3 seconds
Started Jan 24 10:21:57 PM PST 24
Finished Jan 24 10:22:05 PM PST 24
Peak memory 212568 kb
Host smart-58cb828f-2568-45f9-b831-c880888f0f04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757805816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.2757805816
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3436257907
Short name T374
Test name
Test status
Simulation time 1130004536 ps
CPU time 26.86 seconds
Started Jan 24 10:21:38 PM PST 24
Finished Jan 24 10:22:06 PM PST 24
Peak memory 202564 kb
Host smart-94cbddfa-6cbd-4932-867a-c214a684480a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436257907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3436257907
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.2201495185
Short name T1100
Test name
Test status
Simulation time 57471056694 ps
CPU time 1188.7 seconds
Started Jan 24 10:21:58 PM PST 24
Finished Jan 24 10:41:48 PM PST 24
Peak memory 1068900 kb
Host smart-1f7507a6-e838-4b1c-8e8b-e5a62b5dbfc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201495185 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.2201495185
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.4282552833
Short name T1207
Test name
Test status
Simulation time 640069336 ps
CPU time 8.3 seconds
Started Jan 24 10:21:36 PM PST 24
Finished Jan 24 10:21:45 PM PST 24
Peak memory 202580 kb
Host smart-c1290953-3a8a-4df1-9ec7-0228a31d3a45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282552833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.4282552833
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2991359294
Short name T1334
Test name
Test status
Simulation time 45171278875 ps
CPU time 48.83 seconds
Started Jan 24 10:21:36 PM PST 24
Finished Jan 24 10:22:26 PM PST 24
Peak memory 761964 kb
Host smart-3c1216d7-4c60-4582-a6ad-c98e06a0d68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991359294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2991359294
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.1749427667
Short name T927
Test name
Test status
Simulation time 7962501035 ps
CPU time 7.39 seconds
Started Jan 24 10:21:59 PM PST 24
Finished Jan 24 10:22:07 PM PST 24
Peak memory 202692 kb
Host smart-3a12beff-2bd7-4876-a2df-d137c4d2d8c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749427667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.1749427667
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_ovf.2871247409
Short name T762
Test name
Test status
Simulation time 4061540869 ps
CPU time 37.3 seconds
Started Jan 24 10:21:58 PM PST 24
Finished Jan 24 10:22:36 PM PST 24
Peak memory 219548 kb
Host smart-3e7d313d-d1ce-4af0-9226-86b90381898e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871247409 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_tx_ovf.2871247409
Directory /workspace/31.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.2792126500
Short name T670
Test name
Test status
Simulation time 2189584466 ps
CPU time 5.37 seconds
Started Jan 24 10:21:58 PM PST 24
Finished Jan 24 10:22:04 PM PST 24
Peak memory 206192 kb
Host smart-7cd60f11-c6e6-484c-adfa-1f3a4f2913fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792126500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.i2c_target_unexp_stop.2792126500
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2705006214
Short name T454
Test name
Test status
Simulation time 42903546 ps
CPU time 0.62 seconds
Started Jan 24 10:23:10 PM PST 24
Finished Jan 24 10:23:12 PM PST 24
Peak memory 200976 kb
Host smart-f66e8f5a-fa2b-4a36-91aa-a69c911a4790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705006214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2705006214
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1587374502
Short name T899
Test name
Test status
Simulation time 32217325 ps
CPU time 1.61 seconds
Started Jan 24 10:22:38 PM PST 24
Finished Jan 24 10:22:40 PM PST 24
Peak memory 218936 kb
Host smart-b99f9900-3402-4483-8fb5-628a39a30fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587374502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1587374502
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.4213380544
Short name T1354
Test name
Test status
Simulation time 478048091 ps
CPU time 8.2 seconds
Started Jan 24 10:22:09 PM PST 24
Finished Jan 24 10:22:18 PM PST 24
Peak memory 303364 kb
Host smart-9e0653ff-3ccd-453c-9e48-1f55e897bbf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213380544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.4213380544
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.4182091610
Short name T466
Test name
Test status
Simulation time 3111298548 ps
CPU time 219.24 seconds
Started Jan 24 10:22:11 PM PST 24
Finished Jan 24 10:25:51 PM PST 24
Peak memory 861184 kb
Host smart-cb05f620-4ffc-40c8-b9e9-d25b96e751b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182091610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.4182091610
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3576416494
Short name T705
Test name
Test status
Simulation time 78245890774 ps
CPU time 579.37 seconds
Started Jan 24 10:22:12 PM PST 24
Finished Jan 24 10:31:54 PM PST 24
Peak memory 1993824 kb
Host smart-842ef83d-d7f3-4f77-b227-c9ba1156bf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576416494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3576416494
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2548151283
Short name T871
Test name
Test status
Simulation time 734839556 ps
CPU time 1.1 seconds
Started Jan 24 10:22:19 PM PST 24
Finished Jan 24 10:22:22 PM PST 24
Peak memory 202496 kb
Host smart-9fece4d7-eece-4a37-9b48-181576932fe4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548151283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2548151283
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1338703082
Short name T1231
Test name
Test status
Simulation time 241435466 ps
CPU time 7.57 seconds
Started Jan 24 10:22:18 PM PST 24
Finished Jan 24 10:22:28 PM PST 24
Peak memory 250460 kb
Host smart-b84fedd0-2d66-4150-9b3a-c449c2ee5c36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338703082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1338703082
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2064478123
Short name T137
Test name
Test status
Simulation time 9310163429 ps
CPU time 173.91 seconds
Started Jan 24 10:22:12 PM PST 24
Finished Jan 24 10:25:08 PM PST 24
Peak memory 1232648 kb
Host smart-ef120ffc-86ba-42c1-a667-0405aad15629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064478123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2064478123
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3188445525
Short name T346
Test name
Test status
Simulation time 15066565485 ps
CPU time 43.12 seconds
Started Jan 24 10:23:11 PM PST 24
Finished Jan 24 10:23:56 PM PST 24
Peak memory 284076 kb
Host smart-f45185c3-4734-4067-ba1f-850423b1f78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188445525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3188445525
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.3442053304
Short name T955
Test name
Test status
Simulation time 89428008 ps
CPU time 0.62 seconds
Started Jan 24 10:22:17 PM PST 24
Finished Jan 24 10:22:20 PM PST 24
Peak memory 201540 kb
Host smart-d53a4bf8-3c87-4760-9088-d56333c39efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442053304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3442053304
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1495604045
Short name T357
Test name
Test status
Simulation time 7130105570 ps
CPU time 107.32 seconds
Started Jan 24 10:22:17 PM PST 24
Finished Jan 24 10:24:06 PM PST 24
Peak memory 282944 kb
Host smart-21393bc4-2ccb-46b2-85c1-574794b0d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495604045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1495604045
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_rx_oversample.1066008320
Short name T1350
Test name
Test status
Simulation time 2545915198 ps
CPU time 169.22 seconds
Started Jan 24 10:22:18 PM PST 24
Finished Jan 24 10:25:10 PM PST 24
Peak memory 338856 kb
Host smart-db0d8475-ae67-42ff-ad3b-ead79753ba83
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066008320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_rx_oversample
.1066008320
Directory /workspace/32.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.1401772848
Short name T287
Test name
Test status
Simulation time 7431374278 ps
CPU time 62.83 seconds
Started Jan 24 10:22:16 PM PST 24
Finished Jan 24 10:23:20 PM PST 24
Peak memory 308428 kb
Host smart-1baafc08-6499-462b-bb9a-54a1617ba4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401772848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1401772848
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.1006786050
Short name T45
Test name
Test status
Simulation time 47023135953 ps
CPU time 1166.08 seconds
Started Jan 24 10:22:34 PM PST 24
Finished Jan 24 10:42:03 PM PST 24
Peak memory 1680980 kb
Host smart-c4d09464-3165-4f19-9a2d-bf70addc59dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006786050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1006786050
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.371357023
Short name T1263
Test name
Test status
Simulation time 3016019108 ps
CPU time 32.92 seconds
Started Jan 24 10:22:33 PM PST 24
Finished Jan 24 10:23:07 PM PST 24
Peak memory 210828 kb
Host smart-91ab970c-3cf1-4b75-85f2-0924940bbeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371357023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.371357023
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.3724354513
Short name T1297
Test name
Test status
Simulation time 3039953466 ps
CPU time 3.48 seconds
Started Jan 24 10:22:57 PM PST 24
Finished Jan 24 10:23:03 PM PST 24
Peak memory 202656 kb
Host smart-5b00a003-47c3-492d-8b34-25d2d861d675
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724354513 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.3724354513
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.2391194819
Short name T320
Test name
Test status
Simulation time 10624878924 ps
CPU time 12.5 seconds
Started Jan 24 10:22:56 PM PST 24
Finished Jan 24 10:23:11 PM PST 24
Peak memory 273304 kb
Host smart-3f95c426-d55b-4efa-94b7-190d4866963b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391194819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.2391194819
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3393843356
Short name T505
Test name
Test status
Simulation time 10162919797 ps
CPU time 85.81 seconds
Started Jan 24 10:22:53 PM PST 24
Finished Jan 24 10:24:21 PM PST 24
Peak memory 650784 kb
Host smart-d6787877-7e43-48cb-9e71-97cef1bcbb0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393843356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3393843356
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3951262011
Short name T1057
Test name
Test status
Simulation time 545095801 ps
CPU time 2.71 seconds
Started Jan 24 10:22:52 PM PST 24
Finished Jan 24 10:22:57 PM PST 24
Peak memory 202684 kb
Host smart-d7e2d29b-3e9d-4183-bdce-5b40cdb11780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951262011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3951262011
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.1548142589
Short name T64
Test name
Test status
Simulation time 1232369844 ps
CPU time 5.25 seconds
Started Jan 24 10:22:51 PM PST 24
Finished Jan 24 10:23:00 PM PST 24
Peak memory 205800 kb
Host smart-bd4dc2c4-3abd-4cbc-a2d3-8402f479334a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548142589 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.1548142589
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.3592104509
Short name T895
Test name
Test status
Simulation time 20804646811 ps
CPU time 560.01 seconds
Started Jan 24 10:22:56 PM PST 24
Finished Jan 24 10:32:19 PM PST 24
Peak memory 3494956 kb
Host smart-e6174279-7a3a-4956-bbf2-803859b8d3a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592104509 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.3592104509
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.562443163
Short name T1080
Test name
Test status
Simulation time 1446854924 ps
CPU time 4.21 seconds
Started Jan 24 10:22:56 PM PST 24
Finished Jan 24 10:23:03 PM PST 24
Peak memory 203380 kb
Host smart-749b7d9a-478a-44df-8570-5e57b16ba06c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562443163 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_perf.562443163
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3489440739
Short name T545
Test name
Test status
Simulation time 5220130105 ps
CPU time 32.82 seconds
Started Jan 24 10:22:36 PM PST 24
Finished Jan 24 10:23:10 PM PST 24
Peak memory 202640 kb
Host smart-b6f69a8b-6021-4eed-aed4-76d8d8b2753f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489440739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3489440739
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.1375206189
Short name T1148
Test name
Test status
Simulation time 10761796673 ps
CPU time 44.35 seconds
Started Jan 24 10:22:50 PM PST 24
Finished Jan 24 10:23:39 PM PST 24
Peak memory 219044 kb
Host smart-33c72825-895b-4765-ad31-737064930dd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375206189 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.1375206189
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3407710848
Short name T1035
Test name
Test status
Simulation time 1373357147 ps
CPU time 59.16 seconds
Started Jan 24 10:22:35 PM PST 24
Finished Jan 24 10:23:36 PM PST 24
Peak memory 202592 kb
Host smart-dda49d1b-d81d-4b21-bba6-3bf0ceba4ec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407710848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3407710848
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.553350385
Short name T966
Test name
Test status
Simulation time 48885507747 ps
CPU time 340.58 seconds
Started Jan 24 10:22:33 PM PST 24
Finished Jan 24 10:28:15 PM PST 24
Peak memory 2840288 kb
Host smart-b3910589-ac91-4081-817c-e9e96dc50759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553350385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_wr.553350385
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.4250444329
Short name T304
Test name
Test status
Simulation time 23280546892 ps
CPU time 450.21 seconds
Started Jan 24 10:22:52 PM PST 24
Finished Jan 24 10:30:25 PM PST 24
Peak memory 1383956 kb
Host smart-0d1a1b7c-1eb3-42bf-b2aa-8a51fbfd4931
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250444329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.4250444329
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3261184766
Short name T607
Test name
Test status
Simulation time 5957726042 ps
CPU time 6.45 seconds
Started Jan 24 10:22:52 PM PST 24
Finished Jan 24 10:23:01 PM PST 24
Peak memory 202668 kb
Host smart-b388afaf-f0c3-44b2-a7a2-34e527c10f86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261184766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3261184766
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_ovf.3074659395
Short name T300
Test name
Test status
Simulation time 37845729632 ps
CPU time 45.7 seconds
Started Jan 24 10:22:53 PM PST 24
Finished Jan 24 10:23:40 PM PST 24
Peak memory 224372 kb
Host smart-1f4e1209-b4fd-4315-b5a5-b64c9e452704
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074659395 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_tx_ovf.3074659395
Directory /workspace/32.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.4000461273
Short name T892
Test name
Test status
Simulation time 3068176417 ps
CPU time 6.6 seconds
Started Jan 24 10:22:53 PM PST 24
Finished Jan 24 10:23:01 PM PST 24
Peak memory 211520 kb
Host smart-352fc932-f2b3-4f5c-aeab-c171225ea9c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000461273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_target_unexp_stop.4000461273
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1771439052
Short name T751
Test name
Test status
Simulation time 15421275 ps
CPU time 0.6 seconds
Started Jan 24 10:24:04 PM PST 24
Finished Jan 24 10:24:07 PM PST 24
Peak memory 202048 kb
Host smart-3c105d93-b7aa-48aa-8339-aa7f2c9ea988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771439052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1771439052
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3870110713
Short name T241
Test name
Test status
Simulation time 114274811 ps
CPU time 1.51 seconds
Started Jan 24 10:23:27 PM PST 24
Finished Jan 24 10:23:29 PM PST 24
Peak memory 210732 kb
Host smart-4b0e1a6b-a34c-4a26-8e73-0d6fc417b3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870110713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3870110713
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3076363902
Short name T220
Test name
Test status
Simulation time 2919279012 ps
CPU time 29.68 seconds
Started Jan 24 10:23:09 PM PST 24
Finished Jan 24 10:23:40 PM PST 24
Peak memory 324820 kb
Host smart-a0273230-961a-4747-a7ee-7d9488c956f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076363902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3076363902
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1282871781
Short name T665
Test name
Test status
Simulation time 2733198782 ps
CPU time 121.89 seconds
Started Jan 25 12:40:46 AM PST 24
Finished Jan 25 12:42:49 AM PST 24
Peak memory 883108 kb
Host smart-5b232312-f441-466f-80e8-1344f9ff3fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282871781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1282871781
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3202510102
Short name T257
Test name
Test status
Simulation time 22947605321 ps
CPU time 642.04 seconds
Started Jan 24 10:23:11 PM PST 24
Finished Jan 24 10:33:55 PM PST 24
Peak memory 1287560 kb
Host smart-96a3b098-b1f0-4802-89d3-1b64f4393bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202510102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3202510102
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.3692508477
Short name T841
Test name
Test status
Simulation time 590049254 ps
CPU time 0.95 seconds
Started Jan 24 10:23:11 PM PST 24
Finished Jan 24 10:23:14 PM PST 24
Peak memory 202332 kb
Host smart-43701998-c184-4e2f-a622-dea34862997e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692508477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.3692508477
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.615579653
Short name T353
Test name
Test status
Simulation time 269586368 ps
CPU time 6.65 seconds
Started Jan 24 10:23:09 PM PST 24
Finished Jan 24 10:23:17 PM PST 24
Peak memory 256740 kb
Host smart-19f52ca5-d24d-418a-a953-a614406c8fcf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615579653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.
615579653
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1994940060
Short name T139
Test name
Test status
Simulation time 15811935759 ps
CPU time 167.45 seconds
Started Jan 24 10:23:09 PM PST 24
Finished Jan 24 10:25:57 PM PST 24
Peak memory 1191160 kb
Host smart-4917d168-1dcb-4aac-9e6d-163697fd6f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994940060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1994940060
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1764909770
Short name T658
Test name
Test status
Simulation time 8833603714 ps
CPU time 84.05 seconds
Started Jan 24 10:24:04 PM PST 24
Finished Jan 24 10:25:30 PM PST 24
Peak memory 356616 kb
Host smart-5b79d052-5466-4616-bd48-b1bb80015776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764909770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1764909770
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2899212214
Short name T235
Test name
Test status
Simulation time 17176142 ps
CPU time 0.62 seconds
Started Jan 24 10:23:12 PM PST 24
Finished Jan 24 10:23:14 PM PST 24
Peak memory 201492 kb
Host smart-3db73c8a-5636-4138-8dcd-5b66e08d200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899212214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2899212214
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3154412472
Short name T1323
Test name
Test status
Simulation time 552019720 ps
CPU time 8.68 seconds
Started Jan 25 03:31:58 AM PST 24
Finished Jan 25 03:32:07 AM PST 24
Peak memory 210724 kb
Host smart-5dd5853d-fe2f-40e3-9af9-723eb11020d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154412472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3154412472
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_rx_oversample.3230291981
Short name T319
Test name
Test status
Simulation time 1509773033 ps
CPU time 55.22 seconds
Started Jan 24 10:23:09 PM PST 24
Finished Jan 24 10:24:06 PM PST 24
Peak memory 311088 kb
Host smart-f5861097-fcff-45d0-a436-78aa7fa8dbdc
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230291981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_rx_oversample
.3230291981
Directory /workspace/33.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.4261517159
Short name T382
Test name
Test status
Simulation time 6793946202 ps
CPU time 68.53 seconds
Started Jan 24 10:23:10 PM PST 24
Finished Jan 24 10:24:20 PM PST 24
Peak memory 348208 kb
Host smart-a5a7f4fb-c263-4eb3-a531-28cf047b4858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261517159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.4261517159
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2457915084
Short name T1404
Test name
Test status
Simulation time 1422981755 ps
CPU time 15.97 seconds
Started Jan 24 10:23:26 PM PST 24
Finished Jan 24 10:23:43 PM PST 24
Peak memory 210432 kb
Host smart-4ee43bae-ae9e-49ed-b4f9-8b9689e08772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457915084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2457915084
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2228016505
Short name T1282
Test name
Test status
Simulation time 2872689098 ps
CPU time 3.03 seconds
Started Jan 24 10:24:04 PM PST 24
Finished Jan 24 10:24:09 PM PST 24
Peak memory 202684 kb
Host smart-4d1261c3-c5a0-4bf3-b118-530be637d450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228016505 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2228016505
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.1621117372
Short name T1432
Test name
Test status
Simulation time 10592756523 ps
CPU time 16.6 seconds
Started Jan 24 10:23:48 PM PST 24
Finished Jan 24 10:24:05 PM PST 24
Peak memory 317992 kb
Host smart-c75ebf7d-115d-4553-b2c3-419dabab12ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621117372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.1621117372
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.571806168
Short name T297
Test name
Test status
Simulation time 10028411389 ps
CPU time 72.29 seconds
Started Jan 24 10:23:48 PM PST 24
Finished Jan 24 10:25:01 PM PST 24
Peak memory 542736 kb
Host smart-6ee45339-dbac-4837-a12d-8acea2216efe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571806168 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.571806168
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3281615187
Short name T675
Test name
Test status
Simulation time 868525597 ps
CPU time 2.59 seconds
Started Jan 24 10:24:04 PM PST 24
Finished Jan 24 10:24:08 PM PST 24
Peak memory 202668 kb
Host smart-df717745-bb7a-4590-8974-407fbc52780d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281615187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3281615187
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.503882821
Short name T709
Test name
Test status
Simulation time 2378515511 ps
CPU time 5.64 seconds
Started Jan 24 10:23:32 PM PST 24
Finished Jan 24 10:23:38 PM PST 24
Peak memory 205044 kb
Host smart-82afc380-be76-4afa-a364-4946c9a37a81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503882821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.503882821
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.1220561166
Short name T694
Test name
Test status
Simulation time 18206430112 ps
CPU time 176.66 seconds
Started Jan 25 01:19:30 AM PST 24
Finished Jan 25 01:22:27 AM PST 24
Peak memory 1652656 kb
Host smart-24da2f1d-7ca3-4d1c-9812-9a0870ea6d4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220561166 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.1220561166
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.3640997442
Short name T764
Test name
Test status
Simulation time 3011731416 ps
CPU time 4.19 seconds
Started Jan 24 10:24:04 PM PST 24
Finished Jan 24 10:24:10 PM PST 24
Peak memory 207884 kb
Host smart-f3cb1883-9194-46cc-bece-4a4f95d92736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640997442 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.3640997442
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.389054204
Short name T1125
Test name
Test status
Simulation time 6257743817 ps
CPU time 41.46 seconds
Started Jan 24 11:29:58 PM PST 24
Finished Jan 24 11:30:43 PM PST 24
Peak memory 202672 kb
Host smart-3dac62a5-67f2-4231-bf39-46760887dd80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389054204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.389054204
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1112219916
Short name T1016
Test name
Test status
Simulation time 2755408178 ps
CPU time 25.35 seconds
Started Jan 25 12:39:28 AM PST 24
Finished Jan 25 12:39:54 AM PST 24
Peak memory 215516 kb
Host smart-3d9abde3-b1f9-4620-93b8-fc0e778ebebd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112219916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1112219916
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1659470256
Short name T797
Test name
Test status
Simulation time 25508569881 ps
CPU time 195.47 seconds
Started Jan 24 10:23:24 PM PST 24
Finished Jan 24 10:26:40 PM PST 24
Peak memory 2393172 kb
Host smart-d05559d7-43d8-4908-9b97-607e8092035f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659470256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1659470256
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.192340956
Short name T1301
Test name
Test status
Simulation time 18742916162 ps
CPU time 114.06 seconds
Started Jan 24 10:58:34 PM PST 24
Finished Jan 24 11:00:32 PM PST 24
Peak memory 1088360 kb
Host smart-16283b3d-d3fe-4e7a-ad49-e4b5aca57ae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192340956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_t
arget_stretch.192340956
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1172067846
Short name T420
Test name
Test status
Simulation time 2255498677 ps
CPU time 7.65 seconds
Started Jan 24 10:23:48 PM PST 24
Finished Jan 24 10:23:56 PM PST 24
Peak memory 202688 kb
Host smart-c82df039-b2d6-4e1e-954b-4019066faab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172067846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1172067846
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_ovf.4192001716
Short name T930
Test name
Test status
Simulation time 2598505422 ps
CPU time 75.42 seconds
Started Jan 24 10:23:34 PM PST 24
Finished Jan 24 10:24:51 PM PST 24
Peak memory 302860 kb
Host smart-429a4a97-f8e8-4a5b-aad4-c8e62376b7f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192001716 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_tx_ovf.4192001716
Directory /workspace/33.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.224934880
Short name T176
Test name
Test status
Simulation time 4693003236 ps
CPU time 5.07 seconds
Started Jan 24 10:23:47 PM PST 24
Finished Jan 24 10:23:53 PM PST 24
Peak memory 205480 kb
Host smart-afa3ece4-2f2c-450c-b23c-7f8fe089c06b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224934880 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_unexp_stop.224934880
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.75441966
Short name T67
Test name
Test status
Simulation time 14768675 ps
CPU time 0.62 seconds
Started Jan 24 10:25:06 PM PST 24
Finished Jan 24 10:25:08 PM PST 24
Peak memory 201124 kb
Host smart-01fc7d81-9d9c-4d8e-b163-de1500736d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75441966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.75441966
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.447167568
Short name T639
Test name
Test status
Simulation time 167311256 ps
CPU time 1.41 seconds
Started Jan 24 10:24:14 PM PST 24
Finished Jan 24 10:24:17 PM PST 24
Peak memory 218904 kb
Host smart-ee42d1b6-b657-4906-8d2c-723bf60f7a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447167568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.447167568
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3586003573
Short name T2
Test name
Test status
Simulation time 485310757 ps
CPU time 11.41 seconds
Started Jan 24 10:24:16 PM PST 24
Finished Jan 24 10:24:28 PM PST 24
Peak memory 311960 kb
Host smart-f43fae43-df9d-4ab2-a350-f040ba2c4b5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586003573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3586003573
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.3821609343
Short name T1330
Test name
Test status
Simulation time 7286837214 ps
CPU time 152.43 seconds
Started Jan 24 11:40:53 PM PST 24
Finished Jan 24 11:43:26 PM PST 24
Peak memory 1076136 kb
Host smart-54de296a-d7bc-45bc-8670-2decbe9c4d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821609343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3821609343
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1315129070
Short name T1224
Test name
Test status
Simulation time 4233077490 ps
CPU time 507.58 seconds
Started Jan 24 10:24:05 PM PST 24
Finished Jan 24 10:32:34 PM PST 24
Peak memory 1177044 kb
Host smart-f13f075a-102d-4d82-9fec-9dec1ac0e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315129070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1315129070
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3999714350
Short name T1236
Test name
Test status
Simulation time 294142494 ps
CPU time 1.14 seconds
Started Jan 24 10:24:04 PM PST 24
Finished Jan 24 10:24:07 PM PST 24
Peak memory 202460 kb
Host smart-a3301139-1f6e-4e85-9d99-77eef4a39c7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999714350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3999714350
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2297561402
Short name T1061
Test name
Test status
Simulation time 182025724 ps
CPU time 9.33 seconds
Started Jan 24 10:24:15 PM PST 24
Finished Jan 24 10:24:25 PM PST 24
Peak memory 202528 kb
Host smart-140a6a8a-4649-47ba-bc7f-89d965437610
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297561402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2297561402
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1322858951
Short name T75
Test name
Test status
Simulation time 7709225971 ps
CPU time 339.05 seconds
Started Jan 24 10:24:05 PM PST 24
Finished Jan 24 10:29:45 PM PST 24
Peak memory 1087044 kb
Host smart-793e7ff8-deb2-4b49-89cd-7a296c9aa217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322858951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1322858951
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.1250035203
Short name T35
Test name
Test status
Simulation time 1748918424 ps
CPU time 88.11 seconds
Started Jan 24 10:25:09 PM PST 24
Finished Jan 24 10:26:39 PM PST 24
Peak memory 227128 kb
Host smart-8ad3edcd-277d-401e-8860-061daa372f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250035203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.1250035203
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.3325727802
Short name T1359
Test name
Test status
Simulation time 20275994 ps
CPU time 0.65 seconds
Started Jan 24 10:24:03 PM PST 24
Finished Jan 24 10:24:04 PM PST 24
Peak memory 201504 kb
Host smart-a32e04f1-aab0-4299-a82a-5b53e0e4f15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325727802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3325727802
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3430280610
Short name T963
Test name
Test status
Simulation time 1118016650 ps
CPU time 4.91 seconds
Started Jan 24 10:38:10 PM PST 24
Finished Jan 24 10:38:16 PM PST 24
Peak memory 210748 kb
Host smart-f4171ae9-8003-4ef2-9685-003b68e7de24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430280610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3430280610
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_rx_oversample.2427571116
Short name T1211
Test name
Test status
Simulation time 2475483425 ps
CPU time 93.38 seconds
Started Jan 24 10:24:02 PM PST 24
Finished Jan 24 10:25:36 PM PST 24
Peak memory 294108 kb
Host smart-be8c67d8-5408-4757-8689-aaa054e0e69f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427571116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_rx_oversample
.2427571116
Directory /workspace/34.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3341532418
Short name T1259
Test name
Test status
Simulation time 6381023870 ps
CPU time 102.17 seconds
Started Jan 24 10:24:04 PM PST 24
Finished Jan 24 10:25:48 PM PST 24
Peak memory 260684 kb
Host smart-7aa07372-87a4-4c27-91c0-2cf4e3759159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341532418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3341532418
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3201164947
Short name T1309
Test name
Test status
Simulation time 2653244019 ps
CPU time 28.43 seconds
Started Jan 24 10:24:15 PM PST 24
Finished Jan 24 10:24:45 PM PST 24
Peak memory 210720 kb
Host smart-9dc985dc-454f-44e5-9854-f0343a8a2a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201164947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3201164947
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2447140266
Short name T478
Test name
Test status
Simulation time 1937356322 ps
CPU time 4.49 seconds
Started Jan 24 10:25:07 PM PST 24
Finished Jan 24 10:25:14 PM PST 24
Peak memory 202616 kb
Host smart-ad21846f-cd0d-4028-8c7c-e8bee33ebf9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447140266 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2447140266
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.4266917414
Short name T846
Test name
Test status
Simulation time 10034208199 ps
CPU time 63.66 seconds
Started Jan 24 10:24:49 PM PST 24
Finished Jan 24 10:25:54 PM PST 24
Peak memory 529324 kb
Host smart-d464ba0b-5c8a-4752-937e-7abcb78716ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266917414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.4266917414
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.3735193048
Short name T1076
Test name
Test status
Simulation time 10121880771 ps
CPU time 84.85 seconds
Started Jan 24 10:24:47 PM PST 24
Finished Jan 24 10:26:14 PM PST 24
Peak memory 679240 kb
Host smart-c1467494-b702-47d9-941b-9a6002568cec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735193048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.3735193048
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2663648691
Short name T494
Test name
Test status
Simulation time 2987618490 ps
CPU time 2.66 seconds
Started Jan 24 10:25:06 PM PST 24
Finished Jan 24 10:25:10 PM PST 24
Peak memory 202752 kb
Host smart-0b5359f6-d350-4452-bd11-e02931c6dcd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663648691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2663648691
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2656452536
Short name T982
Test name
Test status
Simulation time 1533207402 ps
CPU time 5.75 seconds
Started Jan 24 10:24:47 PM PST 24
Finished Jan 24 10:24:55 PM PST 24
Peak memory 202544 kb
Host smart-bcd9d9f5-b155-410c-880d-67b3565d3737
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656452536 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2656452536
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.30022830
Short name T1502
Test name
Test status
Simulation time 12624651009 ps
CPU time 111.13 seconds
Started Jan 24 10:24:49 PM PST 24
Finished Jan 24 10:26:42 PM PST 24
Peak memory 1492648 kb
Host smart-ed6bffce-e62f-412f-9354-af1aebb09836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30022830 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.30022830
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_perf.3981893562
Short name T714
Test name
Test status
Simulation time 11144919687 ps
CPU time 3.56 seconds
Started Jan 25 12:09:04 AM PST 24
Finished Jan 25 12:09:09 AM PST 24
Peak memory 202680 kb
Host smart-b70713f0-e7d4-4c4a-9904-63c6a4a5c28c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981893562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.3981893562
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.535015324
Short name T1329
Test name
Test status
Simulation time 1425264040 ps
CPU time 14.24 seconds
Started Jan 24 11:22:01 PM PST 24
Finished Jan 24 11:22:19 PM PST 24
Peak memory 202656 kb
Host smart-79ca43d1-77a6-4821-bb1d-8c230ba1607d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535015324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.535015324
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.977163852
Short name T507
Test name
Test status
Simulation time 20301579952 ps
CPU time 272.57 seconds
Started Jan 24 10:24:47 PM PST 24
Finished Jan 24 10:29:22 PM PST 24
Peak memory 2389632 kb
Host smart-1f85864c-ed55-4a70-8c47-852bf5e5aae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977163852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_target_stress_all.977163852
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3196986944
Short name T923
Test name
Test status
Simulation time 11024933580 ps
CPU time 42.59 seconds
Started Jan 24 10:24:32 PM PST 24
Finished Jan 24 10:25:16 PM PST 24
Peak memory 230024 kb
Host smart-9494d35e-ebdf-45df-ba7c-12a5745dbce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196986944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3196986944
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.976332164
Short name T1414
Test name
Test status
Simulation time 42790679426 ps
CPU time 95.47 seconds
Started Jan 24 10:24:31 PM PST 24
Finished Jan 24 10:26:07 PM PST 24
Peak memory 1212548 kb
Host smart-650b8556-328d-424a-9339-fa4a42286545
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976332164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.976332164
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.415047297
Short name T1159
Test name
Test status
Simulation time 8097912324 ps
CPU time 32.64 seconds
Started Jan 24 10:24:31 PM PST 24
Finished Jan 24 10:25:04 PM PST 24
Peak memory 325980 kb
Host smart-1e2abbab-5f1c-42fc-a3ec-6f5c100e4cd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415047297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.415047297
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.115126295
Short name T1345
Test name
Test status
Simulation time 2844775571 ps
CPU time 6.29 seconds
Started Jan 24 10:24:46 PM PST 24
Finished Jan 24 10:24:54 PM PST 24
Peak memory 202612 kb
Host smart-66d9b8b7-4746-4ca9-b519-c16a0e04abfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115126295 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.115126295
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_ovf.2414287855
Short name T677
Test name
Test status
Simulation time 4933811218 ps
CPU time 88.9 seconds
Started Jan 24 10:24:49 PM PST 24
Finished Jan 24 10:26:19 PM PST 24
Peak memory 330552 kb
Host smart-4394d6b3-cdbf-4099-b9ae-5cf159a715d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414287855 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_tx_ovf.2414287855
Directory /workspace/34.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.2013409639
Short name T450
Test name
Test status
Simulation time 4632706232 ps
CPU time 5.83 seconds
Started Jan 24 10:24:47 PM PST 24
Finished Jan 24 10:24:54 PM PST 24
Peak memory 202680 kb
Host smart-34e7bb4d-f843-41c4-9fca-f2f77ca2fb7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013409639 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.2013409639
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.779425200
Short name T947
Test name
Test status
Simulation time 131999336 ps
CPU time 0.59 seconds
Started Jan 24 10:26:10 PM PST 24
Finished Jan 24 10:26:12 PM PST 24
Peak memory 201164 kb
Host smart-9c62d26a-5840-4ecf-8a24-354aeda6efb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779425200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.779425200
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.4236285059
Short name T625
Test name
Test status
Simulation time 69665731 ps
CPU time 1.43 seconds
Started Jan 24 10:38:53 PM PST 24
Finished Jan 24 10:38:56 PM PST 24
Peak memory 210744 kb
Host smart-9da0c6a7-5cef-4dc0-955b-64030da46bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236285059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.4236285059
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1042838477
Short name T829
Test name
Test status
Simulation time 587188589 ps
CPU time 9.08 seconds
Started Jan 24 10:25:08 PM PST 24
Finished Jan 24 10:25:20 PM PST 24
Peak memory 307020 kb
Host smart-152a2503-1e03-4cd5-a517-25c112fcd569
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042838477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1042838477
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1425336462
Short name T557
Test name
Test status
Simulation time 7904857868 ps
CPU time 69.64 seconds
Started Jan 24 10:25:21 PM PST 24
Finished Jan 24 10:26:32 PM PST 24
Peak memory 695960 kb
Host smart-f0d8a4e7-c9c1-48bc-8349-f15058e1fbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425336462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1425336462
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1026997109
Short name T348
Test name
Test status
Simulation time 16284531467 ps
CPU time 227.14 seconds
Started Jan 24 10:25:06 PM PST 24
Finished Jan 24 10:28:55 PM PST 24
Peak memory 1221080 kb
Host smart-354a6fcb-faf8-44fc-babd-0f7841e214db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026997109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1026997109
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.776189846
Short name T1339
Test name
Test status
Simulation time 1128774158 ps
CPU time 6.88 seconds
Started Jan 24 10:25:21 PM PST 24
Finished Jan 24 10:25:29 PM PST 24
Peak memory 202532 kb
Host smart-8e09bb22-5c8e-4419-89f3-66e70889ca6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776189846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.
776189846
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2375218933
Short name T440
Test name
Test status
Simulation time 9363203430 ps
CPU time 267.42 seconds
Started Jan 24 10:25:09 PM PST 24
Finished Jan 24 10:29:39 PM PST 24
Peak memory 1326284 kb
Host smart-78c6e8bf-78a6-4a6d-ae3d-30da6bf4faf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375218933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2375218933
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.1199140408
Short name T289
Test name
Test status
Simulation time 15666840911 ps
CPU time 97.17 seconds
Started Jan 24 10:25:50 PM PST 24
Finished Jan 24 10:27:29 PM PST 24
Peak memory 242540 kb
Host smart-852c64c4-85f6-4721-a0f2-b6a5eea785e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199140408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1199140408
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.2587024951
Short name T1028
Test name
Test status
Simulation time 43081125 ps
CPU time 0.61 seconds
Started Jan 24 10:25:08 PM PST 24
Finished Jan 24 10:25:11 PM PST 24
Peak memory 201512 kb
Host smart-e28ba4c4-43ee-44a1-913d-643a5392300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587024951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2587024951
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.4046937350
Short name T264
Test name
Test status
Simulation time 1736559233 ps
CPU time 17.3 seconds
Started Jan 24 10:25:19 PM PST 24
Finished Jan 24 10:25:38 PM PST 24
Peak memory 210672 kb
Host smart-4b1c11cf-5f87-45de-a5bb-2c3b280a5874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046937350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.4046937350
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_rx_oversample.3680439462
Short name T936
Test name
Test status
Simulation time 2057971919 ps
CPU time 140.41 seconds
Started Jan 24 10:25:05 PM PST 24
Finished Jan 24 10:27:27 PM PST 24
Peak memory 256464 kb
Host smart-5cf5dd42-fd8f-4abf-86dc-2796d7daf252
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680439462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_rx_oversample
.3680439462
Directory /workspace/35.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1172658127
Short name T1357
Test name
Test status
Simulation time 31235899779 ps
CPU time 118.9 seconds
Started Jan 24 10:25:08 PM PST 24
Finished Jan 24 10:27:10 PM PST 24
Peak memory 248416 kb
Host smart-ae840c94-50e4-4094-b940-af5663711b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172658127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1172658127
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.3913192152
Short name T141
Test name
Test status
Simulation time 18054044337 ps
CPU time 1481.2 seconds
Started Jan 24 10:25:20 PM PST 24
Finished Jan 24 10:50:03 PM PST 24
Peak memory 3256176 kb
Host smart-661cf6f7-413d-4f56-bfc3-838600182f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913192152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.3913192152
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.2369036096
Short name T236
Test name
Test status
Simulation time 4921679641 ps
CPU time 18.3 seconds
Started Jan 24 10:37:04 PM PST 24
Finished Jan 24 10:37:23 PM PST 24
Peak memory 227156 kb
Host smart-ab74d9d5-e211-4bd4-93db-e239394d0f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369036096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2369036096
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2002868867
Short name T39
Test name
Test status
Simulation time 1509101079 ps
CPU time 3.08 seconds
Started Jan 24 10:25:49 PM PST 24
Finished Jan 24 10:25:55 PM PST 24
Peak memory 202556 kb
Host smart-af85031d-4d46-4652-824f-43fb25bfc369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002868867 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2002868867
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3883178735
Short name T71
Test name
Test status
Simulation time 10118702640 ps
CPU time 70.25 seconds
Started Jan 24 10:25:29 PM PST 24
Finished Jan 24 10:26:43 PM PST 24
Peak memory 584512 kb
Host smart-140b4565-c898-4c67-943c-5a4028aefd3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883178735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3883178735
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3408707331
Short name T617
Test name
Test status
Simulation time 10110895547 ps
CPU time 17.25 seconds
Started Jan 24 10:25:33 PM PST 24
Finished Jan 24 10:25:58 PM PST 24
Peak memory 338532 kb
Host smart-ea5b7ab7-f03a-4713-8ac3-025b883d291e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408707331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.3408707331
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3048189948
Short name T1419
Test name
Test status
Simulation time 843436956 ps
CPU time 3.63 seconds
Started Jan 25 01:26:09 AM PST 24
Finished Jan 25 01:26:13 AM PST 24
Peak memory 202612 kb
Host smart-db976113-efb5-4483-950c-a27aea787dc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048189948 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3048189948
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.3325835809
Short name T352
Test name
Test status
Simulation time 23655082865 ps
CPU time 466.42 seconds
Started Jan 24 10:25:23 PM PST 24
Finished Jan 24 10:33:11 PM PST 24
Peak memory 2976228 kb
Host smart-bd87436a-8c3f-40e2-a92b-3b6516926b23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325835809 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3325835809
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_perf.4001993288
Short name T1022
Test name
Test status
Simulation time 2558714703 ps
CPU time 3.9 seconds
Started Jan 24 10:25:33 PM PST 24
Finished Jan 24 10:25:45 PM PST 24
Peak memory 202684 kb
Host smart-a8432081-e8a1-443e-8a30-052917557d0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001993288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.4001993288
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.917829336
Short name T1500
Test name
Test status
Simulation time 882729304 ps
CPU time 24.78 seconds
Started Jan 24 10:25:27 PM PST 24
Finished Jan 24 10:25:53 PM PST 24
Peak memory 202576 kb
Host smart-9399484c-d304-4d71-9abd-353cae8b5f32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917829336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_tar
get_smoke.917829336
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.1434022349
Short name T42
Test name
Test status
Simulation time 12802009059 ps
CPU time 65.92 seconds
Started Jan 24 10:25:50 PM PST 24
Finished Jan 24 10:26:58 PM PST 24
Peak memory 269144 kb
Host smart-0dbf1b29-a4f4-421a-9247-019437e1039b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434022349 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_stress_all.1434022349
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1053539014
Short name T1008
Test name
Test status
Simulation time 6340277192 ps
CPU time 28.14 seconds
Started Jan 24 10:25:27 PM PST 24
Finished Jan 24 10:25:56 PM PST 24
Peak memory 214888 kb
Host smart-fe1fcee5-124f-4ed6-8b12-d8798a6c03ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053539014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1053539014
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2186244276
Short name T515
Test name
Test status
Simulation time 23318709439 ps
CPU time 227.92 seconds
Started Jan 24 10:25:27 PM PST 24
Finished Jan 24 10:29:17 PM PST 24
Peak memory 2513056 kb
Host smart-2fda2c24-0495-44de-872d-fa03f59d1103
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186244276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2186244276
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2123264311
Short name T824
Test name
Test status
Simulation time 31358818878 ps
CPU time 804.15 seconds
Started Jan 24 10:25:23 PM PST 24
Finished Jan 24 10:38:48 PM PST 24
Peak memory 3820948 kb
Host smart-661aae2e-a430-4980-9d5e-a7f0b84d959c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123264311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2123264311
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.102183781
Short name T893
Test name
Test status
Simulation time 1352308891 ps
CPU time 6.19 seconds
Started Jan 24 10:25:22 PM PST 24
Finished Jan 24 10:25:30 PM PST 24
Peak memory 202616 kb
Host smart-45f0fe25-a968-40f8-b5e7-8e355cd65ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102183781 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.102183781
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_ovf.2297438918
Short name T770
Test name
Test status
Simulation time 9137229347 ps
CPU time 36.24 seconds
Started Jan 24 10:25:21 PM PST 24
Finished Jan 24 10:25:59 PM PST 24
Peak memory 214724 kb
Host smart-a98ce299-fcbe-4e4e-9c2b-7bfe7b1e7713
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297438918 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_tx_ovf.2297438918
Directory /workspace/35.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.2124484584
Short name T488
Test name
Test status
Simulation time 12162634718 ps
CPU time 7.74 seconds
Started Jan 24 10:25:27 PM PST 24
Finished Jan 24 10:25:36 PM PST 24
Peak memory 204768 kb
Host smart-4534a832-ecb8-4443-b0c4-5a0e2a8565df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124484584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.i2c_target_unexp_stop.2124484584
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2396523414
Short name T281
Test name
Test status
Simulation time 16654226 ps
CPU time 0.62 seconds
Started Jan 24 10:27:48 PM PST 24
Finished Jan 24 10:27:49 PM PST 24
Peak memory 202044 kb
Host smart-2b0b97bc-8309-4453-98ae-a5cd61fb2e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396523414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2396523414
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.197916545
Short name T231
Test name
Test status
Simulation time 152651954 ps
CPU time 1.38 seconds
Started Jan 24 10:26:26 PM PST 24
Finished Jan 24 10:26:28 PM PST 24
Peak memory 202544 kb
Host smart-f682801a-4925-4af1-8276-d221f5cef62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197916545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.197916545
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2773150535
Short name T1254
Test name
Test status
Simulation time 742311117 ps
CPU time 39.86 seconds
Started Jan 24 10:26:09 PM PST 24
Finished Jan 24 10:26:50 PM PST 24
Peak memory 369524 kb
Host smart-73d0b8b9-b568-4ee3-8a69-7a9ef496b356
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773150535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2773150535
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2108278962
Short name T1409
Test name
Test status
Simulation time 15514875891 ps
CPU time 349.16 seconds
Started Jan 24 10:26:07 PM PST 24
Finished Jan 24 10:31:57 PM PST 24
Peak memory 1130204 kb
Host smart-4b0724c4-f6ad-4a21-926f-40b31cc021cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108278962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2108278962
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3775053598
Short name T383
Test name
Test status
Simulation time 14212078769 ps
CPU time 540.93 seconds
Started Jan 24 10:26:08 PM PST 24
Finished Jan 24 10:35:10 PM PST 24
Peak memory 1902356 kb
Host smart-e8977fdd-40a5-4b91-bf62-1a9f3c380664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775053598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3775053598
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.2870721738
Short name T1053
Test name
Test status
Simulation time 266778367 ps
CPU time 0.84 seconds
Started Jan 24 10:26:08 PM PST 24
Finished Jan 24 10:26:10 PM PST 24
Peak memory 202304 kb
Host smart-be432edd-328d-4afb-b61d-5feb7a6c8e25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870721738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.2870721738
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.1276759530
Short name T581
Test name
Test status
Simulation time 164647393 ps
CPU time 4.95 seconds
Started Jan 24 10:26:09 PM PST 24
Finished Jan 24 10:26:16 PM PST 24
Peak memory 231312 kb
Host smart-805f9568-7a4e-4635-a5fc-c2f1144e429d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276759530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.1276759530
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.455969625
Short name T1099
Test name
Test status
Simulation time 14432956489 ps
CPU time 314.34 seconds
Started Jan 24 10:26:09 PM PST 24
Finished Jan 24 10:31:24 PM PST 24
Peak memory 1030876 kb
Host smart-c1d102ab-3920-4ac7-a6e1-dab1abd28af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455969625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.455969625
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1541891291
Short name T717
Test name
Test status
Simulation time 24098636676 ps
CPU time 197.45 seconds
Started Jan 24 10:27:37 PM PST 24
Finished Jan 24 10:30:56 PM PST 24
Peak memory 344912 kb
Host smart-d58c504d-e21b-4424-b1e2-212689079a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541891291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1541891291
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.2321680271
Short name T1507
Test name
Test status
Simulation time 71628641 ps
CPU time 0.62 seconds
Started Jan 24 10:26:07 PM PST 24
Finished Jan 24 10:26:09 PM PST 24
Peak memory 201532 kb
Host smart-2c43987d-daa4-4af6-90ba-98685198a161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321680271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2321680271
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.309010007
Short name T1290
Test name
Test status
Simulation time 455756298 ps
CPU time 8.98 seconds
Started Jan 24 10:26:07 PM PST 24
Finished Jan 24 10:26:17 PM PST 24
Peak memory 210712 kb
Host smart-d1691e60-6895-4ca0-9536-d5efb50c3058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309010007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.309010007
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_rx_oversample.2193142099
Short name T728
Test name
Test status
Simulation time 1563261795 ps
CPU time 78.78 seconds
Started Jan 24 10:26:07 PM PST 24
Finished Jan 24 10:27:27 PM PST 24
Peak memory 325760 kb
Host smart-a7ff5a9e-d774-451d-ab88-ddb1580d3acb
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193142099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_rx_oversample
.2193142099
Directory /workspace/36.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1398636575
Short name T461
Test name
Test status
Simulation time 3644918915 ps
CPU time 38.97 seconds
Started Jan 24 10:26:08 PM PST 24
Finished Jan 24 10:26:49 PM PST 24
Peak memory 280264 kb
Host smart-60e87f42-6904-4242-9b7f-6fb704e1ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398636575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1398636575
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.2187161034
Short name T1219
Test name
Test status
Simulation time 452293835 ps
CPU time 19.67 seconds
Started Jan 24 10:26:26 PM PST 24
Finished Jan 24 10:26:47 PM PST 24
Peak memory 210696 kb
Host smart-0806bbe7-e6a0-44c8-82f2-11abe0d7057e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187161034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.2187161034
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.3400654678
Short name T1428
Test name
Test status
Simulation time 2705676997 ps
CPU time 5.33 seconds
Started Jan 24 10:26:37 PM PST 24
Finished Jan 24 10:26:43 PM PST 24
Peak memory 202672 kb
Host smart-19ba6853-f534-4299-a4d8-4fb966150d7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400654678 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.3400654678
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3580374063
Short name T1407
Test name
Test status
Simulation time 10234928329 ps
CPU time 36.09 seconds
Started Jan 25 01:22:57 AM PST 24
Finished Jan 25 01:23:34 AM PST 24
Peak memory 427960 kb
Host smart-9636f4a8-51e2-4348-a6c2-f448df6e8854
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580374063 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3580374063
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1139525159
Short name T736
Test name
Test status
Simulation time 10040345133 ps
CPU time 82.25 seconds
Started Jan 24 10:26:37 PM PST 24
Finished Jan 24 10:28:01 PM PST 24
Peak memory 640552 kb
Host smart-a86339de-0e5e-4484-ac17-10bdda2a1118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139525159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1139525159
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.2263305505
Short name T816
Test name
Test status
Simulation time 2172374371 ps
CPU time 2.73 seconds
Started Jan 24 10:27:39 PM PST 24
Finished Jan 24 10:27:43 PM PST 24
Peak memory 202720 kb
Host smart-049bbcaa-36d1-42e4-acf0-9542c770710c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263305505 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.2263305505
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.971055891
Short name T216
Test name
Test status
Simulation time 6239177429 ps
CPU time 7.1 seconds
Started Jan 24 10:26:26 PM PST 24
Finished Jan 24 10:26:35 PM PST 24
Peak memory 202640 kb
Host smart-9ff22888-3430-4525-88a9-245d2779c01f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971055891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.971055891
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.102685793
Short name T58
Test name
Test status
Simulation time 3115929786 ps
CPU time 15.03 seconds
Started Jan 24 10:26:29 PM PST 24
Finished Jan 24 10:26:46 PM PST 24
Peak memory 503688 kb
Host smart-1623afa0-f5fa-48ce-85d2-a97571fe71e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102685793 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.102685793
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.2633719884
Short name T356
Test name
Test status
Simulation time 871564028 ps
CPU time 5.15 seconds
Started Jan 24 10:58:29 PM PST 24
Finished Jan 24 10:58:36 PM PST 24
Peak memory 202604 kb
Host smart-514cc09c-1caf-439e-b4e4-c9b1c0358a94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633719884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.2633719884
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3817633875
Short name T1106
Test name
Test status
Simulation time 2055482671 ps
CPU time 18.85 seconds
Started Jan 24 10:26:28 PM PST 24
Finished Jan 24 10:26:49 PM PST 24
Peak memory 202556 kb
Host smart-020c94b6-5f9b-49e6-96af-453c6f46ae56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817633875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3817633875
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.856271248
Short name T954
Test name
Test status
Simulation time 719411096 ps
CPU time 10.56 seconds
Started Jan 24 10:26:27 PM PST 24
Finished Jan 24 10:26:39 PM PST 24
Peak memory 207504 kb
Host smart-8002d90d-c2f2-4089-b8d6-8f5ae2c33fbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856271248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.856271248
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1813974386
Short name T757
Test name
Test status
Simulation time 27729631791 ps
CPU time 1445.82 seconds
Started Jan 25 12:09:53 AM PST 24
Finished Jan 25 12:34:01 AM PST 24
Peak memory 2651608 kb
Host smart-4d519d88-ddbe-467f-81a6-da187946a0f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813974386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1813974386
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1768594846
Short name T604
Test name
Test status
Simulation time 6280827082 ps
CPU time 7.83 seconds
Started Jan 25 12:33:00 AM PST 24
Finished Jan 25 12:33:09 AM PST 24
Peak memory 206124 kb
Host smart-95a08e87-519b-4c83-8c36-a9f0740c08f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768594846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1768594846
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_ovf.1093229046
Short name T15
Test name
Test status
Simulation time 2305215700 ps
CPU time 75.95 seconds
Started Jan 24 11:11:04 PM PST 24
Finished Jan 24 11:12:21 PM PST 24
Peak memory 329884 kb
Host smart-2f407587-85e5-43fb-948a-e1388d9475ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093229046 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_tx_ovf.1093229046
Directory /workspace/36.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.3466562511
Short name T435
Test name
Test status
Simulation time 814069292 ps
CPU time 4.12 seconds
Started Jan 24 10:26:38 PM PST 24
Finished Jan 24 10:26:43 PM PST 24
Peak memory 205352 kb
Host smart-6ea83646-7dd9-44a1-9a38-6f2a5b1f98b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466562511 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.i2c_target_unexp_stop.3466562511
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.740213656
Short name T1086
Test name
Test status
Simulation time 44101686 ps
CPU time 0.59 seconds
Started Jan 24 10:27:54 PM PST 24
Finished Jan 24 10:27:56 PM PST 24
Peak memory 201172 kb
Host smart-fb6e20b7-8f80-422a-b364-ce7a568bca71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740213656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.740213656
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3188772385
Short name T739
Test name
Test status
Simulation time 55937850 ps
CPU time 1.61 seconds
Started Jan 24 10:27:43 PM PST 24
Finished Jan 24 10:27:46 PM PST 24
Peak memory 210764 kb
Host smart-4aec7732-b193-46e8-b52e-501c7f10f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188772385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3188772385
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.849656085
Short name T447
Test name
Test status
Simulation time 447885284 ps
CPU time 23.54 seconds
Started Jan 24 10:27:43 PM PST 24
Finished Jan 24 10:28:07 PM PST 24
Peak memory 298652 kb
Host smart-bc95f573-7eec-4966-ad0b-b78f11407ed4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849656085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.849656085
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.3066491255
Short name T986
Test name
Test status
Simulation time 1912837176 ps
CPU time 73.24 seconds
Started Jan 24 10:27:43 PM PST 24
Finished Jan 24 10:28:58 PM PST 24
Peak memory 658388 kb
Host smart-5b213eb6-03f3-4294-ac31-ab6be824c87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066491255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.3066491255
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2828258881
Short name T644
Test name
Test status
Simulation time 20184080527 ps
CPU time 650.64 seconds
Started Jan 25 12:23:06 AM PST 24
Finished Jan 25 12:33:58 AM PST 24
Peak memory 1373392 kb
Host smart-52322f2e-7ebe-42f7-874f-1dd024852a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828258881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2828258881
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2785085898
Short name T453
Test name
Test status
Simulation time 167036176 ps
CPU time 0.86 seconds
Started Jan 24 10:27:39 PM PST 24
Finished Jan 24 10:27:40 PM PST 24
Peak memory 202344 kb
Host smart-5c5edf73-b751-4d66-8dd1-01907daf073c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785085898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2785085898
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.608318930
Short name T1003
Test name
Test status
Simulation time 218809145 ps
CPU time 12.99 seconds
Started Jan 24 10:27:47 PM PST 24
Finished Jan 24 10:28:01 PM PST 24
Peak memory 245972 kb
Host smart-4f770e78-fba4-4a90-94c8-e21e6f26c3f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608318930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
608318930
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3445493276
Short name T1122
Test name
Test status
Simulation time 3480190117 ps
CPU time 138.89 seconds
Started Jan 24 10:27:43 PM PST 24
Finished Jan 24 10:30:03 PM PST 24
Peak memory 919920 kb
Host smart-a49002be-e01d-4ce3-854c-3bdf80448f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445493276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3445493276
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.2998411751
Short name T1011
Test name
Test status
Simulation time 5292899741 ps
CPU time 175.95 seconds
Started Jan 24 10:27:56 PM PST 24
Finished Jan 24 10:30:53 PM PST 24
Peak memory 270072 kb
Host smart-b5c715c9-835a-40a0-8329-cfa8e5a7b3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998411751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2998411751
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.61320666
Short name T1294
Test name
Test status
Simulation time 36714661 ps
CPU time 0.63 seconds
Started Jan 24 10:27:46 PM PST 24
Finished Jan 24 10:27:48 PM PST 24
Peak memory 201500 kb
Host smart-6f4b0c74-fbb8-4ca4-8979-d3359e8a6309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61320666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.61320666
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3683924968
Short name T863
Test name
Test status
Simulation time 13611934547 ps
CPU time 176.53 seconds
Started Jan 24 10:27:48 PM PST 24
Finished Jan 24 10:30:46 PM PST 24
Peak memory 210804 kb
Host smart-21a5f1be-d20e-4b68-ad02-e9b90df8e74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683924968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3683924968
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_rx_oversample.1177451874
Short name T651
Test name
Test status
Simulation time 2422147568 ps
CPU time 119.48 seconds
Started Jan 24 10:27:40 PM PST 24
Finished Jan 24 10:29:41 PM PST 24
Peak memory 373240 kb
Host smart-66a9e520-d8af-40f8-be91-c2669f630b1b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177451874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_rx_oversample
.1177451874
Directory /workspace/37.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.102369078
Short name T1000
Test name
Test status
Simulation time 4493736824 ps
CPU time 65.91 seconds
Started Jan 24 10:27:37 PM PST 24
Finished Jan 24 10:28:44 PM PST 24
Peak memory 331608 kb
Host smart-cb911659-16d7-4fe7-bbef-fd0e766f407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102369078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.102369078
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.3753153160
Short name T624
Test name
Test status
Simulation time 8512153881 ps
CPU time 816.34 seconds
Started Jan 24 10:27:41 PM PST 24
Finished Jan 24 10:41:19 PM PST 24
Peak memory 1266236 kb
Host smart-eb392a4a-ff68-4744-b779-b9c0c3cfe87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753153160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.3753153160
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3389869630
Short name T1510
Test name
Test status
Simulation time 4954500588 ps
CPU time 44 seconds
Started Jan 24 11:42:00 PM PST 24
Finished Jan 24 11:42:47 PM PST 24
Peak memory 210780 kb
Host smart-ce0095fd-1c65-4c70-99b4-d6a9f74d5744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389869630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3389869630
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1751700728
Short name T1274
Test name
Test status
Simulation time 6003352387 ps
CPU time 5.76 seconds
Started Jan 24 10:30:08 PM PST 24
Finished Jan 24 10:30:15 PM PST 24
Peak memory 203016 kb
Host smart-d8e58fa8-82a5-4ab2-8528-ed2a5c46cfb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751700728 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1751700728
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.719636824
Short name T1338
Test name
Test status
Simulation time 10231913742 ps
CPU time 25.06 seconds
Started Jan 24 10:27:57 PM PST 24
Finished Jan 24 10:28:23 PM PST 24
Peak memory 335924 kb
Host smart-b70367c6-9b15-4c19-9cd8-a4bb40650a64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719636824 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.719636824
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3534289987
Short name T628
Test name
Test status
Simulation time 10052224672 ps
CPU time 66.97 seconds
Started Jan 24 10:42:12 PM PST 24
Finished Jan 24 10:43:20 PM PST 24
Peak memory 560384 kb
Host smart-b0142db9-7d3e-46e5-b163-ecd658dc3275
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534289987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3534289987
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.69664736
Short name T208
Test name
Test status
Simulation time 821370749 ps
CPU time 2.71 seconds
Started Jan 25 01:43:43 AM PST 24
Finished Jan 25 01:43:48 AM PST 24
Peak memory 202664 kb
Host smart-ca25bfa7-0183-4d58-a0c5-58986c903c73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69664736 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.i2c_target_hrst.69664736
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3105235954
Short name T278
Test name
Test status
Simulation time 5742093689 ps
CPU time 5.54 seconds
Started Jan 24 10:45:17 PM PST 24
Finished Jan 24 10:45:23 PM PST 24
Peak memory 202664 kb
Host smart-dc615668-f430-4dc0-b38e-0c1af0463c8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105235954 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3105235954
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3977963063
Short name T1102
Test name
Test status
Simulation time 21286473284 ps
CPU time 258.89 seconds
Started Jan 24 10:59:29 PM PST 24
Finished Jan 24 11:03:51 PM PST 24
Peak memory 2583472 kb
Host smart-19655e96-64ff-4605-b99e-ddacf071e066
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977963063 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3977963063
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.1444247160
Short name T528
Test name
Test status
Simulation time 1153889340 ps
CPU time 3.36 seconds
Started Jan 24 10:27:59 PM PST 24
Finished Jan 24 10:28:03 PM PST 24
Peak memory 202612 kb
Host smart-a81b9e77-df0d-466d-92b0-1b3d2c271a92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444247160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.1444247160
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.646216417
Short name T210
Test name
Test status
Simulation time 1374380924 ps
CPU time 13.32 seconds
Started Jan 24 10:27:59 PM PST 24
Finished Jan 24 10:28:13 PM PST 24
Peak memory 202600 kb
Host smart-70f1733e-1500-477f-8f8e-80a07fdab982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646216417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_tar
get_smoke.646216417
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.2324542826
Short name T1318
Test name
Test status
Simulation time 13464352099 ps
CPU time 290.69 seconds
Started Jan 25 05:03:49 AM PST 24
Finished Jan 25 05:08:48 AM PST 24
Peak memory 1342412 kb
Host smart-b8f468ec-2680-4b6f-8a82-7e29e9e9c6f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324542826 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.2324542826
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3001138175
Short name T600
Test name
Test status
Simulation time 473235779 ps
CPU time 21.4 seconds
Started Jan 25 12:16:43 AM PST 24
Finished Jan 25 12:17:07 AM PST 24
Peak memory 202616 kb
Host smart-2c611711-28e0-4345-861c-6901beb0b69d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001138175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3001138175
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1295229001
Short name T1202
Test name
Test status
Simulation time 76426113459 ps
CPU time 1721.07 seconds
Started Jan 24 10:52:00 PM PST 24
Finished Jan 24 11:20:42 PM PST 24
Peak memory 6765532 kb
Host smart-b59e393c-c7e5-4f07-8176-6c3aca9f26ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295229001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1295229001
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.2384361863
Short name T486
Test name
Test status
Simulation time 6678157590 ps
CPU time 24.82 seconds
Started Jan 24 10:52:34 PM PST 24
Finished Jan 24 10:53:00 PM PST 24
Peak memory 435452 kb
Host smart-d57bca9a-3167-4502-be89-6daa4fb67c5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384361863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.2384361863
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2293024140
Short name T103
Test name
Test status
Simulation time 3335092752 ps
CPU time 7.8 seconds
Started Jan 24 11:30:20 PM PST 24
Finished Jan 24 11:30:30 PM PST 24
Peak memory 214688 kb
Host smart-1e234fdb-7d2a-48da-a7ee-19342db4a3c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293024140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2293024140
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_ovf.1248656430
Short name T540
Test name
Test status
Simulation time 11209292645 ps
CPU time 41.26 seconds
Started Jan 24 10:27:55 PM PST 24
Finished Jan 24 10:28:37 PM PST 24
Peak memory 217300 kb
Host smart-23c5aa2f-9711-4489-8220-ca5e9c49439d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248656430 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_tx_ovf.1248656430
Directory /workspace/37.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.3982870585
Short name T1490
Test name
Test status
Simulation time 989479633 ps
CPU time 5.52 seconds
Started Jan 24 10:27:54 PM PST 24
Finished Jan 24 10:28:01 PM PST 24
Peak memory 204916 kb
Host smart-07b1a47d-ecf7-496e-a97b-14caf92e8dbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982870585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.i2c_target_unexp_stop.3982870585
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2119825663
Short name T860
Test name
Test status
Simulation time 65257645 ps
CPU time 0.6 seconds
Started Jan 24 10:28:53 PM PST 24
Finished Jan 24 10:28:59 PM PST 24
Peak memory 201116 kb
Host smart-aabc47d7-d5ae-46ed-8d1b-1b67424a5cd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119825663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2119825663
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.551085662
Short name T101
Test name
Test status
Simulation time 161808348 ps
CPU time 1.47 seconds
Started Jan 24 10:28:25 PM PST 24
Finished Jan 24 10:28:28 PM PST 24
Peak memory 218916 kb
Host smart-5ae5793b-69cd-43f5-a447-e42af87bede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551085662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.551085662
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.679527334
Short name T1347
Test name
Test status
Simulation time 1051400733 ps
CPU time 11.55 seconds
Started Jan 24 11:12:39 PM PST 24
Finished Jan 24 11:12:54 PM PST 24
Peak memory 309296 kb
Host smart-b3f7a826-d071-4346-8b14-e4038ce63e4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679527334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empt
y.679527334
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.1988055611
Short name T562
Test name
Test status
Simulation time 7642730840 ps
CPU time 319.71 seconds
Started Jan 24 10:28:11 PM PST 24
Finished Jan 24 10:33:37 PM PST 24
Peak memory 1115976 kb
Host smart-4ccd2a59-9538-49ab-a16e-46922d574357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988055611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1988055611
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1487764236
Short name T1044
Test name
Test status
Simulation time 24284343127 ps
CPU time 935.68 seconds
Started Jan 24 10:28:10 PM PST 24
Finished Jan 24 10:43:48 PM PST 24
Peak memory 1707836 kb
Host smart-56c3f0a7-c199-46df-9440-a75adfa8fcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487764236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1487764236
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1891998269
Short name T933
Test name
Test status
Simulation time 315112879 ps
CPU time 0.99 seconds
Started Jan 24 10:28:12 PM PST 24
Finished Jan 24 10:28:21 PM PST 24
Peak memory 202484 kb
Host smart-7c33d0f0-ff82-4a9d-a941-f15df3511cfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891998269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1891998269
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1764253710
Short name T877
Test name
Test status
Simulation time 1839769271 ps
CPU time 14.15 seconds
Started Jan 24 10:28:10 PM PST 24
Finished Jan 24 10:28:26 PM PST 24
Peak memory 253176 kb
Host smart-da3f3bf0-4488-4c25-af91-176741130b38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764253710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1764253710
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.4025326829
Short name T258
Test name
Test status
Simulation time 66728785611 ps
CPU time 439.23 seconds
Started Jan 24 10:28:14 PM PST 24
Finished Jan 24 10:35:40 PM PST 24
Peak memory 1852224 kb
Host smart-7d898425-752c-4e60-88ab-81011799f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025326829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.4025326829
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2845455127
Short name T475
Test name
Test status
Simulation time 4955031084 ps
CPU time 107.61 seconds
Started Jan 24 10:28:55 PM PST 24
Finished Jan 24 10:30:46 PM PST 24
Peak memory 374000 kb
Host smart-9f339221-189d-4a64-9f4c-63dec6ae3180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845455127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2845455127
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.156898235
Short name T1260
Test name
Test status
Simulation time 27549054 ps
CPU time 0.63 seconds
Started Jan 24 10:28:12 PM PST 24
Finished Jan 24 10:28:20 PM PST 24
Peak memory 201540 kb
Host smart-7e5754f4-0ce5-440a-b2bf-69b6c6c16371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156898235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.156898235
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.367410583
Short name T1437
Test name
Test status
Simulation time 47817434663 ps
CPU time 691.7 seconds
Started Jan 24 11:35:00 PM PST 24
Finished Jan 24 11:46:32 PM PST 24
Peak memory 507024 kb
Host smart-dab0d013-835a-45c3-bcd1-ac1b9291ccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367410583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.367410583
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_rx_oversample.1535105226
Short name T944
Test name
Test status
Simulation time 2290753603 ps
CPU time 156.83 seconds
Started Jan 24 10:28:12 PM PST 24
Finished Jan 24 10:30:56 PM PST 24
Peak memory 267780 kb
Host smart-f9f0b627-8460-4067-b52a-9d0204a76701
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535105226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_rx_oversample
.1535105226
Directory /workspace/38.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1745419710
Short name T1340
Test name
Test status
Simulation time 2225551548 ps
CPU time 108.05 seconds
Started Jan 24 10:28:10 PM PST 24
Finished Jan 24 10:30:00 PM PST 24
Peak memory 218976 kb
Host smart-9dd27489-6b7b-4b8b-93a8-e6987006459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745419710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1745419710
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1293877064
Short name T153
Test name
Test status
Simulation time 99469494514 ps
CPU time 1632.33 seconds
Started Jan 24 10:28:24 PM PST 24
Finished Jan 24 10:55:37 PM PST 24
Peak memory 1240020 kb
Host smart-18808785-1c5c-4178-a104-63a4df4a482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293877064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1293877064
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.256888323
Short name T376
Test name
Test status
Simulation time 3166804587 ps
CPU time 34.81 seconds
Started Jan 24 10:28:23 PM PST 24
Finished Jan 24 10:28:59 PM PST 24
Peak memory 210772 kb
Host smart-b6710cc7-6f78-4933-a2bc-57e4cd950109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256888323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.256888323
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3955261425
Short name T513
Test name
Test status
Simulation time 1674601393 ps
CPU time 5.9 seconds
Started Jan 24 10:28:43 PM PST 24
Finished Jan 24 10:28:54 PM PST 24
Peak memory 202564 kb
Host smart-49a8146d-6cb4-41cc-9c66-391ab19bf715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955261425 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3955261425
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.399317625
Short name T1174
Test name
Test status
Simulation time 10122625691 ps
CPU time 21.02 seconds
Started Jan 24 10:28:39 PM PST 24
Finished Jan 24 10:29:06 PM PST 24
Peak memory 348936 kb
Host smart-35df4af8-ce8f-44df-8796-28ee23348c6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399317625 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.399317625
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.540988428
Short name T372
Test name
Test status
Simulation time 10089601309 ps
CPU time 13.42 seconds
Started Jan 24 11:56:10 PM PST 24
Finished Jan 24 11:56:26 PM PST 24
Peak memory 309024 kb
Host smart-27fdb193-99e9-4ac9-8026-28ba4ca5ec96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540988428 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_fifo_reset_tx.540988428
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3800425276
Short name T1395
Test name
Test status
Simulation time 2300552597 ps
CPU time 2.85 seconds
Started Jan 24 10:28:39 PM PST 24
Finished Jan 24 10:28:48 PM PST 24
Peak memory 202716 kb
Host smart-8340fc5c-4f73-453c-8f41-c15cacc5b412
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800425276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3800425276
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3035752239
Short name T571
Test name
Test status
Simulation time 3548311081 ps
CPU time 6.83 seconds
Started Jan 24 10:28:23 PM PST 24
Finished Jan 24 10:28:31 PM PST 24
Peak memory 207772 kb
Host smart-3ca94f87-4b76-4467-b33b-64d9a6e9ab2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035752239 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3035752239
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3351878598
Short name T897
Test name
Test status
Simulation time 26363934035 ps
CPU time 1202.83 seconds
Started Jan 24 10:28:25 PM PST 24
Finished Jan 24 10:48:29 PM PST 24
Peak memory 6461864 kb
Host smart-bf4f9e26-61d6-492e-b9c9-7e7628bca4e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351878598 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3351878598
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.1738870212
Short name T1436
Test name
Test status
Simulation time 534670311 ps
CPU time 3.24 seconds
Started Jan 25 12:46:58 AM PST 24
Finished Jan 25 12:47:05 AM PST 24
Peak memory 202616 kb
Host smart-40551f54-f2d6-4885-8d59-683264d6a381
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738870212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.1738870212
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3168636707
Short name T519
Test name
Test status
Simulation time 928622961 ps
CPU time 12.51 seconds
Started Jan 24 10:28:25 PM PST 24
Finished Jan 24 10:28:39 PM PST 24
Peak memory 202580 kb
Host smart-72ec2c89-6221-4bde-9dc3-cddbed38d8f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168636707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3168636707
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.910307231
Short name T1089
Test name
Test status
Simulation time 2160137671 ps
CPU time 36.28 seconds
Started Jan 24 10:28:23 PM PST 24
Finished Jan 24 10:29:01 PM PST 24
Peak memory 215500 kb
Host smart-f3509284-14d5-40ad-af6b-cae2a28cce52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910307231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.910307231
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.1088763525
Short name T1203
Test name
Test status
Simulation time 8942081847 ps
CPU time 58.4 seconds
Started Jan 24 10:28:26 PM PST 24
Finished Jan 24 10:29:26 PM PST 24
Peak memory 1182688 kb
Host smart-4f4d43c3-3a34-4029-9a3f-1006ec4024bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088763525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.1088763525
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.4056046513
Short name T645
Test name
Test status
Simulation time 26218765922 ps
CPU time 160.75 seconds
Started Jan 24 10:28:24 PM PST 24
Finished Jan 24 10:31:06 PM PST 24
Peak memory 1765540 kb
Host smart-be388876-39b0-4c4d-bfab-9d6fb5ca8ddc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056046513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.4056046513
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2922536124
Short name T1416
Test name
Test status
Simulation time 26430120012 ps
CPU time 7.19 seconds
Started Jan 24 10:28:44 PM PST 24
Finished Jan 24 10:28:55 PM PST 24
Peak memory 212424 kb
Host smart-def0e4ea-9808-4c04-8e79-7044a87f4f3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922536124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2922536124
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_ovf.831274176
Short name T587
Test name
Test status
Simulation time 2104963709 ps
CPU time 45.98 seconds
Started Jan 24 10:28:24 PM PST 24
Finished Jan 24 10:29:11 PM PST 24
Peak memory 231908 kb
Host smart-556d4efd-d1b4-412a-be19-ca86c496992b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831274176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_tx_ovf.831274176
Directory /workspace/38.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.4069130513
Short name T311
Test name
Test status
Simulation time 1419183919 ps
CPU time 6.09 seconds
Started Jan 24 10:28:45 PM PST 24
Finished Jan 24 10:28:54 PM PST 24
Peak memory 205916 kb
Host smart-efe55ff8-0a6a-4d09-a786-0c3a22a10e66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069130513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_target_unexp_stop.4069130513
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3422619957
Short name T1098
Test name
Test status
Simulation time 61064420 ps
CPU time 0.63 seconds
Started Jan 24 10:29:57 PM PST 24
Finished Jan 24 10:29:58 PM PST 24
Peak memory 202048 kb
Host smart-bfa6c734-5dcf-474e-8c36-4d836b69d083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422619957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3422619957
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.166014106
Short name T228
Test name
Test status
Simulation time 52664605 ps
CPU time 1.48 seconds
Started Jan 24 10:29:21 PM PST 24
Finished Jan 24 10:29:24 PM PST 24
Peak memory 210768 kb
Host smart-aa49db81-f619-4fbd-8de4-5ba3154b3142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166014106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.166014106
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2154771511
Short name T1215
Test name
Test status
Simulation time 381550250 ps
CPU time 8.69 seconds
Started Jan 24 10:28:57 PM PST 24
Finished Jan 24 10:29:10 PM PST 24
Peak memory 282052 kb
Host smart-5a990fa3-ec91-46d6-8cd1-fd9456a731d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154771511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2154771511
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.4037842347
Short name T622
Test name
Test status
Simulation time 16341269375 ps
CPU time 45.46 seconds
Started Jan 24 10:29:07 PM PST 24
Finished Jan 24 10:29:53 PM PST 24
Peak memory 210812 kb
Host smart-8bf3b55d-f850-4788-b9e9-39a328be4a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037842347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.4037842347
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.3734180446
Short name T286
Test name
Test status
Simulation time 36062705734 ps
CPU time 270.27 seconds
Started Jan 24 10:28:55 PM PST 24
Finished Jan 24 10:33:29 PM PST 24
Peak memory 1375656 kb
Host smart-578aa364-a534-4312-8695-637337822717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734180446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.3734180446
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1319388022
Short name T1400
Test name
Test status
Simulation time 208068140 ps
CPU time 1 seconds
Started Jan 24 10:29:03 PM PST 24
Finished Jan 24 10:29:06 PM PST 24
Peak memory 202428 kb
Host smart-0b1a93e3-e526-4c97-b4fa-8fdc33fac29b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319388022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1319388022
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2688552647
Short name T1320
Test name
Test status
Simulation time 818131406 ps
CPU time 11.07 seconds
Started Jan 24 10:29:06 PM PST 24
Finished Jan 24 10:29:18 PM PST 24
Peak memory 202448 kb
Host smart-7271e67c-25e8-44c7-bb1a-823616922ffb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688552647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2688552647
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.2219006854
Short name T1296
Test name
Test status
Simulation time 23696615969 ps
CPU time 779.13 seconds
Started Jan 24 10:29:01 PM PST 24
Finished Jan 24 10:42:02 PM PST 24
Peak memory 1710064 kb
Host smart-488ad486-8026-431e-bd03-e310276e4d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219006854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.2219006854
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2394279338
Short name T1281
Test name
Test status
Simulation time 3303217350 ps
CPU time 104.06 seconds
Started Jan 24 10:29:53 PM PST 24
Finished Jan 24 10:31:38 PM PST 24
Peak memory 326380 kb
Host smart-6e9380e9-b923-4569-ba2d-1350ccd37daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394279338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2394279338
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.4048846882
Short name T1283
Test name
Test status
Simulation time 54892564 ps
CPU time 0.66 seconds
Started Jan 24 10:29:00 PM PST 24
Finished Jan 24 10:29:03 PM PST 24
Peak memory 202184 kb
Host smart-e0f01785-06bd-4c48-a478-6dde4ba609c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048846882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.4048846882
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1446310178
Short name T1052
Test name
Test status
Simulation time 6353618560 ps
CPU time 291.94 seconds
Started Jan 24 10:29:19 PM PST 24
Finished Jan 24 10:34:12 PM PST 24
Peak memory 215100 kb
Host smart-e85b4350-715f-4ac3-933e-ee5aa4a15a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446310178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1446310178
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_rx_oversample.3604236873
Short name T186
Test name
Test status
Simulation time 13119299039 ps
CPU time 223.6 seconds
Started Jan 24 10:28:56 PM PST 24
Finished Jan 24 10:32:42 PM PST 24
Peak memory 404328 kb
Host smart-45b40c46-ab29-4b00-98ea-889e04600a5b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604236873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_rx_oversample
.3604236873
Directory /workspace/39.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.3662976822
Short name T1431
Test name
Test status
Simulation time 2620514905 ps
CPU time 58.33 seconds
Started Jan 24 10:29:04 PM PST 24
Finished Jan 24 10:30:04 PM PST 24
Peak memory 292188 kb
Host smart-1afe0115-c715-4f91-8dc0-79ef89332c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662976822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3662976822
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1432602356
Short name T1410
Test name
Test status
Simulation time 1582706210 ps
CPU time 37.72 seconds
Started Jan 24 10:29:23 PM PST 24
Finished Jan 24 10:30:01 PM PST 24
Peak memory 210716 kb
Host smart-d9ece700-4688-445d-8f75-04b69162d955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432602356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1432602356
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.4173315409
Short name T910
Test name
Test status
Simulation time 837741777 ps
CPU time 3.43 seconds
Started Jan 24 10:29:53 PM PST 24
Finished Jan 24 10:29:57 PM PST 24
Peak memory 202612 kb
Host smart-bbd6e18e-06d3-4546-bb27-891e004b3eb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173315409 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.4173315409
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1133842472
Short name T623
Test name
Test status
Simulation time 10924960568 ps
CPU time 6.33 seconds
Started Jan 24 10:29:51 PM PST 24
Finished Jan 24 10:29:58 PM PST 24
Peak memory 225276 kb
Host smart-9abb3606-35de-4728-add3-f0444f8cbc77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133842472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1133842472
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3787835681
Short name T390
Test name
Test status
Simulation time 10151920004 ps
CPU time 13.41 seconds
Started Jan 24 10:29:52 PM PST 24
Finished Jan 24 10:30:07 PM PST 24
Peak memory 291024 kb
Host smart-ef33c9de-420a-4cd3-bc40-9ead1cb9be6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787835681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3787835681
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.3466371803
Short name T870
Test name
Test status
Simulation time 1081550486 ps
CPU time 2.61 seconds
Started Jan 24 10:29:52 PM PST 24
Finished Jan 24 10:29:56 PM PST 24
Peak memory 202660 kb
Host smart-a4a08cef-c9bf-41a7-a2af-725975faa698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466371803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.3466371803
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.311091839
Short name T763
Test name
Test status
Simulation time 1397244221 ps
CPU time 3.42 seconds
Started Jan 24 10:29:33 PM PST 24
Finished Jan 24 10:29:37 PM PST 24
Peak memory 202564 kb
Host smart-a0a2453b-80d0-4186-b7f1-d9b62184d403
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311091839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.311091839
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.358484039
Short name T553
Test name
Test status
Simulation time 4907517406 ps
CPU time 3.64 seconds
Started Jan 24 10:29:34 PM PST 24
Finished Jan 24 10:29:39 PM PST 24
Peak memory 242136 kb
Host smart-0cc6cbff-e751-4e39-83f0-d19da552677a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358484039 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.358484039
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.1247965824
Short name T428
Test name
Test status
Simulation time 3256757720 ps
CPU time 3.67 seconds
Started Jan 24 10:29:51 PM PST 24
Finished Jan 24 10:29:56 PM PST 24
Peak memory 205436 kb
Host smart-d36861a3-552d-464a-b8bc-ebf1c537859b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247965824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.1247965824
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.14484788
Short name T279
Test name
Test status
Simulation time 1653001606 ps
CPU time 19.03 seconds
Started Jan 24 10:29:20 PM PST 24
Finished Jan 24 10:29:40 PM PST 24
Peak memory 202596 kb
Host smart-e2858633-a40d-478f-8228-a75210588b33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14484788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_targ
et_smoke.14484788
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.2027733145
Short name T1307
Test name
Test status
Simulation time 48844753477 ps
CPU time 631.67 seconds
Started Jan 24 10:29:51 PM PST 24
Finished Jan 24 10:40:24 PM PST 24
Peak memory 2314404 kb
Host smart-a2f7fd15-5ca3-421d-a8aa-e4f20044159d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027733145 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.2027733145
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2922674632
Short name T1216
Test name
Test status
Simulation time 4057878245 ps
CPU time 43.81 seconds
Started Jan 24 10:29:21 PM PST 24
Finished Jan 24 10:30:05 PM PST 24
Peak memory 202692 kb
Host smart-61107683-37a3-4801-8b44-5dd3f5e18bea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922674632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2922674632
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.4180075186
Short name T324
Test name
Test status
Simulation time 17694014437 ps
CPU time 140.62 seconds
Started Jan 24 10:29:22 PM PST 24
Finished Jan 24 10:31:43 PM PST 24
Peak memory 1831004 kb
Host smart-3d9d076d-8917-4863-a64c-2cb1aa6ad716
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180075186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.4180075186
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1084727580
Short name T61
Test name
Test status
Simulation time 12693784175 ps
CPU time 183.06 seconds
Started Jan 24 10:29:37 PM PST 24
Finished Jan 24 10:32:42 PM PST 24
Peak memory 813532 kb
Host smart-09da5df0-9ef6-4912-870f-3e76e34aa030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084727580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1084727580
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1813975481
Short name T734
Test name
Test status
Simulation time 1735575587 ps
CPU time 7.07 seconds
Started Jan 24 10:29:34 PM PST 24
Finished Jan 24 10:29:42 PM PST 24
Peak memory 202572 kb
Host smart-12f1bfeb-549d-467e-8de8-f5a599cac29c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813975481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1813975481
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_ovf.1877193850
Short name T398
Test name
Test status
Simulation time 11348943958 ps
CPU time 205.42 seconds
Started Jan 24 10:29:36 PM PST 24
Finished Jan 24 10:33:03 PM PST 24
Peak memory 382680 kb
Host smart-200d3f3d-814f-4bae-9e3d-26ff7ac477d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877193850 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_tx_ovf.1877193850
Directory /workspace/39.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.1200837185
Short name T969
Test name
Test status
Simulation time 5303276923 ps
CPU time 5.99 seconds
Started Jan 24 10:29:37 PM PST 24
Finished Jan 24 10:29:44 PM PST 24
Peak memory 204904 kb
Host smart-4c8c5729-20f1-410f-9227-92cd08aa3467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200837185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.i2c_target_unexp_stop.1200837185
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.383171063
Short name T1268
Test name
Test status
Simulation time 35880408 ps
CPU time 0.6 seconds
Started Jan 24 09:57:12 PM PST 24
Finished Jan 24 09:57:16 PM PST 24
Peak memory 201136 kb
Host smart-ef155068-dd8c-4949-b03d-db7b91d755ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383171063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.383171063
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.983197756
Short name T621
Test name
Test status
Simulation time 183906802 ps
CPU time 1.42 seconds
Started Jan 24 09:56:45 PM PST 24
Finished Jan 24 09:56:47 PM PST 24
Peak memory 210784 kb
Host smart-fe3fbd9c-1ebc-4851-ad94-82ea04b055a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983197756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.983197756
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.274058267
Short name T242
Test name
Test status
Simulation time 284183917 ps
CPU time 5.22 seconds
Started Jan 24 11:47:32 PM PST 24
Finished Jan 24 11:47:38 PM PST 24
Peak memory 260388 kb
Host smart-bf9d7ed4-4312-420f-b2f9-d336dbc2708a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274058267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.274058267
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2617413461
Short name T559
Test name
Test status
Simulation time 6042902919 ps
CPU time 353.19 seconds
Started Jan 24 09:56:38 PM PST 24
Finished Jan 24 10:02:32 PM PST 24
Peak memory 1037876 kb
Host smart-4b26d76a-e37d-4f13-8d69-951f1cd4eb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617413461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2617413461
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.2346351830
Short name T1229
Test name
Test status
Simulation time 14725636364 ps
CPU time 225.02 seconds
Started Jan 24 11:18:46 PM PST 24
Finished Jan 24 11:22:34 PM PST 24
Peak memory 1122968 kb
Host smart-a303bc50-5bfe-40f4-8318-e06ced3b21d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346351830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.2346351830
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2408663857
Short name T291
Test name
Test status
Simulation time 203712129 ps
CPU time 0.91 seconds
Started Jan 24 09:56:52 PM PST 24
Finished Jan 24 09:56:54 PM PST 24
Peak memory 202336 kb
Host smart-5aab839c-ca78-4830-a3c6-1c272c6b8c60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408663857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2408663857
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3101251619
Short name T337
Test name
Test status
Simulation time 295928271 ps
CPU time 17.28 seconds
Started Jan 24 09:56:35 PM PST 24
Finished Jan 24 09:56:54 PM PST 24
Peak memory 262736 kb
Host smart-1736b3d9-b164-48da-adf9-2f14ca07c423
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101251619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3101251619
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.2411409661
Short name T756
Test name
Test status
Simulation time 4870979088 ps
CPU time 504.53 seconds
Started Jan 24 09:56:51 PM PST 24
Finished Jan 24 10:05:17 PM PST 24
Peak memory 1355844 kb
Host smart-77842985-7e73-42b2-8d8c-dc1f24eec586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411409661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2411409661
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.620261016
Short name T697
Test name
Test status
Simulation time 1960251186 ps
CPU time 57.27 seconds
Started Jan 24 09:57:10 PM PST 24
Finished Jan 24 09:58:09 PM PST 24
Peak memory 278728 kb
Host smart-54967756-1ab8-49b5-acef-ee9aa3744dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620261016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.620261016
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2338164826
Short name T1063
Test name
Test status
Simulation time 16239238 ps
CPU time 0.62 seconds
Started Jan 24 09:56:39 PM PST 24
Finished Jan 24 09:56:41 PM PST 24
Peak memory 201420 kb
Host smart-a15c9920-1e0c-4b10-b5fc-c8b6677ff4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338164826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2338164826
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1083067150
Short name T487
Test name
Test status
Simulation time 540547652 ps
CPU time 13.25 seconds
Started Jan 24 09:56:37 PM PST 24
Finished Jan 24 09:56:51 PM PST 24
Peak memory 210736 kb
Host smart-1c5b3cc8-4cb6-48e1-bf8a-cdfaab2c3b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083067150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1083067150
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_rx_oversample.1651040376
Short name T329
Test name
Test status
Simulation time 14220000769 ps
CPU time 102.84 seconds
Started Jan 24 09:56:36 PM PST 24
Finished Jan 24 09:58:19 PM PST 24
Peak memory 283656 kb
Host smart-e7c37ae7-6128-44d6-ae58-460bd733a3b7
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651040376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_rx_oversample.
1651040376
Directory /workspace/4.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.711326590
Short name T1204
Test name
Test status
Simulation time 7778646786 ps
CPU time 69.93 seconds
Started Jan 24 09:56:39 PM PST 24
Finished Jan 24 09:57:50 PM PST 24
Peak memory 323684 kb
Host smart-c9660e71-786f-4fbe-9b6d-beaa6afe5323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711326590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.711326590
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.673192711
Short name T32
Test name
Test status
Simulation time 10648035796 ps
CPU time 1133.93 seconds
Started Jan 24 09:56:37 PM PST 24
Finished Jan 24 10:15:32 PM PST 24
Peak memory 1375808 kb
Host smart-f2d40d1d-b632-47fb-b01a-63aa771821f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673192711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.673192711
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.762797202
Short name T913
Test name
Test status
Simulation time 2358018592 ps
CPU time 19.69 seconds
Started Jan 24 09:56:45 PM PST 24
Finished Jan 24 09:57:06 PM PST 24
Peak memory 218984 kb
Host smart-d2387644-8f9c-48c5-9861-0affa77936ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762797202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.762797202
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3182102147
Short name T78
Test name
Test status
Simulation time 242392887 ps
CPU time 0.93 seconds
Started Jan 24 09:57:10 PM PST 24
Finished Jan 24 09:57:14 PM PST 24
Peak memory 218456 kb
Host smart-8070e45f-6948-45f6-892a-197896ba5671
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182102147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3182102147
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3205699078
Short name T894
Test name
Test status
Simulation time 908858141 ps
CPU time 4.02 seconds
Started Jan 24 09:56:51 PM PST 24
Finished Jan 24 09:56:56 PM PST 24
Peak memory 202580 kb
Host smart-38a78b5f-e7e0-47a9-83da-290f2d89a6af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205699078 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3205699078
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2637241030
Short name T782
Test name
Test status
Simulation time 10107059766 ps
CPU time 59.12 seconds
Started Jan 24 11:07:37 PM PST 24
Finished Jan 24 11:08:37 PM PST 24
Peak memory 497604 kb
Host smart-56f8fc83-f4f0-49a4-9ca2-891b83640658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637241030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2637241030
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.4088218934
Short name T520
Test name
Test status
Simulation time 10460864208 ps
CPU time 14.37 seconds
Started Jan 24 09:56:51 PM PST 24
Finished Jan 24 09:57:06 PM PST 24
Peak memory 301736 kb
Host smart-3825edc3-b968-44bf-9154-5b4fa34d2998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088218934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.4088218934
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3227177430
Short name T629
Test name
Test status
Simulation time 1116874938 ps
CPU time 2.78 seconds
Started Jan 24 09:56:52 PM PST 24
Finished Jan 24 09:56:55 PM PST 24
Peak memory 202640 kb
Host smart-e62bc2a2-afd5-429d-9942-038e72c097bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227177430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3227177430
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3129943847
Short name T421
Test name
Test status
Simulation time 1997670771 ps
CPU time 4.04 seconds
Started Jan 24 09:56:50 PM PST 24
Finished Jan 24 09:56:55 PM PST 24
Peak memory 202644 kb
Host smart-ce926b6c-cf91-48e9-b774-1c3594aeb57c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129943847 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3129943847
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3323221994
Short name T1002
Test name
Test status
Simulation time 14496618355 ps
CPU time 157.54 seconds
Started Jan 24 09:56:50 PM PST 24
Finished Jan 24 09:59:29 PM PST 24
Peak memory 1755468 kb
Host smart-77784611-6104-469f-bccb-0cd6e47316cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323221994 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3323221994
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.2775923569
Short name T1084
Test name
Test status
Simulation time 3403576863 ps
CPU time 4.71 seconds
Started Jan 24 09:56:51 PM PST 24
Finished Jan 24 09:56:57 PM PST 24
Peak memory 202636 kb
Host smart-c6a0814c-bb38-4c6c-b799-3b46a21dac64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775923569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.2775923569
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3635454251
Short name T1447
Test name
Test status
Simulation time 1383351789 ps
CPU time 34.77 seconds
Started Jan 24 09:56:45 PM PST 24
Finished Jan 24 09:57:21 PM PST 24
Peak memory 202588 kb
Host smart-29a6040e-8169-4c48-ad72-5ec299da5bb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635454251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3635454251
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.3203468877
Short name T988
Test name
Test status
Simulation time 37976265799 ps
CPU time 2167.89 seconds
Started Jan 24 09:56:50 PM PST 24
Finished Jan 24 10:32:59 PM PST 24
Peak memory 1922296 kb
Host smart-a1dba467-7151-4c4b-9423-9a76dc609898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203468877 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.3203468877
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.2050359224
Short name T940
Test name
Test status
Simulation time 2777647547 ps
CPU time 24.7 seconds
Started Jan 24 09:56:51 PM PST 24
Finished Jan 24 09:57:17 PM PST 24
Peak memory 202668 kb
Host smart-df0f78ba-81ce-4d47-bdb9-ce08227f1671
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050359224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.2050359224
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2120967802
Short name T290
Test name
Test status
Simulation time 53443566052 ps
CPU time 79.34 seconds
Started Jan 24 09:56:51 PM PST 24
Finished Jan 24 09:58:11 PM PST 24
Peak memory 1007696 kb
Host smart-c02f2842-946a-4367-8848-cc8d2dd144c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120967802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2120967802
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.3790865862
Short name T438
Test name
Test status
Simulation time 15962967997 ps
CPU time 181.85 seconds
Started Jan 24 09:56:40 PM PST 24
Finished Jan 24 09:59:43 PM PST 24
Peak memory 912836 kb
Host smart-b3f21cb8-0745-4d1e-b9d0-98e824e06767
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790865862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.3790865862
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2083708939
Short name T1168
Test name
Test status
Simulation time 6274151301 ps
CPU time 7.34 seconds
Started Jan 24 09:56:52 PM PST 24
Finished Jan 24 09:57:00 PM PST 24
Peak memory 208320 kb
Host smart-7aff37c6-853b-4df9-9680-6fa01ce55ff6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083708939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2083708939
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_ovf.1671857929
Short name T335
Test name
Test status
Simulation time 2822968597 ps
CPU time 110.29 seconds
Started Jan 24 10:12:05 PM PST 24
Finished Jan 24 10:13:56 PM PST 24
Peak memory 346976 kb
Host smart-3552ba99-0051-4e05-ac10-ca04d326b68f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671857929 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_tx_ovf.1671857929
Directory /workspace/4.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.1480770126
Short name T663
Test name
Test status
Simulation time 1190689227 ps
CPU time 6.78 seconds
Started Jan 24 09:56:47 PM PST 24
Finished Jan 24 09:56:55 PM PST 24
Peak memory 202572 kb
Host smart-fe28ade8-6c6a-4d1d-b66f-af76b98684f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480770126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.i2c_target_unexp_stop.1480770126
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.122503621
Short name T684
Test name
Test status
Simulation time 15683601 ps
CPU time 0.58 seconds
Started Jan 24 10:30:50 PM PST 24
Finished Jan 24 10:30:52 PM PST 24
Peak memory 201088 kb
Host smart-af780b8e-cfc5-4828-9af2-925c63b3de31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122503621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.122503621
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3932197938
Short name T1186
Test name
Test status
Simulation time 40553100 ps
CPU time 1.31 seconds
Started Jan 24 10:30:13 PM PST 24
Finished Jan 24 10:30:16 PM PST 24
Peak memory 210764 kb
Host smart-c71f4ab3-28f1-413c-a5e1-7b9f596ccb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932197938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3932197938
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3785455849
Short name T368
Test name
Test status
Simulation time 508390644 ps
CPU time 8.98 seconds
Started Jan 24 10:30:13 PM PST 24
Finished Jan 24 10:30:24 PM PST 24
Peak memory 307880 kb
Host smart-a75d4a17-2841-4a18-b7c2-fb712e5bf9f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785455849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3785455849
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.118916040
Short name T732
Test name
Test status
Simulation time 4325132173 ps
CPU time 70.6 seconds
Started Jan 24 11:59:10 PM PST 24
Finished Jan 25 12:00:22 AM PST 24
Peak memory 720452 kb
Host smart-201a8e2a-37dc-4629-827a-2dd10ae84d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118916040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.118916040
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1613008325
Short name T499
Test name
Test status
Simulation time 5212719403 ps
CPU time 668.2 seconds
Started Jan 24 10:37:31 PM PST 24
Finished Jan 24 10:48:40 PM PST 24
Peak memory 1384312 kb
Host smart-6b4bda73-380f-41f9-91f3-55c27db45784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613008325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1613008325
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.309638234
Short name T1153
Test name
Test status
Simulation time 135385737 ps
CPU time 0.81 seconds
Started Jan 25 12:07:37 AM PST 24
Finished Jan 25 12:07:38 AM PST 24
Peak memory 201476 kb
Host smart-e0768c86-9d16-40fd-be14-230a0b77b5cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309638234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.309638234
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1352105935
Short name T1249
Test name
Test status
Simulation time 138861297 ps
CPU time 4.27 seconds
Started Jan 24 11:43:12 PM PST 24
Finished Jan 24 11:43:17 PM PST 24
Peak memory 223964 kb
Host smart-3ee3f904-fb71-40b7-8f8e-570b5626b54e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352105935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1352105935
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.668853471
Short name T1351
Test name
Test status
Simulation time 3426981012 ps
CPU time 303.33 seconds
Started Jan 24 10:38:02 PM PST 24
Finished Jan 24 10:43:06 PM PST 24
Peak memory 1018056 kb
Host smart-235c4da7-bba1-4f63-bb74-d7813b814d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668853471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.668853471
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1871631540
Short name T541
Test name
Test status
Simulation time 8233853492 ps
CPU time 152.58 seconds
Started Jan 24 10:30:48 PM PST 24
Finished Jan 24 10:33:21 PM PST 24
Peak memory 355108 kb
Host smart-8382446d-59d0-4f27-a718-c5535b91c6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871631540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1871631540
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.1219653740
Short name T263
Test name
Test status
Simulation time 16498488 ps
CPU time 0.63 seconds
Started Jan 24 10:29:53 PM PST 24
Finished Jan 24 10:29:55 PM PST 24
Peak memory 201524 kb
Host smart-625c56ee-632d-413d-a5cf-06084c9966ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219653740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1219653740
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3311824255
Short name T862
Test name
Test status
Simulation time 24937301840 ps
CPU time 249.12 seconds
Started Jan 24 11:27:53 PM PST 24
Finished Jan 24 11:32:03 PM PST 24
Peak memory 247652 kb
Host smart-85449787-f175-4a00-ab66-c73cde66ed7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311824255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3311824255
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_rx_oversample.3491352717
Short name T185
Test name
Test status
Simulation time 7515374512 ps
CPU time 64.96 seconds
Started Jan 24 10:30:09 PM PST 24
Finished Jan 24 10:31:16 PM PST 24
Peak memory 283844 kb
Host smart-7192a02c-4f56-4120-ae19-a105734188dc
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491352717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_rx_oversample
.3491352717
Directory /workspace/40.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.4075452945
Short name T315
Test name
Test status
Simulation time 2443433067 ps
CPU time 57.84 seconds
Started Jan 24 10:29:50 PM PST 24
Finished Jan 24 10:30:49 PM PST 24
Peak memory 295428 kb
Host smart-ba61ac3f-7c8c-4efb-9565-044f8da891d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075452945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.4075452945
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2709891911
Short name T1449
Test name
Test status
Simulation time 19213528146 ps
CPU time 485.27 seconds
Started Jan 24 10:30:23 PM PST 24
Finished Jan 24 10:38:29 PM PST 24
Peak memory 1167480 kb
Host smart-496346c1-bb93-4a82-8b89-22c0c29d5f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709891911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2709891911
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.951445103
Short name T1021
Test name
Test status
Simulation time 2117073794 ps
CPU time 22.71 seconds
Started Jan 24 10:30:09 PM PST 24
Finished Jan 24 10:30:34 PM PST 24
Peak memory 210720 kb
Host smart-c53cca4a-fedf-4f9f-b5a5-d9c40a25d091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951445103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.951445103
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.830857311
Short name T1238
Test name
Test status
Simulation time 677191014 ps
CPU time 3.04 seconds
Started Jan 24 10:30:48 PM PST 24
Finished Jan 24 10:30:53 PM PST 24
Peak memory 202648 kb
Host smart-5bdc8fd6-76d8-467e-a614-66ca7f159301
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830857311 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.830857311
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2302178096
Short name T1214
Test name
Test status
Simulation time 10088510950 ps
CPU time 57.54 seconds
Started Jan 24 10:30:32 PM PST 24
Finished Jan 24 10:31:32 PM PST 24
Peak memory 484236 kb
Host smart-9130a48f-c941-4d5a-b9e4-bc750c2797ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302178096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2302178096
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.561241620
Short name T1459
Test name
Test status
Simulation time 10232364217 ps
CPU time 14.35 seconds
Started Jan 24 10:30:30 PM PST 24
Finished Jan 24 10:30:46 PM PST 24
Peak memory 318112 kb
Host smart-fc002a8b-4b80-4b52-9a2b-fbc5f40ec903
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561241620 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.561241620
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.3287768227
Short name T853
Test name
Test status
Simulation time 778030374 ps
CPU time 2.45 seconds
Started Jan 24 10:30:47 PM PST 24
Finished Jan 24 10:30:50 PM PST 24
Peak memory 202680 kb
Host smart-bf9dcbd9-a1d7-4200-8a26-9e9bce3d64eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287768227 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.3287768227
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2366620029
Short name T880
Test name
Test status
Simulation time 3149409793 ps
CPU time 4.26 seconds
Started Jan 25 01:24:22 AM PST 24
Finished Jan 25 01:24:28 AM PST 24
Peak memory 202640 kb
Host smart-25885cb0-9c2d-4598-b5e9-45099754389f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366620029 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2366620029
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.1403648453
Short name T586
Test name
Test status
Simulation time 18264879847 ps
CPU time 92.97 seconds
Started Jan 24 10:30:37 PM PST 24
Finished Jan 24 10:32:11 PM PST 24
Peak memory 1117312 kb
Host smart-7f8dc163-68b4-4516-b2ac-8cd5e8d85fe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403648453 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.1403648453
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.4118493367
Short name T882
Test name
Test status
Simulation time 5313291840 ps
CPU time 5.89 seconds
Started Jan 24 10:30:30 PM PST 24
Finished Jan 24 10:30:38 PM PST 24
Peak memory 211288 kb
Host smart-ffcd4596-2d9b-4c03-a069-773ce40e91d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118493367 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.4118493367
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3268623694
Short name T878
Test name
Test status
Simulation time 7737166662 ps
CPU time 46.44 seconds
Started Jan 24 10:30:21 PM PST 24
Finished Jan 24 10:31:08 PM PST 24
Peak memory 202572 kb
Host smart-d9d66d55-6119-468e-8744-1d16ab46cefe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268623694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3268623694
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.1614187324
Short name T1257
Test name
Test status
Simulation time 14459957592 ps
CPU time 60.13 seconds
Started Jan 24 10:56:36 PM PST 24
Finished Jan 24 10:57:38 PM PST 24
Peak memory 202664 kb
Host smart-73fe9b65-cb29-4dfa-a923-62c4de613fe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614187324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.1614187324
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.2353103732
Short name T1037
Test name
Test status
Simulation time 43451177091 ps
CPU time 3059.45 seconds
Started Jan 25 03:19:21 AM PST 24
Finished Jan 25 04:10:22 AM PST 24
Peak memory 9707240 kb
Host smart-fcf6fcad-6db6-4504-8536-7713d61664cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353103732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.2353103732
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1711232025
Short name T643
Test name
Test status
Simulation time 26955105554 ps
CPU time 191.81 seconds
Started Jan 25 02:23:23 AM PST 24
Finished Jan 25 02:26:37 AM PST 24
Peak memory 1396400 kb
Host smart-c920c492-d5e3-4fb8-9feb-c95eae34c319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711232025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1711232025
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.318047881
Short name T464
Test name
Test status
Simulation time 8625221817 ps
CPU time 8.17 seconds
Started Jan 24 10:30:31 PM PST 24
Finished Jan 24 10:30:41 PM PST 24
Peak memory 204472 kb
Host smart-123bd5c7-57ee-423a-88c2-61bf6e33fb77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318047881 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.318047881
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_ovf.606913085
Short name T724
Test name
Test status
Simulation time 14027574088 ps
CPU time 97.7 seconds
Started Jan 24 10:30:32 PM PST 24
Finished Jan 24 10:32:11 PM PST 24
Peak memory 374044 kb
Host smart-a58a1698-0ab6-4485-beec-3b8c0bcfbcc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606913085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_tx_ovf.606913085
Directory /workspace/40.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.2387393513
Short name T325
Test name
Test status
Simulation time 15144283945 ps
CPU time 5.63 seconds
Started Jan 24 10:30:37 PM PST 24
Finished Jan 24 10:30:44 PM PST 24
Peak memory 204248 kb
Host smart-a8178caa-8f99-45b2-9dba-8a6af7e85a3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387393513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.i2c_target_unexp_stop.2387393513
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3287536688
Short name T783
Test name
Test status
Simulation time 14436370 ps
CPU time 0.62 seconds
Started Jan 24 10:32:09 PM PST 24
Finished Jan 24 10:32:11 PM PST 24
Peak memory 200380 kb
Host smart-da80fc26-b4bc-4ddc-af05-6426c4b4ab51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287536688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3287536688
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3269117368
Short name T229
Test name
Test status
Simulation time 87937888 ps
CPU time 1.63 seconds
Started Jan 24 10:31:03 PM PST 24
Finished Jan 24 10:31:10 PM PST 24
Peak memory 210732 kb
Host smart-911b824d-5a4f-4558-a772-18e3be163807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269117368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3269117368
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.892217239
Short name T1418
Test name
Test status
Simulation time 1468788410 ps
CPU time 6.55 seconds
Started Jan 24 10:31:04 PM PST 24
Finished Jan 24 10:31:15 PM PST 24
Peak memory 263000 kb
Host smart-58e02f3b-af47-4c29-95a7-75265e16b573
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892217239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.892217239
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.116058757
Short name T905
Test name
Test status
Simulation time 2675514577 ps
CPU time 92.91 seconds
Started Jan 24 10:31:04 PM PST 24
Finished Jan 24 10:32:41 PM PST 24
Peak memory 527880 kb
Host smart-85a8b309-5c2a-4ef5-b19f-9d27db176f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116058757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.116058757
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.2565720611
Short name T1421
Test name
Test status
Simulation time 4567504712 ps
CPU time 558.67 seconds
Started Jan 24 10:31:05 PM PST 24
Finished Jan 24 10:40:27 PM PST 24
Peak memory 1293772 kb
Host smart-4148f6fd-01d4-4412-a816-f32aa076bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565720611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.2565720611
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3624562872
Short name T298
Test name
Test status
Simulation time 62476760 ps
CPU time 0.92 seconds
Started Jan 24 10:31:02 PM PST 24
Finished Jan 24 10:31:09 PM PST 24
Peak memory 202328 kb
Host smart-1c083021-5ca3-4412-9f7f-b1b4a84b62ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624562872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3624562872
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3136043965
Short name T158
Test name
Test status
Simulation time 764512949 ps
CPU time 11.59 seconds
Started Jan 24 10:31:07 PM PST 24
Finished Jan 24 10:31:24 PM PST 24
Peak memory 238276 kb
Host smart-aff72249-b3e6-42ec-b8c8-d37cf97bd5f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136043965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3136043965
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.579068167
Short name T630
Test name
Test status
Simulation time 6464708511 ps
CPU time 433.85 seconds
Started Jan 24 10:31:07 PM PST 24
Finished Jan 24 10:38:26 PM PST 24
Peak memory 1782740 kb
Host smart-fed202e8-216d-48ed-a6ca-faaae126a3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579068167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.579068167
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1346346166
Short name T497
Test name
Test status
Simulation time 8665801641 ps
CPU time 47.58 seconds
Started Jan 24 10:32:08 PM PST 24
Finished Jan 24 10:32:57 PM PST 24
Peak memory 244600 kb
Host smart-bac8c71f-3a11-4aac-8bd3-5561f93d1759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346346166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1346346166
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.759057881
Short name T975
Test name
Test status
Simulation time 91958719 ps
CPU time 0.62 seconds
Started Jan 24 10:31:04 PM PST 24
Finished Jan 24 10:31:09 PM PST 24
Peak memory 201504 kb
Host smart-6bc9bf79-51a7-49b9-ba1e-8d68270d2107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759057881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.759057881
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3541636165
Short name T154
Test name
Test status
Simulation time 4574787127 ps
CPU time 243.7 seconds
Started Jan 24 10:31:05 PM PST 24
Finished Jan 24 10:35:12 PM PST 24
Peak memory 242496 kb
Host smart-988e78bd-91ac-4a4e-a3b7-a3009c0df45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541636165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3541636165
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_rx_oversample.2578564566
Short name T1352
Test name
Test status
Simulation time 2613849113 ps
CPU time 108.88 seconds
Started Jan 24 10:31:07 PM PST 24
Finished Jan 24 10:33:01 PM PST 24
Peak memory 340796 kb
Host smart-0169256e-535c-4815-873c-08c95fb0c4aa
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578564566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_rx_oversample
.2578564566
Directory /workspace/41.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.994457045
Short name T753
Test name
Test status
Simulation time 6675755931 ps
CPU time 94.94 seconds
Started Jan 24 10:31:06 PM PST 24
Finished Jan 24 10:32:47 PM PST 24
Peak memory 251072 kb
Host smart-926110db-51e0-4b23-98e4-7b286cea4ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994457045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.994457045
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.327551047
Short name T476
Test name
Test status
Simulation time 29449482082 ps
CPU time 2334.64 seconds
Started Jan 24 10:31:20 PM PST 24
Finished Jan 24 11:10:16 PM PST 24
Peak memory 2643680 kb
Host smart-45d0893c-9d60-493b-ac70-b39d32e4dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327551047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.327551047
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3919453144
Short name T1484
Test name
Test status
Simulation time 776230504 ps
CPU time 11.65 seconds
Started Jan 24 10:31:04 PM PST 24
Finished Jan 24 10:31:20 PM PST 24
Peak memory 218900 kb
Host smart-4676e526-a68c-41a3-8003-78a934ab6441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919453144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3919453144
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2364800708
Short name T655
Test name
Test status
Simulation time 933598809 ps
CPU time 3.72 seconds
Started Jan 24 10:32:08 PM PST 24
Finished Jan 24 10:32:13 PM PST 24
Peak memory 202628 kb
Host smart-3bdd5603-00ae-4156-a36e-d1aa5930fe82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364800708 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2364800708
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.946680088
Short name T1197
Test name
Test status
Simulation time 11739756879 ps
CPU time 5.83 seconds
Started Jan 24 10:32:06 PM PST 24
Finished Jan 24 10:32:13 PM PST 24
Peak memory 227892 kb
Host smart-00db7e6f-9a7b-449d-8b6f-2c631ef481ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946680088 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.946680088
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.880198375
Short name T1069
Test name
Test status
Simulation time 10208456465 ps
CPU time 61.57 seconds
Started Jan 24 10:32:09 PM PST 24
Finished Jan 24 10:33:12 PM PST 24
Peak memory 530516 kb
Host smart-93272338-aab9-471f-a6fe-6cbde2a00707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880198375 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.880198375
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1088347367
Short name T1451
Test name
Test status
Simulation time 2571373854 ps
CPU time 2.67 seconds
Started Jan 24 10:31:43 PM PST 24
Finished Jan 24 10:31:53 PM PST 24
Peak memory 202720 kb
Host smart-afeb9f11-86ec-4f04-ab48-3579ac4da74c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088347367 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1088347367
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.4156945466
Short name T529
Test name
Test status
Simulation time 2841010409 ps
CPU time 5.68 seconds
Started Jan 24 10:31:34 PM PST 24
Finished Jan 24 10:31:45 PM PST 24
Peak memory 202632 kb
Host smart-ff0eed26-398d-49e1-ac14-096e138dd120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156945466 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.4156945466
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.337445820
Short name T1466
Test name
Test status
Simulation time 25120911666 ps
CPU time 1420.09 seconds
Started Jan 24 10:31:37 PM PST 24
Finished Jan 24 10:55:24 PM PST 24
Peak memory 6001020 kb
Host smart-36c0fb97-0e5d-49fa-a8bc-232bb46492ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337445820 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.337445820
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.3840654681
Short name T1300
Test name
Test status
Simulation time 2421278490 ps
CPU time 4.01 seconds
Started Jan 24 10:32:08 PM PST 24
Finished Jan 24 10:32:13 PM PST 24
Peak memory 205068 kb
Host smart-fb2dcb10-43f1-4b43-a316-10ee28f3f0d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840654681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.3840654681
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3506492632
Short name T223
Test name
Test status
Simulation time 1522471305 ps
CPU time 16.49 seconds
Started Jan 24 10:31:24 PM PST 24
Finished Jan 24 10:31:42 PM PST 24
Peak memory 202572 kb
Host smart-6d9ad525-988a-459e-84f4-65ed71bd58df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506492632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3506492632
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.38803994
Short name T7
Test name
Test status
Simulation time 7870189609 ps
CPU time 8.48 seconds
Started Jan 24 10:31:19 PM PST 24
Finished Jan 24 10:31:29 PM PST 24
Peak memory 202628 kb
Host smart-784abcd6-4d50-4730-a45b-92f197c2e3e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38803994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stress_rd.38803994
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1247364907
Short name T737
Test name
Test status
Simulation time 32733767683 ps
CPU time 50.13 seconds
Started Jan 24 10:31:24 PM PST 24
Finished Jan 24 10:32:16 PM PST 24
Peak memory 912264 kb
Host smart-264cc1f5-f3f2-4165-afe2-b6a7451aeaa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247364907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1247364907
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.1640188469
Short name T799
Test name
Test status
Simulation time 26811597797 ps
CPU time 160.11 seconds
Started Jan 24 10:31:25 PM PST 24
Finished Jan 24 10:34:06 PM PST 24
Peak memory 1441548 kb
Host smart-2fd415fa-89d6-4e06-9d39-f2d77d692958
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640188469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.1640188469
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.269479974
Short name T1443
Test name
Test status
Simulation time 3442525648 ps
CPU time 7.47 seconds
Started Jan 24 10:31:37 PM PST 24
Finished Jan 24 10:31:51 PM PST 24
Peak memory 202664 kb
Host smart-53ab0116-67a0-4e1e-84f4-4f8ef7d0b4af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269479974 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_timeout.269479974
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_ovf.3015331483
Short name T1355
Test name
Test status
Simulation time 5769222605 ps
CPU time 149.27 seconds
Started Jan 24 10:31:37 PM PST 24
Finished Jan 24 10:34:13 PM PST 24
Peak memory 364808 kb
Host smart-b302b57d-ec80-4db3-8d76-eb82c1a6462a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015331483 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_tx_ovf.3015331483
Directory /workspace/41.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.2587225306
Short name T1342
Test name
Test status
Simulation time 11850836780 ps
CPU time 6.2 seconds
Started Jan 24 10:32:06 PM PST 24
Finished Jan 24 10:32:13 PM PST 24
Peak memory 205240 kb
Host smart-b0b77937-80e1-4cf5-a8c4-b31fe37a6f7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587225306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.i2c_target_unexp_stop.2587225306
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3760883980
Short name T91
Test name
Test status
Simulation time 168015750 ps
CPU time 0.63 seconds
Started Jan 24 11:11:47 PM PST 24
Finished Jan 24 11:11:50 PM PST 24
Peak memory 202072 kb
Host smart-d623614a-9545-45ed-9794-1565f3b7b3ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760883980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3760883980
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3853308299
Short name T1508
Test name
Test status
Simulation time 195634761 ps
CPU time 1.67 seconds
Started Jan 25 12:21:20 AM PST 24
Finished Jan 25 12:21:25 AM PST 24
Peak memory 212900 kb
Host smart-fb7e614a-7a04-4e9e-b40c-d4fc4ff8993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853308299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3853308299
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1298639412
Short name T754
Test name
Test status
Simulation time 1161429183 ps
CPU time 12.3 seconds
Started Jan 24 11:43:53 PM PST 24
Finished Jan 24 11:44:07 PM PST 24
Peak memory 310672 kb
Host smart-d801a91f-3fd7-4a73-b8e7-391f2025dbef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298639412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1298639412
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.198433656
Short name T536
Test name
Test status
Simulation time 2578455618 ps
CPU time 168.06 seconds
Started Jan 24 10:32:40 PM PST 24
Finished Jan 24 10:35:30 PM PST 24
Peak memory 636176 kb
Host smart-8f92de7e-dc26-494f-a0f7-f2ea39b2af80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198433656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.198433656
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2166434482
Short name T614
Test name
Test status
Simulation time 16637749241 ps
CPU time 202.28 seconds
Started Jan 24 10:32:39 PM PST 24
Finished Jan 24 10:36:03 PM PST 24
Peak memory 1201868 kb
Host smart-4f8f4174-ec12-4fde-83a1-8052156bd3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166434482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2166434482
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2070264464
Short name T1196
Test name
Test status
Simulation time 92176906 ps
CPU time 0.89 seconds
Started Jan 24 10:32:45 PM PST 24
Finished Jan 24 10:32:48 PM PST 24
Peak memory 202352 kb
Host smart-7c219f6f-7dfe-45af-8ae5-934a5dd9d7e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070264464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2070264464
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1844302631
Short name T549
Test name
Test status
Simulation time 826154933 ps
CPU time 5.3 seconds
Started Jan 24 10:32:40 PM PST 24
Finished Jan 24 10:32:47 PM PST 24
Peak memory 241684 kb
Host smart-17564632-6d2c-4afe-82db-69728999c5ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844302631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1844302631
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1498046428
Short name T729
Test name
Test status
Simulation time 7148661153 ps
CPU time 338.16 seconds
Started Jan 24 10:32:40 PM PST 24
Finished Jan 24 10:38:19 PM PST 24
Peak memory 1093556 kb
Host smart-213a56df-ab7f-4b06-a698-6d781a814b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498046428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1498046428
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3614424331
Short name T262
Test name
Test status
Simulation time 1929612493 ps
CPU time 104.99 seconds
Started Jan 24 10:32:58 PM PST 24
Finished Jan 24 10:34:44 PM PST 24
Peak memory 243260 kb
Host smart-4bd196b1-4f5e-487c-a363-0a5c5abcce8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614424331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3614424331
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1621937016
Short name T1147
Test name
Test status
Simulation time 16663523 ps
CPU time 0.65 seconds
Started Jan 25 02:03:43 AM PST 24
Finished Jan 25 02:03:44 AM PST 24
Peak memory 201496 kb
Host smart-3ba3b1cd-a927-4b5e-b516-558f12ec468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621937016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1621937016
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_rx_oversample.1090635726
Short name T1303
Test name
Test status
Simulation time 3391528413 ps
CPU time 263.94 seconds
Started Jan 24 10:32:42 PM PST 24
Finished Jan 24 10:37:07 PM PST 24
Peak memory 381828 kb
Host smart-b67b7042-a96e-468b-891c-aaef4cc0ff20
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090635726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_rx_oversample
.1090635726
Directory /workspace/42.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.1793099798
Short name T1488
Test name
Test status
Simulation time 9059441358 ps
CPU time 121.28 seconds
Started Jan 24 10:32:39 PM PST 24
Finished Jan 24 10:34:42 PM PST 24
Peak memory 244896 kb
Host smart-a52901bc-d445-4d54-8224-c6ae1b4f31f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793099798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1793099798
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.2957155869
Short name T188
Test name
Test status
Simulation time 78053922798 ps
CPU time 2975.24 seconds
Started Jan 25 12:10:06 AM PST 24
Finished Jan 25 12:59:43 AM PST 24
Peak memory 1026448 kb
Host smart-a77e1e5d-15ec-43e5-ba82-64b9cbc4bb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957155869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.2957155869
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all_with_rand_reset.2485485818
Short name T82
Test name
Test status
Simulation time 96785309661 ps
CPU time 351.58 seconds
Started Jan 24 10:33:01 PM PST 24
Finished Jan 24 10:38:54 PM PST 24
Peak memory 1515756 kb
Host smart-83766479-0bae-4bd5-9865-5fc47b631ed2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485485818 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 42.i2c_host_stress_all_with_rand_reset.2485485818
Directory /workspace/42.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.460531019
Short name T339
Test name
Test status
Simulation time 4812195045 ps
CPU time 20.14 seconds
Started Jan 24 10:32:41 PM PST 24
Finished Jan 24 10:33:02 PM PST 24
Peak memory 210744 kb
Host smart-ee33c958-b8bc-40a9-b0a8-7eb33aa6ec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460531019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.460531019
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1749765343
Short name T1082
Test name
Test status
Simulation time 9665816890 ps
CPU time 3.86 seconds
Started Jan 24 10:32:59 PM PST 24
Finished Jan 24 10:33:04 PM PST 24
Peak memory 202692 kb
Host smart-acc7ed68-461f-4fb9-aa57-277a28ea511d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749765343 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1749765343
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.343456671
Short name T1391
Test name
Test status
Simulation time 10223096874 ps
CPU time 25.58 seconds
Started Jan 24 10:32:57 PM PST 24
Finished Jan 24 10:33:24 PM PST 24
Peak memory 385832 kb
Host smart-9b29f71c-5579-46fc-bfce-5f2fd889298c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343456671 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.343456671
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.848891414
Short name T347
Test name
Test status
Simulation time 10112345791 ps
CPU time 68.23 seconds
Started Jan 24 10:32:59 PM PST 24
Finished Jan 24 10:34:08 PM PST 24
Peak memory 544928 kb
Host smart-5c25aea9-af7a-4257-a35c-82c59eb66513
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848891414 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.848891414
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3390683732
Short name T167
Test name
Test status
Simulation time 1807089611 ps
CPU time 2.44 seconds
Started Jan 24 10:32:59 PM PST 24
Finished Jan 24 10:33:03 PM PST 24
Peak memory 202652 kb
Host smart-a7c36b08-d494-4d9a-bade-7c16b80d4de0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390683732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3390683732
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2537625420
Short name T269
Test name
Test status
Simulation time 4346375723 ps
CPU time 4.91 seconds
Started Jan 24 10:32:41 PM PST 24
Finished Jan 24 10:32:47 PM PST 24
Peak memory 202632 kb
Host smart-098c4825-7684-487f-8ade-11623b38fb57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537625420 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2537625420
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.965256874
Short name T343
Test name
Test status
Simulation time 7079639188 ps
CPU time 37.73 seconds
Started Jan 24 11:36:56 PM PST 24
Finished Jan 24 11:37:41 PM PST 24
Peak memory 859496 kb
Host smart-527d6f53-7d27-424a-9638-680056c647b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965256874 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.965256874
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.2429262858
Short name T280
Test name
Test status
Simulation time 444747416 ps
CPU time 2.84 seconds
Started Jan 24 10:32:58 PM PST 24
Finished Jan 24 10:33:03 PM PST 24
Peak memory 202600 kb
Host smart-9c2bf08a-5f54-4895-859d-3b6073e8ab02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429262858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.2429262858
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1025743033
Short name T436
Test name
Test status
Simulation time 19647373293 ps
CPU time 17.45 seconds
Started Jan 25 12:17:12 AM PST 24
Finished Jan 25 12:17:31 AM PST 24
Peak memory 202652 kb
Host smart-4d9842e5-dc3f-4069-86d9-f67f76646310
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025743033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1025743033
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.2309683180
Short name T633
Test name
Test status
Simulation time 77840005559 ps
CPU time 482.17 seconds
Started Jan 24 10:32:59 PM PST 24
Finished Jan 24 10:41:03 PM PST 24
Peak memory 2460656 kb
Host smart-023ce429-5e0d-45f0-8849-91b82fe9d4de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309683180 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.2309683180
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.3591802161
Short name T935
Test name
Test status
Simulation time 1867118738 ps
CPU time 24.47 seconds
Started Jan 24 11:21:41 PM PST 24
Finished Jan 24 11:22:07 PM PST 24
Peak memory 224436 kb
Host smart-bc5ca812-eccb-4c53-a10f-c437a4ce4e4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591802161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.3591802161
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.330460075
Short name T456
Test name
Test status
Simulation time 40793390834 ps
CPU time 224.61 seconds
Started Jan 24 10:32:41 PM PST 24
Finished Jan 24 10:36:26 PM PST 24
Peak memory 2443164 kb
Host smart-51a089a8-45e0-4d6c-9f0c-3d6376c72e68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330460075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.330460075
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.4035385274
Short name T245
Test name
Test status
Simulation time 1701992097 ps
CPU time 7.94 seconds
Started Jan 25 12:00:03 AM PST 24
Finished Jan 25 12:00:15 AM PST 24
Peak memory 211984 kb
Host smart-35554fbc-d916-444f-bd48-caad545ae64a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035385274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.4035385274
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.1665105489
Short name T41
Test name
Test status
Simulation time 2289735101 ps
CPU time 7.37 seconds
Started Jan 24 10:33:01 PM PST 24
Finished Jan 24 10:33:10 PM PST 24
Peak memory 208456 kb
Host smart-a2c72bba-eff1-497f-a650-03be6449b3b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665105489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.1665105489
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3942223655
Short name T1495
Test name
Test status
Simulation time 47157190 ps
CPU time 0.66 seconds
Started Jan 24 10:34:08 PM PST 24
Finished Jan 24 10:34:14 PM PST 24
Peak memory 201172 kb
Host smart-bcbf4f5e-9456-4772-83b0-707248a37311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942223655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3942223655
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1000855158
Short name T1264
Test name
Test status
Simulation time 48845511 ps
CPU time 1.54 seconds
Started Jan 25 01:21:42 AM PST 24
Finished Jan 25 01:21:44 AM PST 24
Peak memory 210748 kb
Host smart-17d2cff2-765e-4b6d-87fa-207fa675df76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000855158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1000855158
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3181024524
Short name T313
Test name
Test status
Simulation time 646258419 ps
CPU time 34.25 seconds
Started Jan 24 10:33:13 PM PST 24
Finished Jan 24 10:33:49 PM PST 24
Peak memory 347320 kb
Host smart-a04f32ec-c433-4c05-b3ea-40a55b7bed58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181024524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3181024524
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2398135960
Short name T972
Test name
Test status
Simulation time 3561968632 ps
CPU time 165.62 seconds
Started Jan 25 12:00:36 AM PST 24
Finished Jan 25 12:03:23 AM PST 24
Peak memory 979588 kb
Host smart-77945cfc-487f-454c-a00b-02df1f849ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398135960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2398135960
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.3975749606
Short name T1280
Test name
Test status
Simulation time 14293741943 ps
CPU time 210.73 seconds
Started Jan 24 10:33:13 PM PST 24
Finished Jan 24 10:36:45 PM PST 24
Peak memory 1060212 kb
Host smart-b0cacd32-0ee8-4720-a9c3-bb4c4f47648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975749606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3975749606
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.773069084
Short name T987
Test name
Test status
Simulation time 118282372 ps
CPU time 0.99 seconds
Started Jan 24 10:33:15 PM PST 24
Finished Jan 24 10:33:17 PM PST 24
Peak memory 202308 kb
Host smart-4a25f482-ff26-4685-b7b5-d6d52643d199
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773069084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.773069084
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1858108877
Short name T1064
Test name
Test status
Simulation time 4000557072 ps
CPU time 8.63 seconds
Started Jan 24 10:33:14 PM PST 24
Finished Jan 24 10:33:25 PM PST 24
Peak memory 272480 kb
Host smart-76939dc9-69bd-4299-8286-79f483f93c4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858108877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1858108877
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2976668730
Short name T1258
Test name
Test status
Simulation time 14936202908 ps
CPU time 246.61 seconds
Started Jan 25 01:50:32 AM PST 24
Finished Jan 25 01:54:39 AM PST 24
Peak memory 1247944 kb
Host smart-7f64140d-fb93-4878-a4ad-24bc593068e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976668730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2976668730
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.120382765
Short name T971
Test name
Test status
Simulation time 1105979494 ps
CPU time 21.16 seconds
Started Jan 24 10:34:05 PM PST 24
Finished Jan 24 10:34:31 PM PST 24
Peak memory 227060 kb
Host smart-f12c8ac2-363d-4938-869e-39bdbd61f4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120382765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.120382765
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.2837680246
Short name T292
Test name
Test status
Simulation time 26560787 ps
CPU time 0.64 seconds
Started Jan 24 10:45:18 PM PST 24
Finished Jan 24 10:45:19 PM PST 24
Peak memory 201496 kb
Host smart-a80fb261-f9d6-449e-ac39-11a34fa8cae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837680246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2837680246
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.3035379368
Short name T1403
Test name
Test status
Simulation time 28207282328 ps
CPU time 161.27 seconds
Started Jan 24 10:33:14 PM PST 24
Finished Jan 24 10:35:57 PM PST 24
Peak memory 353776 kb
Host smart-7d3c6b19-4389-4f23-bfa6-e2da3bba7ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035379368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.3035379368
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_rx_oversample.815819097
Short name T354
Test name
Test status
Simulation time 9688793168 ps
CPU time 104.55 seconds
Started Jan 24 11:08:38 PM PST 24
Finished Jan 24 11:10:25 PM PST 24
Peak memory 316344 kb
Host smart-d454b40e-36e5-4058-ba5c-30d04bc980cc
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815819097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_rx_oversample.
815819097
Directory /workspace/43.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.123552466
Short name T1312
Test name
Test status
Simulation time 48249153325 ps
CPU time 92.36 seconds
Started Jan 24 10:33:12 PM PST 24
Finished Jan 24 10:34:46 PM PST 24
Peak memory 324472 kb
Host smart-acf0f81d-2cc6-4cf2-994e-c545df2b7adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123552466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.123552466
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.2007744458
Short name T1142
Test name
Test status
Simulation time 51641843209 ps
CPU time 2259.21 seconds
Started Jan 24 10:33:15 PM PST 24
Finished Jan 24 11:10:55 PM PST 24
Peak memory 2019244 kb
Host smart-4c11137b-b83f-4ce1-b329-b0dcdfa3a91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007744458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.2007744458
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2036556618
Short name T393
Test name
Test status
Simulation time 758570021 ps
CPU time 10.29 seconds
Started Jan 24 10:33:14 PM PST 24
Finished Jan 24 10:33:26 PM PST 24
Peak memory 215852 kb
Host smart-efd0f36b-ac99-4e4b-8c6c-96a2de45e08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036556618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2036556618
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2672837994
Short name T470
Test name
Test status
Simulation time 1627698020 ps
CPU time 6.04 seconds
Started Jan 24 10:33:45 PM PST 24
Finished Jan 24 10:33:52 PM PST 24
Peak memory 202672 kb
Host smart-4119e587-feea-4b25-8100-066ad56b9f87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672837994 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2672837994
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1482206670
Short name T1386
Test name
Test status
Simulation time 10161362915 ps
CPU time 8.43 seconds
Started Jan 24 10:33:48 PM PST 24
Finished Jan 24 10:33:58 PM PST 24
Peak memory 254948 kb
Host smart-744acd0f-f854-434b-b9a6-4b49c8a59ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482206670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1482206670
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3215223232
Short name T1160
Test name
Test status
Simulation time 10206313539 ps
CPU time 70.57 seconds
Started Jan 24 10:33:49 PM PST 24
Finished Jan 24 10:35:01 PM PST 24
Peak memory 608204 kb
Host smart-03b61820-b0e6-415d-87a2-e0abe3352bd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215223232 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3215223232
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3359291281
Short name T920
Test name
Test status
Simulation time 449080251 ps
CPU time 2.24 seconds
Started Jan 24 10:34:06 PM PST 24
Finished Jan 24 10:34:15 PM PST 24
Peak memory 202676 kb
Host smart-be745b77-a38b-4e51-9739-d6dbffa0734b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359291281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3359291281
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2769537802
Short name T523
Test name
Test status
Simulation time 983919601 ps
CPU time 4.99 seconds
Started Jan 24 10:33:46 PM PST 24
Finished Jan 24 10:33:53 PM PST 24
Peak memory 204060 kb
Host smart-9e7d04fe-922d-45e7-9ce7-5203ca1cb005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769537802 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2769537802
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.4231701723
Short name T1288
Test name
Test status
Simulation time 9957967922 ps
CPU time 161.43 seconds
Started Jan 24 10:33:44 PM PST 24
Finished Jan 24 10:36:27 PM PST 24
Peak memory 2213004 kb
Host smart-ae00ea03-6ed2-4616-b81e-c55feb662243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231701723 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.4231701723
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_perf.522923392
Short name T1306
Test name
Test status
Simulation time 3007034995 ps
CPU time 4.18 seconds
Started Jan 24 10:33:44 PM PST 24
Finished Jan 24 10:33:50 PM PST 24
Peak memory 205820 kb
Host smart-8a404365-4faf-4843-bf5e-779629ba0a95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522923392 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_perf.522923392
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3512540776
Short name T490
Test name
Test status
Simulation time 812192932 ps
CPU time 9.42 seconds
Started Jan 24 10:33:28 PM PST 24
Finished Jan 24 10:33:38 PM PST 24
Peak memory 202528 kb
Host smart-9f448916-1491-4e2b-962d-64e7d1dd8e1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512540776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3512540776
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.1525378398
Short name T477
Test name
Test status
Simulation time 3521315992 ps
CPU time 20.79 seconds
Started Jan 24 10:33:47 PM PST 24
Finished Jan 24 10:34:09 PM PST 24
Peak memory 220388 kb
Host smart-df2616c0-af01-463d-ace7-a8776cd4b0c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525378398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.1525378398
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3714197749
Short name T1149
Test name
Test status
Simulation time 68383151345 ps
CPU time 621.3 seconds
Started Jan 24 10:33:31 PM PST 24
Finished Jan 24 10:43:53 PM PST 24
Peak memory 4018140 kb
Host smart-d216b97d-9dc9-4374-985c-88683b0874fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714197749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3714197749
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2725580218
Short name T1370
Test name
Test status
Simulation time 18992972303 ps
CPU time 897.79 seconds
Started Jan 24 10:33:47 PM PST 24
Finished Jan 24 10:48:46 PM PST 24
Peak memory 3937200 kb
Host smart-55021e63-5291-444b-bb56-7a128e6aa0db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725580218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2725580218
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2267479057
Short name T530
Test name
Test status
Simulation time 3072777154 ps
CPU time 7.98 seconds
Started Jan 24 10:33:46 PM PST 24
Finished Jan 24 10:33:55 PM PST 24
Peak memory 202636 kb
Host smart-bd27631e-136b-43cc-9f92-b5f19d7c388e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267479057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2267479057
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_ovf.1473293979
Short name T591
Test name
Test status
Simulation time 2618572956 ps
CPU time 105.32 seconds
Started Jan 24 10:33:46 PM PST 24
Finished Jan 24 10:35:33 PM PST 24
Peak memory 338220 kb
Host smart-738d7ea1-cd23-4255-9439-57272d9388bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473293979 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_tx_ovf.1473293979
Directory /workspace/43.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.127766545
Short name T1155
Test name
Test status
Simulation time 1244213705 ps
CPU time 5.59 seconds
Started Jan 24 10:33:48 PM PST 24
Finished Jan 24 10:33:55 PM PST 24
Peak memory 202652 kb
Host smart-69b29b21-ef23-4ca6-ac08-2603687ae9df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127766545 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_unexp_stop.127766545
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1346679631
Short name T403
Test name
Test status
Simulation time 17737969 ps
CPU time 0.64 seconds
Started Jan 24 10:34:59 PM PST 24
Finished Jan 24 10:35:06 PM PST 24
Peak memory 202068 kb
Host smart-f134b7b6-ea9c-46aa-b0cc-55e5a9fa9505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346679631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1346679631
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3255882529
Short name T1394
Test name
Test status
Simulation time 737841369 ps
CPU time 1.48 seconds
Started Jan 24 10:34:22 PM PST 24
Finished Jan 24 10:34:24 PM PST 24
Peak memory 210716 kb
Host smart-a2f5bd4a-63db-420b-a772-774fdf645853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255882529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3255882529
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1288395466
Short name T309
Test name
Test status
Simulation time 2113079910 ps
CPU time 10.08 seconds
Started Jan 24 10:34:21 PM PST 24
Finished Jan 24 10:34:32 PM PST 24
Peak memory 323836 kb
Host smart-a93afcef-6e11-44a1-9e4c-d6f50e9d85be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288395466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1288395466
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2935067490
Short name T1468
Test name
Test status
Simulation time 4073900540 ps
CPU time 93.72 seconds
Started Jan 24 10:34:21 PM PST 24
Finished Jan 24 10:35:55 PM PST 24
Peak memory 740092 kb
Host smart-ab109af0-0ce0-4456-af4f-1472f5bb1305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935067490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2935067490
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3151194960
Short name T1183
Test name
Test status
Simulation time 4455340175 ps
CPU time 241 seconds
Started Jan 24 10:34:22 PM PST 24
Finished Jan 24 10:38:24 PM PST 24
Peak memory 1214224 kb
Host smart-9e2f9987-c6d2-44fa-8865-60c7b2364857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151194960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3151194960
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3218960145
Short name T1485
Test name
Test status
Simulation time 188526665 ps
CPU time 0.94 seconds
Started Jan 24 10:34:21 PM PST 24
Finished Jan 24 10:34:23 PM PST 24
Peak memory 202336 kb
Host smart-ce728d38-5586-4693-9fb9-9cc3991d902a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218960145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3218960145
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.510465444
Short name T556
Test name
Test status
Simulation time 562995148 ps
CPU time 5.65 seconds
Started Jan 24 10:34:22 PM PST 24
Finished Jan 24 10:34:29 PM PST 24
Peak memory 202556 kb
Host smart-88a48776-4047-443d-af58-84e42178a9b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510465444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
510465444
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.1332126885
Short name T773
Test name
Test status
Simulation time 12576620935 ps
CPU time 348.29 seconds
Started Jan 24 10:34:06 PM PST 24
Finished Jan 24 10:40:00 PM PST 24
Peak memory 1729372 kb
Host smart-13efb98a-f68f-4b1b-b421-035d2694cf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332126885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1332126885
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3361938259
Short name T1366
Test name
Test status
Simulation time 2273345363 ps
CPU time 65.76 seconds
Started Jan 24 10:34:56 PM PST 24
Finished Jan 24 10:36:09 PM PST 24
Peak memory 323208 kb
Host smart-3dcdfb27-75c3-4ff7-9e13-92d6563ca3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361938259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3361938259
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.4046185870
Short name T1132
Test name
Test status
Simulation time 20684930 ps
CPU time 0.66 seconds
Started Jan 24 10:34:04 PM PST 24
Finished Jan 24 10:34:06 PM PST 24
Peak memory 201544 kb
Host smart-39831cd1-0fd0-4b5c-8234-b871a5022baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046185870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.4046185870
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.4278822
Short name T308
Test name
Test status
Simulation time 5308030609 ps
CPU time 59.54 seconds
Started Jan 24 10:34:21 PM PST 24
Finished Jan 24 10:35:21 PM PST 24
Peak memory 264952 kb
Host smart-558d8298-7c6a-4c2c-a14e-2681a3f9884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.4278822
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_rx_oversample.4162214603
Short name T10
Test name
Test status
Simulation time 8506946001 ps
CPU time 142.72 seconds
Started Jan 24 10:34:05 PM PST 24
Finished Jan 24 10:36:33 PM PST 24
Peak memory 274048 kb
Host smart-2b71ad2d-30b5-4e09-8ae9-5d2d66ad4a6b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162214603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_rx_oversample
.4162214603
Directory /workspace/44.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.893803322
Short name T656
Test name
Test status
Simulation time 33839772430 ps
CPU time 99.04 seconds
Started Jan 24 10:34:04 PM PST 24
Finished Jan 24 10:35:45 PM PST 24
Peak memory 259496 kb
Host smart-5eccd15b-a5b5-4847-8b7e-464256274a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893803322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.893803322
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.288278129
Short name T654
Test name
Test status
Simulation time 18075315425 ps
CPU time 2368.94 seconds
Started Jan 24 10:34:21 PM PST 24
Finished Jan 24 11:13:52 PM PST 24
Peak memory 4110624 kb
Host smart-05a842d6-a45c-4bd8-8b16-5ddc197c5bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288278129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.288278129
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.396451180
Short name T388
Test name
Test status
Simulation time 3742176203 ps
CPU time 17.57 seconds
Started Jan 24 10:34:23 PM PST 24
Finished Jan 24 10:34:41 PM PST 24
Peak memory 218852 kb
Host smart-5f80add1-1197-4705-83a9-32374b0ee253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396451180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.396451180
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3624555716
Short name T785
Test name
Test status
Simulation time 3707861880 ps
CPU time 3.94 seconds
Started Jan 24 10:34:57 PM PST 24
Finished Jan 24 10:35:07 PM PST 24
Peak memory 202700 kb
Host smart-854feb2d-4d1e-4086-b254-e0a7d68f2c5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624555716 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3624555716
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1149116816
Short name T1372
Test name
Test status
Simulation time 10276266677 ps
CPU time 26.78 seconds
Started Jan 24 10:34:39 PM PST 24
Finished Jan 24 10:35:11 PM PST 24
Peak memory 357148 kb
Host smart-bdd8e797-96a9-453a-8afc-aca343551b32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149116816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1149116816
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.109651444
Short name T171
Test name
Test status
Simulation time 10064185161 ps
CPU time 80.62 seconds
Started Jan 24 10:34:39 PM PST 24
Finished Jan 24 10:36:04 PM PST 24
Peak memory 636380 kb
Host smart-974d333a-6495-4e11-80cf-6dcb5c9dc991
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109651444 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.109651444
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.2690585962
Short name T399
Test name
Test status
Simulation time 2140441156 ps
CPU time 2.6 seconds
Started Jan 24 10:35:02 PM PST 24
Finished Jan 24 10:35:08 PM PST 24
Peak memory 202640 kb
Host smart-c6244e91-888d-4888-aaf7-bde911a94271
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690585962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.2690585962
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1822167417
Short name T791
Test name
Test status
Simulation time 5348705992 ps
CPU time 5.6 seconds
Started Jan 24 10:34:37 PM PST 24
Finished Jan 24 10:34:47 PM PST 24
Peak memory 202688 kb
Host smart-02fc8130-e17c-46b4-be84-ab563a46b680
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822167417 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1822167417
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1384259405
Short name T839
Test name
Test status
Simulation time 8890377374 ps
CPU time 30.48 seconds
Started Jan 24 10:34:40 PM PST 24
Finished Jan 24 10:35:18 PM PST 24
Peak memory 669612 kb
Host smart-2a19db26-2351-4a6c-8603-19a51ab70751
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384259405 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1384259405
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.328089396
Short name T1009
Test name
Test status
Simulation time 494213986 ps
CPU time 3.15 seconds
Started Jan 24 10:34:56 PM PST 24
Finished Jan 24 10:35:03 PM PST 24
Peak memory 202588 kb
Host smart-835b4ab1-b7ae-4e44-bec2-7ec7efd6bb75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328089396 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_perf.328089396
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.1145611271
Short name T102
Test name
Test status
Simulation time 8697172172 ps
CPU time 11.36 seconds
Started Jan 24 10:34:41 PM PST 24
Finished Jan 24 10:34:59 PM PST 24
Peak memory 202680 kb
Host smart-fc9a3603-2474-4125-8e10-6284261ce09c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145611271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.1145611271
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2214596423
Short name T964
Test name
Test status
Simulation time 10819078360 ps
CPU time 73.6 seconds
Started Jan 24 10:34:38 PM PST 24
Finished Jan 24 10:35:57 PM PST 24
Peak memory 203980 kb
Host smart-41a02fb6-8770-4b09-b18c-5bb903bcc8a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214596423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2214596423
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.4085649534
Short name T563
Test name
Test status
Simulation time 30346756237 ps
CPU time 942.57 seconds
Started Jan 24 10:34:39 PM PST 24
Finished Jan 24 10:50:26 PM PST 24
Peak memory 6476532 kb
Host smart-b72027ff-5b85-44c4-aba7-29b2bce6734c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085649534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.4085649534
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.104334796
Short name T806
Test name
Test status
Simulation time 8463056911 ps
CPU time 13.11 seconds
Started Jan 24 10:34:39 PM PST 24
Finished Jan 24 10:34:56 PM PST 24
Peak memory 304140 kb
Host smart-9d05234c-58ce-4426-bd38-a7c7fd692537
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104334796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.104334796
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3525551349
Short name T294
Test name
Test status
Simulation time 3361404657 ps
CPU time 6.55 seconds
Started Jan 24 10:34:43 PM PST 24
Finished Jan 24 10:34:56 PM PST 24
Peak memory 202652 kb
Host smart-b1034840-ebbc-4a09-9682-fb3bda577333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525551349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3525551349
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_ovf.3366050514
Short name T1048
Test name
Test status
Simulation time 8187429446 ps
CPU time 160.16 seconds
Started Jan 24 10:34:41 PM PST 24
Finished Jan 24 10:37:28 PM PST 24
Peak memory 408284 kb
Host smart-81a3c371-c5ea-43dd-8ae3-d750aa726915
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366050514 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_tx_ovf.3366050514
Directory /workspace/44.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.3515340581
Short name T917
Test name
Test status
Simulation time 991356220 ps
CPU time 4.6 seconds
Started Jan 24 10:34:41 PM PST 24
Finished Jan 24 10:34:53 PM PST 24
Peak memory 202512 kb
Host smart-4caa77ff-84f8-4fed-bfa2-6ef4919bb9ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515340581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.i2c_target_unexp_stop.3515340581
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.2229231297
Short name T1462
Test name
Test status
Simulation time 16345000 ps
CPU time 0.63 seconds
Started Jan 24 10:35:59 PM PST 24
Finished Jan 24 10:36:00 PM PST 24
Peak memory 201124 kb
Host smart-ea33fbd2-5638-4f77-b4ce-c3c9215af202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229231297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2229231297
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.189673677
Short name T1192
Test name
Test status
Simulation time 47554114 ps
CPU time 1.43 seconds
Started Jan 24 10:35:07 PM PST 24
Finished Jan 24 10:35:09 PM PST 24
Peak memory 210748 kb
Host smart-4014419f-0ce8-4c93-8fe1-38f73a84194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189673677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.189673677
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.372896489
Short name T506
Test name
Test status
Simulation time 1589578335 ps
CPU time 19.15 seconds
Started Jan 24 10:35:05 PM PST 24
Finished Jan 24 10:35:25 PM PST 24
Peak memory 273684 kb
Host smart-b6108b6a-fa31-42eb-bab6-09473c2cd326
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372896489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.372896489
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3666778701
Short name T276
Test name
Test status
Simulation time 3567943219 ps
CPU time 148.76 seconds
Started Jan 24 10:35:05 PM PST 24
Finished Jan 24 10:37:35 PM PST 24
Peak memory 1052820 kb
Host smart-251faed6-bb6b-4536-9cbe-bb5552b08f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666778701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3666778701
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.1459338642
Short name T1253
Test name
Test status
Simulation time 70918849578 ps
CPU time 563.4 seconds
Started Jan 24 10:35:06 PM PST 24
Finished Jan 24 10:44:30 PM PST 24
Peak memory 1263704 kb
Host smart-ac29cc6d-c369-4a02-b4a9-6922e7ec968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459338642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.1459338642
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.720818574
Short name T1333
Test name
Test status
Simulation time 302456706 ps
CPU time 1.14 seconds
Started Jan 24 10:35:09 PM PST 24
Finished Jan 24 10:35:12 PM PST 24
Peak memory 202440 kb
Host smart-4e0301d1-5c2b-4d59-a481-44f8e2f0a754
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720818574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.720818574
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2936543065
Short name T3
Test name
Test status
Simulation time 1053183760 ps
CPU time 6.23 seconds
Started Jan 24 10:35:10 PM PST 24
Finished Jan 24 10:35:17 PM PST 24
Peak memory 241972 kb
Host smart-835cefb6-a649-4076-b66c-ae775eaede51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936543065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2936543065
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.3876679784
Short name T1367
Test name
Test status
Simulation time 5770610291 ps
CPU time 698.8 seconds
Started Jan 24 10:35:04 PM PST 24
Finished Jan 24 10:46:45 PM PST 24
Peak memory 1641312 kb
Host smart-f8657771-0fb9-4941-9968-7ede4c676ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876679784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.3876679784
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2749942605
Short name T1237
Test name
Test status
Simulation time 6591608152 ps
CPU time 82.77 seconds
Started Jan 24 10:35:58 PM PST 24
Finished Jan 24 10:37:22 PM PST 24
Peak memory 244592 kb
Host smart-a0f429ec-5ac3-4330-9dce-4006d1b9ab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749942605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2749942605
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3387951609
Short name T1373
Test name
Test status
Simulation time 56025673 ps
CPU time 0.64 seconds
Started Jan 24 10:35:00 PM PST 24
Finished Jan 24 10:35:06 PM PST 24
Peak memory 201612 kb
Host smart-b3a7f88e-9fd1-472e-812e-c1db4ba17aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387951609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3387951609
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2662232195
Short name T867
Test name
Test status
Simulation time 3477076141 ps
CPU time 18.95 seconds
Started Jan 24 10:35:10 PM PST 24
Finished Jan 24 10:35:30 PM PST 24
Peak memory 211840 kb
Host smart-c6241cbc-51d2-4aac-a6c9-34bafbe73443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662232195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2662232195
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_rx_oversample.1223321423
Short name T1101
Test name
Test status
Simulation time 33849639810 ps
CPU time 119.15 seconds
Started Jan 24 10:34:57 PM PST 24
Finished Jan 24 10:37:03 PM PST 24
Peak memory 246548 kb
Host smart-d0bb2b5b-d145-4b54-9f6d-ef604a78579e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223321423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_rx_oversample
.1223321423
Directory /workspace/45.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2027798910
Short name T277
Test name
Test status
Simulation time 5536059672 ps
CPU time 69.61 seconds
Started Jan 24 10:35:00 PM PST 24
Finished Jan 24 10:36:15 PM PST 24
Peak memory 270784 kb
Host smart-9a751695-a26e-4f03-bc32-6464d3c57a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027798910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2027798910
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.1993913600
Short name T224
Test name
Test status
Simulation time 874724828 ps
CPU time 12.6 seconds
Started Jan 24 11:12:10 PM PST 24
Finished Jan 24 11:12:25 PM PST 24
Peak memory 212400 kb
Host smart-3d7444df-fe80-43e3-a2c0-d1feff9dff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993913600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1993913600
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3925516746
Short name T330
Test name
Test status
Simulation time 2156220206 ps
CPU time 4.03 seconds
Started Jan 24 10:35:49 PM PST 24
Finished Jan 24 10:35:54 PM PST 24
Peak memory 202732 kb
Host smart-0b45f6bb-e503-4b18-859d-a21162d86076
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925516746 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3925516746
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3784162381
Short name T1124
Test name
Test status
Simulation time 10110164521 ps
CPU time 10.64 seconds
Started Jan 24 10:35:43 PM PST 24
Finished Jan 24 10:35:55 PM PST 24
Peak memory 253720 kb
Host smart-6c0714a4-5b5c-4712-9161-af5cab6b71e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784162381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3784162381
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2268252828
Short name T458
Test name
Test status
Simulation time 10096290895 ps
CPU time 96.64 seconds
Started Jan 24 10:35:45 PM PST 24
Finished Jan 24 10:37:23 PM PST 24
Peak memory 650368 kb
Host smart-109b65ad-889c-49c4-b7ce-e53d2c88fe9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268252828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2268252828
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.3469280090
Short name T168
Test name
Test status
Simulation time 2934349995 ps
CPU time 3.33 seconds
Started Jan 24 10:35:47 PM PST 24
Finished Jan 24 10:35:52 PM PST 24
Peak memory 202744 kb
Host smart-549fecf8-8d62-4514-b76a-5b4850336392
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469280090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.3469280090
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1995098298
Short name T1045
Test name
Test status
Simulation time 3205883615 ps
CPU time 5.9 seconds
Started Jan 24 10:35:33 PM PST 24
Finished Jan 24 10:35:41 PM PST 24
Peak memory 202668 kb
Host smart-6db37c82-63e8-4e41-a6e7-05c90a2345d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995098298 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1995098298
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3036819427
Short name T1141
Test name
Test status
Simulation time 9274399692 ps
CPU time 172.17 seconds
Started Jan 24 10:35:31 PM PST 24
Finished Jan 24 10:38:25 PM PST 24
Peak memory 1969908 kb
Host smart-5f920e25-42ee-4f7b-822e-13a3ad09f464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036819427 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3036819427
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.4016813260
Short name T1066
Test name
Test status
Simulation time 5285339065 ps
CPU time 5.51 seconds
Started Jan 24 10:35:45 PM PST 24
Finished Jan 24 10:35:52 PM PST 24
Peak memory 211212 kb
Host smart-42ed516a-a68d-4440-b7f3-3d7ef9c7b035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016813260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.4016813260
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2388637653
Short name T283
Test name
Test status
Simulation time 5975485050 ps
CPU time 34.93 seconds
Started Jan 24 10:35:17 PM PST 24
Finished Jan 24 10:35:54 PM PST 24
Peak memory 202628 kb
Host smart-d26b36d2-f99e-4b98-b9ec-d96ffd5eaf07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388637653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2388637653
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.1071171452
Short name T653
Test name
Test status
Simulation time 57432767459 ps
CPU time 55.96 seconds
Started Jan 24 10:35:48 PM PST 24
Finished Jan 24 10:36:45 PM PST 24
Peak memory 215460 kb
Host smart-609d59f5-caea-4181-827b-1791496c25e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071171452 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.1071171452
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3151847343
Short name T1243
Test name
Test status
Simulation time 4752855625 ps
CPU time 44.41 seconds
Started Jan 24 10:35:18 PM PST 24
Finished Jan 24 10:36:03 PM PST 24
Peak memory 202636 kb
Host smart-543ef04c-4b3f-448f-8dfa-3e38c0e9386c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151847343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3151847343
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.622494675
Short name T1112
Test name
Test status
Simulation time 23469594679 ps
CPU time 733.47 seconds
Started Jan 24 10:35:17 PM PST 24
Finished Jan 24 10:47:32 PM PST 24
Peak memory 4900496 kb
Host smart-7bc97e1a-5afb-43dd-ac0c-7e39d655cc16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622494675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.622494675
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.4089058788
Short name T700
Test name
Test status
Simulation time 31233519606 ps
CPU time 1353.39 seconds
Started Jan 24 10:35:34 PM PST 24
Finished Jan 24 10:58:09 PM PST 24
Peak memory 2639024 kb
Host smart-a274e95e-40d1-47ee-a294-33e025390711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089058788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.4089058788
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.4073597844
Short name T911
Test name
Test status
Simulation time 1780073903 ps
CPU time 7.58 seconds
Started Jan 24 10:35:33 PM PST 24
Finished Jan 24 10:35:41 PM PST 24
Peak memory 202568 kb
Host smart-02d49721-feb8-430a-a25f-89efb4450784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073597844 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.4073597844
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_ovf.3008024628
Short name T731
Test name
Test status
Simulation time 4393171589 ps
CPU time 67.46 seconds
Started Jan 24 10:35:34 PM PST 24
Finished Jan 24 10:36:43 PM PST 24
Peak memory 300500 kb
Host smart-a3b2d6fe-275e-43ab-a20a-f2cfe3a3b040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008024628 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_tx_ovf.3008024628
Directory /workspace/45.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.2828754321
Short name T1317
Test name
Test status
Simulation time 1254470784 ps
CPU time 6.24 seconds
Started Jan 24 10:35:44 PM PST 24
Finished Jan 24 10:35:52 PM PST 24
Peak memory 202600 kb
Host smart-446421ca-31f8-4dff-b14b-73e64e02c45e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828754321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.i2c_target_unexp_stop.2828754321
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3665817841
Short name T916
Test name
Test status
Simulation time 15479032 ps
CPU time 0.6 seconds
Started Jan 24 10:36:54 PM PST 24
Finished Jan 24 10:36:55 PM PST 24
Peak memory 202056 kb
Host smart-07c1ec87-1eb9-4905-84d9-e98742fd609c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665817841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3665817841
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3311247688
Short name T48
Test name
Test status
Simulation time 47721585 ps
CPU time 2.2 seconds
Started Jan 24 10:36:21 PM PST 24
Finished Jan 24 10:36:24 PM PST 24
Peak memory 210744 kb
Host smart-9b83b470-8215-49a8-ab02-9a6635bb6f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311247688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3311247688
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3355198816
Short name T767
Test name
Test status
Simulation time 2009606799 ps
CPU time 11.83 seconds
Started Jan 24 10:36:02 PM PST 24
Finished Jan 24 10:36:15 PM PST 24
Peak memory 223040 kb
Host smart-e992fca6-8577-453c-b8fd-46da4a883588
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355198816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3355198816
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.868891743
Short name T1324
Test name
Test status
Simulation time 2098142703 ps
CPU time 47.42 seconds
Started Jan 24 10:35:59 PM PST 24
Finished Jan 24 10:36:47 PM PST 24
Peak memory 457332 kb
Host smart-23d0a49c-475f-4e38-9476-aa41e6626494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868891743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.868891743
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.3906056142
Short name T812
Test name
Test status
Simulation time 4241150326 ps
CPU time 358.17 seconds
Started Jan 24 10:36:02 PM PST 24
Finished Jan 24 10:42:01 PM PST 24
Peak memory 1057732 kb
Host smart-3b8965f8-fbe9-4f32-9eff-b2a9534bc0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906056142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3906056142
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1634566764
Short name T727
Test name
Test status
Simulation time 541673926 ps
CPU time 0.93 seconds
Started Jan 24 10:35:57 PM PST 24
Finished Jan 24 10:35:59 PM PST 24
Peak memory 202496 kb
Host smart-fcbb1aaf-6103-4e0f-9b37-5d2ce25771b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634566764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1634566764
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.4068604265
Short name T1265
Test name
Test status
Simulation time 254099331 ps
CPU time 14.89 seconds
Started Jan 24 10:36:02 PM PST 24
Finished Jan 24 10:36:18 PM PST 24
Peak memory 252268 kb
Host smart-3f6c7855-bf62-450e-9b41-1b6a38594ead
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068604265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.4068604265
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1374356389
Short name T133
Test name
Test status
Simulation time 13151920218 ps
CPU time 408.42 seconds
Started Jan 24 10:36:02 PM PST 24
Finished Jan 24 10:42:52 PM PST 24
Peak memory 1876000 kb
Host smart-5efa0fae-5453-4641-aacc-bb7da0aa10c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374356389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1374356389
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.4043525578
Short name T1135
Test name
Test status
Simulation time 2904457511 ps
CPU time 176.81 seconds
Started Jan 24 10:36:58 PM PST 24
Finished Jan 24 10:39:55 PM PST 24
Peak memory 276120 kb
Host smart-d107637d-eead-4cb1-b05d-15eea1d63611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043525578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.4043525578
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2256523314
Short name T532
Test name
Test status
Simulation time 46802687 ps
CPU time 0.65 seconds
Started Jan 24 10:36:00 PM PST 24
Finished Jan 24 10:36:03 PM PST 24
Peak memory 201592 kb
Host smart-25260f59-1d1a-4f17-a333-ddcf62a6c9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256523314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2256523314
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1817559976
Short name T602
Test name
Test status
Simulation time 400393882 ps
CPU time 18.81 seconds
Started Jan 24 10:36:16 PM PST 24
Finished Jan 24 10:36:36 PM PST 24
Peak memory 222892 kb
Host smart-e71c8c8c-a3e6-4b6d-80df-d63c7b8726e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817559976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1817559976
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_rx_oversample.837674012
Short name T876
Test name
Test status
Simulation time 7784476841 ps
CPU time 131.52 seconds
Started Jan 24 10:35:59 PM PST 24
Finished Jan 24 10:38:11 PM PST 24
Peak memory 351112 kb
Host smart-84980ab7-4434-44d9-8aa1-9be125b662e8
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837674012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_rx_oversample.
837674012
Directory /workspace/46.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1717557829
Short name T1033
Test name
Test status
Simulation time 1277228800 ps
CPU time 24.39 seconds
Started Jan 24 10:35:59 PM PST 24
Finished Jan 24 10:36:26 PM PST 24
Peak memory 247204 kb
Host smart-6a05e07c-3e34-4f1f-9e28-29b1cfe01163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717557829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1717557829
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.835103886
Short name T752
Test name
Test status
Simulation time 573866930 ps
CPU time 8.71 seconds
Started Jan 24 10:36:17 PM PST 24
Finished Jan 24 10:36:27 PM PST 24
Peak memory 212556 kb
Host smart-682f2f47-dd48-4d6c-80d9-92c3ac378dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835103886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.835103886
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.409562444
Short name T1469
Test name
Test status
Simulation time 2532005275 ps
CPU time 2.68 seconds
Started Jan 24 10:36:38 PM PST 24
Finished Jan 24 10:36:41 PM PST 24
Peak memory 202664 kb
Host smart-11b3e522-a811-43c2-9496-727681f2be00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409562444 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.409562444
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.868913396
Short name T1397
Test name
Test status
Simulation time 10169034957 ps
CPU time 23.73 seconds
Started Jan 24 10:36:29 PM PST 24
Finished Jan 24 10:36:54 PM PST 24
Peak memory 330252 kb
Host smart-8b8df5dd-58d1-437f-a3d0-735f8e892b50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868913396 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.868913396
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.1244914054
Short name T1375
Test name
Test status
Simulation time 10227810244 ps
CPU time 28.91 seconds
Started Jan 24 10:36:36 PM PST 24
Finished Jan 24 10:37:06 PM PST 24
Peak memory 413088 kb
Host smart-224f69a7-7f15-4216-9ac6-77659ae99fd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244914054 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.1244914054
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1289340418
Short name T765
Test name
Test status
Simulation time 1699184166 ps
CPU time 2.47 seconds
Started Jan 24 10:36:56 PM PST 24
Finished Jan 24 10:37:00 PM PST 24
Peak memory 202652 kb
Host smart-995aa248-cdbb-4b8f-babc-9a6e6300aa21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289340418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1289340418
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1944114215
Short name T1435
Test name
Test status
Simulation time 1023994822 ps
CPU time 4.71 seconds
Started Jan 24 10:36:27 PM PST 24
Finished Jan 24 10:36:32 PM PST 24
Peak memory 206436 kb
Host smart-1578f52b-6e34-4d9f-ba7a-5f137a4ea160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944114215 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1944114215
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_perf.1557692834
Short name T400
Test name
Test status
Simulation time 1780200159 ps
CPU time 2.95 seconds
Started Jan 24 10:36:38 PM PST 24
Finished Jan 24 10:36:42 PM PST 24
Peak memory 202592 kb
Host smart-57efe172-aefb-48a7-a29a-a9a75b6d02b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557692834 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.1557692834
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.3659677048
Short name T1314
Test name
Test status
Simulation time 2408862505 ps
CPU time 32.59 seconds
Started Jan 24 10:36:17 PM PST 24
Finished Jan 24 10:36:51 PM PST 24
Peak memory 202640 kb
Host smart-9240fe14-e205-4074-bdb8-956911075122
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659677048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.3659677048
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.2039040295
Short name T1438
Test name
Test status
Simulation time 43452597576 ps
CPU time 88.21 seconds
Started Jan 24 10:36:38 PM PST 24
Finished Jan 24 10:38:07 PM PST 24
Peak memory 577040 kb
Host smart-61aa56f9-edf4-48c0-8e6e-b95c77bf963b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039040295 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_stress_all.2039040295
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1653551661
Short name T1271
Test name
Test status
Simulation time 4029393928 ps
CPU time 34.73 seconds
Started Jan 24 10:36:18 PM PST 24
Finished Jan 24 10:36:54 PM PST 24
Peak memory 237136 kb
Host smart-bf3ddf67-357a-4c4e-a1df-d6fda1db65eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653551661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1653551661
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.14314140
Short name T1092
Test name
Test status
Simulation time 9004883621 ps
CPU time 5.29 seconds
Started Jan 24 10:36:19 PM PST 24
Finished Jan 24 10:36:25 PM PST 24
Peak memory 282432 kb
Host smart-225fd6af-d222-4890-bf9c-c19cebbafae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14314140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stress_wr.14314140
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1942775014
Short name T1068
Test name
Test status
Simulation time 10076522825 ps
CPU time 133.63 seconds
Started Jan 24 10:36:21 PM PST 24
Finished Jan 24 10:38:35 PM PST 24
Peak memory 751792 kb
Host smart-ff52f613-b8bf-474a-9741-2741c89c592a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942775014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1942775014
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3825162824
Short name T1299
Test name
Test status
Simulation time 21466610602 ps
CPU time 6.72 seconds
Started Jan 24 10:36:25 PM PST 24
Finished Jan 24 10:36:33 PM PST 24
Peak memory 202648 kb
Host smart-1b210593-cf56-4558-8e0b-d7298d1f0f25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825162824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3825162824
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_ovf.4235984662
Short name T542
Test name
Test status
Simulation time 5064587938 ps
CPU time 47.35 seconds
Started Jan 24 10:36:24 PM PST 24
Finished Jan 24 10:37:12 PM PST 24
Peak memory 230464 kb
Host smart-14d1c2c0-7729-46c1-89e9-560be04b4192
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235984662 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_tx_ovf.4235984662
Directory /workspace/46.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.2026578801
Short name T1005
Test name
Test status
Simulation time 1353888607 ps
CPU time 7.71 seconds
Started Jan 24 10:36:26 PM PST 24
Finished Jan 24 10:36:35 PM PST 24
Peak memory 202648 kb
Host smart-d2f84f46-15c7-49fc-9794-716d8825524e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026578801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.i2c_target_unexp_stop.2026578801
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1623054178
Short name T952
Test name
Test status
Simulation time 19729350 ps
CPU time 0.63 seconds
Started Jan 24 10:37:40 PM PST 24
Finished Jan 24 10:37:44 PM PST 24
Peak memory 201084 kb
Host smart-13699c06-c829-4cc7-a8eb-6df12f3cc6bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623054178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1623054178
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1181077704
Short name T205
Test name
Test status
Simulation time 113127118 ps
CPU time 1.37 seconds
Started Jan 24 10:37:18 PM PST 24
Finished Jan 24 10:37:24 PM PST 24
Peak memory 210768 kb
Host smart-4d1c9b08-bd11-4cd0-8e73-1d6b57e5bb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181077704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1181077704
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1063419155
Short name T807
Test name
Test status
Simulation time 216635999 ps
CPU time 3.87 seconds
Started Jan 24 10:36:56 PM PST 24
Finished Jan 24 10:37:01 PM PST 24
Peak memory 227884 kb
Host smart-ee905b51-b54f-4697-a5b2-9b2f58feeeb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063419155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1063419155
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3992251220
Short name T1273
Test name
Test status
Simulation time 9779164303 ps
CPU time 88.3 seconds
Started Jan 24 10:37:18 PM PST 24
Finished Jan 24 10:38:51 PM PST 24
Peak memory 813304 kb
Host smart-7f7f0f76-8f42-4e06-a526-993da741be91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992251220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3992251220
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2571896836
Short name T960
Test name
Test status
Simulation time 3469671521 ps
CPU time 298.79 seconds
Started Jan 24 10:36:58 PM PST 24
Finished Jan 24 10:41:58 PM PST 24
Peak memory 887720 kb
Host smart-1136a6c1-bc72-436d-9cbe-3b0dcee5312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571896836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2571896836
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1821400519
Short name T199
Test name
Test status
Simulation time 80438683 ps
CPU time 0.86 seconds
Started Jan 24 10:36:56 PM PST 24
Finished Jan 24 10:36:58 PM PST 24
Peak memory 202324 kb
Host smart-c6bc64f8-38b1-48b0-bfd8-6488d2faaa38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821400519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1821400519
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.557402283
Short name T1250
Test name
Test status
Simulation time 166934043 ps
CPU time 4.24 seconds
Started Jan 24 10:37:16 PM PST 24
Finished Jan 24 10:37:22 PM PST 24
Peak memory 230884 kb
Host smart-c9579747-00e6-48fe-8043-cff92dff7bd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557402283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
557402283
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.192839929
Short name T804
Test name
Test status
Simulation time 21975477043 ps
CPU time 639 seconds
Started Jan 24 10:36:54 PM PST 24
Finished Jan 24 10:47:34 PM PST 24
Peak memory 1547680 kb
Host smart-b54af38d-2dc2-49c5-bf9f-985945bd255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192839929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.192839929
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.459748017
Short name T1114
Test name
Test status
Simulation time 3993642227 ps
CPU time 47.19 seconds
Started Jan 24 10:37:39 PM PST 24
Finished Jan 24 10:38:30 PM PST 24
Peak memory 260404 kb
Host smart-5d163b98-1ce6-4a15-9ea7-ba0b03f65156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459748017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.459748017
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2476712539
Short name T956
Test name
Test status
Simulation time 52818529 ps
CPU time 0.63 seconds
Started Jan 24 10:36:55 PM PST 24
Finished Jan 24 10:36:56 PM PST 24
Peak memory 201504 kb
Host smart-a411107c-fb5f-46f3-9432-65174753e878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476712539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2476712539
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2098451583
Short name T579
Test name
Test status
Simulation time 5232657295 ps
CPU time 78.1 seconds
Started Jan 24 10:37:17 PM PST 24
Finished Jan 24 10:38:39 PM PST 24
Peak memory 218988 kb
Host smart-fc1ad138-b63f-4c89-bf3a-aee7eab7cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098451583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2098451583
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_rx_oversample.1750710447
Short name T1453
Test name
Test status
Simulation time 37834281101 ps
CPU time 62.61 seconds
Started Jan 24 10:36:55 PM PST 24
Finished Jan 24 10:37:58 PM PST 24
Peak memory 296216 kb
Host smart-75d288a4-2394-46d9-94dc-885d637ee79b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750710447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_rx_oversample
.1750710447
Directory /workspace/47.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3602512143
Short name T1396
Test name
Test status
Simulation time 10381286569 ps
CPU time 70.73 seconds
Started Jan 24 10:36:55 PM PST 24
Finished Jan 24 10:38:07 PM PST 24
Peak memory 313912 kb
Host smart-b5d984fd-72ff-4fe6-98eb-178112ef5d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602512143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3602512143
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3892468541
Short name T1430
Test name
Test status
Simulation time 35337149889 ps
CPU time 2199.87 seconds
Started Jan 24 10:37:19 PM PST 24
Finished Jan 24 11:14:03 PM PST 24
Peak memory 3876980 kb
Host smart-7cf2a6b7-f424-4a76-8878-2d87e261b86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892468541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3892468541
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all_with_rand_reset.2106446962
Short name T104
Test name
Test status
Simulation time 22279307380 ps
CPU time 1018.57 seconds
Started Jan 24 10:37:37 PM PST 24
Finished Jan 24 10:54:41 PM PST 24
Peak memory 1545964 kb
Host smart-070583fd-0549-47be-9156-8ec6c141b06b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106446962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.i2c_host_stress_all_with_rand_reset.2106446962
Directory /workspace/47.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.2215547688
Short name T251
Test name
Test status
Simulation time 1092011269 ps
CPU time 20.38 seconds
Started Jan 24 10:37:19 PM PST 24
Finished Jan 24 10:37:43 PM PST 24
Peak memory 218828 kb
Host smart-62ef1c21-28e1-417e-993f-5abd22fd7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215547688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.2215547688
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1735465140
Short name T744
Test name
Test status
Simulation time 3057454501 ps
CPU time 3.5 seconds
Started Jan 24 10:37:38 PM PST 24
Finished Jan 24 10:37:46 PM PST 24
Peak memory 202708 kb
Host smart-60142c92-e09c-4adc-b035-1f3089049a6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735465140 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1735465140
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.868288968
Short name T1441
Test name
Test status
Simulation time 10072736892 ps
CPU time 70.16 seconds
Started Jan 24 10:37:38 PM PST 24
Finished Jan 24 10:38:52 PM PST 24
Peak memory 594372 kb
Host smart-82582db9-8e84-48e1-823d-8e6b614d9d12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868288968 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.868288968
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1560968861
Short name T471
Test name
Test status
Simulation time 10106874216 ps
CPU time 20.65 seconds
Started Jan 24 11:03:52 PM PST 24
Finished Jan 24 11:04:13 PM PST 24
Peak memory 344084 kb
Host smart-ef3c619e-a94c-41b0-9c38-2e235b194579
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560968861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1560968861
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.4054818602
Short name T1295
Test name
Test status
Simulation time 1557982680 ps
CPU time 3.39 seconds
Started Jan 24 10:37:35 PM PST 24
Finished Jan 24 10:37:46 PM PST 24
Peak memory 202620 kb
Host smart-3973e1fb-2c19-4676-894c-cf63c11e29eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054818602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.4054818602
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.4042388584
Short name T1429
Test name
Test status
Simulation time 2204275755 ps
CPU time 6.85 seconds
Started Jan 24 10:37:19 PM PST 24
Finished Jan 24 10:37:30 PM PST 24
Peak memory 202572 kb
Host smart-7f17701e-0473-4c0d-83ce-ee0d2a5b62cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042388584 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.4042388584
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1402669969
Short name T474
Test name
Test status
Simulation time 3841398320 ps
CPU time 26.77 seconds
Started Jan 24 10:37:20 PM PST 24
Finished Jan 24 10:37:50 PM PST 24
Peak memory 703448 kb
Host smart-7b7bf189-6b16-4f84-bd46-ed1d87a2ce48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402669969 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1402669969
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.828554599
Short name T1156
Test name
Test status
Simulation time 3714639071 ps
CPU time 5.36 seconds
Started Jan 24 10:37:39 PM PST 24
Finished Jan 24 10:37:48 PM PST 24
Peak memory 208840 kb
Host smart-2f2f22c4-5d76-43cf-bfd1-584b06c2341b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828554599 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_perf.828554599
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2542088043
Short name T973
Test name
Test status
Simulation time 4943356867 ps
CPU time 16.18 seconds
Started Jan 24 10:37:16 PM PST 24
Finished Jan 24 10:37:33 PM PST 24
Peak memory 202660 kb
Host smart-c541792a-1a9b-4be8-81d8-7a7d2869f818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542088043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2542088043
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.358718607
Short name T97
Test name
Test status
Simulation time 1702301363 ps
CPU time 16.86 seconds
Started Jan 24 10:37:19 PM PST 24
Finished Jan 24 10:37:40 PM PST 24
Peak memory 202668 kb
Host smart-82b11b19-a5a6-49da-9e13-9775f4004710
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358718607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.358718607
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2036592330
Short name T525
Test name
Test status
Simulation time 59731296097 ps
CPU time 1497.57 seconds
Started Jan 24 10:37:16 PM PST 24
Finished Jan 24 11:02:15 PM PST 24
Peak memory 7194160 kb
Host smart-0172cd35-a841-407b-8aad-bd1ef246252e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036592330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2036592330
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.3124677020
Short name T1184
Test name
Test status
Simulation time 6694537660 ps
CPU time 7.18 seconds
Started Jan 24 10:54:57 PM PST 24
Finished Jan 24 10:55:05 PM PST 24
Peak memory 202680 kb
Host smart-e41c57f2-d451-4346-a6e7-8ba4ec66c46e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124677020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.3124677020
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_ovf.1645144708
Short name T271
Test name
Test status
Simulation time 4702597073 ps
CPU time 87.18 seconds
Started Jan 24 10:37:18 PM PST 24
Finished Jan 24 10:38:50 PM PST 24
Peak memory 322628 kb
Host smart-0403c078-5081-4406-8759-2bf918bf5a29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645144708 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_tx_ovf.1645144708
Directory /workspace/47.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.2634470358
Short name T999
Test name
Test status
Simulation time 7423615525 ps
CPU time 8.53 seconds
Started Jan 24 10:37:17 PM PST 24
Finished Jan 24 10:37:31 PM PST 24
Peak memory 215772 kb
Host smart-345ee1bc-6c68-4fbb-ac20-e6e83c11d203
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634470358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.i2c_target_unexp_stop.2634470358
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1465960848
Short name T693
Test name
Test status
Simulation time 15818058 ps
CPU time 0.67 seconds
Started Jan 24 10:38:39 PM PST 24
Finished Jan 24 10:38:40 PM PST 24
Peak memory 201172 kb
Host smart-703f0524-b9b2-4489-bbda-17a5881ce9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465960848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1465960848
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2539242078
Short name T305
Test name
Test status
Simulation time 633302070 ps
CPU time 1.2 seconds
Started Jan 24 10:38:21 PM PST 24
Finished Jan 24 10:38:23 PM PST 24
Peak memory 211784 kb
Host smart-8f8631ec-bd8d-47f6-acd5-84ecd8367a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539242078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2539242078
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3822012377
Short name T214
Test name
Test status
Simulation time 970878281 ps
CPU time 9.19 seconds
Started Jan 24 10:38:23 PM PST 24
Finished Jan 24 10:38:34 PM PST 24
Peak memory 286008 kb
Host smart-64301172-79a2-4ad1-8ef6-4995edf1aa85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822012377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3822012377
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1922910425
Short name T650
Test name
Test status
Simulation time 4271305862 ps
CPU time 192.48 seconds
Started Jan 24 10:38:21 PM PST 24
Finished Jan 24 10:41:35 PM PST 24
Peak memory 742844 kb
Host smart-932d145a-9b32-4011-aab2-6f3dfae4a721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922910425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1922910425
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1479418557
Short name T1503
Test name
Test status
Simulation time 22650034181 ps
CPU time 357.96 seconds
Started Jan 24 10:38:20 PM PST 24
Finished Jan 24 10:44:19 PM PST 24
Peak memory 1050268 kb
Host smart-13128b4e-7bb0-4acb-8dcb-921bbf1d73ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479418557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1479418557
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3197098768
Short name T201
Test name
Test status
Simulation time 166920078 ps
CPU time 0.79 seconds
Started Jan 24 10:38:20 PM PST 24
Finished Jan 24 10:38:22 PM PST 24
Peak memory 202304 kb
Host smart-0585b5f2-e18b-4f8a-b0dc-8d56c903decd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197098768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3197098768
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.2521541798
Short name T820
Test name
Test status
Simulation time 683974315 ps
CPU time 7.9 seconds
Started Jan 24 10:38:22 PM PST 24
Finished Jan 24 10:38:31 PM PST 24
Peak memory 256444 kb
Host smart-b593b5ef-7b20-4c3c-b463-c1aaa07a81eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521541798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.2521541798
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1085520460
Short name T1165
Test name
Test status
Simulation time 17873827158 ps
CPU time 442.22 seconds
Started Jan 24 10:38:23 PM PST 24
Finished Jan 24 10:45:47 PM PST 24
Peak memory 1228664 kb
Host smart-e6e19f19-bc93-4230-ac6b-1bc02dddde77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085520460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1085520460
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1753057614
Short name T316
Test name
Test status
Simulation time 3076288532 ps
CPU time 37.34 seconds
Started Jan 24 10:38:46 PM PST 24
Finished Jan 24 10:39:24 PM PST 24
Peak memory 265284 kb
Host smart-991b897b-d3d1-461f-9875-6a0ca2f60223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753057614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1753057614
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2735325946
Short name T4
Test name
Test status
Simulation time 16700007 ps
CPU time 0.64 seconds
Started Jan 24 10:37:36 PM PST 24
Finished Jan 24 10:37:43 PM PST 24
Peak memory 201500 kb
Host smart-142e461f-c42a-4709-abb0-b49f871dd97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735325946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2735325946
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1290374091
Short name T358
Test name
Test status
Simulation time 7515038479 ps
CPU time 45.34 seconds
Started Jan 24 10:38:20 PM PST 24
Finished Jan 24 10:39:07 PM PST 24
Peak memory 298008 kb
Host smart-22bc7a1c-da40-431c-b8b1-46428b3dde96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290374091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1290374091
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_rx_oversample.4100545609
Short name T687
Test name
Test status
Simulation time 2446711794 ps
CPU time 206.24 seconds
Started Jan 24 10:58:20 PM PST 24
Finished Jan 24 11:01:49 PM PST 24
Peak memory 284140 kb
Host smart-e28e20e0-e04b-4d20-9e4e-2980284abf98
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100545609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_rx_oversample
.4100545609
Directory /workspace/48.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.400347646
Short name T197
Test name
Test status
Simulation time 17051895794 ps
CPU time 3191.21 seconds
Started Jan 24 10:38:23 PM PST 24
Finished Jan 24 11:31:36 PM PST 24
Peak memory 3110776 kb
Host smart-bfe5f513-204b-41ac-a34e-3c8b5a2947c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400347646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.400347646
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3260649208
Short name T1127
Test name
Test status
Simulation time 1623419248 ps
CPU time 35.47 seconds
Started Jan 24 10:38:22 PM PST 24
Finished Jan 24 10:38:59 PM PST 24
Peak memory 210816 kb
Host smart-ab38894a-ab40-4ef4-a2b9-07bb51390840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260649208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3260649208
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.4032500475
Short name T516
Test name
Test status
Simulation time 1244909314 ps
CPU time 4.6 seconds
Started Jan 24 10:38:38 PM PST 24
Finished Jan 24 10:38:44 PM PST 24
Peak memory 202664 kb
Host smart-7d4c68dc-6c1d-4e7e-ad24-41f310e9d13a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032500475 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.4032500475
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.276554559
Short name T1043
Test name
Test status
Simulation time 11123639195 ps
CPU time 4.66 seconds
Started Jan 24 10:38:46 PM PST 24
Finished Jan 24 10:38:51 PM PST 24
Peak memory 225352 kb
Host smart-1c571f48-6075-44fd-afdd-6703363492b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276554559 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.276554559
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1559286917
Short name T887
Test name
Test status
Simulation time 10265443147 ps
CPU time 12.86 seconds
Started Jan 24 10:38:35 PM PST 24
Finished Jan 24 10:38:49 PM PST 24
Peak memory 299796 kb
Host smart-037d452e-8bb6-4252-8ac1-b55c1f72f118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559286917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1559286917
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.772613478
Short name T855
Test name
Test status
Simulation time 868732461 ps
CPU time 2.35 seconds
Started Jan 24 10:38:37 PM PST 24
Finished Jan 24 10:38:40 PM PST 24
Peak memory 202700 kb
Host smart-c8f9bcae-bdd9-4e4a-96b5-f7bf63b48d29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772613478 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.772613478
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2453729620
Short name T1036
Test name
Test status
Simulation time 3265749543 ps
CPU time 6.94 seconds
Started Jan 24 10:38:26 PM PST 24
Finished Jan 24 10:38:34 PM PST 24
Peak memory 208748 kb
Host smart-9d9bced8-584f-4a48-bb29-ef41c03cca41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453729620 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2453729620
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.1505996199
Short name T811
Test name
Test status
Simulation time 24292205466 ps
CPU time 180.13 seconds
Started Jan 24 10:38:46 PM PST 24
Finished Jan 24 10:41:47 PM PST 24
Peak memory 1591268 kb
Host smart-5fd931be-ed99-4ef1-b82e-743e19cb4a60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505996199 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1505996199
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.3991519069
Short name T810
Test name
Test status
Simulation time 3335162277 ps
CPU time 5.42 seconds
Started Jan 24 10:38:37 PM PST 24
Finished Jan 24 10:38:44 PM PST 24
Peak memory 202652 kb
Host smart-d401a48a-215d-4978-8147-06da6166d9b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991519069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.3991519069
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.3695098925
Short name T1504
Test name
Test status
Simulation time 1226563605 ps
CPU time 24.43 seconds
Started Jan 24 10:38:21 PM PST 24
Finished Jan 24 10:38:47 PM PST 24
Peak memory 202628 kb
Host smart-8ffff6cf-f4d8-4a10-b776-b03c0bef1e82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695098925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.3695098925
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2923948316
Short name T1178
Test name
Test status
Simulation time 3242724182 ps
CPU time 11.96 seconds
Started Jan 24 10:38:25 PM PST 24
Finished Jan 24 10:38:39 PM PST 24
Peak memory 207396 kb
Host smart-2a4e6ce7-be07-4622-a010-8bf857dae571
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923948316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2923948316
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3807668591
Short name T707
Test name
Test status
Simulation time 31100405771 ps
CPU time 141.88 seconds
Started Jan 24 10:38:21 PM PST 24
Finished Jan 24 10:40:44 PM PST 24
Peak memory 1837308 kb
Host smart-571cfab9-dfed-4d3a-8449-eacd3eca72fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807668591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3807668591
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.4289580958
Short name T838
Test name
Test status
Simulation time 1640647504 ps
CPU time 6.96 seconds
Started Jan 24 10:38:46 PM PST 24
Finished Jan 24 10:38:53 PM PST 24
Peak memory 202584 kb
Host smart-ddfec403-e8e2-4cd7-846b-53218a255e58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289580958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.4289580958
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_ovf.2590660477
Short name T1348
Test name
Test status
Simulation time 13093508928 ps
CPU time 164.01 seconds
Started Jan 24 10:38:34 PM PST 24
Finished Jan 24 10:41:19 PM PST 24
Peak memory 487288 kb
Host smart-12281ccf-d6a0-4370-baa6-998daf56363e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590660477 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_tx_ovf.2590660477
Directory /workspace/48.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.2712832469
Short name T741
Test name
Test status
Simulation time 1814792960 ps
CPU time 7.72 seconds
Started Jan 24 10:38:35 PM PST 24
Finished Jan 24 10:38:44 PM PST 24
Peak memory 206680 kb
Host smart-dd22bb13-6f6d-4092-943e-db0d5ee1d76f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712832469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.2712832469
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4080543291
Short name T948
Test name
Test status
Simulation time 30715294 ps
CPU time 0.62 seconds
Started Jan 24 10:39:33 PM PST 24
Finished Jan 24 10:39:34 PM PST 24
Peak memory 201160 kb
Host smart-30e06d75-ae32-4af5-ab3e-aa4693ad65ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080543291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4080543291
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.745727469
Short name T410
Test name
Test status
Simulation time 49215916 ps
CPU time 1.58 seconds
Started Jan 25 12:08:59 AM PST 24
Finished Jan 25 12:09:02 AM PST 24
Peak memory 210776 kb
Host smart-cfceb60d-38e4-4f07-b3b8-7ba041d7cecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745727469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.745727469
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.631735510
Short name T502
Test name
Test status
Simulation time 1434483878 ps
CPU time 6.71 seconds
Started Jan 24 10:38:55 PM PST 24
Finished Jan 24 10:39:03 PM PST 24
Peak memory 253640 kb
Host smart-7464091b-a89a-4338-8178-46953172d71a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631735510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.631735510
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2300257963
Short name T1161
Test name
Test status
Simulation time 5061918898 ps
CPU time 88.79 seconds
Started Jan 24 10:39:04 PM PST 24
Finished Jan 24 10:40:34 PM PST 24
Peak memory 749564 kb
Host smart-8c12ba39-ad03-4b63-8ad7-28e34d2613bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300257963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2300257963
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2149831819
Short name T1325
Test name
Test status
Simulation time 116292920 ps
CPU time 0.96 seconds
Started Jan 24 10:38:55 PM PST 24
Finished Jan 24 10:38:57 PM PST 24
Peak memory 202324 kb
Host smart-c1bc9650-7982-4a2d-aedc-f662453c3bfa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149831819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2149831819
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.602024348
Short name T1506
Test name
Test status
Simulation time 728767415 ps
CPU time 4.03 seconds
Started Jan 25 12:48:56 AM PST 24
Finished Jan 25 12:49:01 AM PST 24
Peak memory 225052 kb
Host smart-d1d26ace-6500-426b-8d47-9d0cdb159c8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602024348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
602024348
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.925111048
Short name T573
Test name
Test status
Simulation time 12412161121 ps
CPU time 315.85 seconds
Started Jan 24 10:38:57 PM PST 24
Finished Jan 24 10:44:13 PM PST 24
Peak memory 1007296 kb
Host smart-c4b6eebc-c195-45ce-806c-33cd8a9283e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925111048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.925111048
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1036140855
Short name T565
Test name
Test status
Simulation time 9595302518 ps
CPU time 99.55 seconds
Started Jan 24 10:39:29 PM PST 24
Finished Jan 24 10:41:09 PM PST 24
Peak memory 246536 kb
Host smart-1893cdeb-face-4476-af71-e688f7c96d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036140855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1036140855
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3842402011
Short name T406
Test name
Test status
Simulation time 48782988 ps
CPU time 0.63 seconds
Started Jan 24 10:38:36 PM PST 24
Finished Jan 24 10:38:38 PM PST 24
Peak memory 201488 kb
Host smart-ccee5839-e7df-4a24-9b6d-92e4a1d4ba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842402011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3842402011
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1187192967
Short name T467
Test name
Test status
Simulation time 621315640 ps
CPU time 8.86 seconds
Started Jan 24 11:00:22 PM PST 24
Finished Jan 24 11:00:31 PM PST 24
Peak memory 213736 kb
Host smart-3b4e6688-49b1-4e28-bf5b-4e792dd28d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187192967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1187192967
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_rx_oversample.3434319555
Short name T418
Test name
Test status
Simulation time 9481441458 ps
CPU time 110.21 seconds
Started Jan 24 10:38:53 PM PST 24
Finished Jan 24 10:40:44 PM PST 24
Peak memory 302788 kb
Host smart-6fb5cfd2-46e2-4ba3-bfae-23796193196a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434319555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_rx_oversample
.3434319555
Directory /workspace/49.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.4088279026
Short name T758
Test name
Test status
Simulation time 3920591461 ps
CPU time 54.03 seconds
Started Jan 24 10:38:39 PM PST 24
Finished Jan 24 10:39:34 PM PST 24
Peak memory 299352 kb
Host smart-6684e533-c0ab-4ae8-9e89-40482007011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088279026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.4088279026
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3087118168
Short name T848
Test name
Test status
Simulation time 6962396790 ps
CPU time 19.01 seconds
Started Jan 24 10:39:04 PM PST 24
Finished Jan 24 10:39:24 PM PST 24
Peak memory 218696 kb
Host smart-0b1e4a1a-67d6-4ca6-aa6e-79651f4170fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087118168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3087118168
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.2487201980
Short name T273
Test name
Test status
Simulation time 1450176716 ps
CPU time 5.12 seconds
Started Jan 24 10:39:15 PM PST 24
Finished Jan 24 10:39:21 PM PST 24
Peak memory 202592 kb
Host smart-75bb9030-b651-4fe2-95d9-aecd48d6b113
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487201980 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2487201980
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1730816946
Short name T8
Test name
Test status
Simulation time 10147879455 ps
CPU time 80.57 seconds
Started Jan 24 10:39:18 PM PST 24
Finished Jan 24 10:40:39 PM PST 24
Peak memory 626200 kb
Host smart-19f74b01-51c0-417b-8ae1-b3e0b97fd707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730816946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1730816946
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3794348344
Short name T719
Test name
Test status
Simulation time 10138699362 ps
CPU time 15.77 seconds
Started Jan 24 10:39:15 PM PST 24
Finished Jan 24 10:39:32 PM PST 24
Peak memory 313588 kb
Host smart-1ad121f3-62b3-4b8c-bce4-9bdeadb56635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794348344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3794348344
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2043137666
Short name T1163
Test name
Test status
Simulation time 1889308176 ps
CPU time 2.87 seconds
Started Jan 24 10:39:17 PM PST 24
Finished Jan 24 10:39:20 PM PST 24
Peak memory 202668 kb
Host smart-d4075267-eb8c-40cd-83aa-bbd7cbfc0743
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043137666 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2043137666
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1628326757
Short name T755
Test name
Test status
Simulation time 1050136346 ps
CPU time 4.86 seconds
Started Jan 24 10:39:02 PM PST 24
Finished Jan 24 10:39:07 PM PST 24
Peak memory 202576 kb
Host smart-54824b93-099b-4d61-87af-7454f30fdeaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628326757 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1628326757
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2221172793
Short name T1004
Test name
Test status
Simulation time 50026782683 ps
CPU time 1327.91 seconds
Started Jan 25 01:47:35 AM PST 24
Finished Jan 25 02:09:44 AM PST 24
Peak memory 5982072 kb
Host smart-8b58f92f-4633-4d89-bb16-7c3ded0410c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221172793 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2221172793
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_perf.813372953
Short name T465
Test name
Test status
Simulation time 1010360374 ps
CPU time 5.47 seconds
Started Jan 24 10:39:15 PM PST 24
Finished Jan 24 10:39:22 PM PST 24
Peak memory 204544 kb
Host smart-89443c57-dd18-438d-ac94-28a1c5e8cc79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813372953 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_perf.813372953
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.348443932
Short name T1426
Test name
Test status
Simulation time 5390381181 ps
CPU time 16.81 seconds
Started Jan 24 10:39:05 PM PST 24
Finished Jan 24 10:39:22 PM PST 24
Peak memory 202644 kb
Host smart-cb3f8524-38d9-4ad0-ad74-ba7241928e0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348443932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.348443932
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.1729770604
Short name T432
Test name
Test status
Simulation time 26846090650 ps
CPU time 2883.05 seconds
Started Jan 24 10:39:15 PM PST 24
Finished Jan 24 11:27:19 PM PST 24
Peak memory 3954896 kb
Host smart-ae76e626-c774-46fc-b407-65ae56064def
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729770604 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_stress_all.1729770604
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3813849301
Short name T301
Test name
Test status
Simulation time 973015898 ps
CPU time 8.21 seconds
Started Jan 24 10:39:07 PM PST 24
Finished Jan 24 10:39:16 PM PST 24
Peak memory 202612 kb
Host smart-1a812c1c-6e23-45d5-a6a7-f867ee8b0793
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813849301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3813849301
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.1063405738
Short name T527
Test name
Test status
Simulation time 14047570427 ps
CPU time 64.08 seconds
Started Jan 24 10:39:08 PM PST 24
Finished Jan 24 10:40:13 PM PST 24
Peak memory 1203060 kb
Host smart-43d5e1a3-d2bf-45ad-ad4d-8ef4b0f55b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063405738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.1063405738
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1633193910
Short name T661
Test name
Test status
Simulation time 20151498700 ps
CPU time 417.32 seconds
Started Jan 24 11:25:10 PM PST 24
Finished Jan 24 11:32:10 PM PST 24
Peak memory 2158036 kb
Host smart-a728168e-50bf-459c-bc5a-c3fd7551c7c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633193910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1633193910
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1568709105
Short name T411
Test name
Test status
Simulation time 2157774435 ps
CPU time 8.4 seconds
Started Jan 24 10:39:17 PM PST 24
Finished Jan 24 10:39:26 PM PST 24
Peak memory 205624 kb
Host smart-f0f41029-a496-4d8d-9251-c66110b21604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568709105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1568709105
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_ovf.2591356470
Short name T1234
Test name
Test status
Simulation time 9821921657 ps
CPU time 33.11 seconds
Started Jan 24 10:39:18 PM PST 24
Finished Jan 24 10:39:51 PM PST 24
Peak memory 216188 kb
Host smart-0b332b8f-a068-426b-88bd-68d9ac46f592
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591356470 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_tx_ovf.2591356470
Directory /workspace/49.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.2565356279
Short name T1316
Test name
Test status
Simulation time 3442013843 ps
CPU time 4.61 seconds
Started Jan 24 10:39:16 PM PST 24
Finished Jan 24 10:39:22 PM PST 24
Peak memory 202680 kb
Host smart-f89ecdfd-6e38-40cd-846c-dbb9f9e459ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565356279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.2565356279
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3830232291
Short name T1085
Test name
Test status
Simulation time 17503750 ps
CPU time 0.67 seconds
Started Jan 25 12:00:31 AM PST 24
Finished Jan 25 12:00:34 AM PST 24
Peak memory 201152 kb
Host smart-4e08cb83-40df-429a-8930-9d9bf4f81877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830232291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3830232291
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2095706603
Short name T723
Test name
Test status
Simulation time 129739236 ps
CPU time 1.17 seconds
Started Jan 24 09:57:28 PM PST 24
Finished Jan 24 09:57:30 PM PST 24
Peak memory 202580 kb
Host smart-8a2494ff-0e62-4b7d-83af-51372630d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095706603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2095706603
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2878359206
Short name T1337
Test name
Test status
Simulation time 1389929175 ps
CPU time 6.81 seconds
Started Jan 24 09:57:30 PM PST 24
Finished Jan 24 09:57:38 PM PST 24
Peak memory 278784 kb
Host smart-bda5381a-cbf8-4fb1-af84-2b0d2504fc6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878359206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2878359206
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2126715966
Short name T578
Test name
Test status
Simulation time 3523497664 ps
CPU time 243.8 seconds
Started Jan 24 09:57:26 PM PST 24
Finished Jan 24 10:01:32 PM PST 24
Peak memory 847352 kb
Host smart-389642b5-2b43-408e-9169-0c1912ee3934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126715966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2126715966
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1545410730
Short name T881
Test name
Test status
Simulation time 5604311802 ps
CPU time 780.85 seconds
Started Jan 24 09:57:31 PM PST 24
Finished Jan 24 10:10:33 PM PST 24
Peak memory 1540384 kb
Host smart-ac2e542a-d310-47cd-94ee-405b0492b2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545410730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1545410730
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3285560738
Short name T469
Test name
Test status
Simulation time 620081114 ps
CPU time 0.82 seconds
Started Jan 24 09:57:29 PM PST 24
Finished Jan 24 09:57:31 PM PST 24
Peak memory 202320 kb
Host smart-19b5d55e-d276-4ad1-8e0c-a836f94a8f18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285560738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3285560738
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.303565580
Short name T73
Test name
Test status
Simulation time 765287706 ps
CPU time 4.02 seconds
Started Jan 24 09:57:34 PM PST 24
Finished Jan 24 09:57:40 PM PST 24
Peak memory 202568 kb
Host smart-8987df38-08b5-45b4-932b-9474e22875d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303565580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.303565580
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.2495166767
Short name T1108
Test name
Test status
Simulation time 14085263657 ps
CPU time 166.7 seconds
Started Jan 24 09:57:34 PM PST 24
Finished Jan 24 10:00:22 PM PST 24
Peak memory 1082292 kb
Host smart-4445527c-887d-408e-8944-8cf5b125d4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495166767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.2495166767
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1088334538
Short name T1376
Test name
Test status
Simulation time 12438852238 ps
CPU time 70.05 seconds
Started Jan 24 09:57:40 PM PST 24
Finished Jan 24 09:58:55 PM PST 24
Peak memory 324192 kb
Host smart-fe0e8e57-4cb8-401a-8f44-08c2699e9fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088334538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1088334538
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3047508731
Short name T1217
Test name
Test status
Simulation time 15675310 ps
CPU time 0.65 seconds
Started Jan 24 09:57:28 PM PST 24
Finished Jan 24 09:57:30 PM PST 24
Peak memory 201536 kb
Host smart-5d3b2aa1-c35b-4bca-97cf-b62d70f9466a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047508731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3047508731
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.605947138
Short name T152
Test name
Test status
Simulation time 51207811710 ps
CPU time 350.29 seconds
Started Jan 24 09:57:29 PM PST 24
Finished Jan 24 10:03:20 PM PST 24
Peak memory 218344 kb
Host smart-20070116-3a4b-47a8-ab2b-2886b91a6490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605947138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.605947138
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_rx_oversample.2883220157
Short name T1109
Test name
Test status
Simulation time 15140060483 ps
CPU time 78.56 seconds
Started Jan 24 09:57:30 PM PST 24
Finished Jan 24 09:58:50 PM PST 24
Peak memory 293124 kb
Host smart-215e4e84-170c-4194-9df3-9688eaded7a1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883220157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_rx_oversample.
2883220157
Directory /workspace/5.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3441595178
Short name T642
Test name
Test status
Simulation time 4078690882 ps
CPU time 43.38 seconds
Started Jan 24 09:57:30 PM PST 24
Finished Jan 24 09:58:15 PM PST 24
Peak memory 247792 kb
Host smart-515cef67-5d50-46a2-8913-d2f67d52fa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441595178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3441595178
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.2519286633
Short name T1187
Test name
Test status
Simulation time 82311979124 ps
CPU time 1749.58 seconds
Started Jan 24 09:57:40 PM PST 24
Finished Jan 24 10:26:55 PM PST 24
Peak memory 3471588 kb
Host smart-23e12ce9-606c-4f53-aa01-27b2a1d857bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519286633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2519286633
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2647700173
Short name T495
Test name
Test status
Simulation time 905805020 ps
CPU time 15.12 seconds
Started Jan 24 09:57:30 PM PST 24
Finished Jan 24 09:57:46 PM PST 24
Peak memory 216612 kb
Host smart-a85e908d-c70d-441f-95ba-593144529b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647700173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2647700173
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.822949978
Short name T414
Test name
Test status
Simulation time 834878252 ps
CPU time 2.95 seconds
Started Jan 24 11:35:45 PM PST 24
Finished Jan 24 11:35:50 PM PST 24
Peak memory 202652 kb
Host smart-8c9328be-e931-4895-987c-fdd5095f34fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822949978 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.822949978
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.1586553779
Short name T70
Test name
Test status
Simulation time 10566601803 ps
CPU time 6.03 seconds
Started Jan 24 09:57:44 PM PST 24
Finished Jan 24 09:57:56 PM PST 24
Peak memory 242708 kb
Host smart-a0fb5fdc-7a94-47ec-9029-2926e1aed1e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586553779 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.1586553779
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.309701350
Short name T373
Test name
Test status
Simulation time 10072259934 ps
CPU time 68.27 seconds
Started Jan 24 09:57:40 PM PST 24
Finished Jan 24 09:58:53 PM PST 24
Peak memory 573892 kb
Host smart-5d1eb7bd-e0bf-4732-932d-9dd934d714e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309701350 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.309701350
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.421343282
Short name T162
Test name
Test status
Simulation time 535723698 ps
CPU time 2.52 seconds
Started Jan 24 09:57:47 PM PST 24
Finished Jan 24 09:57:54 PM PST 24
Peak memory 202616 kb
Host smart-b4cf23eb-3010-4f96-b2e1-f8f36f770af8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421343282 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.421343282
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3138742709
Short name T861
Test name
Test status
Simulation time 4978668700 ps
CPU time 5.51 seconds
Started Jan 24 09:57:43 PM PST 24
Finished Jan 24 09:57:54 PM PST 24
Peak memory 202696 kb
Host smart-62a4ac74-15c1-4e1a-90e1-2852746712c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138742709 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3138742709
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3761081670
Short name T843
Test name
Test status
Simulation time 20059915214 ps
CPU time 109.23 seconds
Started Jan 24 09:57:41 PM PST 24
Finished Jan 24 09:59:35 PM PST 24
Peak memory 1258172 kb
Host smart-d143bfde-3d04-47db-b8be-e6c7f6c5af88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761081670 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3761081670
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.3717954476
Short name T426
Test name
Test status
Simulation time 1491654398 ps
CPU time 2.42 seconds
Started Jan 24 09:57:44 PM PST 24
Finished Jan 24 09:57:52 PM PST 24
Peak memory 202584 kb
Host smart-8c644278-a99a-48ca-8c75-cc3b4d6b8903
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717954476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.3717954476
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.1800670256
Short name T989
Test name
Test status
Simulation time 1894529345 ps
CPU time 12.42 seconds
Started Jan 24 09:57:40 PM PST 24
Finished Jan 24 09:57:58 PM PST 24
Peak memory 202548 kb
Host smart-45f39fd6-7e96-4ae3-9ff3-91ba28184db8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800670256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.1800670256
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.2414101998
Short name T1091
Test name
Test status
Simulation time 54105857050 ps
CPU time 2912.27 seconds
Started Jan 24 09:57:40 PM PST 24
Finished Jan 24 10:46:18 PM PST 24
Peak memory 9163668 kb
Host smart-089aafe1-423e-4de8-a5b9-3b4a880b44eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414101998 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.2414101998
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2335276444
Short name T974
Test name
Test status
Simulation time 6849937535 ps
CPU time 16.72 seconds
Started Jan 24 09:57:39 PM PST 24
Finished Jan 24 09:58:01 PM PST 24
Peak memory 206000 kb
Host smart-cb239d19-83aa-452c-b19e-b7ad8bd576ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335276444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2335276444
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1411897844
Short name T1213
Test name
Test status
Simulation time 9167527927 ps
CPU time 23.92 seconds
Started Jan 24 09:57:40 PM PST 24
Finished Jan 24 09:58:09 PM PST 24
Peak memory 691160 kb
Host smart-0b33ee05-a2ed-4faa-9a62-f3bcd4dd13a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411897844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1411897844
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1414732435
Short name T336
Test name
Test status
Simulation time 20329556068 ps
CPU time 1588.12 seconds
Started Jan 24 09:57:40 PM PST 24
Finished Jan 24 10:24:14 PM PST 24
Peak memory 4826596 kb
Host smart-609fdea2-a90a-4d9b-8e7e-15442bad5b27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414732435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1414732435
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3888447349
Short name T361
Test name
Test status
Simulation time 7068906565 ps
CPU time 8.16 seconds
Started Jan 24 09:57:48 PM PST 24
Finished Jan 24 09:57:59 PM PST 24
Peak memory 204552 kb
Host smart-7c91df08-2c45-45d1-afa5-62a52237c29a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888447349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3888447349
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_ovf.2699149563
Short name T1364
Test name
Test status
Simulation time 8022617134 ps
CPU time 144.33 seconds
Started Jan 24 09:57:40 PM PST 24
Finished Jan 24 10:00:09 PM PST 24
Peak memory 424968 kb
Host smart-84907932-f9e6-435e-8957-409ff99481fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699149563 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_tx_ovf.2699149563
Directory /workspace/5.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.1000935478
Short name T483
Test name
Test status
Simulation time 5107798370 ps
CPU time 6.1 seconds
Started Jan 24 09:57:42 PM PST 24
Finished Jan 24 09:57:54 PM PST 24
Peak memory 203444 kb
Host smart-76bfedcb-1c86-4325-80e4-3ed7f60013ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000935478 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_unexp_stop.1000935478
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1835169879
Short name T404
Test name
Test status
Simulation time 29901863 ps
CPU time 0.67 seconds
Started Jan 24 09:58:23 PM PST 24
Finished Jan 24 09:58:26 PM PST 24
Peak memory 202016 kb
Host smart-ed1cd23f-5d8a-4706-b2bb-07a11dc68724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835169879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1835169879
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.678787113
Short name T1067
Test name
Test status
Simulation time 62684736 ps
CPU time 1.06 seconds
Started Jan 24 09:57:59 PM PST 24
Finished Jan 24 09:58:06 PM PST 24
Peak memory 202500 kb
Host smart-168bb646-3acc-4a01-80f3-e7c04522aca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678787113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.678787113
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2104208073
Short name T1151
Test name
Test status
Simulation time 1485289935 ps
CPU time 11.15 seconds
Started Jan 24 09:57:51 PM PST 24
Finished Jan 24 09:58:04 PM PST 24
Peak memory 315208 kb
Host smart-06aeffb0-cad9-4495-8ea9-34c216da7533
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104208073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2104208073
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1195207429
Short name T976
Test name
Test status
Simulation time 12024689546 ps
CPU time 126.45 seconds
Started Jan 24 09:57:51 PM PST 24
Finished Jan 24 09:59:59 PM PST 24
Peak memory 1014476 kb
Host smart-aea2ea7f-804f-47f0-926f-8c67815f7950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195207429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1195207429
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.803943493
Short name T1175
Test name
Test status
Simulation time 49191876703 ps
CPU time 370.28 seconds
Started Jan 24 11:22:38 PM PST 24
Finished Jan 24 11:28:51 PM PST 24
Peak memory 1462532 kb
Host smart-823f1207-31be-44da-acb6-795fff9cb668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803943493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.803943493
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3808623764
Short name T53
Test name
Test status
Simulation time 101529331 ps
CPU time 0.88 seconds
Started Jan 24 09:57:52 PM PST 24
Finished Jan 24 09:57:55 PM PST 24
Peak memory 202340 kb
Host smart-83ebceb7-74d3-4e8c-93dd-2098e987e9f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808623764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3808623764
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3394869518
Short name T637
Test name
Test status
Simulation time 1623011563 ps
CPU time 11.53 seconds
Started Jan 24 09:57:59 PM PST 24
Finished Jan 24 09:58:17 PM PST 24
Peak memory 202484 kb
Host smart-e730bad7-0d1f-41ee-b6a7-e7ecc41b2afc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394869518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3394869518
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2796724594
Short name T796
Test name
Test status
Simulation time 19218926080 ps
CPU time 184.58 seconds
Started Jan 24 09:57:53 PM PST 24
Finished Jan 24 10:01:00 PM PST 24
Peak memory 1163232 kb
Host smart-461faae4-fc48-4c46-a4d9-16cb774ca718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796724594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2796724594
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1890158162
Short name T1171
Test name
Test status
Simulation time 2958733282 ps
CPU time 159.72 seconds
Started Jan 24 09:58:16 PM PST 24
Finished Jan 24 10:01:03 PM PST 24
Peak memory 247044 kb
Host smart-b8e90d7a-8339-4d7f-9b8b-40b7a54ec4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890158162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1890158162
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3907843309
Short name T147
Test name
Test status
Simulation time 19006196 ps
CPU time 0.65 seconds
Started Jan 24 09:57:43 PM PST 24
Finished Jan 24 09:57:50 PM PST 24
Peak memory 201524 kb
Host smart-0b9106eb-f848-443f-b441-035b2af057a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907843309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3907843309
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1097027157
Short name T685
Test name
Test status
Simulation time 3498069519 ps
CPU time 53.98 seconds
Started Jan 24 11:28:16 PM PST 24
Finished Jan 24 11:29:11 PM PST 24
Peak memory 224804 kb
Host smart-c8065027-0657-478f-83ed-cbc0f6af92ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097027157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1097027157
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_rx_oversample.1408309783
Short name T462
Test name
Test status
Simulation time 2032045006 ps
CPU time 89.56 seconds
Started Jan 24 09:57:59 PM PST 24
Finished Jan 24 09:59:35 PM PST 24
Peak memory 314164 kb
Host smart-c3b4ec67-769c-47e8-94cb-69d7789e10d1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408309783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_rx_oversample.
1408309783
Directory /workspace/6.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.2051183291
Short name T620
Test name
Test status
Simulation time 1949084551 ps
CPU time 71.49 seconds
Started Jan 24 09:57:47 PM PST 24
Finished Jan 24 09:59:03 PM PST 24
Peak memory 308460 kb
Host smart-6fe450e2-5354-4edb-9481-f70e6053a37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051183291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.2051183291
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.1297558478
Short name T203
Test name
Test status
Simulation time 55361507188 ps
CPU time 2125.06 seconds
Started Jan 24 09:57:53 PM PST 24
Finished Jan 24 10:33:22 PM PST 24
Peak memory 3394364 kb
Host smart-cc9b5f95-0122-4861-b328-a6d47ded5d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297558478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.1297558478
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all_with_rand_reset.3076766222
Short name T105
Test name
Test status
Simulation time 12156795505 ps
CPU time 846.27 seconds
Started Jan 24 09:58:17 PM PST 24
Finished Jan 24 10:12:30 PM PST 24
Peak memory 417320 kb
Host smart-4e469b5a-7d07-4b57-8334-859aeabb867d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076766222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.i2c_host_stress_all_with_rand_reset.3076766222
Directory /workspace/6.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1918412028
Short name T1031
Test name
Test status
Simulation time 2268578154 ps
CPU time 7.68 seconds
Started Jan 24 10:32:31 PM PST 24
Finished Jan 24 10:32:39 PM PST 24
Peak memory 210752 kb
Host smart-e52d84aa-020e-45b8-8f49-941f22bd264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918412028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1918412028
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.2557601760
Short name T1480
Test name
Test status
Simulation time 2421378071 ps
CPU time 4.58 seconds
Started Jan 24 09:58:12 PM PST 24
Finished Jan 24 09:58:18 PM PST 24
Peak memory 202616 kb
Host smart-edf5b3a8-7147-45d1-bada-ba09ecfd591a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557601760 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2557601760
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.3339355065
Short name T612
Test name
Test status
Simulation time 11062526612 ps
CPU time 6.08 seconds
Started Jan 24 09:58:12 PM PST 24
Finished Jan 24 09:58:20 PM PST 24
Peak memory 225800 kb
Host smart-f2cf1062-2b2c-4479-9e19-3391ae6d564f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339355065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.3339355065
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2985813077
Short name T995
Test name
Test status
Simulation time 10068184249 ps
CPU time 54.57 seconds
Started Jan 24 09:58:13 PM PST 24
Finished Jan 24 09:59:09 PM PST 24
Peak memory 530044 kb
Host smart-e2462c4f-4547-4717-82f5-47f116f26710
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985813077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2985813077
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1468217848
Short name T716
Test name
Test status
Simulation time 601523223 ps
CPU time 2.84 seconds
Started Jan 24 09:58:13 PM PST 24
Finished Jan 24 09:58:16 PM PST 24
Peak memory 202680 kb
Host smart-d0cfc07c-7217-4c05-a4dd-4e5076d9d6c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468217848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1468217848
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.2531661082
Short name T1054
Test name
Test status
Simulation time 44403622784 ps
CPU time 8.35 seconds
Started Jan 24 09:58:06 PM PST 24
Finished Jan 24 09:58:17 PM PST 24
Peak memory 206796 kb
Host smart-6aa9d023-2d1a-43e5-8ce1-51f08a283bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531661082 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.2531661082
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1391404490
Short name T1139
Test name
Test status
Simulation time 17741782580 ps
CPU time 707.48 seconds
Started Jan 24 09:58:09 PM PST 24
Finished Jan 24 10:09:58 PM PST 24
Peak memory 4091572 kb
Host smart-a9e293b4-0b5e-46b0-b55f-90fa9d87b51f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391404490 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1391404490
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.1809912246
Short name T265
Test name
Test status
Simulation time 2144764816 ps
CPU time 3.64 seconds
Started Jan 24 09:58:19 PM PST 24
Finished Jan 24 09:58:28 PM PST 24
Peak memory 202584 kb
Host smart-1f76cfa3-1470-4316-a20f-03cc4d8b6443
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809912246 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.1809912246
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.681723805
Short name T942
Test name
Test status
Simulation time 22559413685 ps
CPU time 30.13 seconds
Started Jan 24 09:57:54 PM PST 24
Finished Jan 24 09:58:27 PM PST 24
Peak memory 202680 kb
Host smart-bcd83b39-db44-4cd7-92ce-92bccbd01f39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681723805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.681723805
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.4269346778
Short name T317
Test name
Test status
Simulation time 55003088844 ps
CPU time 298.6 seconds
Started Jan 24 09:58:15 PM PST 24
Finished Jan 24 10:03:15 PM PST 24
Peak memory 1483908 kb
Host smart-5c4ff154-cfa3-4a2e-ad32-efbedacb3962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269346778 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.4269346778
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3372813524
Short name T424
Test name
Test status
Simulation time 2045317042 ps
CPU time 29.7 seconds
Started Jan 24 09:57:59 PM PST 24
Finished Jan 24 09:58:35 PM PST 24
Peak memory 226316 kb
Host smart-d9f8295c-5558-418e-8561-9cc04cbc23c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372813524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3372813524
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1626537115
Short name T627
Test name
Test status
Simulation time 33451102918 ps
CPU time 154 seconds
Started Jan 24 11:52:39 PM PST 24
Finished Jan 24 11:55:15 PM PST 24
Peak memory 1990304 kb
Host smart-c162a003-fd9f-4ca9-80a2-4ec2b8021945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626537115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1626537115
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.381973725
Short name T1040
Test name
Test status
Simulation time 11465051682 ps
CPU time 31.19 seconds
Started Jan 24 09:58:09 PM PST 24
Finished Jan 24 09:58:41 PM PST 24
Peak memory 536628 kb
Host smart-83373548-bd69-452a-a07a-a65e32242349
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381973725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.381973725
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.4189585107
Short name T1439
Test name
Test status
Simulation time 6699055693 ps
CPU time 6.83 seconds
Started Jan 24 09:58:10 PM PST 24
Finished Jan 24 09:58:18 PM PST 24
Peak memory 202712 kb
Host smart-946555eb-6ac9-4785-9f85-9702bb0f9164
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189585107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.4189585107
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_ovf.876394122
Short name T1093
Test name
Test status
Simulation time 32992993017 ps
CPU time 59.91 seconds
Started Jan 24 09:58:03 PM PST 24
Finished Jan 24 09:59:08 PM PST 24
Peak memory 271416 kb
Host smart-ecfdaa1e-f9d6-462b-a954-281234e7749c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876394122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_tx_ovf.876394122
Directory /workspace/6.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.3733566307
Short name T547
Test name
Test status
Simulation time 1237451547 ps
CPU time 4.65 seconds
Started Jan 24 09:58:22 PM PST 24
Finished Jan 24 09:58:29 PM PST 24
Peak memory 202628 kb
Host smart-c96a146c-9167-4e44-8f9c-c7724cd28264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733566307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.3733566307
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.400575308
Short name T1077
Test name
Test status
Simulation time 16092643 ps
CPU time 0.62 seconds
Started Jan 24 09:59:04 PM PST 24
Finished Jan 24 09:59:05 PM PST 24
Peak memory 201176 kb
Host smart-f6283e50-9d6f-4887-845d-2fad5cdb8ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400575308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.400575308
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1011301923
Short name T255
Test name
Test status
Simulation time 86586136 ps
CPU time 2.15 seconds
Started Jan 24 09:58:37 PM PST 24
Finished Jan 24 09:58:41 PM PST 24
Peak memory 210800 kb
Host smart-1570a8a7-f547-4de0-8034-58db3aa5fa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011301923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1011301923
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.1372571348
Short name T310
Test name
Test status
Simulation time 1267605385 ps
CPU time 7.35 seconds
Started Jan 24 09:58:29 PM PST 24
Finished Jan 24 09:58:39 PM PST 24
Peak memory 281444 kb
Host smart-084bf860-b06f-44df-bf65-1c511aead19a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372571348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.1372571348
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.4263846272
Short name T749
Test name
Test status
Simulation time 3941509461 ps
CPU time 176.57 seconds
Started Jan 24 09:58:29 PM PST 24
Finished Jan 24 10:01:27 PM PST 24
Peak memory 1147308 kb
Host smart-065dd079-1b7a-4b91-9193-ab074aff4043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263846272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.4263846272
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3381508253
Short name T1230
Test name
Test status
Simulation time 12985568839 ps
CPU time 849.12 seconds
Started Jan 24 09:58:29 PM PST 24
Finished Jan 24 10:12:40 PM PST 24
Peak memory 1637812 kb
Host smart-bcb9e186-6f51-47c6-872e-58b2e30e0310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381508253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3381508253
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1717728734
Short name T1129
Test name
Test status
Simulation time 405996489 ps
CPU time 0.82 seconds
Started Jan 24 09:58:28 PM PST 24
Finished Jan 24 09:58:31 PM PST 24
Peak memory 202304 kb
Host smart-567bca84-c855-4f02-9d3c-24d7cc673847
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717728734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1717728734
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.692626279
Short name T537
Test name
Test status
Simulation time 189631085 ps
CPU time 10.78 seconds
Started Jan 25 01:12:39 AM PST 24
Finished Jan 25 01:12:51 AM PST 24
Peak memory 202564 kb
Host smart-4dea96e9-0f5a-4859-807d-dabdefa69f66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692626279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.692626279
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2867102343
Short name T401
Test name
Test status
Simulation time 3997302169 ps
CPU time 396.04 seconds
Started Jan 24 09:58:27 PM PST 24
Finished Jan 24 10:05:05 PM PST 24
Peak memory 1106552 kb
Host smart-8de8e9e2-e372-4e22-a2b6-6d3a8c9049bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867102343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2867102343
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.3242516441
Short name T1326
Test name
Test status
Simulation time 9529759387 ps
CPU time 123.76 seconds
Started Jan 24 09:59:05 PM PST 24
Finished Jan 24 10:01:10 PM PST 24
Peak memory 235192 kb
Host smart-481f0786-4007-4c00-ae61-ae6213a7877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242516441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.3242516441
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.539480031
Short name T1079
Test name
Test status
Simulation time 15252534 ps
CPU time 0.65 seconds
Started Jan 24 11:16:04 PM PST 24
Finished Jan 24 11:16:06 PM PST 24
Peak memory 201532 kb
Host smart-eb8cdf54-ba65-4052-9528-59d96453902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539480031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.539480031
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.893274405
Short name T610
Test name
Test status
Simulation time 1133637130 ps
CPU time 11.69 seconds
Started Jan 24 09:58:41 PM PST 24
Finished Jan 24 09:58:54 PM PST 24
Peak memory 210712 kb
Host smart-87db92aa-26f2-44e7-926f-e36ec7a15d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893274405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.893274405
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_rx_oversample.683984473
Short name T819
Test name
Test status
Simulation time 3441192310 ps
CPU time 186.86 seconds
Started Jan 24 09:58:15 PM PST 24
Finished Jan 24 10:01:23 PM PST 24
Peak memory 351772 kb
Host smart-0926fdc9-3a60-49f5-aae9-ff55654453a3
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683984473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_rx_oversample.683984473
Directory /workspace/7.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.395649737
Short name T890
Test name
Test status
Simulation time 5318847694 ps
CPU time 70.7 seconds
Started Jan 24 09:58:17 PM PST 24
Finished Jan 24 09:59:34 PM PST 24
Peak memory 227140 kb
Host smart-1ee6a41e-580b-4f71-a9f3-8d1bb2c6cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395649737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.395649737
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.239141645
Short name T801
Test name
Test status
Simulation time 1163075824 ps
CPU time 8.6 seconds
Started Jan 24 09:58:41 PM PST 24
Finished Jan 24 09:58:51 PM PST 24
Peak memory 217284 kb
Host smart-2768688d-d0ac-410d-bcfe-37fcee669c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239141645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.239141645
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.1848102543
Short name T543
Test name
Test status
Simulation time 1453322138 ps
CPU time 5.36 seconds
Started Jan 24 09:59:01 PM PST 24
Finished Jan 24 09:59:08 PM PST 24
Peak memory 202564 kb
Host smart-239abd9e-a8fc-4c2b-9fdb-1239d6769afe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848102543 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1848102543
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2944616019
Short name T789
Test name
Test status
Simulation time 10251371107 ps
CPU time 22.84 seconds
Started Jan 24 09:58:53 PM PST 24
Finished Jan 24 09:59:17 PM PST 24
Peak memory 329224 kb
Host smart-0bf2f32e-93b4-4ebe-9eba-9ceb335519c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944616019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2944616019
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1595867978
Short name T1405
Test name
Test status
Simulation time 10136109635 ps
CPU time 77.04 seconds
Started Jan 24 09:58:53 PM PST 24
Finished Jan 24 10:00:12 PM PST 24
Peak memory 682352 kb
Host smart-bd077dd7-5672-45c0-85ec-ee30bca67c49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595867978 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1595867978
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.1186252954
Short name T1321
Test name
Test status
Simulation time 922206664 ps
CPU time 1.94 seconds
Started Jan 24 09:59:04 PM PST 24
Finished Jan 24 09:59:07 PM PST 24
Peak memory 202680 kb
Host smart-2af0ae2e-c6ea-4c2f-bc99-c455a4349697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186252954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.1186252954
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1765936492
Short name T854
Test name
Test status
Simulation time 1948256940 ps
CPU time 4.2 seconds
Started Jan 24 09:58:52 PM PST 24
Finished Jan 24 09:58:58 PM PST 24
Peak memory 202576 kb
Host smart-2147ea02-1f10-4962-a68d-e30c28b3c637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765936492 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1765936492
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.1303533531
Short name T605
Test name
Test status
Simulation time 11932243445 ps
CPU time 182.11 seconds
Started Jan 24 09:58:53 PM PST 24
Finished Jan 24 10:01:57 PM PST 24
Peak memory 2213476 kb
Host smart-655b0f5f-b482-4235-84b2-9fb98fb6c3b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303533531 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1303533531
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.406829484
Short name T1442
Test name
Test status
Simulation time 4892245838 ps
CPU time 5.44 seconds
Started Jan 25 01:25:22 AM PST 24
Finished Jan 25 01:25:29 AM PST 24
Peak memory 208232 kb
Host smart-5671aeca-9adf-4e01-8c48-18d7cb55d065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406829484 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_perf.406829484
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.1170377088
Short name T1138
Test name
Test status
Simulation time 2448098135 ps
CPU time 13.25 seconds
Started Jan 24 09:58:52 PM PST 24
Finished Jan 24 09:59:07 PM PST 24
Peak memory 202628 kb
Host smart-e07d9397-913f-40b6-9088-0bb75af4090a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170377088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.1170377088
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.1000787852
Short name T1412
Test name
Test status
Simulation time 31755526543 ps
CPU time 819.37 seconds
Started Jan 24 09:58:50 PM PST 24
Finished Jan 24 10:12:31 PM PST 24
Peak memory 3708112 kb
Host smart-b2ee72b3-c263-4aeb-b967-15e5f8face9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000787852 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.1000787852
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.4130887655
Short name T552
Test name
Test status
Simulation time 3090567130 ps
CPU time 10.41 seconds
Started Jan 24 09:58:50 PM PST 24
Finished Jan 24 09:59:02 PM PST 24
Peak memory 205472 kb
Host smart-765ca42a-5da3-49cf-a179-d242c2f3843e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130887655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.4130887655
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3844441627
Short name T365
Test name
Test status
Simulation time 18177826143 ps
CPU time 385.38 seconds
Started Jan 24 09:58:52 PM PST 24
Finished Jan 24 10:05:18 PM PST 24
Peak memory 3502776 kb
Host smart-5dfb6429-df9a-48bb-ac07-21033b8ce48d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844441627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.3844441627
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3016510316
Short name T1083
Test name
Test status
Simulation time 39197559376 ps
CPU time 313.52 seconds
Started Jan 25 12:24:11 AM PST 24
Finished Jan 25 12:29:27 AM PST 24
Peak memory 1779296 kb
Host smart-1cf37d12-95ca-4727-9975-252379a29af8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016510316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3016510316
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.704282930
Short name T669
Test name
Test status
Simulation time 9126053471 ps
CPU time 7.92 seconds
Started Jan 24 09:58:54 PM PST 24
Finished Jan 24 09:59:04 PM PST 24
Peak memory 202668 kb
Host smart-f3947649-9210-4a35-ae99-6b9649bfea4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704282930 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.704282930
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_ovf.3741370842
Short name T683
Test name
Test status
Simulation time 2626140864 ps
CPU time 89.97 seconds
Started Jan 24 09:58:54 PM PST 24
Finished Jan 24 10:00:25 PM PST 24
Peak memory 314096 kb
Host smart-5234fa20-a37c-463f-a6be-4ac15b85309e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741370842 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_tx_ovf.3741370842
Directory /workspace/7.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.1041110136
Short name T667
Test name
Test status
Simulation time 5917953576 ps
CPU time 7.45 seconds
Started Jan 24 09:58:52 PM PST 24
Finished Jan 24 09:59:00 PM PST 24
Peak memory 204712 kb
Host smart-f2eb7a61-f82d-452a-a169-e90d33d84dae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041110136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.i2c_target_unexp_stop.1041110136
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2638604978
Short name T570
Test name
Test status
Simulation time 18103029 ps
CPU time 0.63 seconds
Started Jan 24 09:59:57 PM PST 24
Finished Jan 24 09:59:58 PM PST 24
Peak memory 201160 kb
Host smart-d48968b5-a726-4e29-b948-ec3e165a9e6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638604978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2638604978
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2708808848
Short name T1285
Test name
Test status
Simulation time 66562987 ps
CPU time 1.63 seconds
Started Jan 24 09:59:21 PM PST 24
Finished Jan 24 09:59:23 PM PST 24
Peak memory 210824 kb
Host smart-3014b34f-9bba-430b-b4d4-e64315a4583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708808848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2708808848
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1338472981
Short name T1095
Test name
Test status
Simulation time 3361316093 ps
CPU time 16.69 seconds
Started Jan 24 11:08:39 PM PST 24
Finished Jan 24 11:08:58 PM PST 24
Peak memory 401344 kb
Host smart-88df633e-4f36-49d0-9dda-48671a4bf1c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338472981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1338472981
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.654172513
Short name T1169
Test name
Test status
Simulation time 5182239675 ps
CPU time 88.85 seconds
Started Jan 24 09:59:22 PM PST 24
Finished Jan 24 10:00:52 PM PST 24
Peak memory 798012 kb
Host smart-abfc3c78-79ca-4559-9914-dd34707b0be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654172513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.654172513
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3964419460
Short name T1486
Test name
Test status
Simulation time 6415587055 ps
CPU time 496.59 seconds
Started Jan 24 11:09:30 PM PST 24
Finished Jan 24 11:17:47 PM PST 24
Peak memory 1770184 kb
Host smart-f63a2f86-0b3c-4b83-9a42-92d7f7d6e876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964419460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3964419460
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3234519411
Short name T1051
Test name
Test status
Simulation time 155942952 ps
CPU time 1.09 seconds
Started Jan 25 12:49:00 AM PST 24
Finished Jan 25 12:49:02 AM PST 24
Peak memory 202352 kb
Host smart-96d3042b-730d-43b7-a069-12c55e06f807
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234519411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3234519411
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.333572626
Short name T1251
Test name
Test status
Simulation time 761864186 ps
CPU time 4.91 seconds
Started Jan 24 09:59:22 PM PST 24
Finished Jan 24 09:59:27 PM PST 24
Peak memory 202528 kb
Host smart-b5a4600d-4116-4bf0-b2d2-0ba4ce811432
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333572626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.333572626
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.574103155
Short name T1402
Test name
Test status
Simulation time 3717271333 ps
CPU time 347.42 seconds
Started Jan 24 09:59:22 PM PST 24
Finished Jan 24 10:05:11 PM PST 24
Peak memory 1044192 kb
Host smart-5bd52c1f-76ca-4b7d-ba04-5f2e299b1021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574103155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.574103155
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.3254935643
Short name T1200
Test name
Test status
Simulation time 35956202766 ps
CPU time 99.26 seconds
Started Jan 24 09:59:55 PM PST 24
Finished Jan 24 10:01:35 PM PST 24
Peak memory 226748 kb
Host smart-9ea27907-4d5d-4da9-a80d-3036abf65232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254935643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3254935643
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.48623205
Short name T1289
Test name
Test status
Simulation time 16293935 ps
CPU time 0.64 seconds
Started Jan 24 09:59:21 PM PST 24
Finished Jan 24 09:59:23 PM PST 24
Peak memory 201628 kb
Host smart-f0f674ff-6fad-4876-8708-c45b5062a58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48623205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.48623205
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1778337238
Short name T1056
Test name
Test status
Simulation time 251020041 ps
CPU time 3.43 seconds
Started Jan 24 09:59:19 PM PST 24
Finished Jan 24 09:59:23 PM PST 24
Peak memory 202492 kb
Host smart-8cdea35a-60c2-4c52-a9eb-abf913177675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778337238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1778337238
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_rx_oversample.1161482814
Short name T702
Test name
Test status
Simulation time 2891082965 ps
CPU time 131.45 seconds
Started Jan 24 09:59:22 PM PST 24
Finished Jan 24 10:01:34 PM PST 24
Peak memory 316840 kb
Host smart-159e9bee-c006-4005-a136-162d13387179
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161482814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_rx_oversample.
1161482814
Directory /workspace/8.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.802191321
Short name T11
Test name
Test status
Simulation time 4554824331 ps
CPU time 19.78 seconds
Started Jan 24 09:59:05 PM PST 24
Finished Jan 24 09:59:26 PM PST 24
Peak memory 218084 kb
Host smart-9bc8e481-fc9d-4e69-939c-543fffd9c781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802191321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.802191321
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.4030142501
Short name T130
Test name
Test status
Simulation time 8929961010 ps
CPU time 385.5 seconds
Started Jan 24 09:59:33 PM PST 24
Finished Jan 24 10:05:59 PM PST 24
Peak memory 1340380 kb
Host smart-94ad61e1-a5a2-499a-9dc6-175e20c82148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030142501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.4030142501
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3836157575
Short name T443
Test name
Test status
Simulation time 9451789621 ps
CPU time 13.31 seconds
Started Jan 25 12:07:31 AM PST 24
Finished Jan 25 12:07:45 AM PST 24
Peak memory 210804 kb
Host smart-43803781-18b0-40ca-94c8-62bed0c9a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836157575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3836157575
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3563438325
Short name T609
Test name
Test status
Simulation time 9876076647 ps
CPU time 6.16 seconds
Started Jan 24 09:59:54 PM PST 24
Finished Jan 24 10:00:01 PM PST 24
Peak memory 206272 kb
Host smart-95100d30-6ed4-4a44-a77e-1a7a42b8c64a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563438325 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3563438325
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3069312731
Short name T704
Test name
Test status
Simulation time 10053768417 ps
CPU time 56.23 seconds
Started Jan 24 09:59:48 PM PST 24
Finished Jan 24 10:00:45 PM PST 24
Peak memory 507512 kb
Host smart-87329880-607b-4599-8508-551b105eb698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069312731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3069312731
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2163192207
Short name T828
Test name
Test status
Simulation time 10038018000 ps
CPU time 70.89 seconds
Started Jan 24 09:59:48 PM PST 24
Finished Jan 24 10:01:00 PM PST 24
Peak memory 645240 kb
Host smart-9212d513-934a-4225-a103-f0a06d7b70b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163192207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2163192207
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1506302025
Short name T1460
Test name
Test status
Simulation time 1611615490 ps
CPU time 2.46 seconds
Started Jan 24 09:59:53 PM PST 24
Finished Jan 24 09:59:57 PM PST 24
Peak memory 202628 kb
Host smart-c8cffc5e-f52f-4203-b433-02a6e1872fa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506302025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1506302025
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2610375991
Short name T422
Test name
Test status
Simulation time 2265594134 ps
CPU time 5.78 seconds
Started Jan 24 09:59:35 PM PST 24
Finished Jan 24 09:59:42 PM PST 24
Peak memory 203956 kb
Host smart-5085d2bd-6a60-404c-8b7e-525053935365
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610375991 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2610375991
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2242609771
Short name T1461
Test name
Test status
Simulation time 4035295528 ps
CPU time 6.34 seconds
Started Jan 24 09:59:35 PM PST 24
Finished Jan 24 09:59:42 PM PST 24
Peak memory 308064 kb
Host smart-c753c9b2-54c0-4786-a81e-a00a55663ec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242609771 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2242609771
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.135173867
Short name T1070
Test name
Test status
Simulation time 3500316174 ps
CPU time 4.98 seconds
Started Jan 24 09:59:42 PM PST 24
Finished Jan 24 09:59:48 PM PST 24
Peak memory 202636 kb
Host smart-84bb206c-878d-4ca3-817f-4606b937671a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135173867 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_perf.135173867
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.570815555
Short name T699
Test name
Test status
Simulation time 3995162684 ps
CPU time 9.52 seconds
Started Jan 24 09:59:35 PM PST 24
Finished Jan 24 09:59:45 PM PST 24
Peak memory 202564 kb
Host smart-d90d7948-a518-4dd8-be42-55935e572a0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570815555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.570815555
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.1909466900
Short name T891
Test name
Test status
Simulation time 100117633318 ps
CPU time 1163.05 seconds
Started Jan 24 09:59:46 PM PST 24
Finished Jan 24 10:19:10 PM PST 24
Peak memory 1232688 kb
Host smart-3db04e90-fad9-4f60-b267-019e64d53260
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909466900 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.1909466900
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.862599384
Short name T1398
Test name
Test status
Simulation time 4453051190 ps
CPU time 45.77 seconds
Started Jan 24 11:19:58 PM PST 24
Finished Jan 24 11:20:44 PM PST 24
Peak memory 202696 kb
Host smart-d7b6c879-877b-40df-ae06-a1c3e9d717c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862599384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.862599384
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2651005095
Short name T766
Test name
Test status
Simulation time 17207932133 ps
CPU time 2369.02 seconds
Started Jan 24 10:33:35 PM PST 24
Finished Jan 24 11:13:05 PM PST 24
Peak memory 3549796 kb
Host smart-673881c7-a32c-4d9e-92e1-469d7d9f02c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651005095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2651005095
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.405091485
Short name T226
Test name
Test status
Simulation time 3654786771 ps
CPU time 6.83 seconds
Started Jan 24 09:59:45 PM PST 24
Finished Jan 24 09:59:52 PM PST 24
Peak memory 202640 kb
Host smart-63e055a6-02d7-46d4-8e77-204b3a7fee82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405091485 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.405091485
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_ovf.3283603249
Short name T480
Test name
Test status
Simulation time 17831222316 ps
CPU time 130.55 seconds
Started Jan 24 09:59:33 PM PST 24
Finished Jan 24 10:01:44 PM PST 24
Peak memory 397828 kb
Host smart-e25606b8-f96b-4f26-aea6-cd1245bfcbb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283603249 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_tx_ovf.3283603249
Directory /workspace/8.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.1223474686
Short name T407
Test name
Test status
Simulation time 972488868 ps
CPU time 4.9 seconds
Started Jan 24 09:59:45 PM PST 24
Finished Jan 24 09:59:51 PM PST 24
Peak memory 202656 kb
Host smart-8f960244-8db3-4f24-9ed7-f3fae5af6830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223474686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.i2c_target_unexp_stop.1223474686
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2125692966
Short name T1492
Test name
Test status
Simulation time 46737098 ps
CPU time 0.63 seconds
Started Jan 24 10:00:41 PM PST 24
Finished Jan 24 10:00:42 PM PST 24
Peak memory 201160 kb
Host smart-d602dadc-88ef-4942-a9a2-db9c624f23b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125692966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2125692966
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2076635901
Short name T743
Test name
Test status
Simulation time 156172911 ps
CPU time 1.3 seconds
Started Jan 24 10:00:11 PM PST 24
Finished Jan 24 10:00:13 PM PST 24
Peak memory 210736 kb
Host smart-b4b95ad5-c38b-4da7-a94e-0bcab8400f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076635901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2076635901
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1373931016
Short name T511
Test name
Test status
Simulation time 1005727572 ps
CPU time 9.71 seconds
Started Jan 24 11:35:16 PM PST 24
Finished Jan 24 11:35:27 PM PST 24
Peak memory 312776 kb
Host smart-8b6e3e79-71be-4c9f-8bc7-2e20ae74859f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373931016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1373931016
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.4138325635
Short name T590
Test name
Test status
Simulation time 3137285783 ps
CPU time 126.88 seconds
Started Jan 24 10:00:09 PM PST 24
Finished Jan 24 10:02:17 PM PST 24
Peak memory 941860 kb
Host smart-51547940-3657-439a-9d5f-a1d6fc4231ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138325635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.4138325635
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1258698806
Short name T959
Test name
Test status
Simulation time 14645131613 ps
CPU time 565.49 seconds
Started Jan 24 10:56:36 PM PST 24
Finished Jan 24 11:06:03 PM PST 24
Peak memory 1915812 kb
Host smart-14b9610f-d12f-4c4d-829a-13f7f9fa34a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258698806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1258698806
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3225842807
Short name T328
Test name
Test status
Simulation time 160345496 ps
CPU time 0.9 seconds
Started Jan 24 10:00:09 PM PST 24
Finished Jan 24 10:00:12 PM PST 24
Peak memory 202344 kb
Host smart-a8ca3450-2f52-4ebb-afcd-ebc0734a4924
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225842807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.3225842807
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3182279068
Short name T1087
Test name
Test status
Simulation time 306471973 ps
CPU time 6.11 seconds
Started Jan 24 10:00:10 PM PST 24
Finished Jan 24 10:00:18 PM PST 24
Peak memory 202544 kb
Host smart-f18dcdfa-963a-4650-9d87-0df7e7999585
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182279068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3182279068
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.255616496
Short name T671
Test name
Test status
Simulation time 5838858853 ps
CPU time 710.98 seconds
Started Jan 25 12:37:13 AM PST 24
Finished Jan 25 12:49:06 AM PST 24
Peak memory 1687328 kb
Host smart-419ae498-d277-4dd9-a42e-1c62639ec4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255616496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.255616496
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2213278944
Short name T34
Test name
Test status
Simulation time 5222901988 ps
CPU time 70.28 seconds
Started Jan 24 10:00:43 PM PST 24
Finished Jan 24 10:01:54 PM PST 24
Peak memory 311336 kb
Host smart-dc184737-d9d1-4575-9877-83fab52cd90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213278944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2213278944
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2967403481
Short name T1020
Test name
Test status
Simulation time 60387168 ps
CPU time 0.65 seconds
Started Jan 24 09:59:55 PM PST 24
Finished Jan 24 09:59:57 PM PST 24
Peak memory 201500 kb
Host smart-4a17fd23-2ad4-4ef1-b937-1a1680675af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967403481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2967403481
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2808266124
Short name T151
Test name
Test status
Simulation time 48811265902 ps
CPU time 223.59 seconds
Started Jan 24 10:00:07 PM PST 24
Finished Jan 24 10:03:52 PM PST 24
Peak memory 210788 kb
Host smart-c7c92b3c-7ebb-4349-a5b2-f324c51ddbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808266124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2808266124
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_rx_oversample.3518742281
Short name T550
Test name
Test status
Simulation time 1959817405 ps
CPU time 77.66 seconds
Started Jan 24 09:59:54 PM PST 24
Finished Jan 24 10:01:13 PM PST 24
Peak memory 309372 kb
Host smart-2199398c-21bb-43e4-97e4-f1a9de8040cd
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518742281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_rx_oversample.
3518742281
Directory /workspace/9.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.4164828292
Short name T240
Test name
Test status
Simulation time 8598486427 ps
CPU time 58.57 seconds
Started Jan 24 10:20:47 PM PST 24
Finished Jan 24 10:21:47 PM PST 24
Peak memory 311612 kb
Host smart-c65375eb-3005-4f52-994f-a2d93e694ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164828292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.4164828292
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.948909152
Short name T539
Test name
Test status
Simulation time 4284845397 ps
CPU time 15.32 seconds
Started Jan 24 10:00:10 PM PST 24
Finished Jan 24 10:00:27 PM PST 24
Peak memory 218924 kb
Host smart-9a716add-7b25-43b6-9b13-88c4732dbe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948909152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.948909152
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1598400622
Short name T38
Test name
Test status
Simulation time 760704764 ps
CPU time 3.1 seconds
Started Jan 24 10:00:38 PM PST 24
Finished Jan 24 10:00:43 PM PST 24
Peak memory 202628 kb
Host smart-08635650-c562-48d8-a062-770713ea8508
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598400622 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1598400622
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.576052741
Short name T472
Test name
Test status
Simulation time 10042061784 ps
CPU time 56.26 seconds
Started Jan 24 10:00:28 PM PST 24
Finished Jan 24 10:01:32 PM PST 24
Peak memory 487568 kb
Host smart-0b6320a4-d53f-4c44-b099-ae55bab4fab5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576052741 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.576052741
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.16057024
Short name T688
Test name
Test status
Simulation time 10088194026 ps
CPU time 74.75 seconds
Started Jan 24 10:00:28 PM PST 24
Finished Jan 24 10:01:50 PM PST 24
Peak memory 628112 kb
Host smart-2cd2a33c-061b-4295-8b3c-3e476de8296f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16057024 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_fifo_reset_tx.16057024
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1952685321
Short name T1006
Test name
Test status
Simulation time 954900244 ps
CPU time 2.52 seconds
Started Jan 24 10:00:43 PM PST 24
Finished Jan 24 10:00:46 PM PST 24
Peak memory 202576 kb
Host smart-2a87f573-cae9-4311-b9ca-8d4210e31352
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952685321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1952685321
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2218573817
Short name T1120
Test name
Test status
Simulation time 978789063 ps
CPU time 4.62 seconds
Started Jan 24 10:00:29 PM PST 24
Finished Jan 24 10:00:40 PM PST 24
Peak memory 202596 kb
Host smart-0f78b9da-3000-407e-8eeb-96f078a07de1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218573817 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2218573817
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.85994706
Short name T597
Test name
Test status
Simulation time 22120886542 ps
CPU time 117.1 seconds
Started Jan 24 10:00:27 PM PST 24
Finished Jan 24 10:02:31 PM PST 24
Peak memory 1346096 kb
Host smart-dbf0bd9c-7c78-4b51-b87b-2425fa720ec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85994706 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.85994706
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.335622604
Short name T1058
Test name
Test status
Simulation time 3845873928 ps
CPU time 5.45 seconds
Started Jan 24 10:00:42 PM PST 24
Finished Jan 24 10:00:49 PM PST 24
Peak memory 202596 kb
Host smart-b0eb5b3c-172f-4f44-9d94-9c29dd3eefcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335622604 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_perf.335622604
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.4245528274
Short name T501
Test name
Test status
Simulation time 3467635710 ps
CPU time 46.91 seconds
Started Jan 24 10:00:29 PM PST 24
Finished Jan 24 10:01:22 PM PST 24
Peak memory 202584 kb
Host smart-93242960-8301-4fbd-a256-0d44eb233acc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245528274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.4245528274
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.875548963
Short name T802
Test name
Test status
Simulation time 1404757339 ps
CPU time 22.94 seconds
Started Jan 24 10:00:28 PM PST 24
Finished Jan 24 10:00:58 PM PST 24
Peak memory 216276 kb
Host smart-3412772b-1aa0-458a-956d-be0a656039c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875548963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.875548963
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.4214156805
Short name T1455
Test name
Test status
Simulation time 44902824421 ps
CPU time 62.74 seconds
Started Jan 24 10:00:28 PM PST 24
Finished Jan 24 10:01:38 PM PST 24
Peak memory 747904 kb
Host smart-5b8850a9-336a-46a7-8f6e-a490b8a6f3b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214156805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.4214156805
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.808345345
Short name T1041
Test name
Test status
Simulation time 1277987879 ps
CPU time 6.33 seconds
Started Jan 24 10:00:27 PM PST 24
Finished Jan 24 10:00:41 PM PST 24
Peak memory 205952 kb
Host smart-ffe305e1-f9d9-4ee6-a4f1-135b8fd58e5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808345345 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.808345345
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_ovf.2859894370
Short name T321
Test name
Test status
Simulation time 4824796585 ps
CPU time 43.33 seconds
Started Jan 24 10:00:26 PM PST 24
Finished Jan 24 10:01:17 PM PST 24
Peak memory 226072 kb
Host smart-117c0ef2-6de7-4048-88f0-9e99f60be45c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859894370 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_tx_ovf.2859894370
Directory /workspace/9.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.1769712355
Short name T1228
Test name
Test status
Simulation time 3596642659 ps
CPU time 5.34 seconds
Started Jan 24 10:00:27 PM PST 24
Finished Jan 24 10:00:41 PM PST 24
Peak memory 202692 kb
Host smart-54fe0189-439e-498a-b486-4e6b8f7b4c5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769712355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.1769712355
Directory /workspace/9.i2c_target_unexp_stop/latest
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