Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

237595

1

T7

21

T8

1

T9

1021

ack

19445

1

T7

2

T8

28

T9

30

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	942	1			T9	6		T33	14		T11	8
high	52620	1			T7	2		T8	1		T9	230
med	95714	1			T7	9		T8	4		T9	390
sml	106786	1			T7	11		T8	24		T9	423
all_zero	978	1			T7	1		T9	2		T33	19

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128230

1

T7

9

T8

15

T9

530

auto[1]

128810

1

T7

14

T8

14

T9

521

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176180

1

T7

14

T8

23

T9

723

auto[1]

80860

1

T7

9

T8

6

T9

328

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245803

1

T7

19

T8

12

T9

1040

auto[1]

11237

1

T7

4

T8

17

T9

11

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242792

1

T7

21

T8

17

T9

1028

auto[1]

14248

1

T7

2

T8

12

T9

23

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244620

1

T7

22

T8

18

T9

1029

auto[1]

12420

1

T7

1

T8

11

T9

22

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128230

1

T7

9

T8

15

T9

530

auto[1]

128810

1

T7

14

T8

14

T9

521

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176180

1

T7

14

T8

23

T9

723

auto[1]

80860

1

T7

9

T8

6

T9

328

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245803

1

T7

19

T8

12

T9

1040

auto[1]

11237

1

T7

4

T8

17

T9

11

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242792

1

T7

21

T8

17

T9

1028

auto[1]

14248

1

T7

2

T8

12

T9

23

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244620

1

T7

22

T8

18

T9

1029

auto[1]

12420

1

T7

1

T8

11

T9

22

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T33

1

T173

1

T174

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

5

1

T175

2

T176

1

T177

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

9

1

T131

1

T178

1

T179

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

591

1

T9

2

T33

5

T11

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

290

1

T9

1

T33

2

T12

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

305

1

T9

1

T33

6

T11

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1157

1

T9

4

T33

20

T11

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

570

1

T9

2

T33

6

T11

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

587

1

T9

1

T33

7

T11

5

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1168

1

T9

2

T33

18

T11

6

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

598

1

T33

7

T11

3

T65

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

559

1

T9

4

T33

5

T11

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

13

1

T180

1

T178

1

T181

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T182

1

T183

1

T184

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T30

1

T185

1

T186

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	75483	1			T7	4		T9	350		T33	1315
write_address_byte	14248	1			T7	2		T8	12		T9	23
read_with_ack	3903	1			T7	3		T8	6		T33	1
read_with_nack	7334	1			T7	1		T8	11		T9	11
stop_byte	12420	1			T7	1		T8	11		T9	22
write_address_byte_nak	9294	1			T7	1		T9	20		T33	136
data_byte_nack	237595	1			T7	21		T8	1		T9	1021
stop_byte_nack	8900	1			T7	1		T8	1		T9	20
nakok_byte_nack	119096	1			T7	14		T9	503		T33	2053
nakok_addr_byte_nack	4713	1			T7	1		T9	8		T33	66