Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fifo_level_cg

Group : i2c_env_pkg::i2c_fifo_level_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	91.18	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.rx_fifo_level_cg	82.35	1	100	1	64	64
i2c_env_pkg.fmt_fifo_level_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
82.35	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	3	5	62.50

Variables for Group Instance i2c_env_pkg.rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	0	5	100.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	3	5	62.50	100	1	1	0

---

Group Instance : i2c_env_pkg.fmt_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.fmt_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_fifolvl	5	0	5	100.00	100	1	1	0
cp_irq	2	0	2	100.00	100	1	1	2
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fifo_threshold_cross	8	0	8	100.00	100	1	1	0

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fifolvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	33235	1			T1	7		T2	4		T3	7
lvl[1]	179	1			T33	7		T65	1		T30	2
lvl[4]	232	1			T33	39		T65	3		T200	2
lvl[8]	155	1			T33	6		T65	1		T30	4
lvl[16]	266	1			T33	12		T65	2		T30	3

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30296

1

T1

7

T2

4

T3

7

auto[1]

3771

1

T9

27

T10

2

T33

43

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31418

1

T1

6

T2

3

T3

6

auto[1]

2649

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	3	5	62.50	3
Automatically Generated Cross Bins	8	3	5	62.50	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Uncovered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	NUMBER	STATUS
[lvl[1]]	[auto[1]]	0	1	1
[lvl[8] , lvl[16]]	[auto[1]]	--	--	2

Covered bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lvl[1]	auto[0]	179	1			T33	7		T65	1		T30	2
lvl[4]	auto[0]	190	1			T33	25		T65	3		T200	2
lvl[4]	auto[1]	42	1			T33	14		T140	28		-	-
lvl[8]	auto[0]	155	1			T33	6		T65	1		T30	4
lvl[16]	auto[0]	266	1			T33	12		T65	2		T30	3

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded

Summary for Variable cp_fifolvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fifolvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	31431	1			T1	7		T2	4		T3	7
lvl[1]	1475	1			T33	89		T65	10		T30	16
lvl[4]	430	1			T33	11		T65	2		T30	3
lvl[8]	404	1			T33	10		T65	4		T30	27
lvl[16]	327	1			T33	9		T65	2		T30	6

---

Summary for Variable cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_irq

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28223

1

T1

7

T2

4

T3

7

auto[1]

5844

1

T9

28

T33

69

T64

16

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31075

1

T1

6

T2

3

T3

6

auto[1]

2992

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_fifo_threshold_cross

Bins

cp_fifolvl	cp_irq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lvl[1]	auto[0]	1292	1			T33	61		T65	10		T30	16
lvl[1]	auto[1]	183	1			T33	28		T48	4		T49	4
lvl[4]	auto[0]	356	1			T33	11		T65	2		T30	3
lvl[4]	auto[1]	74	1			T48	2		T50	2		T201	2
lvl[8]	auto[0]	324	1			T33	10		T65	4		T30	8
lvl[8]	auto[1]	80	1			T30	19		T49	2		T202	2
lvl[16]	auto[0]	323	1			T33	9		T65	2		T30	6
lvl[16]	auto[1]	4	1			T203	2		T204	2		-	-

User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
reserved_values	0	Excluded