Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	577104198	20842	0	0
ctrl_rd_A	577104198	1937	0	0
fifo_ctrl_rd_A	577104198	6011	0	0
host_timeout_ctrl_rd_A	577104198	1533	0	0
intr_enable_rd_A	577104198	4636	0	0
ovrd_rd_A	577104198	2377	0	0
target_id_rd_A	577104198	2360	0	0
timeout_ctrl_rd_A	577104198	1802	0	0
timing0_rd_A	577104198	1675	0	0
timing1_rd_A	577104198	1640	0	0
timing2_rd_A	577104198	1763	0	0
timing3_rd_A	577104198	1632	0	0
timing4_rd_A	577104198	1794	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	20842	0	0
T20	7264	439	0	0
T21	2688	0	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	6	0	0
T26	1301	0	0	0
T27	5657	4	0	0
T67	3523	51	0	0
T68	0	399	0	0
T69	0	4	0	0
T73	0	4	0	0
T103	1163	0	0	0
T121	0	15	0	0
T134	0	29	0	0
T135	0	64	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	1937	0	0
T21	2688	11	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	10	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	4	0	0
T75	0	9	0	0
T82	0	159	0	0
T85	0	382	0	0
T103	1163	11	0	0
T107	0	9	0	0
T108	0	10	0	0
T136	0	5	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	6011	0	0
T21	2688	17	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	9	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	21	0	0
T75	0	9	0	0
T82	0	294	0	0
T103	1163	18	0	0
T107	0	30	0	0
T108	0	29	0	0
T109	0	16	0	0
T136	0	3	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	1533	0	0
T21	2688	24	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	11	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	6	0	0
T75	0	13	0	0
T82	0	111	0	0
T85	0	387	0	0
T103	1163	0	0	0
T106	0	15	0	0
T107	0	13	0	0
T108	0	9	0	0
T136	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	4636	0	0
T21	2688	7	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	21	0	0
T25	1774	19	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	18	0	0
T103	1163	26	0	0
T107	0	5	0	0
T118	0	8	0	0
T120	0	19	0	0
T137	0	8	0	0
T138	0	23	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	2377	0	0
T6	0	61	0	0
T21	2688	8	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	10	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	8	0	0
T75	0	12	0	0
T82	0	117	0	0
T103	1163	0	0	0
T107	0	11	0	0
T108	0	10	0	0
T109	0	9	0	0
T136	0	10	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	2360	0	0
T21	2688	19	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	12	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	8	0	0
T75	0	28	0	0
T82	0	233	0	0
T103	1163	14	0	0
T107	0	6	0	0
T108	0	5	0	0
T109	0	19	0	0
T136	0	13	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	1802	0	0
T21	2688	15	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	19	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	17	0	0
T75	0	30	0	0
T82	0	124	0	0
T103	1163	8	0	0
T107	0	14	0	0
T108	0	10	0	0
T109	0	13	0	0
T136	0	5	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	1675	0	0
T21	2688	3	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	10	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	23	0	0
T75	0	3	0	0
T82	0	110	0	0
T85	0	307	0	0
T103	1163	0	0	0
T106	0	18	0	0
T107	0	11	0	0
T109	0	4	0	0
T136	0	2	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	1640	0	0
T21	2688	2	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	14	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	19	0	0
T75	0	8	0	0
T82	0	87	0	0
T103	1163	5	0	0
T107	0	10	0	0
T108	0	12	0	0
T109	0	11	0	0
T136	0	22	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	1763	0	0
T21	2688	11	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	10	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	27	0	0
T75	0	2	0	0
T82	0	107	0	0
T103	1163	6	0	0
T107	0	12	0	0
T108	0	5	0	0
T109	0	5	0	0
T136	0	4	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	1632	0	0
T21	2688	16	0	0
T22	27693	0	0	0
T23	1399	0	0	0
T24	1499	0	0	0
T25	1774	16	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T74	0	15	0	0
T75	0	9	0	0
T82	0	92	0	0
T85	0	391	0	0
T103	1163	5	0	0
T107	0	10	0	0
T109	0	2	0	0
T136	0	9	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577104198	1794	0	0
T25	1774	17	0	0
T26	1301	0	0	0
T27	5657	0	0	0
T60	1172	0	0	0
T67	3523	0	0	0
T68	3587	0	0	0
T74	0	19	0	0
T75	0	12	0	0
T82	0	103	0	0
T85	0	454	0	0
T103	1163	0	0	0
T106	0	29	0	0
T107	0	14	0	0
T109	0	6	0	0
T111	0	6	0	0
T118	1338	0	0	0
T119	1816	0	0	0
T120	1241	0	0	0
T136	0	12	0	0