Unified Coverage Report :: Module :: i2c_reg_top

Module : i2c_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.90	100.00	99.59			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.90	100.00	99.59			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.90	100.00	99.59			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	99.26	99.44	100.00		99.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acqdata_abyte	100.00	100.00
u_acqdata_signal	100.00	100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_enablehost	100.00	100.00	100.00			100.00
u_ctrl_enabletarget	100.00	100.00	100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_fdata0_qe	100.00	100.00				100.00
u_fdata_fbyte	100.00	100.00	100.00			100.00
u_fdata_nakok	100.00	100.00	100.00			100.00
u_fdata_rcont	100.00	100.00	100.00			100.00
u_fdata_readb	100.00	100.00	100.00			100.00
u_fdata_start	100.00	100.00	100.00			100.00
u_fdata_stop	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_acqrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtilvl	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxilvl	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_fifo_status_acqlvl	100.00	100.00
u_fifo_status_fmtlvl	100.00	100.00
u_fifo_status_rxlvl	100.00	100.00
u_fifo_status_txlvl	100.00	100.00
u_host_timeout_ctrl	100.00	100.00	100.00			100.00
u_intr_enable_acq_full	100.00	100.00	100.00			100.00
u_intr_enable_cmd_complete	100.00	100.00	100.00			100.00
u_intr_enable_fmt_overflow	100.00	100.00	100.00			100.00
u_intr_enable_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_enable_host_timeout	100.00	100.00	100.00			100.00
u_intr_enable_nak	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_scl_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_unstable	100.00	100.00	100.00			100.00
u_intr_enable_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_enable_tx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_tx_stretch	100.00	100.00	100.00			100.00
u_intr_enable_unexp_stop	100.00	100.00	100.00			100.00
u_intr_state_acq_full	62.59	77.78	50.00			60.00
u_intr_state_cmd_complete	100.00	100.00	100.00			100.00
u_intr_state_fmt_overflow	100.00	100.00	100.00			100.00
u_intr_state_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_state_host_timeout	100.00	100.00	100.00			100.00
u_intr_state_nak	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_threshold	100.00	100.00	100.00			100.00
u_intr_state_scl_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_unstable	100.00	100.00	100.00			100.00
u_intr_state_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_state_tx_overflow	100.00	100.00	100.00			100.00
u_intr_state_tx_stretch	62.59	77.78	50.00			60.00
u_intr_state_unexp_stop	100.00	100.00	100.00			100.00
u_intr_test_acq_full	100.00	100.00
u_intr_test_cmd_complete	100.00	100.00
u_intr_test_fmt_overflow	100.00	100.00
u_intr_test_fmt_threshold	100.00	100.00
u_intr_test_host_timeout	100.00	100.00
u_intr_test_nak	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_threshold	100.00	100.00
u_intr_test_scl_interference	100.00	100.00
u_intr_test_sda_interference	100.00	100.00
u_intr_test_sda_unstable	100.00	100.00
u_intr_test_stretch_timeout	100.00	100.00
u_intr_test_tx_overflow	100.00	100.00
u_intr_test_tx_stretch	100.00	100.00
u_intr_test_unexp_stop	100.00	100.00
u_ovrd_sclval	100.00	100.00	100.00			100.00
u_ovrd_sdaval	100.00	100.00	100.00			100.00
u_ovrd_txovrden	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_rdata	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_acqempty	100.00	100.00
u_status_acqfull	100.00	100.00
u_status_fmtempty	100.00	100.00
u_status_fmtfull	100.00	100.00
u_status_hostidle	100.00	100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_targetidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_target_id_address0	100.00	100.00	100.00			100.00
u_target_id_address1	100.00	100.00	100.00			100.00
u_target_id_mask0	100.00	100.00	100.00			100.00
u_target_id_mask1	100.00	100.00	100.00			100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timing0_thigh	100.00	100.00	100.00			100.00
u_timing0_tlow	100.00	100.00	100.00			100.00
u_timing1_t_f	100.00	100.00	100.00			100.00
u_timing1_t_r	100.00	100.00	100.00			100.00
u_timing2_thd_sta	100.00	100.00	100.00			100.00
u_timing2_tsu_sta	100.00	100.00	100.00			100.00
u_timing3_thd_dat	100.00	100.00	100.00			100.00
u_timing3_tsu_dat	100.00	100.00	100.00			100.00
u_timing4_t_buf	100.00	100.00	100.00			100.00
u_timing4_tsu_sto	100.00	100.00	100.00			100.00
u_txdata	100.00	100.00	100.00			100.00
u_txdata0_qe	100.00	100.00				100.00
u_val_scl_rx	66.67	66.67
u_val_sda_rx	66.67	66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
TOTAL		295	295	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	1119	1	1	100.00
CONT_ASSIGN	1134	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1166	1	1	100.00
CONT_ASSIGN	1182	1	1	100.00
CONT_ASSIGN	1198	1	1	100.00
CONT_ASSIGN	1214	1	1	100.00
CONT_ASSIGN	1230	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1358	1	1	100.00
CONT_ASSIGN	1364	1	1	100.00
CONT_ASSIGN	1378	1	1	100.00
CONT_ASSIGN	1670	1	1	100.00
CONT_ASSIGN	1698	1	1	100.00
CONT_ASSIGN	1726	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1782	1	1	100.00
CONT_ASSIGN	1810	1	1	100.00
CONT_ASSIGN	1851	1	1	100.00
CONT_ASSIGN	1879	1	1	100.00
CONT_ASSIGN	1907	1	1	100.00
CONT_ASSIGN	1935	1	1	100.00
CONT_ASSIGN	1963	1	1	100.00
CONT_ASSIGN	1991	1	1	100.00
CONT_ASSIGN	2686	1	1	100.00
ALWAYS	2720	23	23	100.00
CONT_ASSIGN	2745	1	1	100.00
ALWAYS	2749	1	1	100.00
CONT_ASSIGN	2775	1	1	100.00
CONT_ASSIGN	2777	1	1	100.00
CONT_ASSIGN	2779	1	1	100.00
CONT_ASSIGN	2781	1	1	100.00
CONT_ASSIGN	2783	1	1	100.00
CONT_ASSIGN	2785	1	1	100.00
CONT_ASSIGN	2787	1	1	100.00
CONT_ASSIGN	2789	1	1	100.00
CONT_ASSIGN	2791	1	1	100.00
CONT_ASSIGN	2793	1	1	100.00
CONT_ASSIGN	2795	1	1	100.00
CONT_ASSIGN	2797	1	1	100.00
CONT_ASSIGN	2799	1	1	100.00
CONT_ASSIGN	2801	1	1	100.00
CONT_ASSIGN	2802	1	1	100.00
CONT_ASSIGN	2804	1	1	100.00
CONT_ASSIGN	2806	1	1	100.00
CONT_ASSIGN	2808	1	1	100.00
CONT_ASSIGN	2810	1	1	100.00
CONT_ASSIGN	2812	1	1	100.00
CONT_ASSIGN	2814	1	1	100.00
CONT_ASSIGN	2816	1	1	100.00
CONT_ASSIGN	2818	1	1	100.00
CONT_ASSIGN	2820	1	1	100.00
CONT_ASSIGN	2822	1	1	100.00
CONT_ASSIGN	2824	1	1	100.00
CONT_ASSIGN	2826	1	1	100.00
CONT_ASSIGN	2828	1	1	100.00
CONT_ASSIGN	2830	1	1	100.00
CONT_ASSIGN	2832	1	1	100.00
CONT_ASSIGN	2833	1	1	100.00
CONT_ASSIGN	2835	1	1	100.00
CONT_ASSIGN	2837	1	1	100.00
CONT_ASSIGN	2839	1	1	100.00
CONT_ASSIGN	2841	1	1	100.00
CONT_ASSIGN	2843	1	1	100.00
CONT_ASSIGN	2845	1	1	100.00
CONT_ASSIGN	2847	1	1	100.00
CONT_ASSIGN	2849	1	1	100.00
CONT_ASSIGN	2851	1	1	100.00
CONT_ASSIGN	2853	1	1	100.00
CONT_ASSIGN	2855	1	1	100.00
CONT_ASSIGN	2857	1	1	100.00
CONT_ASSIGN	2859	1	1	100.00
CONT_ASSIGN	2861	1	1	100.00
CONT_ASSIGN	2863	1	1	100.00
CONT_ASSIGN	2864	1	1	100.00
CONT_ASSIGN	2866	1	1	100.00
CONT_ASSIGN	2867	1	1	100.00
CONT_ASSIGN	2869	1	1	100.00
CONT_ASSIGN	2871	1	1	100.00
CONT_ASSIGN	2873	1	1	100.00
CONT_ASSIGN	2874	1	1	100.00
CONT_ASSIGN	2875	1	1	100.00
CONT_ASSIGN	2876	1	1	100.00
CONT_ASSIGN	2878	1	1	100.00
CONT_ASSIGN	2880	1	1	100.00
CONT_ASSIGN	2882	1	1	100.00
CONT_ASSIGN	2884	1	1	100.00
CONT_ASSIGN	2886	1	1	100.00
CONT_ASSIGN	2888	1	1	100.00
CONT_ASSIGN	2889	1	1	100.00
CONT_ASSIGN	2891	1	1	100.00
CONT_ASSIGN	2893	1	1	100.00
CONT_ASSIGN	2895	1	1	100.00
CONT_ASSIGN	2897	1	1	100.00
CONT_ASSIGN	2899	1	1	100.00
CONT_ASSIGN	2901	1	1	100.00
CONT_ASSIGN	2902	1	1	100.00
CONT_ASSIGN	2903	1	1	100.00
CONT_ASSIGN	2905	1	1	100.00
CONT_ASSIGN	2907	1	1	100.00
CONT_ASSIGN	2909	1	1	100.00
CONT_ASSIGN	2910	1	1	100.00
CONT_ASSIGN	2911	1	1	100.00
CONT_ASSIGN	2913	1	1	100.00
CONT_ASSIGN	2915	1	1	100.00
CONT_ASSIGN	2916	1	1	100.00
CONT_ASSIGN	2918	1	1	100.00
CONT_ASSIGN	2920	1	1	100.00
CONT_ASSIGN	2921	1	1	100.00
CONT_ASSIGN	2923	1	1	100.00
CONT_ASSIGN	2925	1	1	100.00
CONT_ASSIGN	2926	1	1	100.00
CONT_ASSIGN	2928	1	1	100.00
CONT_ASSIGN	2930	1	1	100.00
CONT_ASSIGN	2931	1	1	100.00
CONT_ASSIGN	2933	1	1	100.00
CONT_ASSIGN	2935	1	1	100.00
CONT_ASSIGN	2936	1	1	100.00
CONT_ASSIGN	2938	1	1	100.00
CONT_ASSIGN	2940	1	1	100.00
CONT_ASSIGN	2941	1	1	100.00
CONT_ASSIGN	2943	1	1	100.00
CONT_ASSIGN	2945	1	1	100.00
CONT_ASSIGN	2947	1	1	100.00
CONT_ASSIGN	2949	1	1	100.00
CONT_ASSIGN	2950	1	1	100.00
CONT_ASSIGN	2951	1	1	100.00
CONT_ASSIGN	2953	1	1	100.00
CONT_ASSIGN	2954	1	1	100.00
CONT_ASSIGN	2956	1	1	100.00
ALWAYS	2960	23	23	100.00
ALWAYS	2987	103	103	100.00
CONT_ASSIGN	3167	0	0
CONT_ASSIGN	3175	1	1	100.00
CONT_ASSIGN	3176	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
1119	1	1
1134	1	1
1150	1	1
1166	1	1
1182	1	1
1198	1	1
1214	1	1
1230	1	1
1246	1	1
1262	1	1
1278	1	1
1294	1	1
1310	1	1
1326	1	1
1342	1	1
1358	1	1
1364	1	1
1378	1	1
1670	1	1
1698	1	1
1726	1	1
1754	1	1
1782	1	1
1810	1	1
1851	1	1
1879	1	1
1907	1	1
1935	1	1
1963	1	1
1991	1	1
2686	1	1
2720	1	1
2721	1	1
2722	1	1
2723	1	1
2724	1	1
2725	1	1
2726	1	1
2727	1	1
2728	1	1
2729	1	1
2730	1	1
2731	1	1
2732	1	1
2733	1	1
2734	1	1
2735	1	1
2736	1	1
2737	1	1
2738	1	1
2739	1	1
2740	1	1
2741	1	1
2742	1	1
2745	1	1
2749	1	1
2775	1	1
2777	1	1
2779	1	1
2781	1	1
2783	1	1
2785	1	1
2787	1	1
2789	1	1
2791	1	1
2793	1	1
2795	1	1
2797	1	1
2799	1	1
2801	1	1
2802	1	1
2804	1	1
2806	1	1
2808	1	1
2810	1	1
2812	1	1
2814	1	1
2816	1	1
2818	1	1
2820	1	1
2822	1	1
2824	1	1
2826	1	1
2828	1	1
2830	1	1
2832	1	1
2833	1	1
2835	1	1
2837	1	1
2839	1	1
2841	1	1
2843	1	1
2845	1	1
2847	1	1
2849	1	1
2851	1	1
2853	1	1
2855	1	1
2857	1	1
2859	1	1
2861	1	1
2863	1	1
2864	1	1
2866	1	1
2867	1	1
2869	1	1
2871	1	1
2873	1	1
2874	1	1
2875	1	1
2876	1	1
2878	1	1
2880	1	1
2882	1	1
2884	1	1
2886	1	1
2888	1	1
2889	1	1
2891	1	1
2893	1	1
2895	1	1
2897	1	1
2899	1	1
2901	1	1
2902	1	1
2903	1	1
2905	1	1
2907	1	1
2909	1	1
2910	1	1
2911	1	1
2913	1	1
2915	1	1
2916	1	1
2918	1	1
2920	1	1
2921	1	1
2923	1	1
2925	1	1
2926	1	1
2928	1	1
2930	1	1
2931	1	1
2933	1	1
2935	1	1
2936	1	1
2938	1	1
2940	1	1
2941	1	1
2943	1	1
2945	1	1
2947	1	1
2949	1	1
2950	1	1
2951	1	1
2953	1	1
2954	1	1
2956	1	1
2960	1	1
2961	1	1
2962	1	1
2963	1	1
2964	1	1
2965	1	1
2966	1	1
2967	1	1
2968	1	1
2969	1	1
2970	1	1
2971	1	1
2972	1	1
2973	1	1
2974	1	1
2975	1	1
2976	1	1
2977	1	1
2978	1	1
2979	1	1
2980	1	1
2981	1	1
2982	1	1
2987	1	1
2988	1	1
2990	1	1
2991	1	1
2992	1	1
2993	1	1
2994	1	1
2995	1	1
2996	1	1
2997	1	1
2998	1	1
2999	1	1
3000	1	1
3001	1	1
3002	1	1
3003	1	1
3004	1	1
3008	1	1
3009	1	1
3010	1	1
3011	1	1
3012	1	1
3013	1	1
3014	1	1
3015	1	1
3016	1	1
3017	1	1
3018	1	1
3019	1	1
3020	1	1
3021	1	1
3022	1	1
3026	1	1
3027	1	1
3028	1	1
3029	1	1
3030	1	1
3031	1	1
3032	1	1
3033	1	1
3034	1	1
3035	1	1
3036	1	1
3037	1	1
3038	1	1
3039	1	1
3040	1	1
3044	1	1
3048	1	1
3049	1	1
3050	1	1
3054	1	1
3055	1	1
3056	1	1
3057	1	1
3058	1	1
3059	1	1
3060	1	1
3061	1	1
3062	1	1
3063	1	1
3067	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3080	1	1
3081	1	1
3082	1	1
3083	1	1
3084	1	1
3085	1	1
3089	1	1
3090	1	1
3091	1	1
3092	1	1
3096	1	1
3097	1	1
3098	1	1
3102	1	1
3103	1	1
3107	1	1
3108	1	1
3112	1	1
3113	1	1
3117	1	1
3118	1	1
3122	1	1
3123	1	1
3127	1	1
3128	1	1
3132	1	1
3133	1	1
3137	1	1
3138	1	1
3139	1	1
3140	1	1
3144	1	1
3145	1	1
3149	1	1
3153	1	1
3167		unreachable
3175	1	1
3176	1	1

---

Cond Coverage for Module : i2c_reg_top

	Total	Covered	Percent
Conditions	243	242	99.59
Logical	243	242	99.59
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T70,T71
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T73,T74,T75
1	0	Covered	T76,T77,T78

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T73,T74,T75
0	1	0	Covered	T76,T77,T78
1	0	0	Covered	T73,T74,T75

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T76,T77,T78
0	1	0	Covered	T68,T69,T70
1	0	0	Covered	T69,T70,T71

 LINE       2721
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2722
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2723
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T20,T26

 LINE       2724
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T20,T31

 LINE       2725
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2726
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2727
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T9

 LINE       2728
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T11,T8

 LINE       2729
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2730
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_STATUS_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       2731
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T20,T31

 LINE       2732
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T20,T31

 LINE       2733
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2734
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2735
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2736
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2737
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2738
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2739
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       2740
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       2741
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       2742
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       2745
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2745
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       2749
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T68,T69,T70

 LINE       2749
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
22 (addr_hit[21] & ((|(4'...	Covered	T11,T20,T31
21 (addr_hit[20] & ((|(4'...	Covered	T11,T20,T31
20 (addr_hit[19] & ((|(4'...	Covered	T1,T2,T11
19 (addr_hit[18] & ((|(4'...	Covered	T11,T20,T31
18 (addr_hit[17] & ((|(4'...	Covered	T11,T20,T31
17 (addr_hit[16] & ((|(4'...	Covered	T11,T20,T31
16 (addr_hit[15] & ((|(4'...	Covered	T11,T20,T31
15 (addr_hit[14] & ((|(4'...	Covered	T11,T20,T31
14 (addr_hit[13] & ((|(4'...	Covered	T11,T20,T31
13 (addr_hit[12] & ((|(4'...	Covered	T11,T20,T31
12 (addr_hit[11] & ((|(4'...	Covered	T11,T20,T31
11 (addr_hit[10] & ((|(4'...	Covered	T11,T20,T31
10 (addr_hit[9] & ((|(4'b...	Covered	T1,T2,T11
9 (addr_hit[8] & ((|(4'b...	Covered	T11,T20,T31
8 (addr_hit[7] & ((|(4'b...	Covered	T11,T20,T31
7 (addr_hit[6] & ((|(4'b...	Covered	T3,T11,T9
6 (addr_hit[5] & ((|(4'b...	Covered	T1,T2,T3
5 (addr_hit[4] & ((|(4'b...	Covered	T11,T20,T31
4 (addr_hit[3] & ((|(4'b...	Covered	T11,T20,T31
3 (addr_hit[2] & ((|(4'b...	Covered	T11,T20,T26
2 (addr_hit[1] & ((|(4'b...	Covered	T11,T20,T26
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       2749
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2749
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T20,T26

 LINE       2749
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T20,T26
1	1	Covered	T11,T20,T26

 LINE       2749
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T20,T31
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T8
1	1	Covered	T1,T2,T3

 LINE       2749
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T9
1	1	Covered	T3,T11,T9

 LINE       2749
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T8
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T20,T31
1	1	Covered	T1,T2,T11

 LINE       2749
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T20,T31
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T20,T31
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T11

 LINE       2749
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T11,T20,T31

 LINE       2749
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T11,T20,T31

 LINE       2775
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T70,T71,T79
1	1	1	Covered	T1,T2,T3

 LINE       2802
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T72,T71,T79
1	1	1	Covered	T1,T2,T3

 LINE       2833
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T20,T26
1	1	0	Covered	T80,T81,T82
1	1	1	Covered	T26,T61,T59

 LINE       2864
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T20,T31
1	1	0	Covered	T69,T71,T76
1	1	1	Covered	T83,T84,T85

 LINE       2867
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T70,T71,T76
1	1	1	Covered	T1,T2,T3

 LINE       2874
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T76,T86,T87
1	1	1	Covered	T1,T2,T3

 LINE       2875
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T11,T9
1	1	0	Covered	T76,T88,T89
1	1	1	Covered	T3,T9,T10

 LINE       2876
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T11,T8
1	1	0	Covered	T71,T79,T90
1	1	1	Covered	T3,T11,T8

 LINE       2889
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T76,T79,T77
1	1	1	Covered	T1,T2,T3

 LINE       2902
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T11
1	1	0	Covered	T91
1	1	1	Covered	T1,T2,T7

 LINE       2903
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T20,T31
1	1	0	Covered	T69,T71,T79
1	1	1	Covered	T4,T5,T6

 LINE       2910
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T20,T31
1	1	0	Covered	T92,T93
1	1	1	Not Covered

 LINE       2911
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T69,T70,T71
1	1	1	Covered	T1,T2,T3

 LINE       2916
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T69,T70,T79
1	1	1	Covered	T1,T2,T3

 LINE       2921
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T72,T79,T94
1	1	1	Covered	T1,T2,T3

 LINE       2926
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T72,T71,T79
1	1	1	Covered	T1,T2,T3

 LINE       2931
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T71,T95,T80
1	1	1	Covered	T1,T2,T3

 LINE       2936
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T70,T71,T79
1	1	1	Covered	T1,T2,T3

 LINE       2941
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T11
1	1	0	Covered	T69,T72,T79
1	1	1	Covered	T1,T2,T7

 LINE       2950
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T11
1	1	0	Covered	T86,T96,T93
1	1	1	Covered	T1,T2,T7

 LINE       2951
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T11
1	1	0	Covered	T68,T70,T71
1	1	1	Covered	T1,T2,T7

 LINE       2954
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T11
1	1	0	Covered	T80,T97,T98
1	1	1	Covered	T1,T2,T7

---

Branch Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
Branches		28	28	100.00
TERNARY	2745	2	2	100.00
IF	68	3	3	100.00
CASE	2988	23	23	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2745	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T73,T74,T75
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	2988	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	540514081	64808046	0	0
reAfterRv	540514081	64807909	0	0
rePulse	540514081	57633366	0	0
wePulse	540514081	7174543	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	64808046	0	0
T1	109861	842	0	0
T2	264299	29006	0	0
T3	223136	106355	0	0
T7	155529	1984	0	0
T8	2939	181	0	0
T9	255169	418709	0	0
T11	17261	1798	0	0
T18	314978	1695	0	0
T19	228070	1233	0	0
T20	858768	7049	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	64807909	0	0
T1	109861	842	0	0
T2	264299	29006	0	0
T3	223136	106355	0	0
T7	155529	1984	0	0
T8	2939	180	0	0
T9	255169	418709	0	0
T11	17261	1798	0	0
T18	314978	1695	0	0
T19	228070	1233	0	0
T20	858768	7049	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	57633366	0	0
T1	109861	561	0	0
T2	264299	19103	0	0
T3	223136	83265	0	0
T7	155529	1522	0	0
T8	2939	105	0	0
T9	255169	314086	0	0
T11	17261	1782	0	0
T18	314978	1677	0	0
T19	228070	1215	0	0
T20	858768	4939	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	7174543	0	0
T1	109861	281	0	0
T2	264299	9903	0	0
T3	223136	23090	0	0
T7	155529	462	0	0
T8	2939	75	0	0
T9	255169	104623	0	0
T11	17261	16	0	0
T18	314978	18	0	0
T19	228070	18	0	0
T20	858768	2110	0	0