Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	100.00	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.85	99.12	96.72	100.00	93.04	98.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i2c_core	96.35	98.94	92.65		93.04	97.12	100.00
i2c_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_reg	99.58	99.26	99.44	100.00		99.18	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
67	1	1
126	1	1
127	1	1

---

Cond Coverage for Module : i2c

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       67
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T83,T84,T85
1	0	Covered	T1,T2,T3
1	1	Covered	T83,T84,T99

---

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	45	45	100.00
Total Bits	370	370	100.00
Total Bits 0->1	185	185	100.00
Total Bits 1->0	185	185	100.00

Ports	45	45	100.00
Port Bits	370	370	100.00
Port Bits 0->1	185	185	100.00
Port Bits 1->0	185	185	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T8,T20	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T11	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T11,T20,T31	Yes	T11,T20,T31	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T11	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T67,T68,T69	Yes	T67,T68,T69	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T83,T84,T73	Yes	T83,T84,T73	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T83,T84,T73	Yes	T83,T84,T73	OUTPUT
cio_scl_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_sda_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	OUTPUT
intr_rx_threshold_o	Yes	Yes	T3,T11,T9	Yes	T3,T11,T9	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T26,T12,T13	Yes	T26,T12,T13	OUTPUT
intr_rx_overflow_o	Yes	Yes	T26,T15,T12	Yes	T26,T15,T12	OUTPUT
intr_nak_o	Yes	Yes	T26,T59,T60	Yes	T26,T59,T60	OUTPUT
intr_scl_interference_o	Yes	Yes	T26,T61,T59	Yes	T26,T61,T59	OUTPUT
intr_sda_interference_o	Yes	Yes	T3,T11,T8	Yes	T3,T11,T8	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T3,T8,T9	Yes	T3,T8,T9	OUTPUT
intr_sda_unstable_o	Yes	Yes	T3,T11,T8	Yes	T3,T11,T8	OUTPUT
intr_cmd_complete_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
intr_tx_stretch_o	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
intr_tx_overflow_o	Yes	Yes	T2,T26,T16	Yes	T2,T26,T16	OUTPUT
intr_acq_full_o	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
intr_unexp_stop_o	Yes	Yes	T7,T31,T32	Yes	T7,T31,T32	OUTPUT
intr_host_timeout_o	Yes	Yes	T20,T26,T21	Yes	T20,T26,T21	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : i2c

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	539900328	539720526	0	0
CioSclEnKnownO_A	539900328	539720526	0	0
CioSclKnownO_A	539900328	539720526	0	0
CioSdaEnKnownO_A	539900328	539720526	0	0
CioSdaKnownO_A	539900328	539720526	0	0
FpvSecCmRegWeOnehotCheck_A	539900328	70	0	0
IntrAcqFulllwKnownO_A	539900328	539720526	0	0
IntrCommandCompleteKnownO_A	539900328	539720526	0	0
IntrFmtOflwKnownO_A	539900328	539720526	0	0
IntrFmtWtmkKnownO_A	539900328	539720526	0	0
IntrHostTimeoutKnownO_A	539900328	539720526	0	0
IntrNakKnownO_A	539900328	539720526	0	0
IntrRxOflwKnownO_A	539900328	539720526	0	0
IntrRxWtmkKnownO_A	539900328	539720526	0	0
IntrSclInterfKnownO_A	539900328	539720526	0	0
IntrSdaInterfKnownO_A	539900328	539720526	0	0
IntrSdaUnstableKnownO_A	539900328	539720526	0	0
IntrStretchTimeoutKnownO_A	539900328	539720526	0	0
IntrTxOflwKnownO_A	539900328	539720526	0	0
IntrTxStretchKnownO_A	539900328	539720526	0	0
IntrUnexpStopKnownO_A	539900328	539720526	0	0
TlAReadyKnownO_A	539900328	539720526	0	0
TlDValidKnownO_A	539900328	539720526	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

CioSclEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

CioSclKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

CioSdaEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

CioSdaKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	70	0	0
T73	4564	10	0	0
T74	0	20	0	0
T75	0	10	0	0
T100	0	20	0	0
T101	0	10	0	0
T102	379745	0	0	0
T103	50859	0	0	0
T104	61762	0	0	0
T105	85541	0	0	0
T106	507552	0	0	0
T107	661064	0	0	0
T108	2898	0	0	0
T109	150169	0	0	0
T110	3528	0	0	0

IntrAcqFulllwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrCommandCompleteKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrFmtOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrFmtWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrHostTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrNakKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrRxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrRxWtmkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrSclInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrSdaInterfKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrSdaUnstableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrStretchTimeoutKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrTxOflwKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrTxStretchKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

IntrUnexpStopKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539900328	539720526	0	0
T1	109861	109763	0	0
T2	264299	264220	0	0
T3	223136	222989	0	0
T7	155529	155464	0	0
T8	2939	2505	0	0
T9	255169	255160	0	0
T11	17261	17170	0	0
T18	314978	314971	0	0
T19	228070	228063	0	0
T20	858768	858506	0	0