Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	540514081	11976	0	0
ctrl_rd_A	540514081	1679	0	0
fifo_ctrl_rd_A	540514081	4761	0	0
host_timeout_ctrl_rd_A	540514081	1101	0	0
intr_enable_rd_A	540514081	5257	0	0
ovrd_rd_A	540514081	2306	0	0
target_id_rd_A	540514081	2022	0	0
timeout_ctrl_rd_A	540514081	1375	0	0
timing0_rd_A	540514081	1436	0	0
timing1_rd_A	540514081	1542	0	0
timing2_rd_A	540514081	1508	0	0
timing3_rd_A	540514081	1466	0	0
timing4_rd_A	540514081	1362	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	11976	0	0
T67	2674	27	0	0
T68	2992	52	0	0
T69	3705	191	0	0
T70	11935	903	0	0
T71	5332	258	0	0
T72	2571	114	0	0
T76	8154	10	0	0
T77	6833	1	0	0
T79	12548	786	0	0
T95	3136	25	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	1679	0	0
T67	2674	3	0	0
T71	5332	7	0	0
T77	6833	75	0	0
T79	12548	34	0	0
T87	11389	186	0	0
T95	3136	22	0	0
T113	2154	3	0	0
T129	2367	7	0	0
T131	21072	209	0	0
T132	3465	97	0	0

fifo_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	4761	0	0
T6	1136	0	0	0
T61	0	129	0	0
T107	661064	77	0	0
T108	2898	0	0	0
T109	150169	0	0	0
T110	3528	0	0	0
T133	0	84	0	0
T134	0	137	0	0
T135	0	52	0	0
T136	0	71	0	0
T137	0	51	0	0
T138	0	100	0	0
T139	0	25	0	0
T140	0	126	0	0
T141	19896	0	0	0
T142	59020	0	0	0
T143	307884	0	0	0
T144	969539	0	0	0
T145	200102	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	1101	0	0
T67	2674	7	0	0
T77	6833	39	0	0
T79	12548	8	0	0
T82	3758	1	0	0
T87	11389	66	0	0
T95	3136	16	0	0
T97	4285	5	0	0
T113	2154	3	0	0
T131	21072	243	0	0
T132	3465	85	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	5257	0	0
T59	0	11	0	0
T61	124794	13	0	0
T138	0	12	0	0
T140	0	19	0	0
T146	0	14	0	0
T147	0	3	0	0
T148	0	10	0	0
T149	0	27	0	0
T150	0	25	0	0
T151	0	50	0	0
T152	429417	0	0	0
T153	41958	0	0	0
T154	169717	0	0	0
T155	46220	0	0	0
T156	98839	0	0	0
T157	93908	0	0	0
T158	377303	0	0	0
T159	54355	0	0	0
T160	206889	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	2306	0	0
T161	1984	27	0	0
T162	1430	82	0	0
T163	0	34	0	0
T164	0	29	0	0
T165	0	31	0	0
T166	0	33	0	0
T167	0	29	0	0
T168	0	66	0	0
T169	0	27	0	0
T170	0	35	0	0
T171	200929	0	0	0
T172	50818	0	0	0
T173	372001	0	0	0
T174	176519	0	0	0
T175	140645	0	0	0
T176	311088	0	0	0
T177	133806	0	0	0
T178	236904	0	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	2022	0	0
T67	2674	8	0	0
T77	6833	71	0	0
T79	12548	20	0	0
T87	11389	177	0	0
T95	3136	25	0	0
T97	4285	15	0	0
T113	2154	4	0	0
T131	21072	252	0	0
T132	3465	77	0	0
T179	3064	13	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	1375	0	0
T67	2674	6	0	0
T77	6833	44	0	0
T79	12548	21	0	0
T87	11389	117	0	0
T95	3136	15	0	0
T97	4285	10	0	0
T113	2154	4	0	0
T129	2367	30	0	0
T131	21072	201	0	0
T132	3465	82	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	1436	0	0
T67	2674	21	0	0
T71	5332	2	0	0
T77	6833	47	0	0
T79	12548	15	0	0
T95	3136	22	0	0
T97	4285	11	0	0
T113	2154	1	0	0
T129	2367	14	0	0
T131	21072	214	0	0
T132	3465	73	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	1542	0	0
T67	2674	25	0	0
T71	5332	9	0	0
T77	6833	63	0	0
T79	12548	42	0	0
T95	3136	44	0	0
T97	4285	11	0	0
T113	2154	1	0	0
T129	2367	27	0	0
T131	21072	219	0	0
T132	3465	91	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	1508	0	0
T67	2674	8	0	0
T77	6833	69	0	0
T79	12548	6	0	0
T87	11389	95	0	0
T95	3136	15	0	0
T97	4285	9	0	0
T113	2154	9	0	0
T131	21072	230	0	0
T132	3465	88	0	0
T179	3064	24	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	1466	0	0
T67	2674	5	0	0
T77	6833	60	0	0
T79	12548	42	0	0
T82	3758	3	0	0
T87	11389	109	0	0
T95	3136	9	0	0
T129	2367	12	0	0
T131	21072	255	0	0
T132	3465	78	0	0
T179	3064	1	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540514081	1362	0	0
T67	2674	7	0	0
T71	5332	3	0	0
T77	6833	75	0	0
T79	12548	10	0	0
T87	11389	116	0	0
T95	3136	32	0	0
T113	2154	8	0	0
T129	2367	19	0	0
T131	21072	193	0	0
T132	3465	72	0	0