Line Coverage for Module :
i2c
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 127 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
67 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
Cond Coverage for Module :
i2c
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 67
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T77,T78,T79 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T77,T78,T79 |
Toggle Coverage for Module :
i2c
| Total | Covered | Percent |
Totals |
45 |
45 |
100.00 |
Total Bits |
370 |
370 |
100.00 |
Total Bits 0->1 |
185 |
185 |
100.00 |
Total Bits 1->0 |
185 |
185 |
100.00 |
| | | |
Ports |
45 |
45 |
100.00 |
Port Bits |
370 |
370 |
100.00 |
Port Bits 0->1 |
185 |
185 |
100.00 |
Port Bits 1->0 |
185 |
185 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T3,T23,T14 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T8,T20,T21 |
Yes |
T8,T20,T21 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T2,T3,T6 |
Yes |
T2,T3,T6 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T3,T6 |
Yes |
T1,T3,T6 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T64,T65,T66 |
Yes |
T64,T65,T66 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T3,T6 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T77,T78,T79 |
Yes |
T77,T78,T79 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T77,T78,T79 |
Yes |
T77,T78,T79 |
OUTPUT |
cio_scl_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T2,T3,T6 |
INPUT |
cio_scl_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_scl_en_o |
Yes |
Yes |
T2,T3,T6 |
Yes |
T1,T2,T3 |
OUTPUT |
cio_sda_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
cio_sda_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_sda_en_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
intr_fmt_threshold_o |
Yes |
Yes |
T3,T16,T11 |
Yes |
T3,T6,T7 |
OUTPUT |
intr_rx_threshold_o |
Yes |
Yes |
T11,T13,T14 |
Yes |
T11,T13,T14 |
OUTPUT |
intr_acq_threshold_o |
Yes |
Yes |
T6,T7,T20 |
Yes |
T6,T7,T20 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T13,T14,T15 |
Yes |
T13,T14,T15 |
OUTPUT |
intr_nak_o |
Yes |
Yes |
T14,T15,T27 |
Yes |
T14,T15,T27 |
OUTPUT |
intr_scl_interference_o |
Yes |
Yes |
T14,T15,T27 |
Yes |
T14,T15,T27 |
OUTPUT |
intr_sda_interference_o |
Yes |
Yes |
T1,T3,T16 |
Yes |
T1,T2,T3 |
OUTPUT |
intr_stretch_timeout_o |
Yes |
Yes |
T3,T16,T11 |
Yes |
T3,T16,T11 |
OUTPUT |
intr_sda_unstable_o |
Yes |
Yes |
T3,T16,T11 |
Yes |
T3,T16,T11 |
OUTPUT |
intr_cmd_complete_o |
Yes |
Yes |
T3,T6,T7 |
Yes |
T3,T6,T7 |
OUTPUT |
intr_tx_stretch_o |
Yes |
Yes |
T6,T7,T8 |
Yes |
T6,T7,T8 |
OUTPUT |
intr_tx_threshold_o |
Yes |
Yes |
T3,T6,T7 |
Yes |
T3,T6,T7 |
OUTPUT |
intr_acq_full_o |
Yes |
Yes |
T22,T43,T23 |
Yes |
T22,T43,T23 |
OUTPUT |
intr_unexp_stop_o |
Yes |
Yes |
T32,T23,T14 |
Yes |
T32,T23,T14 |
OUTPUT |
intr_host_timeout_o |
Yes |
Yes |
T23,T14,T24 |
Yes |
T23,T14,T24 |
OUTPUT |
*Tests covering at least one bit in the range
Assert Coverage for Module :
i2c
Assertion Details
AlertKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
CioSclEnKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
CioSclKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
CioSdaEnKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
CioSdaKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
80 |
0 |
0 |
T70 |
6291 |
20 |
0 |
0 |
T71 |
0 |
20 |
0 |
0 |
T72 |
0 |
10 |
0 |
0 |
T89 |
0 |
20 |
0 |
0 |
T90 |
0 |
10 |
0 |
0 |
T91 |
194708 |
0 |
0 |
0 |
T92 |
245569 |
0 |
0 |
0 |
T93 |
689622 |
0 |
0 |
0 |
T94 |
7565 |
0 |
0 |
0 |
T95 |
127719 |
0 |
0 |
0 |
T96 |
517554 |
0 |
0 |
0 |
T97 |
214066 |
0 |
0 |
0 |
T98 |
16627 |
0 |
0 |
0 |
T99 |
348443 |
0 |
0 |
0 |
IntrAcqFulllwKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrAcqWtmkKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrCommandCompleteKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrFmtWtmkKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrHostTimeoutKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrNakKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrRxOflwKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrRxWtmkKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrSclInterfKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrSdaInterfKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrSdaUnstableKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrStretchTimeoutKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrTxStretchKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrTxWtmkKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
IntrUnexpStopKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
TlAReadyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |
TlDValidKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516278484 |
516110567 |
0 |
0 |
T1 |
7138 |
7062 |
0 |
0 |
T2 |
1021 |
948 |
0 |
0 |
T3 |
199443 |
199298 |
0 |
0 |
T6 |
104488 |
104388 |
0 |
0 |
T7 |
124469 |
124409 |
0 |
0 |
T8 |
116431 |
116369 |
0 |
0 |
T16 |
56807 |
56729 |
0 |
0 |
T20 |
69676 |
69586 |
0 |
0 |
T21 |
31517 |
31443 |
0 |
0 |
T22 |
238457 |
238452 |
0 |
0 |