Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	516868043	10729	0	0
ctrl_rd_A	516868043	727	0	0
host_fifo_config_rd_A	516868043	3749	0	0
host_timeout_ctrl_rd_A	516868043	708	0	0
intr_enable_rd_A	516868043	2150	0	0
ovrd_rd_A	516868043	1663	0	0
target_fifo_config_rd_A	516868043	760	0	0
target_id_rd_A	516868043	879	0	0
timeout_ctrl_rd_A	516868043	742	0	0
timing0_rd_A	516868043	790	0	0
timing1_rd_A	516868043	774	0	0
timing2_rd_A	516868043	721	0	0
timing3_rd_A	516868043	779	0	0
timing4_rd_A	516868043	812	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	10729	0	0
T64	6108	1	0	0
T65	2012	20	0	0
T66	4661	715	0	0
T67	1557	72	0	0
T68	11381	6	0	0
T69	12292	603	0	0
T73	11024	4	0	0
T74	2261	199	0	0
T75	10626	509	0	0
T100	1638	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	727	0	0
T64	6108	62	0	0
T69	12292	33	0	0
T83	9250	4	0	0
T100	1638	15	0	0
T101	6093	99	0	0
T119	2174	11	0	0
T120	3147	1	0	0
T123	4011	14	0	0
T125	7893	7	0	0
T126	2284	24	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	3749	0	0
T44	312654	0	0	0
T47	38727	0	0	0
T127	573489	109	0	0
T128	0	84	0	0
T129	0	150	0	0
T130	0	168	0	0
T131	0	247	0	0
T132	0	193	0	0
T133	0	145	0	0
T134	0	107	0	0
T135	0	143	0	0
T136	0	123	0	0
T137	236772	0	0	0
T138	122593	0	0	0
T139	841	0	0	0
T140	161111	0	0	0
T141	164779	0	0	0
T142	1306	0	0	0
T143	26622	0	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	708	0	0
T64	6108	33	0	0
T69	12292	26	0	0
T83	9250	5	0	0
T100	1638	3	0	0
T101	6093	60	0	0
T119	2174	8	0	0
T120	3147	1	0	0
T123	4011	42	0	0
T125	7893	17	0	0
T126	2284	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	2150	0	0
T27	868026	7	0	0
T37	0	8	0	0
T64	0	272	0	0
T69	0	14	0	0
T100	0	10	0	0
T119	0	60	0	0
T144	0	21	0	0
T145	0	39	0	0
T146	0	17	0	0
T147	0	7	0	0
T148	2616	0	0	0
T149	51453	0	0	0
T150	612176	0	0	0
T151	256610	0	0	0
T152	199756	0	0	0
T153	600483	0	0	0
T154	1525	0	0	0
T155	112896	0	0	0
T156	157844	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	1663	0	0
T4	1107	5	0	0
T5	1154	0	0	0
T154	0	36	0	0
T157	0	52	0	0
T158	0	67	0	0
T159	0	70	0	0
T160	0	61	0	0
T161	0	39	0	0
T162	0	53	0	0
T163	0	69	0	0
T164	0	34	0	0
T165	7962	0	0	0
T166	711336	0	0	0
T167	935822	0	0	0
T168	157602	0	0	0
T169	62413	0	0	0
T170	250619	0	0	0
T171	173313	0	0	0
T172	206654	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	760	0	0
T64	6108	44	0	0
T69	12292	11	0	0
T83	9250	6	0	0
T100	1638	15	0	0
T101	6093	90	0	0
T119	2174	2	0	0
T120	3147	5	0	0
T123	4011	4	0	0
T125	7893	9	0	0
T126	2284	8	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	879	0	0
T64	6108	101	0	0
T69	12292	17	0	0
T83	9250	7	0	0
T100	1638	3	0	0
T101	6093	79	0	0
T119	2174	14	0	0
T120	3147	18	0	0
T123	4011	25	0	0
T125	7893	19	0	0
T126	2284	45	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	742	0	0
T64	6108	35	0	0
T69	12292	21	0	0
T83	9250	12	0	0
T100	1638	9	0	0
T101	6093	69	0	0
T119	2174	19	0	0
T120	3147	8	0	0
T123	4011	39	0	0
T125	7893	1	0	0
T126	2284	20	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	790	0	0
T64	6108	37	0	0
T69	12292	21	0	0
T83	9250	6	0	0
T100	1638	10	0	0
T101	6093	36	0	0
T119	2174	9	0	0
T120	3147	39	0	0
T123	4011	20	0	0
T125	7893	4	0	0
T126	2284	17	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	774	0	0
T64	6108	50	0	0
T69	12292	9	0	0
T83	9250	5	0	0
T100	1638	7	0	0
T101	6093	59	0	0
T119	2174	3	0	0
T120	3147	46	0	0
T123	4011	5	0	0
T125	7893	9	0	0
T126	2284	20	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	721	0	0
T64	6108	73	0	0
T69	12292	1	0	0
T100	1638	11	0	0
T101	6093	63	0	0
T119	2174	14	0	0
T120	3147	14	0	0
T123	4011	28	0	0
T125	7893	7	0	0
T126	2284	16	0	0
T173	24515	227	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	779	0	0
T64	6108	40	0	0
T69	12292	41	0	0
T100	1638	2	0	0
T101	6093	73	0	0
T119	2174	2	0	0
T120	3147	21	0	0
T123	4011	16	0	0
T125	7893	5	0	0
T126	2284	20	0	0
T173	24515	213	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516868043	812	0	0
T64	6108	52	0	0
T69	12292	20	0	0
T83	9250	14	0	0
T100	1638	7	0	0
T101	6093	43	0	0
T119	2174	15	0	0
T120	3147	28	0	0
T123	4011	34	0	0
T125	7893	2	0	0
T126	2284	8	0	0