Module Definition
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Module : i2c_target_fsm
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core.u_i2c_target_fsm 0.00 0.00 0.00 0.00 0.00



Module Instance : tb.dut.i2c_core.u_i2c_target_fsm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_target_fsm
Line No.TotalCoveredPercent
TOTAL36300.00
ALWAYS133800.00
ALWAYS147300.00
ALWAYS160700.00
ALWAYS175500.00
ALWAYS186500.00
CONT_ASSIGN196100.00
CONT_ASSIGN197100.00
CONT_ASSIGN198100.00
CONT_ASSIGN199100.00
ALWAYS203300.00
ALWAYS212500.00
ALWAYS223700.00
ALWAYS247600.00
ALWAYS257600.00
ALWAYS267600.00
CONT_ASSIGN277100.00
CONT_ASSIGN278100.00
CONT_ASSIGN281100.00
CONT_ASSIGN282100.00
CONT_ASSIGN285100.00
ALWAYS289900.00
CONT_ASSIGN304100.00
CONT_ASSIGN305100.00
CONT_ASSIGN306100.00
ALWAYS310700.00
ALWAYS321500.00
CONT_ASSIGN338100.00
CONT_ASSIGN341100.00
CONT_ASSIGN342100.00
ALWAYS373400.00
CONT_ASSIGN390100.00
CONT_ASSIGN394100.00
CONT_ASSIGN397100.00
ALWAYS40112600.00
CONT_ASSIGN693100.00
CONT_ASSIGN694100.00
CONT_ASSIGN698100.00
CONT_ASSIGN707100.00
CONT_ASSIGN712100.00
ALWAYS71611700.00
CONT_ASSIGN1048100.00
ALWAYS1052300.00
ALWAYS1061300.00
CONT_ASSIGN1068100.00
CONT_ASSIGN1069100.00
CONT_ASSIGN1072100.00
CONT_ASSIGN1075100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
133 0 1
134 0 1
135 0 1
136 0 1
137 0 1
138 0 1
141 0 1
142 0 1
==> MISSING_ELSE
147 0 1
148 0 1
150 0 1
160 0 1
161 0 1
162 0 1
164 0 1
165 0 1
166 0 1
168 0 1
175 0 1
176 0 1
177 0 1
178 0 1
180 0 1
186 0 1
187 0 1
188 0 1
190 0 1
192 0 1
196 0 1
197 0 1
198 0 1
199 0 1
203 0 1
204 0 1
206 0 1
212 0 1
213 0 1
214 0 1
216 0 1
217 0 1
223 0 1
224 0 1
225 0 1
226 0 1
228 0 1
229 0 1
230 0 1
247 0 1
248 0 1
249 0 1
250 0 1
251 0 1
252 0 1
==> MISSING_ELSE
257 0 1
258 0 1
259 0 1
260 0 1
261 0 1
262 0 1
==> MISSING_ELSE
267 0 1
268 0 1
269 0 1
270 0 1
271 0 1
272 0 1
==> MISSING_ELSE
277 0 1
278 0 1
281 0 1
282 0 1
285 0 1
289 0 1
290 0 1
291 0 1
292 0 1
293 0 1
296 0 2
297 0 1
299 0 1
304 0 1
305 0 1
306 0 1
310 0 1
311 0 1
312 0 1
313 0 1
314 0 1
315 0 2
==> MISSING_ELSE
==> MISSING_ELSE
321 0 1
322 0 1
323 0 1
324 0 2
==> MISSING_ELSE
==> MISSING_ELSE
338 0 1
341 0 1
342 0 1
373 0 1
374 0 1
375 0 1
376 0 1
==> MISSING_ELSE
390 0 1
394 0 1
397 0 1
401 0 1
402 0 1
403 0 1
404 0 1
405 0 1
406 0 1
407 0 1
408 0 1
409 0 1
410 0 1
411 0 1
412 0 1
413 0 1
414 0 1
415 0 1
416 0 1
418 0 1
423 0 1
424 0 1
425 0 1
426 0 1
427 0 1
428 0 1
437 0 1
438 0 1
439 0 1
443 0 1
444 0 1
446 0 1
447 0 1
448 0 1
449 0 1
==> MISSING_ELSE
==> MISSING_ELSE
455 0 1
457 0 1
460 0 1
==> MISSING_ELSE
465 0 1
466 0 1
470 0 1
471 0 1
475 0 1
476 0 1
479 0 1
480 0 1
484 0 1
486 0 1
==> MISSING_ELSE
489 0 1
490 0 1
492 0 1
==> MISSING_ELSE
498 0 1
502 0 1
503 0 1
507 0 1
510 0 1
514 0 1
517 0 1
521 0 1
524 0 1
525 0 1
527 0 1
==> MISSING_ELSE
532 0 1
533 0 1
534 0 1
538 0 1
542 0 1
543 0 1
546 0 1
==> MISSING_ELSE
551 0 1
552 0 1
556 0 1
557 0 1
561 0 1
562 0 1
564 0 1
565 0 1
566 0 1
567 0 1
==> MISSING_ELSE
573 0 1
574 0 1
575 0 1
577 0 1
578 0 1
582 0 1
583 0 1
==> MISSING_ELSE
589 0 1
590 0 1
591 0 1
596 0 1
597 0 1
598 0 1
600 0 1
601 0 1
605 0 1
606 0 1
607 0 1
608 0 1
609 0 1
610 0 1
612 0 1
==> MISSING_ELSE
618 0 1
619 0 1
620 0 1
622 0 1
626 0 1
==> MISSING_ELSE
631 0 1
632 0 1
633 0 1
637 0 1
638 0 1
639 0 1
640 0 1
643 0 1
644 0 1
645 0 1
646 0 1
==> MISSING_ELSE
652 0 1
653 0 1
654 0 1
675 0 1
676 0 1
681 0 1
682 0 1
683 0 1
685 0 1
687 0 1
688 0 1
689 0 1
==> MISSING_ELSE
693 0 1
694 0 1
698 0 1
707 0 1
712 0 1
716 0 1
717 0 1
718 0 1
719 0 1
720 0 1
722 0 1
734 0 1
735 0 1
736 0 1
==> MISSING_ELSE
743 0 1
744 0 1
745 0 1
747 0 1
748 0 1
751 0 1
==> MISSING_ELSE
757 0 1
759 0 1
760 0 1
761 0 1
763 0 1
765 0 1
772 0 1
773 0 1
776 0 1
780 0 1
==> MISSING_ELSE
787 0 2
==> MISSING_ELSE
791 0 1
792 0 1
793 0 1
794 0 1
==> MISSING_ELSE
799 0 1
805 0 1
811 0 1
812 0 1
818 0 1
819 0 1
821 0 1
824 0 1
==> MISSING_ELSE
830 0 1
831 0 1
833 0 1
838 0 2
==> MISSING_ELSE
842 0 1
843 0 1
844 0 1
845 0 1
==> MISSING_ELSE
850 0 1
851 0 1
852 0 1
854 0 1
855 0 1
856 0 1
==> MISSING_ELSE
862 0 1
863 0 1
==> MISSING_ELSE
869 0 1
871 0 1
872 0 1
875 0 1
==> MISSING_ELSE
883 0 1
887 0 1
888 0 1
889 0 1
890 0 1
==> MISSING_ELSE
895 0 1
897 0 1
898 0 1
899 0 1
900 0 1
901 0 1
905 0 1
907 0 1
==> MISSING_ELSE
913 0 2
==> MISSING_ELSE
917 0 1
918 0 1
919 0 1
920 0 1
==> MISSING_ELSE
925 0 1
926 0 1
==> MISSING_ELSE
934 0 1
935 0 1
936 0 1
937 0 1
938 0 1
939 0 1
==> MISSING_ELSE
945 0 1
946 0 1
==> MISSING_ELSE
954 0 1
955 0 1
956 0 1
962 0 1
==> MISSING_ELSE
968 0 1
969 0 1
970 0 1
971 0 1
978 0 1
979 0 1
980 0 1
983 0 1
==> MISSING_ELSE
988 0 1
989 0 1
==> MISSING_ELSE
1000 0 1
1001 0 1
1002 0 1
1003 0 1
1004 0 1
1005 0 1
==> MISSING_ELSE
1011 0 1
1012 0 1
==> MISSING_ELSE
1028 0 1
1037 0 1
1038 0 1
1039 0 1
1040 0 1
1041 0 1
==> MISSING_ELSE
1048 0 1
1052 0 1
1053 0 1
1055 0 1
1061 0 1
1062 0 1
1064 0 1
1068 0 1
1069 0 1
1072 0 1
1075 0 1


Cond Coverage for Module : i2c_target_fsm
TotalCoveredPercent
Conditions14800.00
Logical14800.00
Non-Logical00
Event00

 LINE       162
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       165
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       188
 EXPRESSION (auto_ack_load_i && ack_ctrl_stretching)
             -------1-------    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       196
 EXPRESSION (((!ack_ctrl_mode_i)) || (auto_ack_cnt_q > '0))
             ----------1---------    ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       249
 EXPRESSION (start_det_trigger || stop_det_trigger)
             --------1--------    --------2-------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       251
 EXPRESSION (start_det_pending || stop_det_pending)
             --------1--------    --------2-------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       261
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || start_det || stop_det_trigger)
             ----------1---------    -----2----    ----3----    --------4-------
-1--2--3--4-StatusTests
0000Not Covered
0001Not Covered
0010Not Covered
0100Not Covered
1000Not Covered

 LINE       271
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || stop_det || start_det_trigger)
             ----------1---------    -----2----    ----3---    --------4--------
-1--2--3--4-StatusTests
0000Not Covered
0001Not Covered
0010Not Covered
0100Not Covered
1000Not Covered

 LINE       277
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       277
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       277
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       277
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       278
 EXPRESSION (target_enable_i && start_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2--------    --------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       281
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       281
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       281
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       281
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       282
 EXPRESSION (target_enable_i && stop_det_pending && (ctrl_det_count >= thd_dat_i))
             -------1-------    --------2-------    --------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       285
 EXPRESSION (bit_idx == 4'd8)
            --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       293
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       296
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       304
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       305
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       306
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       314
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       323
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       375
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       394
 EXPRESSION (xfer_for_us_q & rw_bit_q & stop_det & ((!expect_stop)))
             ------1------   ----2---   ----3---   --------4-------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       397
 EXPRESSION (((!nack_transaction_q)) && nack_transaction_d)
             -----------1-----------    ---------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       479
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       564
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       643
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       643
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       693
 EXPRESSION (((!acq_fifo_plenty_space)) || ((!can_auto_ack)))
             -------------1------------    --------2--------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       698
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       707
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       760
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       799
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       850
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       898
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       925
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       945
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       962
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---
-1-StatusTests
0Not Covered
1Not Covered

 LINE       988
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       1000
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       1000
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1011
 EXPRESSION (tcount_q == 20'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       1028
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1048
 EXPRESSION (target_enable_i && ((!target_idle)) && (stop_det | start_det))
             -------1-------    --------2-------    -----------3----------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       1048
 SUB-EXPRESSION (stop_det | start_det)
                 ----1---   ----2----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       1072
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

FSM Coverage for Module : i2c_target_fsm
Summary for FSM :: state_q
TotalCoveredPercent
States 26 0 0.00 (Not included in score)
Transitions 90 0 0.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AcquireAckHold 918 Not Covered
AcquireAckPulse 913 Not Covered
AcquireAckSetup 907 Not Covered
AcquireAckWait 888 Not Covered
AcquireByte 824 Not Covered
AcquireStart 1039 Not Covered
AddrAckHold 792 Not Covered
AddrAckPulse 787 Not Covered
AddrAckSetup 763 Not Covered
AddrAckWait 745 Not Covered
AddrRead 735 Not Covered
Idle 1037 Not Covered
StretchAcqFull 905 Not Covered
StretchAcqSetup 1003 Not Covered
StretchAddr 818 Not Covered
StretchAddrAck 776 Not Covered
StretchAddrAckSetup 937 Not Covered
StretchTx 831 Not Covered
StretchTxSetup 978 Not Covered
TransmitAck 852 Not Covered
TransmitAckPulse 863 Not Covered
TransmitHold 843 Not Covered
TransmitPulse 838 Not Covered
TransmitSetup 833 Not Covered
TransmitWait 821 Not Covered
WaitForStop 751 Not Covered


transitionsLine No.CoveredTests
AcquireAckHold->AcquireByte 926 Not Covered
AcquireAckHold->AcquireStart 1039 Not Covered
AcquireAckHold->Idle 1037 Not Covered
AcquireAckPulse->AcquireAckHold 918 Not Covered
AcquireAckPulse->AcquireStart 1039 Not Covered
AcquireAckPulse->Idle 1037 Not Covered
AcquireAckSetup->AcquireAckPulse 913 Not Covered
AcquireAckSetup->AcquireStart 1039 Not Covered
AcquireAckSetup->Idle 1037 Not Covered
AcquireAckWait->AcquireAckSetup 907 Not Covered
AcquireAckWait->AcquireStart 1039 Not Covered
AcquireAckWait->Idle 1037 Not Covered
AcquireAckWait->StretchAcqFull 905 Not Covered
AcquireAckWait->WaitForStop 897 Not Covered
AcquireByte->AcquireAckWait 888 Not Covered
AcquireByte->AcquireStart 1039 Not Covered
AcquireByte->Idle 1037 Not Covered
AcquireStart->AddrRead 735 Not Covered
AcquireStart->Idle 1037 Not Covered
AddrAckHold->AcquireByte 824 Not Covered
AddrAckHold->AcquireStart 1039 Not Covered
AddrAckHold->Idle 1037 Not Covered
AddrAckHold->StretchAddr 818 Not Covered
AddrAckHold->TransmitWait 821 Not Covered
AddrAckHold->WaitForStop 811 Not Covered
AddrAckPulse->AcquireStart 1039 Not Covered
AddrAckPulse->AddrAckHold 792 Not Covered
AddrAckPulse->Idle 1037 Not Covered
AddrAckSetup->AcquireStart 1039 Not Covered
AddrAckSetup->AddrAckPulse 787 Not Covered
AddrAckSetup->Idle 1037 Not Covered
AddrAckWait->AcquireStart 1039 Not Covered
AddrAckWait->AddrAckSetup 763 Not Covered
AddrAckWait->Idle 1037 Not Covered
AddrAckWait->StretchAddrAck 776 Not Covered
AddrAckWait->WaitForStop 759 Not Covered
AddrRead->AcquireStart 1039 Not Covered
AddrRead->AddrAckWait 745 Not Covered
AddrRead->Idle 1037 Not Covered
AddrRead->WaitForStop 751 Not Covered
Idle->AcquireStart 1039 Not Covered
StretchAcqFull->AcquireStart 1039 Not Covered
StretchAcqFull->Idle 1037 Not Covered
StretchAcqFull->StretchAcqSetup 1003 Not Covered
StretchAcqFull->WaitForStop 1001 Not Covered
StretchAcqSetup->AcquireAckSetup 1012 Not Covered
StretchAcqSetup->AcquireStart 1039 Not Covered
StretchAcqSetup->Idle 1037 Not Covered
StretchAddr->AcquireByte 962 Not Covered
StretchAddr->AcquireStart 1039 Not Covered
StretchAddr->Idle 1037 Not Covered
StretchAddr->StretchTx 962 Not Covered
StretchAddr->WaitForStop 955 Not Covered
StretchAddrAck->AcquireStart 1039 Not Covered
StretchAddrAck->Idle 1037 Not Covered
StretchAddrAck->StretchAddrAckSetup 937 Not Covered
StretchAddrAck->WaitForStop 935 Not Covered
StretchAddrAckSetup->AcquireStart 1039 Not Covered
StretchAddrAckSetup->AddrAckSetup 946 Not Covered
StretchAddrAckSetup->Idle 1037 Not Covered
StretchTx->AcquireStart 1039 Not Covered
StretchTx->Idle 1037 Not Covered
StretchTx->StretchTxSetup 978 Not Covered
StretchTx->WaitForStop 970 Not Covered
StretchTxSetup->AcquireStart 1039 Not Covered
StretchTxSetup->Idle 1037 Not Covered
StretchTxSetup->TransmitSetup 989 Not Covered
TransmitAck->AcquireStart 1039 Not Covered
TransmitAck->Idle 1037 Not Covered
TransmitAck->TransmitAckPulse 863 Not Covered
TransmitAckPulse->AcquireStart 1039 Not Covered
TransmitAckPulse->Idle 1037 Not Covered
TransmitAckPulse->TransmitWait 872 Not Covered
TransmitAckPulse->WaitForStop 875 Not Covered
TransmitHold->AcquireStart 1039 Not Covered
TransmitHold->Idle 1037 Not Covered
TransmitHold->TransmitAck 852 Not Covered
TransmitHold->TransmitSetup 856 Not Covered
TransmitPulse->AcquireStart 1039 Not Covered
TransmitPulse->Idle 1037 Not Covered
TransmitPulse->TransmitHold 843 Not Covered
TransmitSetup->AcquireStart 1039 Not Covered
TransmitSetup->Idle 1037 Not Covered
TransmitSetup->TransmitPulse 838 Not Covered
TransmitWait->AcquireStart 1039 Not Covered
TransmitWait->Idle 1037 Not Covered
TransmitWait->StretchTx 831 Not Covered
TransmitWait->TransmitSetup 833 Not Covered
WaitForStop->AcquireStart 1039 Not Covered
WaitForStop->Idle 1037 Not Covered



Branch Coverage for Module : i2c_target_fsm
Line No.TotalCoveredPercent
Branches 178 0 0.00
IF 134 6 0 0.00
IF 147 2 0 0.00
IF 160 4 0 0.00
IF 175 3 0 0.00
IF 186 3 0 0.00
IF 203 2 0 0.00
IF 212 2 0 0.00
IF 223 2 0 0.00
IF 247 4 0 0.00
IF 257 4 0 0.00
IF 267 4 0 0.00
IF 289 5 0 0.00
IF 310 5 0 0.00
IF 321 4 0 0.00
IF 373 3 0 0.00
CASE 418 44 0 0.00
IF 675 4 0 0.00
CASE 722 69 0 0.00
IF 1028 4 0 0.00
IF 1052 2 0 0.00
IF 1061 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 134 if (load_tcount) -2-: 135 case (tcount_sel) -3-: 141 if (target_enable_i)

Branches:
-1--2--3-StatusTests
1 tSetupData - Not Covered
1 tHoldData - Not Covered
1 tNoDelay - Not Covered
1 default - Not Covered
0 - 1 Not Covered
0 - 0 Not Covered


LineNo. Expression -1-: 147 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 160 if ((!rst_ni)) -2-: 162 if (((!target_idle_o) && event_host_timeout_o)) -3-: 165 if (((!target_idle_o) && scl_i))

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Not Covered


LineNo. Expression -1-: 175 if ((!rst_ni)) -2-: 177 if (actively_stretching)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 186 if ((!rst_ni)) -2-: 188 if ((auto_ack_load_i && ack_ctrl_stretching))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 203 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 212 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 223 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 247 if ((!rst_ni)) -2-: 249 if ((start_det_trigger || stop_det_trigger)) -3-: 251 if ((start_det_pending || stop_det_pending))

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Not Covered


LineNo. Expression -1-: 257 if ((!rst_ni)) -2-: 259 if (start_det_trigger) -3-: 261 if (((((!target_enable_i) || (!scl_i)) || start_det) || stop_det_trigger))

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Not Covered


LineNo. Expression -1-: 267 if ((!rst_ni)) -2-: 269 if (stop_det_trigger) -3-: 271 if (((((!target_enable_i) || (!scl_i)) || stop_det) || start_det_trigger))

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Not Covered


LineNo. Expression -1-: 289 if ((!rst_ni)) -2-: 291 if (start_det) -3-: 293 if ((scl_i_q && (!scl_i))) -4-: 296 if ((input_byte_clr || bit_ack))

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Not Covered


LineNo. Expression -1-: 310 if ((!rst_ni)) -2-: 312 if (input_byte_clr) -3-: 314 if (((!scl_i_q) && scl_i)) -4-: 315 if ((!bit_ack))

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Not Covered


LineNo. Expression -1-: 321 if ((!rst_ni)) -2-: 323 if (((!scl_i_q) && scl_i)) -3-: 324 if (bit_ack)

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Not Covered


LineNo. Expression -1-: 373 if ((!rst_ni)) -2-: 375 if ((bit_ack && address_match))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 418 case (state_q) -2-: 446 if (bit_ack) -3-: 447 if (address_match) -4-: 457 if (scl_i) -5-: 479 if ((tcount_q == 20'b1)) -6-: 480 if (nack_transaction_q) -7-: 484 if ((!stretch_addr)) -8-: 489 if (restart_det_q) -9-: 525 if ((!scl_i)) -10-: 543 if (scl_i) -11-: 564 if ((tcount_q == 20'b1)) -12-: 577 if (nack_timeout) -13-: 600 if (nack_timeout) -14-: 607 if ((!stretch_addr)) -15-: 609 if (restart_det_q) -16-: 622 if (nack_timeout) -17-: 643 if ((nack_timeout || (sw_nack_i && (!can_auto_ack))))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17-StatusTests
Idle - - - - - - - - - - - - - - - - Not Covered
AcquireStart - - - - - - - - - - - - - - - - Not Covered
AddrRead 1 1 - - - - - - - - - - - - - - Not Covered
AddrRead 1 0 - - - - - - - - - - - - - - Not Covered
AddrRead 0 - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - 1 - - - - - - - - - - - - - Not Covered
AddrAckWait - - 0 - - - - - - - - - - - - - Not Covered
AddrAckSetup - - - - - - - - - - - - - - - - Not Covered
AddrAckPulse - - - - - - - - - - - - - - - - Not Covered
AddrAckHold - - - 1 1 - - - - - - - - - - - Not Covered
AddrAckHold - - - 1 0 1 - - - - - - - - - - Not Covered
AddrAckHold - - - 1 0 0 - - - - - - - - - - Not Covered
AddrAckHold - - - 1 - - 1 - - - - - - - - - Not Covered
AddrAckHold - - - 1 - - 0 - - - - - - - - - Not Covered
AddrAckHold - - - 0 - - - - - - - - - - - - Not Covered
TransmitWait - - - - - - - - - - - - - - - - Not Covered
TransmitSetup - - - - - - - - - - - - - - - - Not Covered
TransmitPulse - - - - - - - - - - - - - - - - Not Covered
TransmitHold - - - - - - - - - - - - - - - - Not Covered
TransmitAck - - - - - - - - - - - - - - - - Not Covered
TransmitAckPulse - - - - - - - 1 - - - - - - - - Not Covered
TransmitAckPulse - - - - - - - 0 - - - - - - - - Not Covered
WaitForStop - - - - - - - - - - - - - - - - Not Covered
AcquireByte - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - 1 - - - - - - - Not Covered
AcquireAckWait - - - - - - - - 0 - - - - - - - Not Covered
AcquireAckSetup - - - - - - - - - - - - - - - - Not Covered
AcquireAckPulse - - - - - - - - - - - - - - - - Not Covered
AcquireAckHold - - - - - - - - - 1 - - - - - - Not Covered
AcquireAckHold - - - - - - - - - 0 - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - 1 - - - - - Not Covered
StretchAddrAck - - - - - - - - - - 0 - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - 1 - - - - Not Covered
StretchAddr - - - - - - - - - - - 0 1 1 - - Not Covered
StretchAddr - - - - - - - - - - - 0 1 0 - - Not Covered
StretchAddr - - - - - - - - - - - 0 0 - - - Not Covered
StretchTx - - - - - - - - - - - - - - 1 - Not Covered
StretchTx - - - - - - - - - - - - - - 0 - Not Covered
StretchTxSetup - - - - - - - - - - - - - - - - Not Covered
StretchAcqFull - - - - - - - - - - - - - - - 1 Not Covered
StretchAcqFull - - - - - - - - - - - - - - - 0 Not Covered
StretchAcqSetup - - - - - - - - - - - - - - - - Not Covered
default - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 675 if (stop_det) -2-: 682 if (nack_transaction_q) -3-: 687 if (start_det)

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 - Not Covered
0 - 1 Not Covered
0 - 0 Not Covered


LineNo. Expression -1-: 722 case (state_q) -2-: 734 if ((!scl_i)) -3-: 743 if (bit_ack) -4-: 744 if (address_match) -5-: 757 if (scl_i) -6-: 760 if ((tcount_q == 20'b1)) -7-: 761 if ((!nack_addr_after_timeout_i)) -8-: 765 if (nack_transaction_q) -9-: 773 if (stretch_addr) -10-: 787 if (scl_i) -11-: 791 if ((!scl_i)) -12-: 799 if ((tcount_q == 20'b1)) -13-: 805 if (nack_transaction_q) -14-: 812 if (stretch_addr) -15-: 819 if (rw_bit_q) -16-: 830 if (stretch_tx) -17-: 838 if (scl_i) -18-: 842 if ((!scl_i)) -19-: 850 if ((tcount_q == 20'b1)) -20-: 851 if (bit_ack) -21-: 862 if (scl_i) -22-: 869 if ((!scl_i)) -23-: 871 if (host_ack) -24-: 887 if (bit_ack) -25-: 895 if (scl_i) -26-: 898 if ((tcount_q == 20'b1)) -27-: 899 if (nack_transaction_q) -28-: 901 if (stretch_rx) -29-: 913 if (scl_i) -30-: 917 if ((!scl_i)) -31-: 925 if ((tcount_q == 20'b1)) -32-: 934 if (nack_timeout) -33-: 936 if ((!stretch_addr)) -34-: 945 if ((tcount_q == 20'b1)) -35-: 954 if (nack_timeout) -36-: 956 if ((!stretch_addr)) -37-: 962 (rw_bit_q) ? -38-: 969 if (nack_timeout) -39-: 971 if ((!stretch_tx)) -40-: 988 if ((tcount_q == 20'b1)) -41-: 1000 if ((nack_timeout || (sw_nack_i && (!can_auto_ack)))) -42-: 1002 if ((~stretch_rx)) -43-: 1011 if ((tcount_q == 20'b1))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28--29--30--31--32--33--34--35--36--37--38--39--40--41--42--43-StatusTests
Idle - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AcquireStart 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AcquireStart 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrRead - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrRead - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrRead - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckSetup - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckSetup - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckPulse - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckPulse - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckHold - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckHold - - - - - - - - - - 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckHold - - - - - - - - - - 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckHold - - - - - - - - - - 1 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckHold - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitWait - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitWait - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitSetup - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitSetup - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitPulse - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitPulse - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitHold - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitHold - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitHold - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitAck - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitAck - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - Not Covered
WaitForStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AcquireByte - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - Not Covered
AcquireByte - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 1 - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 1 - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 0 - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - - - - - - - - - - - Not Covered
AcquireAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - Not Covered
AcquireAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - Not Covered
AcquireAckPulse - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - Not Covered
AcquireAckPulse - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - Not Covered
AcquireAckHold - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - Not Covered
AcquireAckHold - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 1 - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - Not Covered
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - Not Covered
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - Not Covered
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - Not Covered
StretchTxSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - Not Covered
StretchTxSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Not Covered
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - Not Covered
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - Not Covered
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - Not Covered
StretchAcqSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Not Covered
StretchAcqSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Not Covered
default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 1028 if (((!target_idle) && (!target_enable_i))) -2-: 1038 if (start_det) -3-: 1040 if (stop_det)

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Not Covered


LineNo. Expression -1-: 1052 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 1061 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%