Unified Coverage Report :: Module :: i2c_core

Module : i2c_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.i2c_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.62	0.00	0.00	94.87				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
intr_hw_acq_overflow	0.00	0.00	0.00			0.00
intr_hw_acq_threshold	0.00	0.00	0.00			0.00
intr_hw_cmd_complete	0.00	0.00	0.00			0.00
intr_hw_controller_halt	0.00	0.00	0.00			0.00
intr_hw_fmt_threshold	0.00	0.00	0.00			0.00
intr_hw_host_timeout	0.00	0.00	0.00			0.00
intr_hw_rx_overflow	0.00	0.00	0.00			0.00
intr_hw_rx_threshold	0.00	0.00	0.00			0.00
intr_hw_scl_interference	0.00	0.00	0.00			0.00
intr_hw_sda_interference	0.00	0.00	0.00			0.00
intr_hw_sda_unstable	0.00	0.00	0.00			0.00
intr_hw_stretch_timeout	0.00	0.00	0.00			0.00
intr_hw_tx_stretch	0.00	0.00	0.00			0.00
intr_hw_tx_threshold	0.00	0.00	0.00			0.00
intr_hw_unexp_stop	0.00	0.00	0.00			0.00
u_fifos	0.00	0.00	0.00			0.00
u_i2c_controller_fsm	0.00	0.00	0.00		0.00	0.00
u_i2c_sync_scl	0.00	0.00				0.00
u_i2c_sync_sda	0.00	0.00				0.00
u_i2c_target_fsm	0.00	0.00	0.00		0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
TOTAL		109	0	0.00
CONT_ASSIGN	182	1	0	0.00
CONT_ASSIGN	183	1	0	0.00
CONT_ASSIGN	184	1	0	0.00
CONT_ASSIGN	185	1	0	0.00
CONT_ASSIGN	186	1	0	0.00
CONT_ASSIGN	187	1	0	0.00
CONT_ASSIGN	188	1	0	0.00
CONT_ASSIGN	190	1	0	0.00
CONT_ASSIGN	191	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	193	1	0	0.00
CONT_ASSIGN	194	1	0	0.00
CONT_ASSIGN	196	1	0	0.00
CONT_ASSIGN	197	1	0	0.00
CONT_ASSIGN	198	1	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
CONT_ASSIGN	202	1	0	0.00
CONT_ASSIGN	203	1	0	0.00
CONT_ASSIGN	207	1	0	0.00
CONT_ASSIGN	208	1	0	0.00
CONT_ASSIGN	210	1	0	0.00
CONT_ASSIGN	212	1	0	0.00
CONT_ASSIGN	213	1	0	0.00
CONT_ASSIGN	215	1	0	0.00
CONT_ASSIGN	216	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	219	1	0	0.00
CONT_ASSIGN	223	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	226	1	0	0.00
CONT_ASSIGN	227	1	0	0.00
CONT_ASSIGN	228	1	0	0.00
ALWAYS	232	5	0	0.00
ALWAYS	244	5	0	0.00
CONT_ASSIGN	253	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	255	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
CONT_ASSIGN	257	1	0	0.00
CONT_ASSIGN	258	1	0	0.00
CONT_ASSIGN	259	1	0	0.00
CONT_ASSIGN	260	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	267	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	269	1	0	0.00
CONT_ASSIGN	270	1	0	0.00
CONT_ASSIGN	273	1	0	0.00
CONT_ASSIGN	274	1	0	0.00
CONT_ASSIGN	275	1	0	0.00
CONT_ASSIGN	276	1	0	0.00
CONT_ASSIGN	278	1	0	0.00
CONT_ASSIGN	280	1	0	0.00
CONT_ASSIGN	281	1	0	0.00
CONT_ASSIGN	282	1	0	0.00
CONT_ASSIGN	285	1	0	0.00
CONT_ASSIGN	287	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	291	1	0	0.00
CONT_ASSIGN	293	1	0	0.00
CONT_ASSIGN	294	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	305	1	0	0.00
CONT_ASSIGN	306	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	310	1	0	0.00
CONT_ASSIGN	312	1	0	0.00
CONT_ASSIGN	313	1	0	0.00
CONT_ASSIGN	314	1	0	0.00
CONT_ASSIGN	315	1	0	0.00
CONT_ASSIGN	316	1	0	0.00
CONT_ASSIGN	317	1	0	0.00
CONT_ASSIGN	326	1	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	329	1	0	0.00
CONT_ASSIGN	330	1	0	0.00
CONT_ASSIGN	331	1	0	0.00
CONT_ASSIGN	332	1	0	0.00
CONT_ASSIGN	333	1	0	0.00
CONT_ASSIGN	334	1	0	0.00
CONT_ASSIGN	335	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	337	1	0	0.00
CONT_ASSIGN	381	1	0	0.00
CONT_ASSIGN	386	1	0	0.00
CONT_ASSIGN	388	1	0	0.00
CONT_ASSIGN	391	1	0	0.00
CONT_ASSIGN	392	1	0	0.00
CONT_ASSIGN	397	1	0	0.00
CONT_ASSIGN	743	1	0	0.00
CONT_ASSIGN	745	1	0	0.00
CONT_ASSIGN	746	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
190	0	1
191	0	1
192	0	1
193	0	1
194	0	1
196	0	1
197	0	1
198	0	1
199	0	1
200	0	1
201	0	1
202	0	1
203	0	1
207	0	1
208	0	1
210	0	1
212	0	1
213	0	1
215	0	1
216	0	1
217	0	1
219	0	1
223	0	1
225	0	1
226	0	1
227	0	1
228	0	1
232	0	1
233	0	1
234	0	1
237	0	1
238	0	1
244	0	1
245	0	1
246	0	1
248	0	1
249	0	1
253	0	1
254	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
260	0	1
261	0	1
262	0	1
263	0	1
264	0	1
265	0	1
266	0	1
267	0	1
268	0	1
269	0	1
270	0	1
273	0	1
274	0	1
275	0	1
276	0	1
278	0	1
280	0	1
281	0	1
282	0	1
285	0	1
287	0	1
289	0	1
291	0	1
293	0	1
294	0	1
299	0	1
305	0	1
306	0	1
307	0	1
308	0	1
309	0	1
310	0	1
312	0	1
313	0	1
314	0	1
315	0	1
316	0	1
317	0	1
326	0	1
328	0	1
329	0	1
330	0	1
331	0	1
332	0	1
333	0	1
334	0	1
335	0	1
336	0	1
337	0	1
381	0	1
386	0	1
388	0	1
391	0	1
392	0	1
397	0	1
743	0	1
745	0	1
746	0	1

---

Cond Coverage for Module : i2c_core

	Total	Covered	Percent
Conditions	91	0	0.00
Logical	91	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       207
 EXPRESSION (event_target_nack && (reg2hw.target_nack_count.q < 8'hff))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       212
 EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       213
 EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       219
 EXPRESSION (event_controller_cmd_complete | event_target_cmd_complete)
             --------------1--------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       223
 EXPRESSION (target_enable & line_loopback)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       237
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       238
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       270
 EXPRESSION (reg2hw.target_ack_ctrl.nack.qe & reg2hw.target_ack_ctrl.nack.q)
             ---------------1--------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       273
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       274
 EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       278
 EXPRESSION ((reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe) || (reg2hw.target_fifo_config.txrst_on_cond.q & target_sr_p_cond))
             ---------------------------1--------------------------    -------------------------------2------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       278
 SUB-EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       278
 SUB-EXPRESSION (reg2hw.target_fifo_config.txrst_on_cond.q & target_sr_p_cond)
                 --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       280
 EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       293
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       294
 EXPRESSION (acq_fifo_full || target_ack_ctrl_stretching)
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       299
 EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
             ----------1----------   ----------2----------   ----------3---------   ----------4----------   ----------5----------   ----------6----------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Not Covered
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Not Covered
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Not Covered
1	1	1	1	1	0	Not Covered
1	1	1	1	1	1	Not Covered

 LINE       312
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       313
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       314
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       315
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       316
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       317
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       388
 EXPRESSION (target_enable & (acq_type == AcqData))
             ------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION (acq_type == AcqData)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       391
 EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       391
 SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
                 -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       392
 EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       397
 EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
             --------------------------1-------------------------   ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       397
 SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       397
 SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
                 -------1-------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       397
 SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
                 -------1------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       397
 SUB-EXPRESSION (acq_type != AcqData)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
Branches		24	0	0.00
TERNARY	212	2	0	0.00
TERNARY	213	2	0	0.00
TERNARY	312	2	0	0.00
TERNARY	313	2	0	0.00
TERNARY	314	2	0	0.00
TERNARY	315	2	0	0.00
TERNARY	316	2	0	0.00
TERNARY	317	2	0	0.00
TERNARY	391	2	0	0.00
TERNARY	392	2	0	0.00
IF	232	2	0	0.00
IF	244	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(override) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	213	(override) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	312	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	313	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	314	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	315	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	316	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	317	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	391	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	392	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	232	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	244	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered