Unified Coverage Report :: Module :: i2c_core

Module : i2c_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07	97.35	71.29			91.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core	90.07	97.35	71.29			91.67	100.00

---

Module Instance : tb.dut.i2c_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07	97.35	71.29			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.43	96.09	85.91		83.58	91.85	94.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
intr_hw_acq_overflow	100.00	100.00	100.00			100.00	100.00
intr_hw_acq_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_cmd_complete	100.00	100.00	100.00			100.00	100.00
intr_hw_controller_halt	100.00	100.00	100.00			100.00	100.00
intr_hw_fmt_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_host_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_overflow	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_scl_interference	97.92	100.00	91.67			100.00	100.00
intr_hw_sda_interference	100.00	100.00	100.00			100.00	100.00
intr_hw_sda_unstable	100.00	100.00	100.00			100.00	100.00
intr_hw_stretch_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_stretch	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_unexp_stop	100.00	100.00	100.00			100.00	100.00
u_fifos	94.58	99.86	86.32			98.65	93.48
u_i2c_bus_monitor	89.23	96.26	89.25		81.82	89.58
u_i2c_controller_fsm	93.06	94.79	87.27		90.91	92.35	100.00
u_i2c_sync_scl	100.00	100.00				100.00
u_i2c_sync_sda	100.00	100.00				100.00
u_i2c_target_fsm	83.72	87.46	73.33		81.11	76.69	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
TOTAL		113	110	97.35
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
ALWAYS	239	5	5	100.00
ALWAYS	251	5	5	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	341	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	343	1	0	0.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	779	1	1	100.00
CONT_ASSIGN	781	1	1	100.00
CONT_ASSIGN	783	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	791	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	795	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
214	1	1
215	1	1
217	1	1
219	1	1
220	1	1
222	1	1
223	1	1
224	1	1
226	1	1
230	1	1
232	1	1
233	1	1
234	1	1
235	1	1
239	1	1
240	1	1
241	1	1
244	1	1
245	1	1
251	1	1
252	1	1
253	1	1
255	1	1
256	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
273	1	1
275	1	1
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
283	1	1
284	1	1
285	1	1
286	1	1
288	1	1
289	1	1
290	1	1
291	1	1
294	1	1
296	1	1
298	1	1
300	1	1
302	1	1
303	1	1
308	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
335	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	0	1
342	0	1
343	0	1
344	1	1
345	1	1
389	1	1
394	1	1
396	1	1
399	1	1
400	1	1
405	1	1
779	1	1
781	1	1
783	1	1
784	1	1
791	1	1
794	1	1
795	1	1

---

Cond Coverage for Module : i2c_core

	Total	Covered	Percent
Conditions	101	72	71.29
Logical	101	72	71.29
Non-Logical	0	0
Event	0	0

 LINE       214
 EXPRESSION (event_target_nack && (reg2hw.target_nack_count.q < 8'hff))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       219
 EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T49,T53

 LINE       220
 EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T49,T53

 LINE       226
 EXPRESSION (event_controller_cmd_complete | event_target_cmd_complete)
             --------------1--------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T3,T8

 LINE       230
 EXPRESSION (target_enable & line_loopback)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Not Covered

 LINE       244
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode))
             ------------1-----------    -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       271
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode)
                -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode))
             ------------1-----------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T6
1	1	Not Covered

 LINE       273
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       280
 EXPRESSION (reg2hw.target_ack_ctrl.nack.qe & reg2hw.target_ack_ctrl.nack.q)
             ---------------1--------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T11,T12
1	1	Not Covered

 LINE       283
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T43,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       284
 EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T43,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T43,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       289
 EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T33,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       302
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T54,T55,T56

 LINE       303
 EXPRESSION (acq_fifo_full || target_ack_ctrl_stretching)
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T12
1	0	Covered	T19,T20,T21

 LINE       308
 EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
             ----------1----------   ----------2----------   ----------3---------   ----------4----------   ----------5----------   ----------6----------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Not Covered
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Not Covered
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Not Covered
1	1	1	1	1	0	Not Covered
1	1	1	1	1	1	Covered	T2,T3,T8

 LINE       321
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       322
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       323
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       324
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       325
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       326
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       396
 EXPRESSION (target_enable & (acq_type == AcqData))
             ------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       396
 SUB-EXPRESSION (acq_type == AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       399
 SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
                 -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       400
 EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       405
 EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
             --------------------------1-------------------------   ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T5,T6

 LINE       405
 SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T5,T6

 LINE       405
 SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
                 -------1-------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       405
 SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
                 -------1------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T33,T34
1	0	Covered	T1,T2,T3

 LINE       405
 SUB-EXPRESSION (acq_type != AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       783
 EXPRESSION (event_bus_active_timeout && ((!host_idle)))
             ------------1-----------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Not Covered
1	1	Not Covered

 LINE       791
 EXPRESSION (event_read_cmd_received && reg2hw.ctrl.tx_stretch_ctrl_en.q)
             -----------1-----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Not Covered

---

Branch Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
TERNARY	219	2	2	100.00
TERNARY	220	2	2	100.00
TERNARY	321	2	2	100.00
TERNARY	322	2	2	100.00
TERNARY	323	2	2	100.00
TERNARY	324	2	2	100.00
TERNARY	325	2	2	100.00
TERNARY	326	2	2	100.00
TERNARY	399	2	1	50.00
TERNARY	400	2	1	50.00
IF	239	2	2	100.00
IF	251	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	219	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T44,T49,T53
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	220	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T44,T49,T53
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	322	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	325	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	326	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	399	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	400	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	239	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqFifoDepthValid_A	1312	1312	0	0
FifoDepthValid_A	1312	1312	0	0
SclInputGlitch_A	404315798	9712733	0	0

AcqFifoDepthValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1312	1312	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

FifoDepthValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1312	1312	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404315798	9712733	0	0
T1	40896	1686	0	0
T2	212264	11857	0	0
T3	458584	23440	0	0
T4	967	0	0	0
T5	196673	1295	0	0
T6	272230	3365	0	0
T7	82147	4912	0	0
T8	22900	1106	0	0
T9	1343	0	0	0
T10	1603	0	0	0
T11	0	5437	0	0
T31	0	5454	0	0
T57	0	275	0	0