Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40290

1

T1

17

T2

394

T3

198

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35227	1			T1	20		T2	98		T3	47
values[0x0]	15260	1			T1	9		T2	142		T3	79
values[0x1]	15964	1			T1	11		T2	179		T3	88

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18584	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

47867

1

T1

24

T2

413

T3

211

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	261	1			T3	3		T5	3		T6	9
valid_sources[0x01]	317	1			T2	2		T3	1		T9	1
valid_sources[0x02]	179	1			T2	3		T6	8		T11	2
valid_sources[0x03]	162	1			T2	4		T9	1		T7	1
valid_sources[0x04]	213	1			T2	1		T15	1		T11	4
valid_sources[0x05]	128	1			T3	1		T9	2		T5	6
valid_sources[0x06]	265	1			T2	1		T5	4		T11	3
valid_sources[0x07]	234	1			T2	1		T9	1		T12	1
valid_sources[0x08]	217	1			T2	3		T9	1		T5	1
valid_sources[0x09]	138	1			T2	1		T7	1		T16	2
valid_sources[0x0a]	270	1			T7	2		T6	12		T11	3
valid_sources[0x0b]	264	1			T3	5		T9	1		T11	3
valid_sources[0x0c]	212	1			T2	2		T7	1		T10	26
valid_sources[0x0d]	333	1			T8	124		T9	2		T11	2
valid_sources[0x0e]	310	1			T2	2		T3	1		T8	127
valid_sources[0x0f]	186	1			T2	5		T3	1		T10	15
valid_sources[0x10]	212	1			T2	1		T9	2		T5	4
valid_sources[0x11]	159	1			T3	1		T7	1		T10	5
valid_sources[0x12]	168	1			T16	1		T10	1		T11	2
valid_sources[0x13]	255	1			T2	2		T3	2		T9	1
valid_sources[0x14]	194	1			T2	2		T4	5		T11	3
valid_sources[0x15]	218	1			T10	15		T62	1		T37	6
valid_sources[0x16]	184	1			T2	2		T3	1		T11	4
valid_sources[0x17]	251	1			T2	1		T12	1		T4	3
valid_sources[0x18]	183	1			T1	1		T2	4		T9	2
valid_sources[0x19]	250	1			T2	1		T9	1		T11	4
valid_sources[0x1a]	193	1			T2	3		T12	1		T7	1
valid_sources[0x1b]	294	1			T2	3		T9	3		T12	1
valid_sources[0x1c]	266	1			T2	6		T9	1		T10	20
valid_sources[0x1d]	132	1			T2	2		T3	1		T6	2
valid_sources[0x1e]	205	1			T3	1		T9	1		T12	1
valid_sources[0x1f]	312	1			T2	3		T3	1		T16	2
valid_sources[0x20]	186	1			T2	3		T16	3		T11	6
valid_sources[0x21]	179	1			T7	1		T14	1		T37	2
valid_sources[0x22]	170	1			T2	2		T9	1		T4	5
valid_sources[0x23]	217	1			T1	1		T9	1		T5	3
valid_sources[0x24]	288	1			T1	1		T2	1		T9	1
valid_sources[0x25]	330	1			T9	2		T4	1		T6	1
valid_sources[0x26]	212	1			T2	1		T3	2		T4	1
valid_sources[0x27]	364	1			T3	1		T9	2		T5	1
valid_sources[0x28]	163	1			T2	2		T16	1		T11	3
valid_sources[0x29]	449	1			T2	4		T8	128		T9	1
valid_sources[0x2a]	203	1			T2	1		T3	1		T9	1
valid_sources[0x2b]	415	1			T3	3		T8	128		T5	3
valid_sources[0x2c]	180	1			T2	2		T7	1		T10	2
valid_sources[0x2d]	162	1			T2	1		T7	1		T5	1
valid_sources[0x2e]	467	1			T1	2		T8	128		T16	3
valid_sources[0x2f]	294	1			T2	3		T3	1		T8	127
valid_sources[0x30]	244	1			T2	3		T3	1		T10	4
valid_sources[0x31]	299	1			T9	1		T10	30		T11	4
valid_sources[0x32]	256	1			T2	2		T9	1		T10	4
valid_sources[0x33]	232	1			T1	1		T2	4		T3	1
valid_sources[0x34]	127	1			T2	1		T3	3		T5	1
valid_sources[0x35]	181	1			T36	1		T38	1		T18	12
valid_sources[0x36]	188	1			T1	1		T2	1		T3	4
valid_sources[0x37]	131	1			T5	2		T6	10		T11	7
valid_sources[0x38]	181	1			T3	1		T11	4		T21	14
valid_sources[0x39]	254	1			T2	3		T3	3		T11	4
valid_sources[0x3a]	318	1			T2	3		T8	128		T9	1
valid_sources[0x3b]	232	1			T2	1		T3	2		T11	6
valid_sources[0x3c]	253	1			T2	2		T10	7		T11	4
valid_sources[0x3d]	190	1			T2	1		T3	1		T10	5
valid_sources[0x3e]	307	1			T2	1		T9	2		T16	1
valid_sources[0x3f]	149	1			T2	4		T9	1		T12	1
valid_sources[0x40]	253	1			T1	1		T2	2		T3	3
valid_sources[0x41]	203	1			T2	1		T4	3		T16	3
valid_sources[0x42]	197	1			T1	2		T2	1		T3	2
valid_sources[0x43]	445	1			T2	2		T8	128		T9	1
valid_sources[0x44]	186	1			T2	2		T3	2		T37	2
valid_sources[0x45]	150	1			T1	1		T2	3		T5	3
valid_sources[0x46]	251	1			T2	1		T9	1		T4	11
valid_sources[0x47]	184	1			T1	1		T2	2		T3	1
valid_sources[0x48]	190	1			T4	1		T6	30		T11	2
valid_sources[0x49]	271	1			T2	2		T5	1		T16	2
valid_sources[0x4a]	264	1			T2	1		T7	1		T5	1
valid_sources[0x4b]	200	1			T2	5		T9	1		T11	2
valid_sources[0x4c]	278	1			T2	1		T16	2		T11	4
valid_sources[0x4d]	309	1			T2	4		T3	2		T9	1
valid_sources[0x4e]	232	1			T2	4		T10	8		T11	2
valid_sources[0x4f]	242	1			T5	1		T10	2		T11	1
valid_sources[0x50]	158	1			T1	1		T2	4		T15	1
valid_sources[0x51]	169	1			T1	1		T2	1		T3	1
valid_sources[0x52]	508	1			T2	1		T3	2		T8	256
valid_sources[0x53]	227	1			T36	4		T37	3		T38	1
valid_sources[0x54]	192	1			T2	3		T10	2		T14	1
valid_sources[0x55]	269	1			T2	2		T10	8		T11	4
valid_sources[0x56]	358	1			T1	1		T2	3		T11	5
valid_sources[0x57]	185	1			T2	3		T3	1		T9	1
valid_sources[0x58]	206	1			T2	3		T3	2		T12	2
valid_sources[0x59]	146	1			T1	1		T2	2		T3	1
valid_sources[0x5a]	261	1			T2	1		T8	128		T9	4
valid_sources[0x5b]	381	1			T2	2		T3	1		T8	128
valid_sources[0x5c]	167	1			T2	1		T16	1		T11	7
valid_sources[0x5d]	193	1			T2	1		T7	1		T16	4
valid_sources[0x5e]	376	1			T2	2		T3	3		T16	2
valid_sources[0x5f]	286	1			T2	2		T3	1		T9	1
valid_sources[0x60]	156	1			T2	1		T9	1		T16	1
valid_sources[0x61]	257	1			T12	3		T11	4		T36	3
valid_sources[0x62]	373	1			T2	2		T9	1		T16	2
valid_sources[0x63]	214	1			T2	1		T3	1		T9	2
valid_sources[0x64]	354	1			T2	2		T8	128		T9	3
valid_sources[0x65]	257	1			T9	2		T11	1		T38	2
valid_sources[0x66]	363	1			T1	2		T2	2		T12	1
valid_sources[0x67]	286	1			T2	1		T3	1		T12	1
valid_sources[0x68]	178	1			T1	1		T2	2		T9	2
valid_sources[0x69]	174	1			T2	1		T3	1		T9	1
valid_sources[0x6a]	207	1			T1	1		T2	3		T9	3
valid_sources[0x6b]	277	1			T16	3		T11	5		T36	1
valid_sources[0x6c]	451	1			T2	3		T8	128		T9	1
valid_sources[0x6d]	475	1			T2	3		T3	3		T8	128
valid_sources[0x6e]	250	1			T2	1		T9	1		T7	1
valid_sources[0x6f]	205	1			T1	1		T5	1		T16	1
valid_sources[0x70]	157	1			T3	1		T13	22		T4	10
valid_sources[0x71]	228	1			T16	1		T11	2		T37	1
valid_sources[0x72]	300	1			T2	1		T16	2		T11	4
valid_sources[0x73]	202	1			T3	1		T9	2		T12	1
valid_sources[0x74]	161	1			T1	1		T2	3		T3	1
valid_sources[0x75]	180	1			T2	3		T3	1		T9	2
valid_sources[0x76]	131	1			T2	1		T9	1		T12	1
valid_sources[0x77]	141	1			T2	2		T5	1		T16	6
valid_sources[0x78]	438	1			T1	1		T2	1		T3	1
valid_sources[0x79]	339	1			T1	1		T3	1		T8	128
valid_sources[0x7a]	296	1			T2	2		T8	128		T9	2
valid_sources[0x7b]	256	1			T2	2		T5	2		T11	4
valid_sources[0x7c]	286	1			T2	1		T16	1		T11	5
valid_sources[0x7d]	229	1			T2	1		T3	2		T4	35
valid_sources[0x7e]	255	1			T2	1		T3	1		T10	19
valid_sources[0x7f]	329	1			T2	3		T8	128		T7	1
valid_sources[0x80]	152	1			T2	1		T3	1		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15591

1

T1

10

T2

97

T3

47

values[0x0]

all_enables

biggest_size

12749

1

T1

4

T2

141

T3

78

values[0x1]

all_enables

biggest_size

11950

1

T1

3

T2

156

T3

73