Unified Coverage Report :: Group :: i2c_env_pkg::i2c_acq_fifo_cg

Group : i2c_env_pkg::i2c_acq_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
0.00	0.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.acq_fifo_cg	0.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.acq_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.acq_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	11	0	0.00
Crosses	13	13	0	0.00

Variables for Group Instance i2c_env_pkg.acq_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_abyte	5	5	0	0.00	100	1	1	0
cp_action	4	4	0	0.00	100	1	1	0
cp_request_type	2	2	0	0.00	100	1	1	0
cp_target_read_ack_nack	0	0	0				1	0

Crosses for Group Instance i2c_env_pkg.acq_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_abyte_X_cp_action	13	13	0	0.00	100	1	1	0

Summary for Variable cp_abyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	5	0	0.00

User Defined Bins for cp_abyte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_ones	0	1	1
high	0	1	1
med	0	1	1
sml	0	1	1
all_zero	0	1	1

---

Summary for Variable cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	4	0	0.00

User Defined Bins for cp_action

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
rstart	0	1	1
start	0	1	1
stop	0	1	1
none	0	1	1

---

Summary for Variable cp_request_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	2	0	0.00

User Defined Bins for cp_request_type

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
write	0	1	1
read	0	1	1

---

Summary for Variable cp_target_read_ack_nack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	0	0	0

User Defined Bins for cp_target_read_ack_nack

Excluded/Illegal bins

NAME	COUNT	STATUS
read_req_nack_before_rstart	0	Excluded
read_req_ack_before_stop	0	Excluded
read_req_nack_before_stop	0	Excluded
read_req_ack_before_rstart	0	Excluded

---

Summary for Cross cp_abyte_X_cp_action

Samples crossed: cp_abyte cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	13	13	0	0.00	10
Automatically Generated Cross Bins	10	10	0	0.00	10
User Defined Cross Bins	3	3	0	0.00

Automatically Generated Cross Bins for cp_abyte_X_cp_action

Element holes

cp_abyte	cp_action	COUNT	AT LEAST	NUMBER	STATUS
*	[rstart]	--	--	5
*	[stop]	--	--	5

User Defined Cross Bins for cp_abyte_X_cp_action

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
write_address_byte	0	1	1
read_address_byte	0	1	1
data_byte	0	1	1