Unified Coverage Report :: Module :: i2c_core

Module : i2c_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.i2c_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.62	0.00	0.00	94.87				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
intr_hw_acq_overflow	0.00	0.00	0.00			0.00
intr_hw_acq_threshold	0.00	0.00	0.00			0.00
intr_hw_cmd_complete	0.00	0.00	0.00			0.00
intr_hw_controller_halt	0.00	0.00	0.00			0.00
intr_hw_fmt_threshold	0.00	0.00	0.00			0.00
intr_hw_host_timeout	0.00	0.00	0.00			0.00
intr_hw_rx_overflow	0.00	0.00	0.00			0.00
intr_hw_rx_threshold	0.00	0.00	0.00			0.00
intr_hw_scl_interference	0.00	0.00	0.00			0.00
intr_hw_sda_interference	0.00	0.00	0.00			0.00
intr_hw_sda_unstable	0.00	0.00	0.00			0.00
intr_hw_stretch_timeout	0.00	0.00	0.00			0.00
intr_hw_tx_stretch	0.00	0.00	0.00			0.00
intr_hw_tx_threshold	0.00	0.00	0.00			0.00
intr_hw_unexp_stop	0.00	0.00	0.00			0.00
u_fifos	0.00	0.00	0.00			0.00
u_i2c_bus_monitor	0.00	0.00	0.00		0.00	0.00
u_i2c_controller_fsm	0.00	0.00	0.00		0.00	0.00
u_i2c_sync_scl	0.00	0.00				0.00
u_i2c_sync_sda	0.00	0.00				0.00
u_i2c_target_fsm	0.00	0.00	0.00		0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
TOTAL		133	0	0.00
CONT_ASSIGN	212	1	0	0.00
CONT_ASSIGN	213	1	0	0.00
CONT_ASSIGN	214	1	0	0.00
CONT_ASSIGN	215	1	0	0.00
CONT_ASSIGN	216	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	220	1	0	0.00
CONT_ASSIGN	221	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	223	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	226	1	0	0.00
CONT_ASSIGN	227	1	0	0.00
CONT_ASSIGN	228	1	0	0.00
CONT_ASSIGN	229	1	0	0.00
CONT_ASSIGN	230	1	0	0.00
CONT_ASSIGN	231	1	0	0.00
CONT_ASSIGN	232	1	0	0.00
CONT_ASSIGN	233	1	0	0.00
CONT_ASSIGN	237	1	0	0.00
CONT_ASSIGN	238	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	246	1	0	0.00
CONT_ASSIGN	247	1	0	0.00
CONT_ASSIGN	249	1	0	0.00
CONT_ASSIGN	253	1	0	0.00
CONT_ASSIGN	255	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
CONT_ASSIGN	257	1	0	0.00
CONT_ASSIGN	258	1	0	0.00
ALWAYS	262	5	0	0.00
ALWAYS	274	5	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	284	1	0	0.00
CONT_ASSIGN	285	1	0	0.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	287	1	0	0.00
CONT_ASSIGN	288	1	0	0.00
CONT_ASSIGN	289	1	0	0.00
CONT_ASSIGN	290	1	0	0.00
CONT_ASSIGN	291	1	0	0.00
CONT_ASSIGN	292	1	0	0.00
CONT_ASSIGN	293	1	0	0.00
CONT_ASSIGN	294	1	0	0.00
CONT_ASSIGN	296	1	0	0.00
CONT_ASSIGN	298	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	300	1	0	0.00
CONT_ASSIGN	301	1	0	0.00
CONT_ASSIGN	302	1	0	0.00
CONT_ASSIGN	303	1	0	0.00
CONT_ASSIGN	306	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	311	1	0	0.00
CONT_ASSIGN	312	1	0	0.00
CONT_ASSIGN	313	1	0	0.00
CONT_ASSIGN	314	1	0	0.00
CONT_ASSIGN	317	1	0	0.00
CONT_ASSIGN	319	1	0	0.00
CONT_ASSIGN	321	1	0	0.00
CONT_ASSIGN	323	1	0	0.00
CONT_ASSIGN	325	1	0	0.00
CONT_ASSIGN	326	1	0	0.00
CONT_ASSIGN	331	1	0	0.00
CONT_ASSIGN	337	1	0	0.00
CONT_ASSIGN	338	1	0	0.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	340	1	0	0.00
CONT_ASSIGN	341	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	345	1	0	0.00
CONT_ASSIGN	346	1	0	0.00
CONT_ASSIGN	347	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	349	1	0	0.00
CONT_ASSIGN	358	1	0	0.00
CONT_ASSIGN	360	1	0	0.00
CONT_ASSIGN	361	1	0	0.00
CONT_ASSIGN	362	1	0	0.00
CONT_ASSIGN	363	1	0	0.00
CONT_ASSIGN	364	1	0	0.00
CONT_ASSIGN	365	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
CONT_ASSIGN	367	1	0	0.00
CONT_ASSIGN	368	1	0	0.00
CONT_ASSIGN	412	1	0	0.00
CONT_ASSIGN	417	1	0	0.00
CONT_ASSIGN	419	1	0	0.00
CONT_ASSIGN	422	1	0	0.00
CONT_ASSIGN	423	1	0	0.00
CONT_ASSIGN	428	1	0	0.00
CONT_ASSIGN	455	1	0	0.00
CONT_ASSIGN	456	1	0	0.00
ALWAYS	459	5	0	0.00
ALWAYS	469	6	0	0.00
CONT_ASSIGN	485	1	0	0.00
CONT_ASSIGN	486	1	0	0.00
CONT_ASSIGN	488	1	0	0.00
CONT_ASSIGN	489	1	0	0.00
CONT_ASSIGN	491	1	0	0.00
CONT_ASSIGN	850	1	0	0.00
CONT_ASSIGN	852	1	0	0.00
CONT_ASSIGN	854	1	0	0.00
CONT_ASSIGN	856	1	0	0.00
CONT_ASSIGN	857	1	0	0.00
CONT_ASSIGN	865	1	0	0.00
CONT_ASSIGN	868	1	0	0.00
CONT_ASSIGN	870	1	0	0.00
CONT_ASSIGN	871	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	0	1
213	0	1
214	0	1
215	0	1
216	0	1
217	0	1
218	0	1
220	0	1
221	0	1
222	0	1
223	0	1
224	0	1
226	0	1
227	0	1
228	0	1
229	0	1
230	0	1
231	0	1
232	0	1
233	0	1
237	0	1
238	0	1
240	0	1
242	0	1
243	0	1
245	0	1
246	0	1
247	0	1
249	0	1
253	0	1
255	0	1
256	0	1
257	0	1
258	0	1
262	0	1
263	0	1
264	0	1
267	0	1
268	0	1
274	0	1
275	0	1
276	0	1
278	0	1
279	0	1
283	0	1
284	0	1
285	0	1
286	0	1
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
293	0	1
294	0	1
296	0	1
298	0	1
299	0	1
300	0	1
301	0	1
302	0	1
303	0	1
306	0	1
307	0	1
308	0	1
309	0	1
311	0	1
312	0	1
313	0	1
314	0	1
317	0	1
319	0	1
321	0	1
323	0	1
325	0	1
326	0	1
331	0	1
337	0	1
338	0	1
339	0	1
340	0	1
341	0	1
342	0	1
344	0	1
345	0	1
346	0	1
347	0	1
348	0	1
349	0	1
358	0	1
360	0	1
361	0	1
362	0	1
363	0	1
364	0	1
365	0	1
366	0	1
367	0	1
368	0	1
412	0	1
417	0	1
419	0	1
422	0	1
423	0	1
428	0	1
455	0	1
456	0	1
459	0	1
460	0	1
461	0	1
463	0	1
464	0	1
469	0	1
470	0	1
471	0	1
480	0	1
481	0	1
482	0	1
			==> MISSING_ELSE
485	0	1
486	0	1
488	0	1
489	0	1
491	0	1
850	0	1
852	0	1
854	0	1
856	0	1
857	0	1
865	0	1
868	0	1
870	0	1
871	0	1

---

Cond Coverage for Module : i2c_core

	Total	Covered	Percent
Conditions	130	0	0.00
Logical	130	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       237
 EXPRESSION (event_target_nack && (reg2hw.target_nack_count.q < 8'hff))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       242
 EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       243
 EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       249
 EXPRESSION (event_controller_cmd_complete | event_target_cmd_complete)
             --------------1--------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       253
 EXPRESSION (target_enable & line_loopback)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       267
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       268
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       294
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode))
             ------------1-----------    -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       294
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode)
                -------------------------1------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       296
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode))
             ------------1-----------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       296
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode)
                -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       303
 EXPRESSION (reg2hw.target_ack_ctrl.nack.qe & reg2hw.target_ack_ctrl.nack.q)
             ---------------1--------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       306
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       307
 EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       311
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       312
 EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       325
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       326
 EXPRESSION (acq_fifo_full || target_ack_ctrl_stretching)
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       331
 EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
             ----------1----------   ----------2----------   ----------3---------   ----------4----------   ----------5----------   ----------6----------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Not Covered
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Not Covered
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Not Covered
1	1	1	1	1	0	Not Covered
1	1	1	1	1	1	Not Covered

 LINE       344
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       345
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       346
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       347
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       348
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       349
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       419
 EXPRESSION (target_enable & (acq_type == AcqData))
             ------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       419
 SUB-EXPRESSION (acq_type == AcqData)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       422
 EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       422
 SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
                 -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       423
 EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       428
 EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
             --------------------------1-------------------------   ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
                 -------1-------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
                 -------1------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (acq_type != AcqData)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       455
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       456
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       471
 EXPRESSION ((scl_fsm != scl_fsm_q) || (sda_fsm != sda_fsm_q))
             -----------1----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       471
 SUB-EXPRESSION (scl_fsm != scl_fsm_q)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       471
 SUB-EXPRESSION (sda_fsm != sda_fsm_q)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       481
 EXPRESSION (bus_event_detect_cnt != '0)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       485
 EXPRESSION (bus_event_detect_cnt == '0)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       486
 EXPRESSION (bus_event_detect && scl_sync && (sda_fsm_q != sda_sync))
             --------1-------    ----2---    -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       486
 SUB-EXPRESSION (sda_fsm_q != sda_sync)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       488
 EXPRESSION (controller_transmitting && sda_released_but_low)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       489
 EXPRESSION (target_transmitting && sda_released_but_low)
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       854
 EXPRESSION (event_bus_active_timeout && ((!host_idle)))
             ------------1-----------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       865
 EXPRESSION (event_read_cmd_received && reg2hw.ctrl.tx_stretch_ctrl_en.q)
             -----------1-----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
Branches		30	0	0.00
TERNARY	242	2	0	0.00
TERNARY	243	2	0	0.00
TERNARY	344	2	0	0.00
TERNARY	345	2	0	0.00
TERNARY	346	2	0	0.00
TERNARY	347	2	0	0.00
TERNARY	348	2	0	0.00
TERNARY	349	2	0	0.00
TERNARY	422	2	0	0.00
TERNARY	423	2	0	0.00
IF	262	2	0	0.00
IF	274	2	0	0.00
IF	459	2	0	0.00
IF	469	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	242	(override) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	243	(override) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	344	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	345	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	346	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	347	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	348	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	349	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	422	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	423	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	262	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	274	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	459	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	469	if ((!rst_ni))
-2-:	471	if (((scl_fsm != scl_fsm_q) || (sda_fsm != sda_fsm_q)))
-3-:	481	if ((bus_event_detect_cnt != '0))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered