Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.62	0.00	0.00	94.87				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	687294	0	0	0
ctrl_rd_A	687294	2328	0	0
host_fifo_config_rd_A	687294	1484	0	0
host_nack_handler_timeout_rd_A	687294	1537	0	0
host_timeout_ctrl_rd_A	687294	1318	0	0
intr_enable_rd_A	687294	2947	0	0
ovrd_rd_A	687294	1794	0	0
target_fifo_config_rd_A	687294	1509	0	0
target_id_rd_A	687294	1996	0	0
target_timeout_ctrl_rd_A	687294	1694	0	0
timeout_ctrl_rd_A	687294	1777	0	0
timing0_rd_A	687294	1635	0	0
timing1_rd_A	687294	1657	0	0
timing2_rd_A	687294	1588	0	0
timing3_rd_A	687294	1500	0	0
timing4_rd_A	687294	1557	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	2328	0	0
T2	8505	31	0	0
T3	6517	11	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	461	0	0
T9	2791	34	0	0
T10	0	211	0	0
T11	0	85	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	18	0	0
T19	0	24	0	0
T23	0	15	0	0
T41	0	13	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1484	0	0
T2	8505	15	0	0
T3	6517	10	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	431	0	0
T9	2791	7	0	0
T10	0	43	0	0
T11	0	38	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	5	0	0
T19	0	34	0	0
T41	0	8	0	0
T42	0	40	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1537	0	0
T2	8505	20	0	0
T3	6517	8	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	420	0	0
T9	2791	15	0	0
T10	0	59	0	0
T11	0	35	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	24	0	0
T19	0	18	0	0
T23	0	1	0	0
T41	0	16	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1318	0	0
T2	8505	24	0	0
T3	6517	38	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	432	0	0
T9	2791	5	0	0
T10	0	35	0	0
T11	0	19	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	5	0	0
T19	0	37	0	0
T23	0	7	0	0
T41	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	2947	0	0
T1	1144	9	0	0
T2	8505	26	0	0
T3	6517	17	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	425	0	0
T9	2791	54	0	0
T10	0	192	0	0
T11	0	111	0	0
T12	958	0	0	0
T13	1137	0	0	0
T18	0	3	0	0
T23	0	23	0	0
T43	0	10	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1794	0	0
T2	8505	28	0	0
T3	6517	2	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	453	0	0
T9	2791	13	0	0
T10	0	53	0	0
T11	0	67	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	11	0	0
T19	0	33	0	0
T23	0	16	0	0
T41	0	21	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1509	0	0
T2	8505	13	0	0
T3	6517	1	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	462	0	0
T9	2791	19	0	0
T10	0	56	0	0
T11	0	25	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	31	0	0
T19	0	48	0	0
T23	0	5	0	0
T41	0	28	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1996	0	0
T2	8505	4	0	0
T3	6517	16	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	404	0	0
T9	2791	9	0	0
T10	0	113	0	0
T11	0	88	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	8	0	0
T23	0	14	0	0
T41	0	27	0	0
T42	0	78	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1694	0	0
T2	8505	16	0	0
T3	6517	19	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	491	0	0
T9	2791	7	0	0
T10	0	60	0	0
T11	0	29	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	19	0	0
T19	0	33	0	0
T23	0	10	0	0
T41	0	35	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1777	0	0
T2	8505	22	0	0
T3	6517	30	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	436	0	0
T9	2791	7	0	0
T10	0	80	0	0
T11	0	35	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	27	0	0
T19	0	38	0	0
T41	0	18	0	0
T42	0	27	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1635	0	0
T2	8505	6	0	0
T3	6517	26	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	491	0	0
T9	2791	13	0	0
T10	0	67	0	0
T11	0	58	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	2	0	0
T19	0	25	0	0
T23	0	6	0	0
T41	0	9	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1657	0	0
T2	8505	15	0	0
T3	6517	7	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	458	0	0
T9	2791	10	0	0
T10	0	35	0	0
T11	0	42	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	33	0	0
T19	0	17	0	0
T23	0	10	0	0
T41	0	7	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1588	0	0
T2	8505	12	0	0
T3	6517	14	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	426	0	0
T9	2791	10	0	0
T10	0	78	0	0
T11	0	34	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	14	0	0
T19	0	22	0	0
T23	0	11	0	0
T41	0	10	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1500	0	0
T2	8505	20	0	0
T3	6517	2	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	408	0	0
T9	2791	7	0	0
T10	0	85	0	0
T11	0	40	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	33	0	0
T19	0	26	0	0
T23	0	7	0	0
T41	0	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687294	1557	0	0
T2	8505	7	0	0
T3	6517	18	0	0
T4	2170	0	0	0
T5	3142	0	0	0
T7	1199	0	0	0
T8	63336	469	0	0
T9	2791	14	0	0
T10	0	60	0	0
T11	0	42	0	0
T12	958	0	0	0
T13	1137	0	0	0
T16	2523	0	0	0
T18	0	33	0	0
T19	0	15	0	0
T23	0	15	0	0
T41	0	10	0	0