Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28503	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

42658

1

T1

383

T2

573

T3

61

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38208	1			T1	721		T2	922		T3	100
values[0x0]	16132	1			T1	13		T2	299		T3	31
values[0x1]	16821	1			T1	18		T2	297		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20196	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50965

1

T1

461

T2

901

T3

101

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	326	1			T1	4		T2	8		T7	8
valid_sources[0x01]	233	1			T2	1		T7	12		T16	2
valid_sources[0x02]	216	1			T1	1		T2	28		T7	17
valid_sources[0x03]	234	1			T1	2		T7	7		T6	4
valid_sources[0x04]	285	1			T1	7		T2	2		T3	1
valid_sources[0x05]	258	1			T1	7		T3	1		T7	8
valid_sources[0x06]	293	1			T1	3		T2	10		T3	1
valid_sources[0x07]	258	1			T1	4		T7	10		T6	3
valid_sources[0x08]	281	1			T1	4		T3	5		T7	12
valid_sources[0x09]	285	1			T1	3		T2	7		T7	15
valid_sources[0x0a]	188	1			T1	3		T2	6		T3	1
valid_sources[0x0b]	261	1			T1	5		T2	22		T7	15
valid_sources[0x0c]	220	1			T1	5		T2	13		T3	3
valid_sources[0x0d]	241	1			T1	2		T7	6		T6	2
valid_sources[0x0e]	376	1			T1	2		T7	24		T6	2
valid_sources[0x0f]	337	1			T3	3		T7	6		T6	4
valid_sources[0x10]	224	1			T2	6		T3	1		T7	12
valid_sources[0x11]	319	1			T1	3		T3	2		T7	14
valid_sources[0x12]	183	1			T1	4		T7	19		T6	1
valid_sources[0x13]	266	1			T1	2		T2	1		T3	1
valid_sources[0x14]	495	1			T1	3		T2	7		T3	2
valid_sources[0x15]	186	1			T1	2		T2	5		T7	11
valid_sources[0x16]	216	1			T1	4		T2	8		T7	8
valid_sources[0x17]	189	1			T3	1		T7	10		T6	1
valid_sources[0x18]	391	1			T1	3		T2	1		T7	5
valid_sources[0x19]	371	1			T1	6		T2	28		T7	12
valid_sources[0x1a]	205	1			T1	2		T2	15		T3	1
valid_sources[0x1b]	256	1			T1	3		T2	1		T7	13
valid_sources[0x1c]	263	1			T7	1		T6	2		T17	1
valid_sources[0x1d]	175	1			T1	2		T3	1		T7	7
valid_sources[0x1e]	415	1			T1	7		T7	33		T16	1
valid_sources[0x1f]	240	1			T2	1		T7	8		T6	5
valid_sources[0x20]	354	1			T1	2		T3	1		T7	21
valid_sources[0x21]	355	1			T7	16		T6	4		T16	2
valid_sources[0x22]	223	1			T1	6		T2	4		T7	5
valid_sources[0x23]	263	1			T1	1		T2	32		T3	1
valid_sources[0x24]	209	1			T1	7		T2	5		T7	10
valid_sources[0x25]	337	1			T1	3		T2	1		T3	2
valid_sources[0x26]	209	1			T2	12		T7	12		T6	4
valid_sources[0x27]	221	1			T1	5		T2	3		T7	5
valid_sources[0x28]	180	1			T1	4		T6	1		T16	1
valid_sources[0x29]	240	1			T1	1		T2	8		T3	1
valid_sources[0x2a]	255	1			T1	7		T2	17		T3	2
valid_sources[0x2b]	219	1			T1	4		T3	1		T7	12
valid_sources[0x2c]	200	1			T1	1		T3	1		T7	16
valid_sources[0x2d]	197	1			T1	6		T2	12		T7	17
valid_sources[0x2e]	249	1			T1	2		T7	6		T6	2
valid_sources[0x2f]	219	1			T1	3		T2	1		T3	1
valid_sources[0x30]	429	1			T2	12		T3	1		T7	6
valid_sources[0x31]	228	1			T1	5		T2	20		T7	8
valid_sources[0x32]	186	1			T1	1		T3	2		T7	6
valid_sources[0x33]	277	1			T7	14		T6	3		T16	2
valid_sources[0x34]	334	1			T1	1		T2	11		T7	6
valid_sources[0x35]	273	1			T1	3		T2	6		T3	1
valid_sources[0x36]	309	1			T1	3		T2	21		T3	1
valid_sources[0x37]	445	1			T1	5		T7	2		T6	1
valid_sources[0x38]	282	1			T1	1		T2	50		T7	11
valid_sources[0x39]	224	1			T1	4		T2	5		T7	18
valid_sources[0x3a]	297	1			T1	3		T2	23		T3	2
valid_sources[0x3b]	355	1			T1	4		T7	7		T6	1
valid_sources[0x3c]	236	1			T1	3		T2	22		T7	5
valid_sources[0x3d]	213	1			T1	4		T7	17		T6	1
valid_sources[0x3e]	184	1			T1	2		T7	15		T6	2
valid_sources[0x3f]	272	1			T2	7		T3	1		T7	17
valid_sources[0x40]	212	1			T1	2		T7	8		T6	6
valid_sources[0x41]	294	1			T1	5		T2	13		T3	3
valid_sources[0x42]	191	1			T1	2		T2	17		T7	14
valid_sources[0x43]	206	1			T1	4		T7	11		T6	3
valid_sources[0x44]	295	1			T2	5		T7	6		T17	2
valid_sources[0x45]	219	1			T1	3		T2	2		T3	1
valid_sources[0x46]	455	1			T1	5		T7	11		T6	1
valid_sources[0x47]	444	1			T1	2		T2	16		T3	1
valid_sources[0x48]	268	1			T1	2		T2	16		T7	11
valid_sources[0x49]	280	1			T1	5		T2	7		T7	7
valid_sources[0x4a]	339	1			T1	6		T2	22		T7	16
valid_sources[0x4b]	311	1			T1	1		T2	26		T3	1
valid_sources[0x4c]	309	1			T1	1		T2	2		T3	1
valid_sources[0x4d]	289	1			T2	13		T7	12		T6	2
valid_sources[0x4e]	505	1			T1	3		T3	1		T7	26
valid_sources[0x4f]	239	1			T1	2		T2	6		T3	2
valid_sources[0x50]	271	1			T1	5		T2	12		T7	7
valid_sources[0x51]	267	1			T7	13		T6	3		T16	1
valid_sources[0x52]	305	1			T1	2		T7	8		T6	2
valid_sources[0x53]	224	1			T1	4		T2	7		T7	18
valid_sources[0x54]	198	1			T1	6		T2	1		T3	3
valid_sources[0x55]	250	1			T1	6		T7	3		T17	1
valid_sources[0x56]	205	1			T1	4		T3	3		T7	22
valid_sources[0x57]	260	1			T1	5		T7	18		T16	2
valid_sources[0x58]	307	1			T1	3		T2	2		T3	1
valid_sources[0x59]	178	1			T1	3		T3	3		T7	7
valid_sources[0x5a]	278	1			T7	21		T16	1		T17	3
valid_sources[0x5b]	327	1			T1	2		T2	22		T3	2
valid_sources[0x5c]	270	1			T1	2		T3	1		T7	15
valid_sources[0x5d]	304	1			T1	5		T2	2		T7	29
valid_sources[0x5e]	291	1			T1	2		T2	16		T3	2
valid_sources[0x5f]	203	1			T1	1		T2	6		T7	6
valid_sources[0x60]	297	1			T2	16		T7	18		T6	7
valid_sources[0x61]	253	1			T1	4		T2	11		T7	7
valid_sources[0x62]	648	1			T1	6		T3	1		T7	20
valid_sources[0x63]	306	1			T1	7		T2	45		T3	1
valid_sources[0x64]	391	1			T1	1		T2	2		T7	8
valid_sources[0x65]	182	1			T1	1		T3	1		T7	5
valid_sources[0x66]	283	1			T1	2		T2	2		T3	1
valid_sources[0x67]	218	1			T1	2		T2	19		T7	7
valid_sources[0x68]	213	1			T1	2		T7	5		T6	2
valid_sources[0x69]	167	1			T1	4		T7	8		T6	1
valid_sources[0x6a]	259	1			T1	2		T7	15		T6	1
valid_sources[0x6b]	469	1			T2	7		T7	8		T6	2
valid_sources[0x6c]	225	1			T1	1		T2	1		T7	22
valid_sources[0x6d]	297	1			T1	7		T2	9		T7	19
valid_sources[0x6e]	226	1			T1	2		T3	1		T7	7
valid_sources[0x6f]	284	1			T1	7		T3	1		T7	15
valid_sources[0x70]	256	1			T1	4		T2	3		T7	7
valid_sources[0x71]	242	1			T1	4		T2	27		T3	3
valid_sources[0x72]	495	1			T1	7		T3	3		T7	9
valid_sources[0x73]	205	1			T1	2		T2	5		T3	1
valid_sources[0x74]	286	1			T3	1		T7	12		T16	1
valid_sources[0x75]	241	1			T1	4		T2	10		T7	13
valid_sources[0x76]	225	1			T2	9		T7	18		T6	3
valid_sources[0x77]	220	1			T1	2		T2	16		T7	7
valid_sources[0x78]	484	1			T1	2		T2	14		T7	10
valid_sources[0x79]	401	1			T1	2		T3	1		T7	6
valid_sources[0x7a]	307	1			T2	6		T7	7		T6	4
valid_sources[0x7b]	368	1			T1	2		T2	8		T3	1
valid_sources[0x7c]	239	1			T1	2		T2	23		T7	11
valid_sources[0x7d]	200	1			T1	5		T7	13		T6	6
valid_sources[0x7e]	313	1			T1	2		T7	15		T16	1
valid_sources[0x7f]	337	1			T1	1		T7	10		T6	1
valid_sources[0x80]	204	1			T1	3		T2	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16752

1

T1

363

T2

137

T3

17

values[0x0]

all_enables

biggest_size

13379

1

T1

7

T2

215

T3

28

values[0x1]

all_enables

biggest_size

12527

1

T1

13

T2

221

T3

16