Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.30	0.00	0.00	93.91				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	581227	0	0	0
ctrl_rd_A	581227	2056	0	0
host_fifo_config_rd_A	581227	1105	0	0
host_nack_handler_timeout_rd_A	581227	1207	0	0
host_timeout_ctrl_rd_A	581227	989	0	0
intr_enable_rd_A	581227	3890	0	0
ovrd_rd_A	581227	1337	0	0
target_fifo_config_rd_A	581227	1276	0	0
target_id_rd_A	581227	1683	0	0
target_timeout_ctrl_rd_A	581227	1131	0	0
timeout_ctrl_rd_A	581227	1361	0	0
timing0_rd_A	581227	1117	0	0
timing1_rd_A	581227	1084	0	0
timing2_rd_A	581227	1137	0	0
timing3_rd_A	581227	1111	0	0
timing4_rd_A	581227	1174	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	2056	0	0
T1	6907	57	0	0
T2	15588	243	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	47	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	39	0	0
T28	0	111	0	0
T29	0	55	0	0
T47	0	15	0	0
T48	0	4	0	0
T49	0	356	0	0
T50	0	119	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1105	0	0
T1	6907	87	0	0
T2	15588	63	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	8	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	18	0	0
T28	0	118	0	0
T29	0	11	0	0
T48	0	4	0	0
T49	0	156	0	0
T50	0	7	0	0
T51	0	4	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1207	0	0
T1	6907	55	0	0
T2	15588	112	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	22	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	14	0	0
T28	0	107	0	0
T29	0	22	0	0
T47	0	8	0	0
T48	0	1	0	0
T49	0	148	0	0
T51	0	20	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	989	0	0
T1	6907	54	0	0
T2	15588	95	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	22	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	11	0	0
T28	0	102	0	0
T29	0	8	0	0
T47	0	22	0	0
T48	0	29	0	0
T49	0	58	0	0
T51	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	3890	0	0
T1	6907	66	0	0
T2	15588	596	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	8	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T15	0	7	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	26	0	0
T28	0	132	0	0
T29	0	59	0	0
T52	0	17	0	0
T53	0	13	0	0
T54	0	31	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1337	0	0
T1	6907	63	0	0
T2	15588	168	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	7	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T28	0	149	0	0
T29	0	3	0	0
T47	0	2	0	0
T48	0	17	0	0
T49	0	120	0	0
T50	0	38	0	0
T51	0	8	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1276	0	0
T1	6907	81	0	0
T2	15588	106	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	24	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	12	0	0
T28	0	167	0	0
T47	0	22	0	0
T48	0	13	0	0
T49	0	122	0	0
T50	0	50	0	0
T51	0	6	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1683	0	0
T1	6907	98	0	0
T2	15588	218	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	22	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	13	0	0
T28	0	137	0	0
T29	0	20	0	0
T47	0	16	0	0
T48	0	30	0	0
T49	0	202	0	0
T51	0	22	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1131	0	0
T1	6907	83	0	0
T2	15588	91	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	17	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	6	0	0
T28	0	81	0	0
T29	0	18	0	0
T47	0	18	0	0
T48	0	12	0	0
T49	0	144	0	0
T51	0	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1361	0	0
T1	6907	75	0	0
T2	15588	139	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	39	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	22	0	0
T28	0	67	0	0
T29	0	2	0	0
T47	0	16	0	0
T48	0	5	0	0
T49	0	165	0	0
T51	0	5	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1117	0	0
T1	6907	79	0	0
T2	15588	97	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	24	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	5	0	0
T28	0	117	0	0
T29	0	5	0	0
T47	0	13	0	0
T48	0	6	0	0
T49	0	103	0	0
T51	0	15	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1084	0	0
T1	6907	50	0	0
T2	15588	104	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	32	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	6	0	0
T28	0	122	0	0
T29	0	13	0	0
T47	0	37	0	0
T48	0	8	0	0
T49	0	84	0	0
T51	0	10	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1137	0	0
T1	6907	68	0	0
T2	15588	94	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	19	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	14	0	0
T28	0	109	0	0
T29	0	15	0	0
T47	0	6	0	0
T48	0	14	0	0
T49	0	127	0	0
T50	0	40	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1111	0	0
T1	6907	65	0	0
T2	15588	115	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	37	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	17	0	0
T28	0	100	0	0
T29	0	22	0	0
T47	0	5	0	0
T48	0	26	0	0
T49	0	118	0	0
T51	0	1	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581227	1174	0	0
T1	6907	53	0	0
T2	15588	112	0	0
T3	1749	0	0	0
T4	1666	0	0	0
T5	6373	0	0	0
T6	10275	23	0	0
T7	7310	0	0	0
T14	2908	0	0	0
T16	2295	0	0	0
T17	2057	0	0	0
T26	0	6	0	0
T28	0	121	0	0
T29	0	7	0	0
T47	0	12	0	0
T48	0	18	0	0
T49	0	138	0	0
T51	0	8	0	0