Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	341	1			T1	8		T2	1		T3	1
all_values[1]	341	1			T1	8		T2	1		T3	1
all_values[2]	341	1			T1	8		T2	1		T3	1
all_values[3]	341	1			T1	8		T2	1		T3	1
all_values[4]	341	1			T1	8		T2	1		T3	1
all_values[5]	341	1			T1	8		T2	1		T3	1
all_values[6]	341	1			T1	8		T2	1		T3	1
all_values[7]	341	1			T1	8		T2	1		T3	1
all_values[8]	341	1			T1	8		T2	1		T3	1
all_values[9]	341	1			T1	8		T2	1		T3	1
all_values[10]	341	1			T1	8		T2	1		T3	1
all_values[11]	341	1			T1	8		T2	1		T3	1
all_values[12]	341	1			T1	8		T2	1		T3	1
all_values[13]	341	1			T1	8		T2	1		T3	1
all_values[14]	341	1			T1	8		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3261

1

T1

73

T2

15

T3

15

auto[1]

1854

1

T1

47

T12

18

T10

59

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T1

17

T2

15

T3

15

auto[1]

4078

1

T1

103

T12

55

T10

112

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85	1			T1	2		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	142	1			T1	3		T10	5		T11	3
all_values[0]	auto[1]	auto[1]	114	1			T1	3		T10	3		T11	1
all_values[1]	auto[0]	auto[0]	54	1			T2	1		T3	1		T7	1
all_values[1]	auto[0]	auto[1]	176	1			T1	4		T12	2		T10	4
all_values[1]	auto[1]	auto[1]	111	1			T1	4		T12	1		T10	4
all_values[2]	auto[0]	auto[0]	72	1			T1	8		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	153	1			T12	3		T10	4		T11	2
all_values[2]	auto[1]	auto[1]	116	1			T12	2		T10	4		T11	3
all_values[3]	auto[0]	auto[0]	57	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	145	1			T1	4		T12	5		T10	3
all_values[3]	auto[1]	auto[1]	139	1			T1	3		T10	5		T13	1
all_values[4]	auto[0]	auto[0]	74	1			T2	1		T3	1		T7	1
all_values[4]	auto[0]	auto[1]	151	1			T1	7		T12	2		T10	4
all_values[4]	auto[1]	auto[1]	116	1			T1	1		T12	1		T10	4
all_values[5]	auto[0]	auto[0]	65	1			T2	1		T3	1		T7	1
all_values[5]	auto[0]	auto[1]	126	1			T1	3		T12	3		T10	5
all_values[5]	auto[1]	auto[1]	150	1			T1	5		T12	1		T10	3
all_values[6]	auto[0]	auto[0]	68	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	145	1			T1	3		T12	2		T10	4
all_values[6]	auto[1]	auto[1]	128	1			T1	4		T12	3		T10	3
all_values[7]	auto[0]	auto[0]	69	1			T2	1		T3	1		T7	1
all_values[7]	auto[0]	auto[1]	140	1			T1	4		T12	3		T10	1
all_values[7]	auto[1]	auto[1]	132	1			T1	4		T10	5		T11	4
all_values[8]	auto[0]	auto[0]	64	1			T2	1		T3	1		T7	1
all_values[8]	auto[0]	auto[1]	139	1			T1	4		T12	3		T10	3
all_values[8]	auto[1]	auto[1]	138	1			T1	4		T12	2		T10	5
all_values[9]	auto[0]	auto[0]	57	1			T2	1		T3	1		T7	1
all_values[9]	auto[0]	auto[1]	149	1			T1	4		T12	4		T10	3
all_values[9]	auto[1]	auto[1]	135	1			T1	4		T10	3		T11	4
all_values[10]	auto[0]	auto[0]	51	1			T2	1		T3	1		T7	1
all_values[10]	auto[0]	auto[1]	173	1			T1	4		T12	3		T10	4
all_values[10]	auto[1]	auto[1]	117	1			T1	4		T12	2		T10	4
all_values[11]	auto[0]	auto[0]	98	1			T1	1		T2	1		T3	1
all_values[11]	auto[0]	auto[1]	144	1			T1	6		T12	3		T10	4
all_values[11]	auto[1]	auto[1]	99	1			T1	1		T12	2		T10	3
all_values[12]	auto[0]	auto[0]	69	1			T2	1		T3	1		T7	1
all_values[12]	auto[0]	auto[1]	165	1			T1	4		T10	4		T11	3
all_values[12]	auto[1]	auto[1]	107	1			T1	4		T10	4		T11	2
all_values[13]	auto[0]	auto[0]	79	1			T2	1		T3	1		T7	1
all_values[13]	auto[0]	auto[1]	121	1			T1	3		T12	1		T10	4
all_values[13]	auto[1]	auto[1]	141	1			T1	5		T12	2		T10	4
all_values[14]	auto[0]	auto[0]	75	1			T1	4		T2	1		T3	1
all_values[14]	auto[0]	auto[1]	155	1			T1	3		T12	3		T10	1
all_values[14]	auto[1]	auto[1]	111	1			T1	1		T12	2		T10	5