Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
52.65	40.66	40.72	90.72	0.00	42.98	99.68	53.79

Total tests in report: 165

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
44.85	44.85	39.00	39.00	36.96	36.96	93.80	93.80	0.00	0.00	41.70	41.70	91.72	91.72	10.74	10.74	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3844348471
49.90	5.06	40.20	1.19	39.14	2.18	97.02	3.23	0.00	0.00	42.91	1.21	92.04	0.32	38.00	27.26	/workspace/coverage/cover_reg_top/19.i2c_intr_test.652157212
52.07	2.17	40.20	0.00	39.93	0.79	97.02	0.00	0.00	0.00	42.98	0.07	96.82	4.78	47.58	9.58	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2849946032
52.55	0.48	40.66	0.46	40.05	0.11	97.02	0.00	0.00	0.00	42.98	0.00	99.36	2.55	47.79	0.21	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1847984435
52.84	0.29	40.66	0.00	40.05	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.36	0.00	49.79	2.00	/workspace/coverage/cover_reg_top/46.i2c_intr_test.1176831183
52.99	0.15	40.66	0.00	40.05	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.36	0.00	50.84	1.05	/workspace/coverage/cover_reg_top/32.i2c_intr_test.2701994928
53.13	0.14	40.66	0.00	40.08	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.36	0.00	51.79	0.95	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1047503973
53.23	0.11	40.66	0.00	40.08	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.32	52.21	0.42	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2314313379
53.31	0.08	40.66	0.00	40.08	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	52.74	0.53	/workspace/coverage/cover_reg_top/14.i2c_intr_test.3180957543
53.35	0.05	40.66	0.00	40.08	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.05	0.32	/workspace/coverage/cover_reg_top/12.i2c_intr_test.3099995991
53.39	0.03	40.66	0.00	40.31	0.23	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.05	0.00	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.539980829
53.42	0.03	40.66	0.00	40.31	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.26	0.21	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1487673135
53.45	0.03	40.66	0.00	40.31	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.47	0.21	/workspace/coverage/cover_reg_top/21.i2c_intr_test.3248900389
53.47	0.03	40.66	0.00	40.38	0.08	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.58	0.11	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2129631214
53.49	0.02	40.66	0.00	40.50	0.11	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.58	0.00	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1839814939
53.50	0.02	40.66	0.00	40.50	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.68	0.11	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2986891789
53.52	0.02	40.66	0.00	40.50	0.00	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.11	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2621154049
53.53	0.01	40.66	0.00	40.57	0.08	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.00	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3245925794
53.54	0.01	40.66	0.00	40.65	0.08	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.00	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.365998789
53.54	0.01	40.66	0.00	40.68	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.00	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2067371253
53.55	0.01	40.66	0.00	40.72	0.04	97.02	0.00	0.00	0.00	42.98	0.00	99.68	0.00	53.79	0.00	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3025462073

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2891869601
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3604751300
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1990105719
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1213413176
/workspace/coverage/cover_reg_top/0.i2c_intr_test.266109844
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.3078996538
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2707866969
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3964842128
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3326566706
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1640733436
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.3360578019
/workspace/coverage/cover_reg_top/1.i2c_intr_test.2523570104
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3508472942
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3287322522
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.249500564
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1417550794
/workspace/coverage/cover_reg_top/10.i2c_intr_test.2867645634
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3696448813
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2089184728
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1319060225
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3722071946
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.1492344450
/workspace/coverage/cover_reg_top/11.i2c_intr_test.1904492646
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2563379114
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.2905854261
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2742899047
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.503598435
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4009074800
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1628778666
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.1043319606
/workspace/coverage/cover_reg_top/13.i2c_intr_test.2483491756
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3134716314
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.968494212
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.258581275
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.3397487328
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4152751010
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2841563939
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4095583318
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3164503813
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2380519479
/workspace/coverage/cover_reg_top/15.i2c_intr_test.1271477672
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.187628127
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3553334009
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2788287656
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1307832696
/workspace/coverage/cover_reg_top/16.i2c_intr_test.1899380918
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3712703472
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2418912115
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1159479018
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1412322039
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.591371192
/workspace/coverage/cover_reg_top/17.i2c_intr_test.3539298467
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3790945541
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3998007113
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.664271355
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.265588196
/workspace/coverage/cover_reg_top/18.i2c_intr_test.3625343926
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3627655909
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3013297676
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.890100568
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2680849391
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.1074166585
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1519180050
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2444236304
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1648141382
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2123973176
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1758796420
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1015910085
/workspace/coverage/cover_reg_top/2.i2c_intr_test.633041111
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2780716970
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3483625405
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3074969483
/workspace/coverage/cover_reg_top/20.i2c_intr_test.3095630954
/workspace/coverage/cover_reg_top/22.i2c_intr_test.259054579
/workspace/coverage/cover_reg_top/23.i2c_intr_test.3495050684
/workspace/coverage/cover_reg_top/24.i2c_intr_test.3744657870
/workspace/coverage/cover_reg_top/25.i2c_intr_test.1536787895
/workspace/coverage/cover_reg_top/26.i2c_intr_test.322017612
/workspace/coverage/cover_reg_top/27.i2c_intr_test.2876834102
/workspace/coverage/cover_reg_top/28.i2c_intr_test.187808399
/workspace/coverage/cover_reg_top/29.i2c_intr_test.3897448451
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3313089419
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3773350378
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.536091424
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2137265714
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2002881795
/workspace/coverage/cover_reg_top/3.i2c_intr_test.3618932955
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3053829497
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.1640725633
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.46050610
/workspace/coverage/cover_reg_top/30.i2c_intr_test.4224336867
/workspace/coverage/cover_reg_top/31.i2c_intr_test.1449908795
/workspace/coverage/cover_reg_top/33.i2c_intr_test.1402750631
/workspace/coverage/cover_reg_top/34.i2c_intr_test.3348282011
/workspace/coverage/cover_reg_top/35.i2c_intr_test.517408744
/workspace/coverage/cover_reg_top/36.i2c_intr_test.2834522115
/workspace/coverage/cover_reg_top/37.i2c_intr_test.573420128
/workspace/coverage/cover_reg_top/38.i2c_intr_test.3640622046
/workspace/coverage/cover_reg_top/39.i2c_intr_test.761613880
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.4064194697
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2182734347
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3660857403
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2124469939
/workspace/coverage/cover_reg_top/4.i2c_intr_test.3392833062
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1854052576
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.918342290
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.445285440
/workspace/coverage/cover_reg_top/40.i2c_intr_test.2854015968
/workspace/coverage/cover_reg_top/41.i2c_intr_test.1524934012
/workspace/coverage/cover_reg_top/42.i2c_intr_test.3107841497
/workspace/coverage/cover_reg_top/43.i2c_intr_test.1101408545
/workspace/coverage/cover_reg_top/44.i2c_intr_test.1351043059
/workspace/coverage/cover_reg_top/45.i2c_intr_test.2061965622
/workspace/coverage/cover_reg_top/47.i2c_intr_test.1756878292
/workspace/coverage/cover_reg_top/48.i2c_intr_test.2447857766
/workspace/coverage/cover_reg_top/49.i2c_intr_test.1790283249
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3830443971
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.675928040
/workspace/coverage/cover_reg_top/5.i2c_intr_test.659108777
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.3426514105
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1469624360
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.61280387
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.2770415126
/workspace/coverage/cover_reg_top/6.i2c_intr_test.1167600249
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.377578377
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1845445448
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2315443363
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.1831493456
/workspace/coverage/cover_reg_top/7.i2c_intr_test.4155151966
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1705442256
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.3419824665
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3843598732
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4100808672
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.939714334
/workspace/coverage/cover_reg_top/8.i2c_intr_test.113125095
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2904985317
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2984676519
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2003981012
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2609874544
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1580878608
/workspace/coverage/cover_reg_top/9.i2c_intr_test.2383510673
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1621682643
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3143801673
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.720491707

Total test records in report: 165

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/11.i2c_intr_test.1904492646	Jul 05 04:42:25 PM PDT 24	Jul 05 04:42:27 PM PDT 24	41985196 ps
T2	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.539980829	Jul 05 04:42:27 PM PDT 24	Jul 05 04:42:32 PM PDT 24	135326266 ps
T3	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2849946032	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:39 PM PDT 24	105258776 ps
T7	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2984676519	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:33 PM PDT 24	32388829 ps
T4	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3844348471	Jul 05 04:42:11 PM PDT 24	Jul 05 04:42:16 PM PDT 24	460989265 ps
T8	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.2905854261	Jul 05 04:42:28 PM PDT 24	Jul 05 04:42:31 PM PDT 24	119727269 ps
T14	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.187628127	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:40 PM PDT 24	308284691 ps
T5	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.61280387	Jul 05 04:42:27 PM PDT 24	Jul 05 04:42:30 PM PDT 24	121856432 ps
T12	/workspace/coverage/cover_reg_top/37.i2c_intr_test.573420128	Jul 05 04:42:36 PM PDT 24	Jul 05 04:42:40 PM PDT 24	39495922 ps
T6	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3508472942	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:23 PM PDT 24	90146981 ps
T9	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3790945541	Jul 05 04:42:39 PM PDT 24	Jul 05 04:42:44 PM PDT 24	152719477 ps
T10	/workspace/coverage/cover_reg_top/19.i2c_intr_test.652157212	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:40 PM PDT 24	26964345 ps
T15	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1047503973	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:24 PM PDT 24	501710295 ps
T16	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3722071946	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:32 PM PDT 24	91172045 ps
T17	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2788287656	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:37 PM PDT 24	182617234 ps
T19	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.1043319606	Jul 05 04:42:30 PM PDT 24	Jul 05 04:42:33 PM PDT 24	49783679 ps
T18	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1990105719	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:22 PM PDT 24	37169570 ps
T27	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2129631214	Jul 05 04:42:36 PM PDT 24	Jul 05 04:42:43 PM PDT 24	667570970 ps
T20	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.536091424	Jul 05 04:42:20 PM PDT 24	Jul 05 04:42:23 PM PDT 24	22209848 ps
T21	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1307832696	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:37 PM PDT 24	58765895 ps
T11	/workspace/coverage/cover_reg_top/24.i2c_intr_test.3744657870	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:38 PM PDT 24	46237863 ps
T13	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1524934012	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:40 PM PDT 24	18051502 ps
T28	/workspace/coverage/cover_reg_top/32.i2c_intr_test.2701994928	Jul 05 04:42:37 PM PDT 24	Jul 05 04:42:41 PM PDT 24	20269649 ps
T29	/workspace/coverage/cover_reg_top/2.i2c_intr_test.633041111	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:22 PM PDT 24	20818770 ps
T22	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4152751010	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:39 PM PDT 24	186019679 ps
T37	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.1640725633	Jul 05 04:42:22 PM PDT 24	Jul 05 04:42:26 PM PDT 24	51646923 ps
T38	/workspace/coverage/cover_reg_top/46.i2c_intr_test.1176831183	Jul 05 04:42:41 PM PDT 24	Jul 05 04:42:44 PM PDT 24	32455652 ps
T39	/workspace/coverage/cover_reg_top/14.i2c_intr_test.3180957543	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:37 PM PDT 24	20211263 ps
T44	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4100808672	Jul 05 04:42:27 PM PDT 24	Jul 05 04:42:30 PM PDT 24	112826992 ps
T43	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3604751300	Jul 05 04:42:13 PM PDT 24	Jul 05 04:42:21 PM PDT 24	352785473 ps
T40	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.377578377	Jul 05 04:42:25 PM PDT 24	Jul 05 04:42:27 PM PDT 24	60398608 ps
T71	/workspace/coverage/cover_reg_top/33.i2c_intr_test.1402750631	Jul 05 04:42:36 PM PDT 24	Jul 05 04:42:40 PM PDT 24	18101980 ps
T54	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1159479018	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:36 PM PDT 24	68153249 ps
T47	/workspace/coverage/cover_reg_top/4.i2c_intr_test.3392833062	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:22 PM PDT 24	18762517 ps
T48	/workspace/coverage/cover_reg_top/49.i2c_intr_test.1790283249	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:36 PM PDT 24	29441059 ps
T77	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2315443363	Jul 05 04:42:28 PM PDT 24	Jul 05 04:42:31 PM PDT 24	26846803 ps
T50	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1839814939	Jul 05 04:42:25 PM PDT 24	Jul 05 04:42:28 PM PDT 24	303108548 ps
T74	/workspace/coverage/cover_reg_top/12.i2c_intr_test.3099995991	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:36 PM PDT 24	42156124 ps
T78	/workspace/coverage/cover_reg_top/13.i2c_intr_test.2483491756	Jul 05 04:42:26 PM PDT 24	Jul 05 04:42:28 PM PDT 24	104660496 ps
T23	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1847984435	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:22 PM PDT 24	45342209 ps
T41	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2780716970	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:22 PM PDT 24	106115991 ps
T79	/workspace/coverage/cover_reg_top/34.i2c_intr_test.3348282011	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:34 PM PDT 24	43164109 ps
T53	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3998007113	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:41 PM PDT 24	88839925 ps
T75	/workspace/coverage/cover_reg_top/48.i2c_intr_test.2447857766	Jul 05 04:42:43 PM PDT 24	Jul 05 04:42:45 PM PDT 24	16738758 ps
T80	/workspace/coverage/cover_reg_top/16.i2c_intr_test.1899380918	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:37 PM PDT 24	24719859 ps
T42	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1854052576	Jul 05 04:42:23 PM PDT 24	Jul 05 04:42:25 PM PDT 24	33287216 ps
T51	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4095583318	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:36 PM PDT 24	62211629 ps
T81	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2418912115	Jul 05 04:42:32 PM PDT 24	Jul 05 04:42:34 PM PDT 24	65077323 ps
T76	/workspace/coverage/cover_reg_top/17.i2c_intr_test.3539298467	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:38 PM PDT 24	21175526 ps
T24	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2444236304	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:24 PM PDT 24	188167838 ps
T82	/workspace/coverage/cover_reg_top/44.i2c_intr_test.1351043059	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:38 PM PDT 24	17680899 ps
T83	/workspace/coverage/cover_reg_top/40.i2c_intr_test.2854015968	Jul 05 04:42:32 PM PDT 24	Jul 05 04:42:33 PM PDT 24	16057267 ps
T84	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1167600249	Jul 05 04:42:25 PM PDT 24	Jul 05 04:42:27 PM PDT 24	21679780 ps
T58	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.445285440	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:23 PM PDT 24	233799674 ps
T85	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2137265714	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:21 PM PDT 24	107310186 ps
T86	/workspace/coverage/cover_reg_top/26.i2c_intr_test.322017612	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:39 PM PDT 24	24032212 ps
T87	/workspace/coverage/cover_reg_top/31.i2c_intr_test.1449908795	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:40 PM PDT 24	26157989 ps
T88	/workspace/coverage/cover_reg_top/22.i2c_intr_test.259054579	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:34 PM PDT 24	27032098 ps
T89	/workspace/coverage/cover_reg_top/1.i2c_intr_test.2523570104	Jul 05 04:42:17 PM PDT 24	Jul 05 04:42:21 PM PDT 24	42963570 ps
T25	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2314313379	Jul 05 04:42:25 PM PDT 24	Jul 05 04:42:28 PM PDT 24	241419947 ps
T55	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.365998789	Jul 05 04:42:45 PM PDT 24	Jul 05 04:42:48 PM PDT 24	259983172 ps
T90	/workspace/coverage/cover_reg_top/23.i2c_intr_test.3495050684	Jul 05 04:42:36 PM PDT 24	Jul 05 04:42:40 PM PDT 24	50286792 ps
T91	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3660857403	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:22 PM PDT 24	34640776 ps
T26	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.3360578019	Jul 05 04:42:23 PM PDT 24	Jul 05 04:42:25 PM PDT 24	18192821 ps
T92	/workspace/coverage/cover_reg_top/38.i2c_intr_test.3640622046	Jul 05 04:42:48 PM PDT 24	Jul 05 04:42:51 PM PDT 24	21210384 ps
T93	/workspace/coverage/cover_reg_top/10.i2c_intr_test.2867645634	Jul 05 04:42:26 PM PDT 24	Jul 05 04:42:28 PM PDT 24	17284683 ps
T94	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1412322039	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:40 PM PDT 24	24978766 ps
T95	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3627655909	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:40 PM PDT 24	209934781 ps
T72	/workspace/coverage/cover_reg_top/35.i2c_intr_test.517408744	Jul 05 04:42:37 PM PDT 24	Jul 05 04:42:42 PM PDT 24	44829242 ps
T45	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.3426514105	Jul 05 04:42:26 PM PDT 24	Jul 05 04:42:29 PM PDT 24	126381784 ps
T64	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3553334009	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:36 PM PDT 24	691125031 ps
T96	/workspace/coverage/cover_reg_top/25.i2c_intr_test.1536787895	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:38 PM PDT 24	38966131 ps
T97	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2182734347	Jul 05 04:42:23 PM PDT 24	Jul 05 04:42:27 PM PDT 24	65951961 ps
T98	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3964842128	Jul 05 04:42:22 PM PDT 24	Jul 05 04:42:26 PM PDT 24	124173475 ps
T46	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1758796420	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:22 PM PDT 24	71937201 ps
T56	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1519180050	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:37 PM PDT 24	82053141 ps
T99	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.503598435	Jul 05 04:42:26 PM PDT 24	Jul 05 04:42:31 PM PDT 24	110646542 ps
T100	/workspace/coverage/cover_reg_top/5.i2c_intr_test.659108777	Jul 05 04:42:24 PM PDT 24	Jul 05 04:42:26 PM PDT 24	26918646 ps
T30	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2707866969	Jul 05 04:42:23 PM PDT 24	Jul 05 04:42:26 PM PDT 24	359063684 ps
T49	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2841563939	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:40 PM PDT 24	122511283 ps
T59	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.720491707	Jul 05 04:42:25 PM PDT 24	Jul 05 04:42:28 PM PDT 24	79807004 ps
T101	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.258581275	Jul 05 04:42:47 PM PDT 24	Jul 05 04:42:51 PM PDT 24	124965288 ps
T73	/workspace/coverage/cover_reg_top/36.i2c_intr_test.2834522115	Jul 05 04:42:46 PM PDT 24	Jul 05 04:42:49 PM PDT 24	40016222 ps
T52	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3053829497	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:23 PM PDT 24	20056915 ps
T70	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2986891789	Jul 05 04:42:11 PM PDT 24	Jul 05 04:42:14 PM PDT 24	57445090 ps
T102	/workspace/coverage/cover_reg_top/0.i2c_intr_test.266109844	Jul 05 04:42:13 PM PDT 24	Jul 05 04:42:16 PM PDT 24	49677939 ps
T66	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2904985317	Jul 05 04:42:25 PM PDT 24	Jul 05 04:42:30 PM PDT 24	1527947969 ps
T103	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.664271355	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:37 PM PDT 24	30049268 ps
T104	/workspace/coverage/cover_reg_top/29.i2c_intr_test.3897448451	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:35 PM PDT 24	123277021 ps
T105	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.3419824665	Jul 05 04:42:24 PM PDT 24	Jul 05 04:42:26 PM PDT 24	49473963 ps
T31	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2380519479	Jul 05 04:42:37 PM PDT 24	Jul 05 04:42:42 PM PDT 24	19379425 ps
T106	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1271477672	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:38 PM PDT 24	14629626 ps
T32	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1417550794	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:37 PM PDT 24	26279406 ps
T107	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.3078996538	Jul 05 04:42:16 PM PDT 24	Jul 05 04:42:20 PM PDT 24	473535194 ps
T108	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.1074166585	Jul 05 04:42:38 PM PDT 24	Jul 05 04:42:44 PM PDT 24	306219919 ps
T109	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.591371192	Jul 05 04:42:37 PM PDT 24	Jul 05 04:42:41 PM PDT 24	24270818 ps
T110	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1705442256	Jul 05 04:42:25 PM PDT 24	Jul 05 04:42:27 PM PDT 24	21182811 ps
T111	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2124469939	Jul 05 04:42:21 PM PDT 24	Jul 05 04:42:24 PM PDT 24	76440183 ps
T112	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3326566706	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:21 PM PDT 24	59340807 ps
T62	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2067371253	Jul 05 04:42:27 PM PDT 24	Jul 05 04:42:30 PM PDT 24	48466696 ps
T113	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.918342290	Jul 05 04:42:24 PM PDT 24	Jul 05 04:42:28 PM PDT 24	465286898 ps
T114	/workspace/coverage/cover_reg_top/45.i2c_intr_test.2061965622	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:38 PM PDT 24	20134747 ps
T33	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1015910085	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:22 PM PDT 24	16947905 ps
T34	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.3397487328	Jul 05 04:42:47 PM PDT 24	Jul 05 04:42:50 PM PDT 24	42858387 ps
T115	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3134716314	Jul 05 04:42:30 PM PDT 24	Jul 05 04:42:33 PM PDT 24	70548830 ps
T67	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1621682643	Jul 05 04:42:28 PM PDT 24	Jul 05 04:42:31 PM PDT 24	172761413 ps
T35	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2891869601	Jul 05 04:42:08 PM PDT 24	Jul 05 04:42:12 PM PDT 24	27360341 ps
T116	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1640733436	Jul 05 04:42:22 PM PDT 24	Jul 05 04:42:25 PM PDT 24	120434326 ps
T36	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.4064194697	Jul 05 04:42:16 PM PDT 24	Jul 05 04:42:20 PM PDT 24	469283383 ps
T117	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2089184728	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:34 PM PDT 24	125057214 ps
T118	/workspace/coverage/cover_reg_top/8.i2c_intr_test.113125095	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:36 PM PDT 24	62177705 ps
T119	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2002881795	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:22 PM PDT 24	30029510 ps
T63	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.46050610	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:23 PM PDT 24	286622927 ps
T120	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3287322522	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:22 PM PDT 24	195338558 ps
T121	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1580878608	Jul 05 04:42:26 PM PDT 24	Jul 05 04:42:28 PM PDT 24	22111853 ps
T122	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3164503813	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:36 PM PDT 24	43140000 ps
T123	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.1492344450	Jul 05 04:42:28 PM PDT 24	Jul 05 04:42:31 PM PDT 24	31653451 ps
T57	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3025462073	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:34 PM PDT 24	260722968 ps
T124	/workspace/coverage/cover_reg_top/42.i2c_intr_test.3107841497	Jul 05 04:42:36 PM PDT 24	Jul 05 04:42:40 PM PDT 24	16021498 ps
T125	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3830443971	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:37 PM PDT 24	133274621 ps
T126	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.675928040	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:32 PM PDT 24	80621296 ps
T127	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.1831493456	Jul 05 04:42:24 PM PDT 24	Jul 05 04:42:26 PM PDT 24	37556311 ps
T128	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3696448813	Jul 05 04:42:27 PM PDT 24	Jul 05 04:42:31 PM PDT 24	151317172 ps
T129	/workspace/coverage/cover_reg_top/7.i2c_intr_test.4155151966	Jul 05 04:42:26 PM PDT 24	Jul 05 04:42:28 PM PDT 24	87531414 ps
T130	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.939714334	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:32 PM PDT 24	24036543 ps
T131	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.249500564	Jul 05 04:42:28 PM PDT 24	Jul 05 04:42:32 PM PDT 24	46676308 ps
T60	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3074969483	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:23 PM PDT 24	154660890 ps
T132	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1628778666	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:37 PM PDT 24	45138805 ps
T133	/workspace/coverage/cover_reg_top/21.i2c_intr_test.3248900389	Jul 05 04:42:38 PM PDT 24	Jul 05 04:42:42 PM PDT 24	37190408 ps
T134	/workspace/coverage/cover_reg_top/28.i2c_intr_test.187808399	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:39 PM PDT 24	34661633 ps
T135	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1469624360	Jul 05 04:42:27 PM PDT 24	Jul 05 04:42:31 PM PDT 24	47538790 ps
T136	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3143801673	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:32 PM PDT 24	67027959 ps
T137	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2003981012	Jul 05 04:42:27 PM PDT 24	Jul 05 04:42:32 PM PDT 24	190360271 ps
T68	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2680849391	Jul 05 04:42:36 PM PDT 24	Jul 05 04:42:40 PM PDT 24	33269116 ps
T138	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3773350378	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:23 PM PDT 24	186087774 ps
T139	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.968494212	Jul 05 04:42:25 PM PDT 24	Jul 05 04:42:28 PM PDT 24	289419416 ps
T140	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4009074800	Jul 05 04:42:26 PM PDT 24	Jul 05 04:42:29 PM PDT 24	234096041 ps
T141	/workspace/coverage/cover_reg_top/27.i2c_intr_test.2876834102	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:36 PM PDT 24	62637509 ps
T142	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2742899047	Jul 05 04:42:26 PM PDT 24	Jul 05 04:42:29 PM PDT 24	57082693 ps
T61	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3245925794	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:33 PM PDT 24	253455834 ps
T143	/workspace/coverage/cover_reg_top/39.i2c_intr_test.761613880	Jul 05 04:42:45 PM PDT 24	Jul 05 04:42:47 PM PDT 24	52231176 ps
T144	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1648141382	Jul 05 04:42:18 PM PDT 24	Jul 05 04:42:24 PM PDT 24	3303858921 ps
T145	/workspace/coverage/cover_reg_top/9.i2c_intr_test.2383510673	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:32 PM PDT 24	18638771 ps
T146	/workspace/coverage/cover_reg_top/3.i2c_intr_test.3618932955	Jul 05 04:42:23 PM PDT 24	Jul 05 04:42:25 PM PDT 24	16809090 ps
T147	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1213413176	Jul 05 04:42:17 PM PDT 24	Jul 05 04:42:20 PM PDT 24	43235419 ps
T148	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2123973176	Jul 05 04:42:19 PM PDT 24	Jul 05 04:42:22 PM PDT 24	29729430 ps
T149	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.265588196	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:39 PM PDT 24	16207720 ps
T150	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2609874544	Jul 05 04:42:28 PM PDT 24	Jul 05 04:42:32 PM PDT 24	24759881 ps
T151	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3313089419	Jul 05 04:42:17 PM PDT 24	Jul 05 04:42:21 PM PDT 24	101821993 ps
T69	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2621154049	Jul 05 04:42:13 PM PDT 24	Jul 05 04:42:16 PM PDT 24	25952186 ps
T152	/workspace/coverage/cover_reg_top/30.i2c_intr_test.4224336867	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:40 PM PDT 24	40790339 ps
T65	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1487673135	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:39 PM PDT 24	57224797 ps
T153	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1845445448	Jul 05 04:42:26 PM PDT 24	Jul 05 04:42:28 PM PDT 24	664110967 ps
T154	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3843598732	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:33 PM PDT 24	326439338 ps
T155	/workspace/coverage/cover_reg_top/47.i2c_intr_test.1756878292	Jul 05 04:42:41 PM PDT 24	Jul 05 04:42:44 PM PDT 24	20590082 ps
T156	/workspace/coverage/cover_reg_top/20.i2c_intr_test.3095630954	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:38 PM PDT 24	27248706 ps
T157	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3013297676	Jul 05 04:42:35 PM PDT 24	Jul 05 04:42:39 PM PDT 24	72618286 ps
T158	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.2770415126	Jul 05 04:42:28 PM PDT 24	Jul 05 04:42:31 PM PDT 24	16116910 ps
T159	/workspace/coverage/cover_reg_top/18.i2c_intr_test.3625343926	Jul 05 04:42:33 PM PDT 24	Jul 05 04:42:35 PM PDT 24	28377003 ps
T160	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1319060225	Jul 05 04:42:23 PM PDT 24	Jul 05 04:42:26 PM PDT 24	238072858 ps
T161	/workspace/coverage/cover_reg_top/43.i2c_intr_test.1101408545	Jul 05 04:42:36 PM PDT 24	Jul 05 04:42:40 PM PDT 24	45784372 ps
T162	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3712703472	Jul 05 04:42:36 PM PDT 24	Jul 05 04:42:41 PM PDT 24	69292127 ps
T163	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3483625405	Jul 05 04:42:17 PM PDT 24	Jul 05 04:42:21 PM PDT 24	68330173 ps
T164	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.890100568	Jul 05 04:42:34 PM PDT 24	Jul 05 04:42:38 PM PDT 24	29798421 ps
T165	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2563379114	Jul 05 04:42:29 PM PDT 24	Jul 05 04:42:33 PM PDT 24	65569902 ps

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3844348471
Short name	T4
Test name
Test status
Simulation time	460989265 ps
CPU time	2.2 seconds
Started	Jul 05 04:42:11 PM PDT 24
Finished	Jul 05 04:42:16 PM PDT 24
Peak memory	204476 kb
Host	smart-f81d1050-c7e0-44b7-844f-2cd8a2854af4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844348471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3844348471
Directory	/workspace/0.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_intr_test.652157212
Short name	T10
Test name
Test status
Simulation time	26964345 ps
CPU time	0.67 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204272 kb
Host	smart-8a8f129c-97c5-43bf-96c0-376860a30e64
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652157212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.652157212
Directory	/workspace/19.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_errors.2849946032
Short name	T3
Test name
Test status
Simulation time	105258776 ps
CPU time	2.25 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:39 PM PDT 24
Peak memory	204576 kb
Host	smart-d963a232-28aa-4091-b3dd-3802ed759f2e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849946032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2849946032
Directory	/workspace/18.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1847984435
Short name	T23
Test name
Test status
Simulation time	45342209 ps
CPU time	0.74 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204248 kb
Host	smart-fe3ea6f2-1010-441c-822b-b98d54832d8e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847984435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1847984435
Directory	/workspace/4.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/46.i2c_intr_test.1176831183
Short name	T38
Test name
Test status
Simulation time	32455652 ps
CPU time	0.66 seconds
Started	Jul 05 04:42:41 PM PDT 24
Finished	Jul 05 04:42:44 PM PDT 24
Peak memory	204260 kb
Host	smart-096d3027-c787-4c3c-9979-3c47dc7be6e6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176831183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1176831183
Directory	/workspace/46.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.i2c_intr_test.2701994928
Short name	T28
Test name
Test status
Simulation time	20269649 ps
CPU time	0.72 seconds
Started	Jul 05 04:42:37 PM PDT 24
Finished	Jul 05 04:42:41 PM PDT 24
Peak memory	204264 kb
Host	smart-a6c538f5-daf7-4333-bc7c-30f8c9e3953e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701994928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2701994928
Directory	/workspace/32.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1047503973
Short name	T15
Test name
Test status
Simulation time	501710295 ps
CPU time	2.13 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:24 PM PDT 24
Peak memory	204508 kb
Host	smart-99ac2712-1a2f-4824-94dc-1d550deda0bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047503973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1047503973
Directory	/workspace/1.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2314313379
Short name	T25
Test name
Test status
Simulation time	241419947 ps
CPU time	1.22 seconds
Started	Jul 05 04:42:25 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204452 kb
Host	smart-982c6053-69b5-4695-9439-87f3959fe02e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314313379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.2314313379
Directory	/workspace/5.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_intr_test.3180957543
Short name	T39
Test name
Test status
Simulation time	20211263 ps
CPU time	0.65 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:37 PM PDT 24
Peak memory	204260 kb
Host	smart-d431942e-b766-49b0-8c7c-42127b91b62e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180957543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3180957543
Directory	/workspace/14.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_intr_test.3099995991
Short name	T74
Test name
Test status
Simulation time	42156124 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:36 PM PDT 24
Peak memory	204288 kb
Host	smart-a777a5d3-cffd-470f-be51-c6ec65fe54b6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099995991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3099995991
Directory	/workspace/12.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_errors.539980829
Short name	T2
Test name
Test status
Simulation time	135326266 ps
CPU time	2.77 seconds
Started	Jul 05 04:42:27 PM PDT 24
Finished	Jul 05 04:42:32 PM PDT 24
Peak memory	204604 kb
Host	smart-e8b1db1b-fd1a-44aa-bc17-aa9dc13377b5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539980829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.539980829
Directory	/workspace/11.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1487673135
Short name	T65
Test name
Test status
Simulation time	57224797 ps
CPU time	1.14 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:39 PM PDT 24
Peak memory	204500 kb
Host	smart-0c1bfcba-b1c9-4159-b052-eb3305a467e9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487673135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.1487673135
Directory	/workspace/15.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/21.i2c_intr_test.3248900389
Short name	T133
Test name
Test status
Simulation time	37190408 ps
CPU time	0.73 seconds
Started	Jul 05 04:42:38 PM PDT 24
Finished	Jul 05 04:42:42 PM PDT 24
Peak memory	204260 kb
Host	smart-9e19d623-4a11-4146-9434-48c1b26e5fa0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248900389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3248900389
Directory	/workspace/21.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2129631214
Short name	T27
Test name
Test status
Simulation time	667570970 ps
CPU time	2.24 seconds
Started	Jul 05 04:42:36 PM PDT 24
Finished	Jul 05 04:42:43 PM PDT 24
Peak memory	204556 kb
Host	smart-78827a7d-c2d5-4352-8641-933cc2ae4b64
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129631214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2129631214
Directory	/workspace/17.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1839814939
Short name	T50
Test name
Test status
Simulation time	303108548 ps
CPU time	1.03 seconds
Started	Jul 05 04:42:25 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204400 kb
Host	smart-8cf0fbb4-314b-4ecf-a28b-11b1ad3f3ffe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839814939 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1839814939
Directory	/workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2986891789
Short name	T70
Test name
Test status
Simulation time	57445090 ps
CPU time	0.71 seconds
Started	Jul 05 04:42:11 PM PDT 24
Finished	Jul 05 04:42:14 PM PDT 24
Peak memory	204180 kb
Host	smart-5d107c24-8cca-4b34-958e-acc7e89a1c67
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986891789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2986891789
Directory	/workspace/0.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2621154049
Short name	T69
Test name
Test status
Simulation time	25952186 ps
CPU time	0.81 seconds
Started	Jul 05 04:42:13 PM PDT 24
Finished	Jul 05 04:42:16 PM PDT 24
Peak memory	204288 kb
Host	smart-58cb45ee-8806-455b-bbf5-a1e4a83751ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621154049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou tstanding.2621154049
Directory	/workspace/0.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3245925794
Short name	T61
Test name
Test status
Simulation time	253455834 ps
CPU time	1.35 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:33 PM PDT 24
Peak memory	204508 kb
Host	smart-073c4a38-4e0a-4ed1-bb64-22cd1e8009b8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245925794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3245925794
Directory	/workspace/13.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.365998789
Short name	T55
Test name
Test status
Simulation time	259983172 ps
CPU time	2.26 seconds
Started	Jul 05 04:42:45 PM PDT 24
Finished	Jul 05 04:42:48 PM PDT 24
Peak memory	204540 kb
Host	smart-c3f63fad-98fa-4dd7-ad2d-23f41f11f941
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365998789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.365998789
Directory	/workspace/18.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2067371253
Short name	T62
Test name
Test status
Simulation time	48466696 ps
CPU time	1.4 seconds
Started	Jul 05 04:42:27 PM PDT 24
Finished	Jul 05 04:42:30 PM PDT 24
Peak memory	204492 kb
Host	smart-860dc713-3b9b-4c91-aae5-73c678296b54
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067371253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2067371253
Directory	/workspace/11.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3025462073
Short name	T57
Test name
Test status
Simulation time	260722968 ps
CPU time	2.36 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:34 PM PDT 24
Peak memory	204556 kb
Host	smart-53f048a8-92f7-42ca-ae05-e226aeda4c92
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025462073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3025462073
Directory	/workspace/6.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2891869601
Short name	T35
Test name
Test status
Simulation time	27360341 ps
CPU time	1.19 seconds
Started	Jul 05 04:42:08 PM PDT 24
Finished	Jul 05 04:42:12 PM PDT 24
Peak memory	204456 kb
Host	smart-71f05a11-8d8f-4be2-8aba-4fb351245b8d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891869601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2891869601
Directory	/workspace/0.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3604751300
Short name	T43
Test name
Test status
Simulation time	352785473 ps
CPU time	5.22 seconds
Started	Jul 05 04:42:13 PM PDT 24
Finished	Jul 05 04:42:21 PM PDT 24
Peak memory	204452 kb
Host	smart-5577eb8c-f1ae-4b5f-b55b-f397b0007585
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604751300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3604751300
Directory	/workspace/0.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1990105719
Short name	T18
Test name
Test status
Simulation time	37169570 ps
CPU time	1.06 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204292 kb
Host	smart-dea5708f-e6ac-48ba-a5da-14f14b3bb7fe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990105719 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1990105719
Directory	/workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1213413176
Short name	T147
Test name
Test status
Simulation time	43235419 ps
CPU time	0.67 seconds
Started	Jul 05 04:42:17 PM PDT 24
Finished	Jul 05 04:42:20 PM PDT 24
Peak memory	204208 kb
Host	smart-8dd23175-57c4-4ac3-8744-be49e77a5523
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213413176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1213413176
Directory	/workspace/0.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_intr_test.266109844
Short name	T102
Test name
Test status
Simulation time	49677939 ps
CPU time	0.73 seconds
Started	Jul 05 04:42:13 PM PDT 24
Finished	Jul 05 04:42:16 PM PDT 24
Peak memory	204200 kb
Host	smart-2029f09f-62cc-4214-9199-711b9028bf8b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266109844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.266109844
Directory	/workspace/0.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.i2c_tl_errors.3078996538
Short name	T107
Test name
Test status
Simulation time	473535194 ps
CPU time	2.6 seconds
Started	Jul 05 04:42:16 PM PDT 24
Finished	Jul 05 04:42:20 PM PDT 24
Peak memory	212648 kb
Host	smart-137b0e5d-675b-4154-a634-272f83c0e89e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078996538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3078996538
Directory	/workspace/0.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2707866969
Short name	T30
Test name
Test status
Simulation time	359063684 ps
CPU time	1.97 seconds
Started	Jul 05 04:42:23 PM PDT 24
Finished	Jul 05 04:42:26 PM PDT 24
Peak memory	204488 kb
Host	smart-fec15ea4-5d6a-48b0-806f-6faac369217f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707866969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2707866969
Directory	/workspace/1.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3964842128
Short name	T98
Test name
Test status
Simulation time	124173475 ps
CPU time	2.47 seconds
Started	Jul 05 04:42:22 PM PDT 24
Finished	Jul 05 04:42:26 PM PDT 24
Peak memory	204352 kb
Host	smart-bf9ad867-dd60-4c21-a844-d3bb8dbd47bc
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964842128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3964842128
Directory	/workspace/1.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3326566706
Short name	T112
Test name
Test status
Simulation time	59340807 ps
CPU time	0.66 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:21 PM PDT 24
Peak memory	204228 kb
Host	smart-ce5d88cf-c16e-424c-9833-12a2814a7def
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326566706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3326566706
Directory	/workspace/1.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1640733436
Short name	T116
Test name
Test status
Simulation time	120434326 ps
CPU time	1.12 seconds
Started	Jul 05 04:42:22 PM PDT 24
Finished	Jul 05 04:42:25 PM PDT 24
Peak memory	204484 kb
Host	smart-750959bd-8787-46a3-8762-196c44405241
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640733436 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1640733436
Directory	/workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_csr_rw.3360578019
Short name	T26
Test name
Test status
Simulation time	18192821 ps
CPU time	0.69 seconds
Started	Jul 05 04:42:23 PM PDT 24
Finished	Jul 05 04:42:25 PM PDT 24
Peak memory	204112 kb
Host	smart-ccd1f8fd-effe-4a63-9e9f-0c8c0b2b6d61
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360578019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3360578019
Directory	/workspace/1.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_intr_test.2523570104
Short name	T89
Test name
Test status
Simulation time	42963570 ps
CPU time	0.67 seconds
Started	Jul 05 04:42:17 PM PDT 24
Finished	Jul 05 04:42:21 PM PDT 24
Peak memory	204232 kb
Host	smart-8c45085e-da51-4e6f-b067-af45b067206e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523570104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2523570104
Directory	/workspace/1.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3508472942
Short name	T6
Test name
Test status
Simulation time	90146981 ps
CPU time	1.15 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:23 PM PDT 24
Peak memory	204536 kb
Host	smart-a0994e7a-78a0-4b78-b655-a97d9b1ad5e6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508472942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.3508472942
Directory	/workspace/1.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3287322522
Short name	T120
Test name
Test status
Simulation time	195338558 ps
CPU time	2.18 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204564 kb
Host	smart-2c29180e-c18d-484f-934d-c0b7f70bf6b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287322522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3287322522
Directory	/workspace/1.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.249500564
Short name	T131
Test name
Test status
Simulation time	46676308 ps
CPU time	0.83 seconds
Started	Jul 05 04:42:28 PM PDT 24
Finished	Jul 05 04:42:32 PM PDT 24
Peak memory	204292 kb
Host	smart-5c49697f-023a-4243-a019-29bc4ceb4ae2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249500564 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.249500564
Directory	/workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1417550794
Short name	T32
Test name
Test status
Simulation time	26279406 ps
CPU time	0.79 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:37 PM PDT 24
Peak memory	204272 kb
Host	smart-e46b7087-735e-4dff-a9f4-ee0e77eda6db
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417550794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1417550794
Directory	/workspace/10.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_intr_test.2867645634
Short name	T93
Test name
Test status
Simulation time	17284683 ps
CPU time	0.64 seconds
Started	Jul 05 04:42:26 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204256 kb
Host	smart-784def1f-41c3-4a22-8858-cfcbca922f7c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867645634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2867645634
Directory	/workspace/10.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3696448813
Short name	T128
Test name
Test status
Simulation time	151317172 ps
CPU time	1.16 seconds
Started	Jul 05 04:42:27 PM PDT 24
Finished	Jul 05 04:42:31 PM PDT 24
Peak memory	204468 kb
Host	smart-faaa8482-1c35-4028-9d37-81eb8442c083
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696448813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.3696448813
Directory	/workspace/10.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2089184728
Short name	T117
Test name
Test status
Simulation time	125057214 ps
CPU time	2.57 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:34 PM PDT 24
Peak memory	204644 kb
Host	smart-e3c7161a-8eec-4acc-a9f4-99e25dba8e6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089184728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2089184728
Directory	/workspace/10.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1319060225
Short name	T160
Test name
Test status
Simulation time	238072858 ps
CPU time	1.49 seconds
Started	Jul 05 04:42:23 PM PDT 24
Finished	Jul 05 04:42:26 PM PDT 24
Peak memory	204500 kb
Host	smart-c49f95ab-244b-401d-96dd-7b8a5ee36f8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319060225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1319060225
Directory	/workspace/10.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3722071946
Short name	T16
Test name
Test status
Simulation time	91172045 ps
CPU time	0.83 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:32 PM PDT 24
Peak memory	204316 kb
Host	smart-271ddff4-11b6-42d0-a100-f0c0bdf0824f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722071946 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3722071946
Directory	/workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_csr_rw.1492344450
Short name	T123
Test name
Test status
Simulation time	31653451 ps
CPU time	0.74 seconds
Started	Jul 05 04:42:28 PM PDT 24
Finished	Jul 05 04:42:31 PM PDT 24
Peak memory	204288 kb
Host	smart-6f7ebad0-16ec-4fae-acf5-b56d2438e9c5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492344450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1492344450
Directory	/workspace/11.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_intr_test.1904492646
Short name	T1
Test name
Test status
Simulation time	41985196 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:25 PM PDT 24
Finished	Jul 05 04:42:27 PM PDT 24
Peak memory	204272 kb
Host	smart-0b860ade-7a10-484d-92d4-221e0e10f94d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904492646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1904492646
Directory	/workspace/11.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2563379114
Short name	T165
Test name
Test status
Simulation time	65569902 ps
CPU time	0.89 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:33 PM PDT 24
Peak memory	204276 kb
Host	smart-c7076943-e8a9-4d23-8553-4f24fc5c1252
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563379114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o utstanding.2563379114
Directory	/workspace/11.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_csr_rw.2905854261
Short name	T8
Test name
Test status
Simulation time	119727269 ps
CPU time	0.81 seconds
Started	Jul 05 04:42:28 PM PDT 24
Finished	Jul 05 04:42:31 PM PDT 24
Peak memory	204240 kb
Host	smart-b4af15be-b524-480f-af8f-91630144b1dd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905854261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2905854261
Directory	/workspace/12.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2742899047
Short name	T142
Test name
Test status
Simulation time	57082693 ps
CPU time	1.1 seconds
Started	Jul 05 04:42:26 PM PDT 24
Finished	Jul 05 04:42:29 PM PDT 24
Peak memory	204472 kb
Host	smart-47655b93-adcc-492e-a670-39762b01c1b2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742899047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.2742899047
Directory	/workspace/12.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_errors.503598435
Short name	T99
Test name
Test status
Simulation time	110646542 ps
CPU time	2.45 seconds
Started	Jul 05 04:42:26 PM PDT 24
Finished	Jul 05 04:42:31 PM PDT 24
Peak memory	212720 kb
Host	smart-13ce25d4-d4b5-4523-a375-49120bf5b84c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503598435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.503598435
Directory	/workspace/12.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4009074800
Short name	T140
Test name
Test status
Simulation time	234096041 ps
CPU time	1.5 seconds
Started	Jul 05 04:42:26 PM PDT 24
Finished	Jul 05 04:42:29 PM PDT 24
Peak memory	204508 kb
Host	smart-8aa512bc-2797-46cd-a48e-5c524d569eac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009074800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4009074800
Directory	/workspace/12.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1628778666
Short name	T132
Test name
Test status
Simulation time	45138805 ps
CPU time	0.81 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:37 PM PDT 24
Peak memory	204300 kb
Host	smart-e09f6725-a742-41fc-a369-6fa2caaefd38
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628778666 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1628778666
Directory	/workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_csr_rw.1043319606
Short name	T19
Test name
Test status
Simulation time	49783679 ps
CPU time	0.83 seconds
Started	Jul 05 04:42:30 PM PDT 24
Finished	Jul 05 04:42:33 PM PDT 24
Peak memory	204264 kb
Host	smart-acb7516a-5aa5-4c87-940b-b12bae411da3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043319606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1043319606
Directory	/workspace/13.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_intr_test.2483491756
Short name	T78
Test name
Test status
Simulation time	104660496 ps
CPU time	0.64 seconds
Started	Jul 05 04:42:26 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204260 kb
Host	smart-0ad4ef96-0a9d-4fe2-bcfe-9a0e73e27572
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483491756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2483491756
Directory	/workspace/13.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3134716314
Short name	T115
Test name
Test status
Simulation time	70548830 ps
CPU time	1.27 seconds
Started	Jul 05 04:42:30 PM PDT 24
Finished	Jul 05 04:42:33 PM PDT 24
Peak memory	204524 kb
Host	smart-00e59d27-8458-4f53-9073-13e01a5551dd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134716314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.3134716314
Directory	/workspace/13.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.i2c_tl_errors.968494212
Short name	T139
Test name
Test status
Simulation time	289419416 ps
CPU time	1.63 seconds
Started	Jul 05 04:42:25 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204548 kb
Host	smart-ed7e6eef-3ff3-457c-862a-16df5369799e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968494212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.968494212
Directory	/workspace/13.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.258581275
Short name	T101
Test name
Test status
Simulation time	124965288 ps
CPU time	1.63 seconds
Started	Jul 05 04:42:47 PM PDT 24
Finished	Jul 05 04:42:51 PM PDT 24
Peak memory	204628 kb
Host	smart-7d145b5b-ec1c-4b34-86bc-b0ea598fa1fe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258581275 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.258581275
Directory	/workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_csr_rw.3397487328
Short name	T34
Test name
Test status
Simulation time	42858387 ps
CPU time	0.81 seconds
Started	Jul 05 04:42:47 PM PDT 24
Finished	Jul 05 04:42:50 PM PDT 24
Peak memory	204244 kb
Host	smart-9acc2f92-2edf-4410-9a2d-db068a3349df
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397487328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3397487328
Directory	/workspace/14.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4152751010
Short name	T22
Test name
Test status
Simulation time	186019679 ps
CPU time	0.91 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:39 PM PDT 24
Peak memory	204456 kb
Host	smart-f0a9302b-cfdf-4f1a-b079-beb34263a467
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152751010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o utstanding.4152751010
Directory	/workspace/14.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_errors.2841563939
Short name	T49
Test name
Test status
Simulation time	122511283 ps
CPU time	2.38 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204512 kb
Host	smart-20290dd7-6fba-4cac-ac4a-b648e577d757
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841563939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2841563939
Directory	/workspace/14.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4095583318
Short name	T51
Test name
Test status
Simulation time	62211629 ps
CPU time	1.39 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:36 PM PDT 24
Peak memory	204520 kb
Host	smart-680a3374-57d4-41f0-bfcb-f7cbfc932477
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095583318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.4095583318
Directory	/workspace/14.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3164503813
Short name	T122
Test name
Test status
Simulation time	43140000 ps
CPU time	1.08 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:36 PM PDT 24
Peak memory	204368 kb
Host	smart-1de8123f-ecfd-45b1-b9e9-d5ff2240df46
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164503813 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3164503813
Directory	/workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_csr_rw.2380519479
Short name	T31
Test name
Test status
Simulation time	19379425 ps
CPU time	0.73 seconds
Started	Jul 05 04:42:37 PM PDT 24
Finished	Jul 05 04:42:42 PM PDT 24
Peak memory	204240 kb
Host	smart-e1d34b9d-a6b6-4327-8204-47ca84c2da93
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380519479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2380519479
Directory	/workspace/15.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_intr_test.1271477672
Short name	T106
Test name
Test status
Simulation time	14629626 ps
CPU time	0.66 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:38 PM PDT 24
Peak memory	204232 kb
Host	smart-d0181dd3-e8de-4a12-98b1-ae475f665fe6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271477672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1271477672
Directory	/workspace/15.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_errors.187628127
Short name	T14
Test name
Test status
Simulation time	308284691 ps
CPU time	1.54 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204508 kb
Host	smart-d851830f-6711-40a1-bbab-e55b31050670
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187628127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.187628127
Directory	/workspace/15.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3553334009
Short name	T64
Test name
Test status
Simulation time	691125031 ps
CPU time	2.2 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:36 PM PDT 24
Peak memory	204560 kb
Host	smart-f2b44e49-ab32-4890-b510-f0192f062099
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553334009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3553334009
Directory	/workspace/15.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2788287656
Short name	T17
Test name
Test status
Simulation time	182617234 ps
CPU time	0.89 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:37 PM PDT 24
Peak memory	204400 kb
Host	smart-4727138e-ae08-4964-ae51-014cc05615b2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788287656 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2788287656
Directory	/workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1307832696
Short name	T21
Test name
Test status
Simulation time	58765895 ps
CPU time	0.77 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:37 PM PDT 24
Peak memory	204172 kb
Host	smart-b2aad722-0950-4081-9e22-c0ebba8c53c9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307832696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1307832696
Directory	/workspace/16.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_intr_test.1899380918
Short name	T80
Test name
Test status
Simulation time	24719859 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:37 PM PDT 24
Peak memory	204244 kb
Host	smart-942c47dd-3102-4664-b6cd-06f3f3aaa8d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899380918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1899380918
Directory	/workspace/16.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3712703472
Short name	T162
Test name
Test status
Simulation time	69292127 ps
CPU time	1.23 seconds
Started	Jul 05 04:42:36 PM PDT 24
Finished	Jul 05 04:42:41 PM PDT 24
Peak memory	204508 kb
Host	smart-623fd207-dc8a-4e8b-8832-11a8496cf147
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712703472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.3712703472
Directory	/workspace/16.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2418912115
Short name	T81
Test name
Test status
Simulation time	65077323 ps
CPU time	1.42 seconds
Started	Jul 05 04:42:32 PM PDT 24
Finished	Jul 05 04:42:34 PM PDT 24
Peak memory	204600 kb
Host	smart-459940ab-337f-4309-980e-108020241ff0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418912115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2418912115
Directory	/workspace/16.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1159479018
Short name	T54
Test name
Test status
Simulation time	68153249 ps
CPU time	1.45 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:36 PM PDT 24
Peak memory	204432 kb
Host	smart-a2c27759-afb2-46f4-b62e-f81e3557e9db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159479018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1159479018
Directory	/workspace/16.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1412322039
Short name	T94
Test name
Test status
Simulation time	24978766 ps
CPU time	1.22 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204572 kb
Host	smart-912fddbe-21f4-4ac0-b68a-cbedfe8fcaeb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412322039 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1412322039
Directory	/workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_csr_rw.591371192
Short name	T109
Test name
Test status
Simulation time	24270818 ps
CPU time	0.84 seconds
Started	Jul 05 04:42:37 PM PDT 24
Finished	Jul 05 04:42:41 PM PDT 24
Peak memory	204244 kb
Host	smart-18a28b27-2bae-42c4-b842-38777d962ae3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591371192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.591371192
Directory	/workspace/17.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_intr_test.3539298467
Short name	T76
Test name
Test status
Simulation time	21175526 ps
CPU time	0.69 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:38 PM PDT 24
Peak memory	204288 kb
Host	smart-8fa7394e-1b5e-4128-b702-1b5d474a3d39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539298467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3539298467
Directory	/workspace/17.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3790945541
Short name	T9
Test name
Test status
Simulation time	152719477 ps
CPU time	0.98 seconds
Started	Jul 05 04:42:39 PM PDT 24
Finished	Jul 05 04:42:44 PM PDT 24
Peak memory	204272 kb
Host	smart-22949b3a-fa8b-471e-a626-48a64092becb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790945541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o utstanding.3790945541
Directory	/workspace/17.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3998007113
Short name	T53
Test name
Test status
Simulation time	88839925 ps
CPU time	2.33 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:41 PM PDT 24
Peak memory	204612 kb
Host	smart-1ce09306-0524-4810-aac4-de01469cbb06
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998007113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3998007113
Directory	/workspace/17.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.664271355
Short name	T103
Test name
Test status
Simulation time	30049268 ps
CPU time	0.86 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:37 PM PDT 24
Peak memory	204368 kb
Host	smart-533a32bc-b02a-40cf-9faa-4f17622ea71b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664271355 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.664271355
Directory	/workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_csr_rw.265588196
Short name	T149
Test name
Test status
Simulation time	16207720 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:39 PM PDT 24
Peak memory	204240 kb
Host	smart-fa81edb9-d29d-46d4-bfec-5860db388542
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265588196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.265588196
Directory	/workspace/18.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_intr_test.3625343926
Short name	T159
Test name
Test status
Simulation time	28377003 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:35 PM PDT 24
Peak memory	204284 kb
Host	smart-d00ffd3d-d299-4122-b836-d8f4c77caa39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625343926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3625343926
Directory	/workspace/18.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3627655909
Short name	T95
Test name
Test status
Simulation time	209934781 ps
CPU time	1.11 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204484 kb
Host	smart-6d03a44f-70fd-4d04-a1a5-affa2542ca87
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627655909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o utstanding.3627655909
Directory	/workspace/18.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3013297676
Short name	T157
Test name
Test status
Simulation time	72618286 ps
CPU time	0.99 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:39 PM PDT 24
Peak memory	204368 kb
Host	smart-aa0ad190-0ee5-46ca-8d76-1125381e573c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013297676 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3013297676
Directory	/workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_csr_rw.890100568
Short name	T164
Test name
Test status
Simulation time	29798421 ps
CPU time	0.71 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:38 PM PDT 24
Peak memory	204256 kb
Host	smart-316d9561-825f-4248-8fed-eeb40e9783b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890100568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.890100568
Directory	/workspace/19.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2680849391
Short name	T68
Test name
Test status
Simulation time	33269116 ps
CPU time	0.95 seconds
Started	Jul 05 04:42:36 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204288 kb
Host	smart-c66e0f86-8432-418b-9151-2c571bf0af4f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680849391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.2680849391
Directory	/workspace/19.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_errors.1074166585
Short name	T108
Test name
Test status
Simulation time	306219919 ps
CPU time	2.92 seconds
Started	Jul 05 04:42:38 PM PDT 24
Finished	Jul 05 04:42:44 PM PDT 24
Peak memory	212780 kb
Host	smart-6358e63e-0bc0-4b95-b4c0-d8e937cd8693
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074166585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1074166585
Directory	/workspace/19.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1519180050
Short name	T56
Test name
Test status
Simulation time	82053141 ps
CPU time	2.1 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:37 PM PDT 24
Peak memory	204440 kb
Host	smart-f1c056c6-2659-49c5-a2cf-52271ee184a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519180050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1519180050
Directory	/workspace/19.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2444236304
Short name	T24
Test name
Test status
Simulation time	188167838 ps
CPU time	1.82 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:24 PM PDT 24
Peak memory	204416 kb
Host	smart-b075e4cd-89eb-446c-a68a-953792c5519a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444236304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2444236304
Directory	/workspace/2.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1648141382
Short name	T144
Test name
Test status
Simulation time	3303858921 ps
CPU time	2.99 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:24 PM PDT 24
Peak memory	204468 kb
Host	smart-c17af0ac-a3e7-42bd-9cbc-baf6b35821b3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648141382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1648141382
Directory	/workspace/2.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2123973176
Short name	T148
Test name
Test status
Simulation time	29729430 ps
CPU time	0.7 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204260 kb
Host	smart-e902008b-62c4-48b7-9d50-aa17561087e5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123973176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2123973176
Directory	/workspace/2.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1758796420
Short name	T46
Test name
Test status
Simulation time	71937201 ps
CPU time	0.84 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204368 kb
Host	smart-886f961c-d8fe-495b-b8d8-3d35873bfc03
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758796420 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1758796420
Directory	/workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_csr_rw.1015910085
Short name	T33
Test name
Test status
Simulation time	16947905 ps
CPU time	0.71 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204236 kb
Host	smart-1568bc23-f66d-4885-93a6-d1a04ce45513
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015910085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1015910085
Directory	/workspace/2.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_intr_test.633041111
Short name	T29
Test name
Test status
Simulation time	20818770 ps
CPU time	0.71 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204264 kb
Host	smart-b154641e-399f-461f-8af0-45b1c8c1daa2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633041111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.633041111
Directory	/workspace/2.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2780716970
Short name	T41
Test name
Test status
Simulation time	106115991 ps
CPU time	0.92 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204300 kb
Host	smart-5b24b5dc-b193-4e60-ad02-cacb8ebad033
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780716970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou tstanding.2780716970
Directory	/workspace/2.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_errors.3483625405
Short name	T163
Test name
Test status
Simulation time	68330173 ps
CPU time	1.72 seconds
Started	Jul 05 04:42:17 PM PDT 24
Finished	Jul 05 04:42:21 PM PDT 24
Peak memory	204612 kb
Host	smart-e8247888-5411-4936-b9b6-442c50eba4e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483625405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3483625405
Directory	/workspace/2.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3074969483
Short name	T60
Test name
Test status
Simulation time	154660890 ps
CPU time	1.5 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:23 PM PDT 24
Peak memory	204420 kb
Host	smart-84873884-c560-4097-8822-a6bb4e3675fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074969483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3074969483
Directory	/workspace/2.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.i2c_intr_test.3095630954
Short name	T156
Test name
Test status
Simulation time	27248706 ps
CPU time	0.69 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:38 PM PDT 24
Peak memory	204284 kb
Host	smart-0f201081-350d-41c3-a228-ce7aab061c78
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095630954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3095630954
Directory	/workspace/20.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.i2c_intr_test.259054579
Short name	T88
Test name
Test status
Simulation time	27032098 ps
CPU time	0.71 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:34 PM PDT 24
Peak memory	204216 kb
Host	smart-79dabde5-dad9-43ac-8029-f21f2e5d6e27
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259054579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.259054579
Directory	/workspace/22.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.i2c_intr_test.3495050684
Short name	T90
Test name
Test status
Simulation time	50286792 ps
CPU time	0.67 seconds
Started	Jul 05 04:42:36 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204276 kb
Host	smart-ec806b87-6d85-4095-83ec-6f9bf63d5b21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495050684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3495050684
Directory	/workspace/23.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.i2c_intr_test.3744657870
Short name	T11
Test name
Test status
Simulation time	46237863 ps
CPU time	0.65 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:38 PM PDT 24
Peak memory	204156 kb
Host	smart-b5548292-94b7-45d9-b106-5d0d64e93a45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744657870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3744657870
Directory	/workspace/24.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.i2c_intr_test.1536787895
Short name	T96
Test name
Test status
Simulation time	38966131 ps
CPU time	0.72 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:38 PM PDT 24
Peak memory	204220 kb
Host	smart-10aad12c-0b6a-4551-af8d-e83fa242f9f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536787895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1536787895
Directory	/workspace/25.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.i2c_intr_test.322017612
Short name	T86
Test name
Test status
Simulation time	24032212 ps
CPU time	0.73 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:39 PM PDT 24
Peak memory	204216 kb
Host	smart-87cde46c-9189-41bb-8ff1-a4a2a13e0ecc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322017612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.322017612
Directory	/workspace/26.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.i2c_intr_test.2876834102
Short name	T141
Test name
Test status
Simulation time	62637509 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:36 PM PDT 24
Peak memory	204256 kb
Host	smart-27dcfb74-7e74-4527-b164-af34f34f3d61
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876834102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2876834102
Directory	/workspace/27.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.i2c_intr_test.187808399
Short name	T134
Test name
Test status
Simulation time	34661633 ps
CPU time	0.74 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:39 PM PDT 24
Peak memory	204220 kb
Host	smart-02ddf922-c0bc-4a0b-8ad5-5f89af1573c6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187808399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.187808399
Directory	/workspace/28.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.i2c_intr_test.3897448451
Short name	T104
Test name
Test status
Simulation time	123277021 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:35 PM PDT 24
Peak memory	204184 kb
Host	smart-d51fa2d8-a7d3-4fd8-8165-8926ec1d5845
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897448451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3897448451
Directory	/workspace/29.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3313089419
Short name	T151
Test name
Test status
Simulation time	101821993 ps
CPU time	1.22 seconds
Started	Jul 05 04:42:17 PM PDT 24
Finished	Jul 05 04:42:21 PM PDT 24
Peak memory	204304 kb
Host	smart-1deca3f9-9122-4924-b4c5-16ce7c94ac57
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313089419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3313089419
Directory	/workspace/3.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3773350378
Short name	T138
Test name
Test status
Simulation time	186087774 ps
CPU time	2.74 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:23 PM PDT 24
Peak memory	204408 kb
Host	smart-d7f4fa00-648e-496b-b9f2-3a2a7fb6559b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773350378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3773350378
Directory	/workspace/3.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.536091424
Short name	T20
Test name
Test status
Simulation time	22209848 ps
CPU time	0.72 seconds
Started	Jul 05 04:42:20 PM PDT 24
Finished	Jul 05 04:42:23 PM PDT 24
Peak memory	204088 kb
Host	smart-3f18f467-a421-4025-934a-eef68d869d99
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536091424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.536091424
Directory	/workspace/3.i2c_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2137265714
Short name	T85
Test name
Test status
Simulation time	107310186 ps
CPU time	0.98 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:21 PM PDT 24
Peak memory	204328 kb
Host	smart-4b9bc361-e735-43dc-86b4-f087ab199942
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137265714 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2137265714
Directory	/workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2002881795
Short name	T119
Test name
Test status
Simulation time	30029510 ps
CPU time	0.8 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204192 kb
Host	smart-3b6b56d9-c2dc-4d9f-883f-31eb8a7ee2a3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002881795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2002881795
Directory	/workspace/3.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_intr_test.3618932955
Short name	T146
Test name
Test status
Simulation time	16809090 ps
CPU time	0.66 seconds
Started	Jul 05 04:42:23 PM PDT 24
Finished	Jul 05 04:42:25 PM PDT 24
Peak memory	204260 kb
Host	smart-c7598ac9-1973-4e77-9d32-cfd0e7ebbfe9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618932955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3618932955
Directory	/workspace/3.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3053829497
Short name	T52
Test name
Test status
Simulation time	20056915 ps
CPU time	0.88 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:23 PM PDT 24
Peak memory	204272 kb
Host	smart-6aec9f02-0c7e-4554-8455-adf73b1d5fcc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053829497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.3053829497
Directory	/workspace/3.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_errors.1640725633
Short name	T37
Test name
Test status
Simulation time	51646923 ps
CPU time	2.43 seconds
Started	Jul 05 04:42:22 PM PDT 24
Finished	Jul 05 04:42:26 PM PDT 24
Peak memory	204560 kb
Host	smart-0c308d6a-8784-420a-b764-c39ae1066aa9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640725633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1640725633
Directory	/workspace/3.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.46050610
Short name	T63
Test name
Test status
Simulation time	286622927 ps
CPU time	1.5 seconds
Started	Jul 05 04:42:18 PM PDT 24
Finished	Jul 05 04:42:23 PM PDT 24
Peak memory	204488 kb
Host	smart-9f733a55-bf2b-4cd7-a375-1086d14fc6cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46050610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.46050610
Directory	/workspace/3.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.i2c_intr_test.4224336867
Short name	T152
Test name
Test status
Simulation time	40790339 ps
CPU time	0.69 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204292 kb
Host	smart-b3a99bf0-04e9-45b9-bf42-3c14e3c39492
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224336867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.4224336867
Directory	/workspace/30.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.i2c_intr_test.1449908795
Short name	T87
Test name
Test status
Simulation time	26157989 ps
CPU time	0.67 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204264 kb
Host	smart-6ecadb8e-ec15-4035-aedb-9e3beb7cdee8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449908795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1449908795
Directory	/workspace/31.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.i2c_intr_test.1402750631
Short name	T71
Test name
Test status
Simulation time	18101980 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:36 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204256 kb
Host	smart-31c952e5-532c-445c-95d7-f4a7adbcec1f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402750631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1402750631
Directory	/workspace/33.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.i2c_intr_test.3348282011
Short name	T79
Test name
Test status
Simulation time	43164109 ps
CPU time	0.66 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:34 PM PDT 24
Peak memory	204184 kb
Host	smart-1448872a-46e3-46b9-8642-892799482925
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348282011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3348282011
Directory	/workspace/34.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.i2c_intr_test.517408744
Short name	T72
Test name
Test status
Simulation time	44829242 ps
CPU time	0.69 seconds
Started	Jul 05 04:42:37 PM PDT 24
Finished	Jul 05 04:42:42 PM PDT 24
Peak memory	204236 kb
Host	smart-26620a22-8810-48af-a63a-9b29a3cd56ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517408744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.517408744
Directory	/workspace/35.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.i2c_intr_test.2834522115
Short name	T73
Test name
Test status
Simulation time	40016222 ps
CPU time	0.67 seconds
Started	Jul 05 04:42:46 PM PDT 24
Finished	Jul 05 04:42:49 PM PDT 24
Peak memory	204256 kb
Host	smart-55f50be0-ad9a-4f9b-adcd-89631d57650f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834522115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2834522115
Directory	/workspace/36.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.i2c_intr_test.573420128
Short name	T12
Test name
Test status
Simulation time	39495922 ps
CPU time	0.67 seconds
Started	Jul 05 04:42:36 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204028 kb
Host	smart-314df685-73e9-4ecd-8027-0edd40907738
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573420128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.573420128
Directory	/workspace/37.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.i2c_intr_test.3640622046
Short name	T92
Test name
Test status
Simulation time	21210384 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:48 PM PDT 24
Finished	Jul 05 04:42:51 PM PDT 24
Peak memory	204264 kb
Host	smart-d7eb095e-1775-4885-abd0-69cff3352eac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640622046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3640622046
Directory	/workspace/38.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.i2c_intr_test.761613880
Short name	T143
Test name
Test status
Simulation time	52231176 ps
CPU time	0.65 seconds
Started	Jul 05 04:42:45 PM PDT 24
Finished	Jul 05 04:42:47 PM PDT 24
Peak memory	204244 kb
Host	smart-d5e6593d-3e23-471d-83af-83cdb74f7cbe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761613880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.761613880
Directory	/workspace/39.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.4064194697
Short name	T36
Test name
Test status
Simulation time	469283383 ps
CPU time	2.03 seconds
Started	Jul 05 04:42:16 PM PDT 24
Finished	Jul 05 04:42:20 PM PDT 24
Peak memory	204360 kb
Host	smart-f9fbecc2-5b84-41fc-908d-076416aab8e4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064194697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.4064194697
Directory	/workspace/4.i2c_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2182734347
Short name	T97
Test name
Test status
Simulation time	65951961 ps
CPU time	2.55 seconds
Started	Jul 05 04:42:23 PM PDT 24
Finished	Jul 05 04:42:27 PM PDT 24
Peak memory	204404 kb
Host	smart-4710e376-58fd-4975-aaf7-45f75218657c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182734347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2182734347
Directory	/workspace/4.i2c_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3660857403
Short name	T91
Test name
Test status
Simulation time	34640776 ps
CPU time	0.95 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204396 kb
Host	smart-96b529e5-4374-4bcb-b000-7126b01445d9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660857403 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3660857403
Directory	/workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2124469939
Short name	T111
Test name
Test status
Simulation time	76440183 ps
CPU time	0.74 seconds
Started	Jul 05 04:42:21 PM PDT 24
Finished	Jul 05 04:42:24 PM PDT 24
Peak memory	204236 kb
Host	smart-5c5d1108-a2dc-42b7-9649-32a7059cf26e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124469939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2124469939
Directory	/workspace/4.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_intr_test.3392833062
Short name	T47
Test name
Test status
Simulation time	18762517 ps
CPU time	0.66 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:22 PM PDT 24
Peak memory	204200 kb
Host	smart-73bfd0c9-066a-4746-b304-bdedb6e277d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392833062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3392833062
Directory	/workspace/4.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1854052576
Short name	T42
Test name
Test status
Simulation time	33287216 ps
CPU time	0.79 seconds
Started	Jul 05 04:42:23 PM PDT 24
Finished	Jul 05 04:42:25 PM PDT 24
Peak memory	204176 kb
Host	smart-ad106797-d281-49f1-8459-19e508583ea0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854052576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.1854052576
Directory	/workspace/4.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_errors.918342290
Short name	T113
Test name
Test status
Simulation time	465286898 ps
CPU time	2.61 seconds
Started	Jul 05 04:42:24 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204564 kb
Host	smart-594f68cc-8d75-4a0b-8745-e1acdd3718cb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918342290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.918342290
Directory	/workspace/4.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.445285440
Short name	T58
Test name
Test status
Simulation time	233799674 ps
CPU time	1.38 seconds
Started	Jul 05 04:42:19 PM PDT 24
Finished	Jul 05 04:42:23 PM PDT 24
Peak memory	204560 kb
Host	smart-ace49a21-ebba-47ac-8707-78f1242446e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445285440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.445285440
Directory	/workspace/4.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.i2c_intr_test.2854015968
Short name	T83
Test name
Test status
Simulation time	16057267 ps
CPU time	0.71 seconds
Started	Jul 05 04:42:32 PM PDT 24
Finished	Jul 05 04:42:33 PM PDT 24
Peak memory	204232 kb
Host	smart-04a58560-f62c-49a6-b757-8a54a2ced96f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854015968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2854015968
Directory	/workspace/40.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.i2c_intr_test.1524934012
Short name	T13
Test name
Test status
Simulation time	18051502 ps
CPU time	0.67 seconds
Started	Jul 05 04:42:35 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204260 kb
Host	smart-7cfe646a-5669-4b83-ab55-6dde9c7119fc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524934012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1524934012
Directory	/workspace/41.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.i2c_intr_test.3107841497
Short name	T124
Test name
Test status
Simulation time	16021498 ps
CPU time	0.69 seconds
Started	Jul 05 04:42:36 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204004 kb
Host	smart-0f1e3feb-9fc4-4bbe-b89d-e0be17dac6e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107841497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3107841497
Directory	/workspace/42.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.i2c_intr_test.1101408545
Short name	T161
Test name
Test status
Simulation time	45784372 ps
CPU time	0.73 seconds
Started	Jul 05 04:42:36 PM PDT 24
Finished	Jul 05 04:42:40 PM PDT 24
Peak memory	204260 kb
Host	smart-6bb9b9d9-ad44-4103-9ab7-2ac6628c2297
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101408545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1101408545
Directory	/workspace/43.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.i2c_intr_test.1351043059
Short name	T82
Test name
Test status
Simulation time	17680899 ps
CPU time	0.67 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:38 PM PDT 24
Peak memory	204264 kb
Host	smart-8c6b5d07-0f5e-400f-832f-77ed2c60fdc9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351043059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1351043059
Directory	/workspace/44.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.i2c_intr_test.2061965622
Short name	T114
Test name
Test status
Simulation time	20134747 ps
CPU time	0.7 seconds
Started	Jul 05 04:42:34 PM PDT 24
Finished	Jul 05 04:42:38 PM PDT 24
Peak memory	204252 kb
Host	smart-a2b3b2c0-d1e2-4562-bb70-e28dbaa6bb43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061965622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2061965622
Directory	/workspace/45.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.i2c_intr_test.1756878292
Short name	T155
Test name
Test status
Simulation time	20590082 ps
CPU time	0.7 seconds
Started	Jul 05 04:42:41 PM PDT 24
Finished	Jul 05 04:42:44 PM PDT 24
Peak memory	204252 kb
Host	smart-d8983e57-b148-4454-86ac-b386c07bfc21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756878292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1756878292
Directory	/workspace/47.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.i2c_intr_test.2447857766
Short name	T75
Test name
Test status
Simulation time	16738758 ps
CPU time	0.78 seconds
Started	Jul 05 04:42:43 PM PDT 24
Finished	Jul 05 04:42:45 PM PDT 24
Peak memory	204260 kb
Host	smart-94b7d42d-ad76-48b5-be6f-be2136b9cde5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447857766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2447857766
Directory	/workspace/48.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.i2c_intr_test.1790283249
Short name	T48
Test name
Test status
Simulation time	29441059 ps
CPU time	0.71 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:36 PM PDT 24
Peak memory	204260 kb
Host	smart-8ba4a794-e474-4d36-813d-21b8078b1317
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790283249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1790283249
Directory	/workspace/49.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3830443971
Short name	T125
Test name
Test status
Simulation time	133274621 ps
CPU time	0.8 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:37 PM PDT 24
Peak memory	204376 kb
Host	smart-0e2c70a4-c702-41b4-9cad-f8e0ae14a643
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830443971 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3830443971
Directory	/workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_csr_rw.675928040
Short name	T126
Test name
Test status
Simulation time	80621296 ps
CPU time	0.79 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:32 PM PDT 24
Peak memory	204204 kb
Host	smart-b19577a0-9880-4810-a6f4-b491074a51f5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675928040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.675928040
Directory	/workspace/5.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_intr_test.659108777
Short name	T100
Test name
Test status
Simulation time	26918646 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:24 PM PDT 24
Finished	Jul 05 04:42:26 PM PDT 24
Peak memory	204272 kb
Host	smart-f9380315-b3b7-4abd-aff8-2a6adbf68905
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659108777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.659108777
Directory	/workspace/5.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_errors.3426514105
Short name	T45
Test name
Test status
Simulation time	126381784 ps
CPU time	2.41 seconds
Started	Jul 05 04:42:26 PM PDT 24
Finished	Jul 05 04:42:29 PM PDT 24
Peak memory	204576 kb
Host	smart-fc8cfd50-88cf-4eab-b91b-bc53b45f2853
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426514105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3426514105
Directory	/workspace/5.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1469624360
Short name	T135
Test name
Test status
Simulation time	47538790 ps
CPU time	1.4 seconds
Started	Jul 05 04:42:27 PM PDT 24
Finished	Jul 05 04:42:31 PM PDT 24
Peak memory	204588 kb
Host	smart-3b4faa69-207c-4fe9-bfd5-fb2b95a5b0db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469624360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1469624360
Directory	/workspace/5.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.61280387
Short name	T5
Test name
Test status
Simulation time	121856432 ps
CPU time	0.93 seconds
Started	Jul 05 04:42:27 PM PDT 24
Finished	Jul 05 04:42:30 PM PDT 24
Peak memory	204344 kb
Host	smart-52c12c18-9276-44da-8eb7-072611b68050
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61280387 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.61280387
Directory	/workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_csr_rw.2770415126
Short name	T158
Test name
Test status
Simulation time	16116910 ps
CPU time	0.72 seconds
Started	Jul 05 04:42:28 PM PDT 24
Finished	Jul 05 04:42:31 PM PDT 24
Peak memory	204108 kb
Host	smart-a8fd971d-89b7-40b9-8479-7ea2e990e421
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770415126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2770415126
Directory	/workspace/6.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_intr_test.1167600249
Short name	T84
Test name
Test status
Simulation time	21679780 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:25 PM PDT 24
Finished	Jul 05 04:42:27 PM PDT 24
Peak memory	204276 kb
Host	smart-0d6d5707-cf1a-4e46-a587-6b47a973e54e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167600249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1167600249
Directory	/workspace/6.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.377578377
Short name	T40
Test name
Test status
Simulation time	60398608 ps
CPU time	1.17 seconds
Started	Jul 05 04:42:25 PM PDT 24
Finished	Jul 05 04:42:27 PM PDT 24
Peak memory	204456 kb
Host	smart-ef1c78f9-34a6-48ab-94e0-2f0212ed957c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377578377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out standing.377578377
Directory	/workspace/6.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.i2c_tl_errors.1845445448
Short name	T153
Test name
Test status
Simulation time	664110967 ps
CPU time	1.42 seconds
Started	Jul 05 04:42:26 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204528 kb
Host	smart-960205f8-097e-4a75-be85-d0fd87543596
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845445448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1845445448
Directory	/workspace/6.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2315443363
Short name	T77
Test name
Test status
Simulation time	26846803 ps
CPU time	0.89 seconds
Started	Jul 05 04:42:28 PM PDT 24
Finished	Jul 05 04:42:31 PM PDT 24
Peak memory	204344 kb
Host	smart-632a9e49-d122-47cb-84d6-d0191f914c4c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315443363 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2315443363
Directory	/workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_csr_rw.1831493456
Short name	T127
Test name
Test status
Simulation time	37556311 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:24 PM PDT 24
Finished	Jul 05 04:42:26 PM PDT 24
Peak memory	204120 kb
Host	smart-093a9a97-0b93-44f9-b814-f72d80398544
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831493456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1831493456
Directory	/workspace/7.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_intr_test.4155151966
Short name	T129
Test name
Test status
Simulation time	87531414 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:26 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204164 kb
Host	smart-8abc2101-8bb7-449d-9cc2-54e80a10ad05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155151966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.4155151966
Directory	/workspace/7.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1705442256
Short name	T110
Test name
Test status
Simulation time	21182811 ps
CPU time	0.88 seconds
Started	Jul 05 04:42:25 PM PDT 24
Finished	Jul 05 04:42:27 PM PDT 24
Peak memory	204276 kb
Host	smart-6f7e3fe5-f92c-48ba-99fe-c06ef90965d7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705442256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.1705442256
Directory	/workspace/7.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_errors.3419824665
Short name	T105
Test name
Test status
Simulation time	49473963 ps
CPU time	1.3 seconds
Started	Jul 05 04:42:24 PM PDT 24
Finished	Jul 05 04:42:26 PM PDT 24
Peak memory	204492 kb
Host	smart-0e46dfc8-f24d-414b-8b2c-0c64bcadf9dc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419824665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3419824665
Directory	/workspace/7.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3843598732
Short name	T154
Test name
Test status
Simulation time	326439338 ps
CPU time	1.42 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:33 PM PDT 24
Peak memory	204452 kb
Host	smart-e78a1cf8-d8ef-4cdf-8add-e5d805e8741f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843598732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3843598732
Directory	/workspace/7.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4100808672
Short name	T44
Test name
Test status
Simulation time	112826992 ps
CPU time	0.96 seconds
Started	Jul 05 04:42:27 PM PDT 24
Finished	Jul 05 04:42:30 PM PDT 24
Peak memory	204356 kb
Host	smart-6b140cd5-7717-40a4-95d5-60c054e6b681
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100808672 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.4100808672
Directory	/workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_csr_rw.939714334
Short name	T130
Test name
Test status
Simulation time	24036543 ps
CPU time	0.71 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:32 PM PDT 24
Peak memory	204204 kb
Host	smart-66408ff5-7c83-4091-ada3-be4bc7be7543
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939714334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.939714334
Directory	/workspace/8.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_intr_test.113125095
Short name	T118
Test name
Test status
Simulation time	62177705 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:33 PM PDT 24
Finished	Jul 05 04:42:36 PM PDT 24
Peak memory	204272 kb
Host	smart-f1ed98a7-ebc7-4368-8c97-59688eb8dfa7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113125095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.113125095
Directory	/workspace/8.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2904985317
Short name	T66
Test name
Test status
Simulation time	1527947969 ps
CPU time	3.6 seconds
Started	Jul 05 04:42:25 PM PDT 24
Finished	Jul 05 04:42:30 PM PDT 24
Peak memory	204316 kb
Host	smart-7c69d515-930c-4fa4-826d-656739a17bde
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904985317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou tstanding.2904985317
Directory	/workspace/8.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2984676519
Short name	T7
Test name
Test status
Simulation time	32388829 ps
CPU time	1.5 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:33 PM PDT 24
Peak memory	204452 kb
Host	smart-d9ef8376-8ebb-4d67-9e0a-0e9a6099b32d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984676519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2984676519
Directory	/workspace/8.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2003981012
Short name	T137
Test name
Test status
Simulation time	190360271 ps
CPU time	2.24 seconds
Started	Jul 05 04:42:27 PM PDT 24
Finished	Jul 05 04:42:32 PM PDT 24
Peak memory	204480 kb
Host	smart-d8af0b06-c814-4677-907a-7da00e21ecb1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003981012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2003981012
Directory	/workspace/8.i2c_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2609874544
Short name	T150
Test name
Test status
Simulation time	24759881 ps
CPU time	0.84 seconds
Started	Jul 05 04:42:28 PM PDT 24
Finished	Jul 05 04:42:32 PM PDT 24
Peak memory	204400 kb
Host	smart-228a8827-883b-4bc8-88b9-82fb959f0bf2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609874544 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2609874544
Directory	/workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1580878608
Short name	T121
Test name
Test status
Simulation time	22111853 ps
CPU time	0.76 seconds
Started	Jul 05 04:42:26 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204184 kb
Host	smart-c64d2581-d32e-4c62-b740-6e9668945f21
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580878608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1580878608
Directory	/workspace/9.i2c_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_intr_test.2383510673
Short name	T145
Test name
Test status
Simulation time	18638771 ps
CPU time	0.68 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:32 PM PDT 24
Peak memory	204236 kb
Host	smart-883a9656-5d31-4bcc-a29b-6c57550d12cc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383510673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2383510673
Directory	/workspace/9.i2c_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1621682643
Short name	T67
Test name
Test status
Simulation time	172761413 ps
CPU time	0.83 seconds
Started	Jul 05 04:42:28 PM PDT 24
Finished	Jul 05 04:42:31 PM PDT 24
Peak memory	204248 kb
Host	smart-a3d23a87-373a-4b25-a974-547c1d326b86
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621682643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.1621682643
Directory	/workspace/9.i2c_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_errors.3143801673
Short name	T136
Test name
Test status
Simulation time	67027959 ps
CPU time	1.09 seconds
Started	Jul 05 04:42:29 PM PDT 24
Finished	Jul 05 04:42:32 PM PDT 24
Peak memory	204340 kb
Host	smart-7f62a652-ea30-4a53-9daa-e4f9df48a74f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143801673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3143801673
Directory	/workspace/9.i2c_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.720491707
Short name	T59
Test name
Test status
Simulation time	79807004 ps
CPU time	1.48 seconds
Started	Jul 05 04:42:25 PM PDT 24
Finished	Jul 05 04:42:28 PM PDT 24
Peak memory	204556 kb
Host	smart-01aecee2-d3aa-4389-939c-cd1b92a8cad5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720491707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.720491707
Directory	/workspace/9.i2c_tl_intg_err/latest