| | | | | | | |
tb |
52.46 |
40.66 |
40.72 |
90.72 |
0.00 |
42.98 |
99.68 |
| dut |
52.46 |
40.66 |
40.72 |
90.72 |
0.00 |
42.98 |
99.68 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| i2c_core |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| intr_hw_acq_overflow |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_acq_threshold |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_cmd_complete |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_controller_halt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_fmt_threshold |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_host_timeout |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_rx_overflow |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_rx_threshold |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_scl_interference |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_sda_interference |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_sda_unstable |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_stretch_timeout |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_tx_stretch |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_tx_threshold |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| intr_hw_unexp_stop |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_fifos |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_acq_fifo_sram_adapter |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_inp_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_oup_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sram_ptrs |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_fmt_fifo_sram_adapter |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_inp_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_oup_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sram_ptrs |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_ram_1p |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_mem |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_req_d_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_write_d_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_ram_arbiter |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_rx_fifo_sram_adapter |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_inp_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_oup_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sram_ptrs |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_tx_fifo_sram_adapter |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_inp_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_oup_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sram_ptrs |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_i2c_bus_monitor |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_i2c_controller_fsm |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_i2c_sync_scl |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_i2c_sync_sda |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_i2c_target_fsm |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| i2c_csr_assert |
93.75 |
|
|
|
|
|
93.75 |
| tlul_assert_device |
33.33 |
0.00 |
|
|
|
0.00 |
100.00 |
| u_reg |
95.88 |
98.37 |
95.92 |
87.50 |
|
97.58 |
100.00 |
| subtree... |
|
|
|
|
|
|
|