Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 60 0 60 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 15 0 15 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 60 0 60 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 341 1 T1 8 T2 1 T3 1
all_pins[1] 341 1 T1 8 T2 1 T3 1
all_pins[2] 341 1 T1 8 T2 1 T3 1
all_pins[3] 341 1 T1 8 T2 1 T3 1
all_pins[4] 341 1 T1 8 T2 1 T3 1
all_pins[5] 341 1 T1 8 T2 1 T3 1
all_pins[6] 341 1 T1 8 T2 1 T3 1
all_pins[7] 341 1 T1 8 T2 1 T3 1
all_pins[8] 341 1 T1 8 T2 1 T3 1
all_pins[9] 341 1 T1 8 T2 1 T3 1
all_pins[10] 341 1 T1 8 T2 1 T3 1
all_pins[11] 341 1 T1 8 T2 1 T3 1
all_pins[12] 341 1 T1 8 T2 1 T3 1
all_pins[13] 341 1 T1 8 T2 1 T3 1
all_pins[14] 341 1 T1 8 T2 1 T3 1



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 4186 1 T1 93 T2 15 T3 15
values[0x1] 929 1 T1 27 T12 9 T10 31
transitions[0x0=>0x1] 677 1 T1 17 T12 7 T10 20
transitions[0x1=>0x0] 685 1 T1 17 T12 8 T10 20



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 60 0 60 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 283 1 T1 8 T2 1 T3 1
all_pins[0] values[0x1] 58 1 T10 1 T13 2 T29 1
all_pins[0] transitions[0x0=>0x1] 48 1 T10 1 T13 2 T29 1
all_pins[0] transitions[0x1=>0x0] 40 1 T1 4 T10 4 T28 3
all_pins[1] values[0x0] 291 1 T1 4 T2 1 T3 1
all_pins[1] values[0x1] 50 1 T1 4 T10 4 T28 3
all_pins[1] transitions[0x0=>0x1] 35 1 T1 4 T10 3 T28 2
all_pins[1] transitions[0x1=>0x0] 50 1 T10 1 T28 1 T29 1
all_pins[2] values[0x0] 276 1 T1 8 T2 1 T3 1
all_pins[2] values[0x1] 65 1 T10 2 T28 2 T29 1
all_pins[2] transitions[0x0=>0x1] 50 1 T10 2 T28 2 T29 1
all_pins[2] transitions[0x1=>0x0] 47 1 T10 1 T13 1 T29 1
all_pins[3] values[0x0] 279 1 T1 8 T2 1 T3 1
all_pins[3] values[0x1] 62 1 T10 1 T13 1 T29 1
all_pins[3] transitions[0x0=>0x1] 49 1 T10 1 T13 1 T29 1
all_pins[3] transitions[0x1=>0x0] 41 1 T1 1 T10 1 T11 1
all_pins[4] values[0x0] 287 1 T1 7 T2 1 T3 1
all_pins[4] values[0x1] 54 1 T1 1 T10 1 T11 1
all_pins[4] transitions[0x0=>0x1] 36 1 T11 1 T28 2 T38 1
all_pins[4] transitions[0x1=>0x0] 55 1 T1 1 T12 1 T10 1
all_pins[5] values[0x0] 268 1 T1 6 T2 1 T3 1
all_pins[5] values[0x1] 73 1 T1 2 T12 1 T10 2
all_pins[5] transitions[0x0=>0x1] 52 1 T1 2 T12 1 T10 2
all_pins[5] transitions[0x1=>0x0] 38 1 T1 3 T12 2 T10 1
all_pins[6] values[0x0] 282 1 T1 5 T2 1 T3 1
all_pins[6] values[0x1] 59 1 T1 3 T12 2 T10 1
all_pins[6] transitions[0x0=>0x1] 45 1 T1 2 T12 2 T28 1
all_pins[6] transitions[0x1=>0x0] 50 1 T1 1 T10 2 T11 1
all_pins[7] values[0x0] 277 1 T1 6 T2 1 T3 1
all_pins[7] values[0x1] 64 1 T1 2 T10 3 T11 1
all_pins[7] transitions[0x0=>0x1] 37 1 T1 1 T11 1 T28 1
all_pins[7] transitions[0x1=>0x0] 47 1 T1 1 T12 2 T10 2
all_pins[8] values[0x0] 267 1 T1 6 T2 1 T3 1
all_pins[8] values[0x1] 74 1 T1 2 T12 2 T10 5
all_pins[8] transitions[0x0=>0x1] 48 1 T1 1 T12 2 T10 2
all_pins[8] transitions[0x1=>0x0] 59 1 T1 3 T11 2 T13 1
all_pins[9] values[0x0] 256 1 T1 4 T2 1 T3 1
all_pins[9] values[0x1] 85 1 T1 4 T10 3 T11 2
all_pins[9] transitions[0x0=>0x1] 60 1 T1 1 T10 3 T11 1
all_pins[9] transitions[0x1=>0x0] 44 1 T1 1 T12 2 T10 1
all_pins[10] values[0x0] 272 1 T1 4 T2 1 T3 1
all_pins[10] values[0x1] 69 1 T1 4 T12 2 T10 1
all_pins[10] transitions[0x0=>0x1] 59 1 T1 4 T12 1 T10 1
all_pins[10] transitions[0x1=>0x0] 39 1 T1 1 T10 1 T29 3
all_pins[11] values[0x0] 292 1 T1 7 T2 1 T3 1
all_pins[11] values[0x1] 49 1 T1 1 T12 1 T10 1
all_pins[11] transitions[0x0=>0x1] 41 1 T12 1 T10 1 T11 1
all_pins[11] transitions[0x1=>0x0] 38 1 T1 1 T10 2 T13 1
all_pins[12] values[0x0] 295 1 T1 6 T2 1 T3 1
all_pins[12] values[0x1] 46 1 T1 2 T10 2 T13 1
all_pins[12] transitions[0x0=>0x1] 34 1 T1 1 T10 2 T13 1
all_pins[12] transitions[0x1=>0x0] 51 1 T10 1 T11 1 T13 2
all_pins[13] values[0x0] 278 1 T1 7 T2 1 T3 1
all_pins[13] values[0x1] 63 1 T1 1 T10 1 T11 1
all_pins[13] transitions[0x0=>0x1] 48 1 T11 1 T13 2 T38 1
all_pins[13] transitions[0x1=>0x0] 43 1 T12 1 T10 2 T28 1
all_pins[14] values[0x0] 283 1 T1 7 T2 1 T3 1
all_pins[14] values[0x1] 58 1 T1 1 T12 1 T10 3
all_pins[14] transitions[0x0=>0x1] 35 1 T1 1 T10 2 T28 1
all_pins[14] transitions[0x1=>0x0] 43 1 T13 2 T29 1 T47 2

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